MCU controller
By designing the MCU controller, using multiple separate and parallel buses to connect to the memory and registers, the problem of inefficient read and write efficiency in traditional MCU products is solved, and the system performance improvement and startup efficiency optimization is achieved.
CN119690906AInactive Publication Date: 2025-03-25SHENZHEN JINGCUN TECH CO LTD
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Patent Information
- Application Number
- CN202510222178.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-27
- Publication Date
- 2025-03-25
- Estimated Expiration
- Not applicable · inactive patent
AI Technical Summary
Technical Problem
In MCU products with a main frequency of 100MHz or above, the traditional NOR FLASH reading instructions and data methods lead to low reading and writing efficiency, making it difficult to improve system performance.
Method used
A MCU controller is designed to connect to multiple read-only memories, read-write memories and registers through the core, and access data using multiple separate and parallel buses. The flash controller switches between the bus master and the bus slave device to achieve parallel access to data and optimize startup efficiency.
Benefits of technology
The parallel access of instructions, data and external data is achieved through separate bus interfaces, improving system efficiency, optimizing startup efficiency and running time flexibility.
✦ Generated by Eureka AI based on patent content.
Abstract
The invention provides an MCU controller. The MCU controller comprises a kernel, a read-only memory, a read-write memory, a register, a flash memory controller and a flash memory, the read-only memory and the read-write memory store different data types and different mapping addresses; the kernel is respectively connected with the read-only memory, the read-write memory and the register through a plurality of buses, and the plurality of buses are separated and parallel; the flash memory controller is connected with the read-only memory and the read-write memory, and the flash memory controller is switched between the bus master device and the bus slave device; when the flash memory controller is switched to the bus master device, the flash memory controller transmits the data to be transmitted from the flash memory to the read-write memory; when the flash memory controller is switched to a bus slave device, the kernel performs read-write operation on the register; parallel access of instructions, data and external data is achieved through separated bus interfaces, and the system efficiency is improved; the dynamic master-slave switching of the flash memory controller optimizes the starting efficiency and the flexibility during operation.
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