Method for extracting qualier expression in clock domain

Abstract

The invention discloses a method for extracting a qualifier expression in a clock domain. The method comprises the following steps of: 1, extracting a data path when the clock domain of an integrated circuit is crossed; step 2, a qualier expression is extracted; step 3, for each data path, generating a table assertion, and ensuring that the output signal of the source register is kept stable when the qualifier expression is valid; and 4, binding all assertions to the circuit design, carrying out simulation verification, and if the assertion fails, returning to the step 2 to newly extract the qualier expression until the assertion is successful, and extracting a correct qualier expression. According to the method, the qualifier expression can be automatically extracted, the stability of the data is ensured, and the metastable state is avoided.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit verification, and in particular to a method for extracting a qualifier expression in a clock domain. Background Art

[0002] As circuits increase in size and complexity, global synchronization becomes increasingly difficult, and the GALS (Globally Asynchronous Locally Synchronous) system has emerged as an alternative. The GALS system addresses the challenge of global synchronization in complex circuits through local synchronous clock domains and global asynchronous communication. Local synchronous clock domains refer to each module or subsystem running under a local clock, which is synchronized. Global asynchronous communication refers to the interaction between modules through an asynchronous communication mechanism. This approach allows different modules to run at different clock frequencies or phases, improving the flexibility and scalability of the system, and is suitable for handling clock distribution issues in large-scale SoCs (system-on-chip).

[0003] However, clock domain crossing (CDC) in the GALS system can lead to potential data instability issues. CDC refers to the process of transferring a signal from one clock domain to another. Since the frequencies and phases of the two clock domains may be different or unrelated, when the receiving clock domain samples data, the signal may not meet the setup time or hold time requirements of the receiving trigger, resulting in sampling errors. If the data signal sampled by the trigger changes within the setup or hold time, the trigger may enter a metastable state, that is, the output is in an undeterministic state and may oscillate or be unstable for a long time.

[0004] Traditional static timing analysis (STA) cannot guarantee the correctness of clock domain crossing, because the clock signals between clock domains are not synchronized, which may cause setup and hold time violations, thereby causing metastability. In order to avoid metastability, synchronizer structures such as multi-flip-flop (MFS) or asynchronous FIFO are required.

[0005] Multistage trigger (MFS) samples the signal multiple times through multiple stages of triggers when the signal crosses the clock domain to eliminate the influence of metastable state. Each stage of trigger delays the signal by one clock cycle to give the signal time to stabilize to a legal state.

[0006] Asynchronous FIFO is used to transfer multi-bit data across clock domains. It ensures the correctness and stability of data by introducing a buffer between the write clock domain and the read clock domain.

[0007] Qualifier is a conditional logic expression used to control the transfer of data signals between clock domains. It is usually composed of multiple layers of logic, including multi-level conditional judgment, state machine control, and historical state of the signal. For example, the statement "wire qualified_signal = (enable&&(state == IDLE))?data_signal:1'b0" describes a complex qualifier expression, which depends on multiple input signals, and the logic may involve multiple circuit modules, state machines, and time delays.

[0008] Since complex qualifier expressions have complex signal dependencies, unclear clock relationships, and unclear state dependencies, most commercial CDC tools rely on static analysis, assuming that signal values ​​and logic relationships are fixed, and have limited analysis capabilities for timing dependencies and conditional logic branches. Therefore, existing commercial CDC verification tools can identify synchronizer structures, but cannot effectively extract complex qualifier expressions, resulting in inaccurate verification results. Summary of the invention

[0009] In order to solve the technical problem that a complex qualifier expression cannot be effectively extracted in the prior art, the present invention proposes a method for extracting a qualifier expression in a clock domain.

[0010] The present invention provides a method for extracting a qualifier expression in a clock domain, comprising:

[0011] Step 1, extracting the data path when the clock domain of the integrated circuit crosses;

[0012] Step 2, extract the qualifier expression;

[0013] Step 3, for each of the data paths, generating a stable assertion to ensure that when the qualifier expression is valid, the output signal of the source register remains stable;

[0014] Step 4: Bind all assertions to the circuit design and perform simulation verification. If the assertion fails, return to step 2 to extract a new qualifier expression until the assertion succeeds and the correct qualifier expression is extracted.

[0015] Further, the step 1 comprises:

[0016] Determine all components involved in the crossed clock domains and all signals crossing two clock domains; the types of components include registers, flip-flops, asynchronous FIFOs, combinational logic, and clock domains;

[0017] Build a CDC tree using components as nodes and signals as edges;

[0018] The path from the target register to the source register in the CDC tree is used as the data path of the CDC tree, and the data path and the control path are identified and extracted.

[0019] Furthermore, starting from the target register, the CDC tree is traversed upward until the source register is reached, and the signals corresponding to the elements and edges passed through on the path are recorded as the data path.

[0020] Further, the step 2 comprises:

[0021] Initialize the qualifier expression to the logical AND of all control signals or the logical OR of all control signals, and the initial qualifier expression evaluates to true;

[0022] Starting from the end of each path, traverse forward along each edge to each element;

[0023] Update the qualifier expression according to the component type.

[0024] Further, updating the qualifier expression according to the component type includes:

[0025] When the element is a NOT gate, remove the input signal of the element from the qualifier expression;

[0026] When the element is an OR gate, the input signal of the element is added to the qualifier expression through logical OR;

[0027] When the element is an AND gate, the input signal of the element is added to the qualifier expression through logical AND;

[0028] When the element is a MUX gate, the data input signal or control input signal of the element selected according to the value of the selection signal is added to the qualifier expression.

[0029] Furthermore, when the element is a MUX gate, if the selection signal is true, the data input signal is added to the qualifier expression through logical AND; if the selection signal is false, the control input signal is added to the qualifier expression through logical AND.

[0030] Further, re-extracting the qualifier expression includes:

[0031] Modify the initial qualifier expression; and / or remove the input signal of the component that caused the failure from the qualifier expression; and / or re-traverse the data path and update the qualifier expression based on the traversed data path.

[0032] Further, modifying the initial qualifier expression includes removing the false control signal from the initial qualifier expression.

[0033] Aiming at the CDC metastable problem, the present invention proposes a technology for automatically extracting qualifiers, which can correctly extract the combined expressions of all control signals as qualifiers, ensure the stability of data, and avoid the occurrence of metastable states. The algorithm has low complexity, can complete the extraction of qualifiers and the generation of assertions in a short time, and improve design efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The present invention is described in detail below with reference to the embodiments and accompanying drawings, wherein:

[0035] Figure 1 is a flow chart of an embodiment of the present invention. DETAILED DESCRIPTION

[0036] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0037] Thus, a feature indicated in this specification will be used to illustrate one of the features of an embodiment of the present invention, rather than implying that each embodiment of the present invention must have the described feature. In addition, it should be noted that this specification describes many features. Although some features can be combined together to illustrate possible system designs, these features can also be used in other combinations that are not explicitly described. Thus, unless otherwise stated, the described combinations are not intended to be limiting.

[0038] like Figure 1 As shown, the method for extracting the qualifier expression in the clock domain proposed by the present invention mainly includes the following steps.

[0039] Step 1, extracting the data path when the clock domain of the integrated circuit crosses;

[0040] Step 2, extract the qualifier expression;

[0041] Step 3: For each of the data paths, generate a stable assertion to ensure that the output signal of the source register remains stable when the qualifier expression is valid; Stable assertion is an effective formal verification method for detecting the stability of a signal within a specific time range. Stable assertion can verify whether the signal remains stable before being synchronized to the target clock domain.

[0042] Step 4: Bind all assertions to the circuit design and perform simulation verification. If the assertion fails, return to step 2 until the assertion succeeds and the correct qualifier expression is extracted.

[0043] The present invention generates a corresponding stable assertion for each data path and binds it to the circuit design. When performing simulation verification, it can effectively determine whether the qualifier expression is correct to obtain a correct verification result.

[0044] In a specific embodiment, the above step 1 of the present invention includes the following steps.

[0045] Determine all components involved in the crossed clock domains and all signals crossing two clock domains; the types of components include registers, flip-flops, asynchronous FIFOs, combinational logic, and clock domains;

[0046] Build a CDC tree using components as nodes and signals as edges;

[0047] The path from the target register to the source register in the CDC tree is used as the data path of the CDC tree, and the data path and control path are identified and extracted. The specific method is to start from the target register, traverse the CDC tree upward until the source register is reached, and record the components and signals corresponding to the edges on the path.

[0048] In addition to the above method of extracting data paths, you can also extract data paths by traversing register files. Specifically, you can start from the target register and traverse the register file upward to find all signals that directly drive the target register. Then, trace these signals backward until the source register is found. Record the components and signal lines passed during the backward tracing process to obtain the corresponding data path.

[0049] In addition, the data path can be extracted by traversing the watch file of the circuit design. Specifically, you can start from the target register and traverse the netlist upward to find all the signals directly connected to the target register. Then, these signals are traced back until the source register is found. The CDC data path can be obtained by recording the components and signal lines passed during the reverse tracing process.

[0050] In the above three methods, extracting the reverse traversal of the data path according to the register file and the netlist file includes the following steps.

[0051] Step 1.1, starting from the source register, find all the signals that directly drive the source register.

[0052] Step 1.2, trace back each signal to find its driving element.

[0053] In step 1.3, check the input port of the driver component to determine whether it belongs to the CDC data path.

[0054] Step 1.4, if the input port belongs to the CDC data path, add the driving element and signal line to the path.

[0055] Step 1.5, repeat steps 1.2 to 1.4 until the target register is found or all signals are traced.

[0056] The above-mentioned extraction of data paths based on register files and netlist files requires knowing the clock domain corresponding to each signal, so as to determine whether the signal has crossed the clock domain boundary. It is also necessary to know the driving element of each signal so as to track the reverse path of the signal. Finally, it is also necessary to know the input and output ports of each element in order to determine the position of the element in the path. In comparison, extracting data paths through the CDC tree is the simplest and most effective way. The reverse traversal method is less efficient and requires additional information. Therefore, extracting data paths through the CDC tree is a preferred embodiment of the present invention.

[0057] In a specific embodiment, step 2 includes the following steps.

[0058] Initialize the qualifier expression to the logical AND of all control signals or the logical OR of all control signals, and the initial qualifier expression evaluates to true;

[0059] Starting from the end of each path, traverse each element forward along each edge. The path here refers to both data paths and control paths.

[0060] Update the qualifier expression according to the component type.

[0061] The initial value of the qualifier expression is 1, which means it is an expression that is always true, that is, no matter what the value of the qualifier expression is, it will not affect the transmission of the data signal. In the actual CDC data path, the role of the qualifier expression is to control the transmission of the data signal, ensuring that the data signal is sampled only when it is stable, avoiding the occurrence of metastable state.

[0062] When the qualifier expression is initialized to the logical AND of all control signals, the qualifier expression is true only when all control signals are true, and the data signal can be passed;

[0063] When the qualifier expression is initialized to the logical OR of all control signals, the value of the qualifier expression is true, that is, as long as one control signal is true, the qualifier expression is true and the data signal can be passed.

[0064] In a specific embodiment, the method of updating the qualifier expression according to the component type mainly includes the following cases: When the component is a NOT gate, the output signal of the NOT gate is opposite to the input signal, so the input signal needs to be removed from the qualifier expression, that is, qualifier = qualifier AND NOT (input signal) is executed, and input signal is the input signal of the NOT gate.

[0065] When the element is an OR gate, the output signal of the OR gate is the result when any one of the input signals is true, so the input signal needs to be added to the qualifier expression, that is, execute qualifier=qualifier OR(inputsignal), and input signal is the input signal of the OR gate.

[0066] When the element is an AND gate, the output signal of the AND gate is the result when all the input signals are true, so the input signal needs to be added to the qualifier expression, that is, execute qualifier=qualifier AND(inputsignal), and input signal is the input signal of the AND gate.

[0067] When the element is a MUX gate, the output signal of the MUX gate depends on the selection signal and thus needs to be updated according to the selection signal.

[0068] If the selection signal is true, the data input signal is added to the qualifier expression, that is, qualifier = qualifier AND (data input signal) is executed, and the data input signal is the data input signal of the MUX gate.

[0069] If the selection signal is false, the control input signal is added to the qualifier expression, that is, qualifier = qualifier AND (control input signal) is executed, and the control input signal is the control input signal of the MUX gate.

[0070] The following is an example.

[0071] Assume a CDC datapath consists of the following elements:

[0072] * Source register R_s

[0073] *NOT doorNOT1

[0074] *AND gate AND1

[0075] *Destination register R_d

[0076] The control signal of the element AND1 is ctrl1.

[0077] The initialization qualifier expression is ctrl1, which is the logical AND of all control signals, and the initial qualifier expression value is 1.

[0078] Traversing the path and updating the qualifier according to the component type includes the following steps.

[0079] 1. From R_s to NOT1, execute qualifier = qualifier AND NOT (d_in_R_s).

[0080] 2. From NOT1 to AND1, execute qualifier=qualifier AND(d_in_NOT1).

[0081] 3. From AND1 to R_d, execute qualifier=qualifier AND(d_in_AND1).

[0082] Finally, the qualifier expression is (NOT(d_in_R_s))AND(d_in_NOT1)AND(d_in_AND1). Only when these three conditions are met can the data signal be passed from R_s to R_d.

[0083] When the assertion fails and the qualifier expression needs to be re-extracted, the following method can be used.

[0084] First, you need to analyze the cause of the assertion failure and determine which control signals cause the metastable state of the data signal. Then you can take any one or more of the following measures based on the specific cause of the failure.

[0085] Modify the initialization of the qualifier expression: Depending on the reason for the assertion failure, modify the initialization of the qualifier expression. For example, if the assertion fails because a control signal is false, you can remove the control signal from the initial qualifier expression.

[0086] Update the update rules of the qualifier expression: Update the update rules of the qualifier expression according to the component type. For example, if the assertion failure is due to a NOT gate, the input signal of the NOT gate can be removed from the qualifier expression.

[0087] Re-traverse the CDC data path: Use the modified qualifier expression to initialize and update the rules, re-traverse the CDC data path, and generate a new qualifier expression.

[0088] After obtaining the new qualifier expression, a new stable assertion is generated based on the new qualifier expression.

[0089] Then replace the old assertion with the new one and bind it to the circuit design. Perform simulation verification again to see if the correct qualifier expression can be obtained.

[0090] If it is still incorrect, repeat the above steps to re-extract the qualifier expression to obtain the correct qualifier expression to ensure the stability of the data signal.

[0091] For example:

[0092] Assume a CDC datapath consists of the following elements:

[0093] * Source register R_s

[0094] *NOT doorNOT1

[0095] *AND gate AND1

[0096] *Destination register R_d

[0097] Among them, the control signal of AND1 is ctrl1.

[0098] Initialize the qualifier expression to ctrl1, which is the logical AND of all control signals.

[0099] First analyze the reasons for the assertion failure:

[0100] Assume that the simulation results show that when ctrl1 is false, the data signal d_in_R_s flips within the setup time window of R_d, resulting in a metastable state. Then modify the initialization process of the qualifier expression, that is, since ctrl1 will cause a metastable state when it is false, ctrl1 can be removed from the initialization expression of the qualifier.

[0101] Re-traverse the CDC data path, use the modified initial qualifier expression, re-traverse the CDC data path, and generate a new qualifier expression:

[0102] qualifier=NOT(d_in_R_s)AND(d_in_NOT1)AND(d_in_AND1)

[0103] Using the new qualifier expression, a new stable assertion is generated:

[0104] stable:assert property@(posedge clk_dest)(qualifier)|->$stable(d_in_R_s)

[0105] The new assertion is simulated and verified to ensure the stability of the data signal d_in_R_s.

[0106] The above method is only one possible way to re-extract the qualifier. In actual applications, those skilled in the art may need to perform analysis and adjustments based on specific circumstances. That is, the above example is not the only way of the present invention.

[0107] The process of re-extracting the qualifier expression may require multiple iterations before the correct qualifier expression is found.

[0108] The present invention proposes a general method that can automatically detect all control signals and construct correct qualifier expressions. At the same time, these qualifier expressions can also be successfully detected regardless of the type of synchronization protocol. In addition, the present invention proves through simulation verification that the assertions generated by this method are more reliable than those generated by commercial tools.

[0109] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for extracting a qualifier expression in a clock domain, characterized in that: include: Step 1, extracting the data path when the clock domain of the integrated circuit crosses; Step 2, extract the qualifier expression; Step 3, for each of the data paths, generating a stable assertion to ensure that when the qualifier expression is valid, the output signal of the source register remains stable; Step 4: Bind all assertions to the circuit design and perform simulation verification. If the assertion fails, return to step 2 to re-extract the qualifier expression until the assertion succeeds and the correct qualifier expression is extracted.

2. The method for extracting a qualifier expression in a clock domain according to claim 1, characterized in that: The step 1 comprises: Determine all components involved in the crossed clock domains and all signals crossing two clock domains; the types of components include registers, flip-flops, asynchronous FIFOs, combinational logic, and clock domains; Build a CDC tree using components as nodes and signals as edges; The path from the target register to the source register in the CDC tree is used as the data path of the CDC tree, and the data path and the control path are identified and extracted.

3. The method for extracting a qualifier expression in a clock domain according to claim 2, characterized in that: Starting from the target register, traverse the CDC tree upward until the source register is reached, and record the signals corresponding to the elements and edges passed on the path as the data path.

4. The method for extracting a qualifier expression in a clock domain according to claim 2, characterized in that: The step 2 comprises: Initialize the qualifier expression to the logical AND of all control signals or the logical OR of all control signals, and The initial qualifier expression evaluates to true; Starting from the end of each path, traverse forward along each edge to each element; Update the qualifier expression according to the component type.

5. The method for extracting a qualifier expression in a clock domain as claimed in claim 2, characterized in that: Updates to qualifier expressions based on component type include: When the element is a NOT gate, remove the input signal of the element from the qualifier expression; When the element is an OR gate, the input signal of the element is added to the qualifier expression through logical OR; When the element is an AND gate, the input signal of the element is added to the qualifier expression through logical AND; When the element is a MUX gate, the data input signal or control input signal of the element selected according to the value of the selection signal is added to the qualifier expression.

6. The method for extracting a qualifier expression in a clock domain according to claim 5, characterized in that: When the element is a MUX gate, if the selection signal is true, the data input signal is added to the qualifier expression through logical AND; if the selection signal is false, the control input signal is added to the qualifier expression through logical AND.

7. The method for extracting a qualifier expression in a clock domain according to any one of claims 1 to 6, characterized in that: Re-extracting the qualifier expression includes: Modify the initial qualifier expression; and / or remove the input signal of the component that caused the failure from the qualifier expression; and / or re-traverse the data path and update the qualifier expression based on the traversed data path.

8. The method for extracting a qualifier expression in a clock domain according to claim 7, characterized in that: Modifying the original qualifier expression includes removing the false control signal from the original qualifier expression.

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