Method, device, equipment and medium for generating integrated circuit synthetic scanning electron microscope images
By rounding the layout contours, adjusting the roughness, and adding noise information to generate a synthetic scanning electron microscope image of the integrated circuit, the problem of long CDSEM measurement time is solved, and efficient analysis and cost reduction are achieved without CDSEM.
Patent Information
- Application Number
- CN202411574414.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-06
- Publication Date
- 2025-09-23
- Estimated Expiration
- 2044-11-06
AI Technical Summary
Due to the long measurement time of CDSEM, it is impossible to obtain enough SEM images in a short period of time, resulting in slow progress of the research project.
By obtaining the layout parameters, determining the test image, rounding the target corners in the layout outline, adjusting the roughness, adding grayscale intensity background information and noise information, a synthetic scanning electron microscope image of the integrated circuit is generated.
The generated synthetic SEM images of integrated circuits are similar to real SEM images and can be analyzed without the need for CDSEM, speeding up research projects and reducing costs.
Smart Images
Figure CN119693492B_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor manufacturing technology, and in particular to a method, device, equipment and medium for generating a synthetic scanning electron microscope image of an integrated circuit. Background Art
[0002] After each process step in the semiconductor manufacturing production line, it is necessary to promptly use a scanning electron microscope (Critical Dimension Scanning Electron Microscope, CDSEM) for feature dimension measurement to conduct random inspections of wafer products, and judge whether the integrated circuits in the wafer products meet the requirements after the exposure, development, etching, grinding and other steps based on the obtained SEM images. If the requirements are met, the subsequent steps can be promoted. If the requirements are not met, the loss can be stopped in time. In addition, the computational lithography and yield improvement departments will also frequently use CDSEM to collect data. The computational lithography department uses the collected SEM images to establish lithography models, etching models, model verification, etc. These SEM images provide strong data support for lithography simulation verification, and the yield improvement department can propose targeted yield improvement methods by analyzing the collected SEM images.
[0003] In recent years, with the advancement of semiconductor manufacturing processes, the use of CDSEM to measure and inspect products has become increasingly important.
[0004] However, the applicant found that due to the long measurement time of CDSEM, it is impossible to obtain a large number of SEM images in a short period of time. As a result, it is difficult to obtain enough SEM images for analysis in some research projects, which slows down the progress of the research projects. Summary of the Invention
[0005] In order to solve the problems in the related art, the embodiments of the present disclosure provide a method, device, equipment and medium for generating a synthetic scanning electron microscope image of an integrated circuit.
[0006] In a first aspect, an embodiment of the present disclosure provides a method for generating a synthetic scanning electron microscope image of an integrated circuit, comprising:
[0007] Obtaining layout parameters and determining a test image according to the layout parameters, wherein the test image includes a layout matching the layout parameters;
[0008] Rounding target corners in the layout outline of the test image to obtain a rounded corner image, where the target corners are other corners in the layout outline except for the corners generated by intercepting the test image.
[0009] performing roughness adjustment on the layout outline in the rounded corner processed image to obtain a roughness adjusted image;
[0010] adding grayscale value intensity background information to the roughness-adjusted image to obtain a grayscale-adjusted image;
[0011] Noise information is added to the grayscale adjusted image to obtain a synthetic SEM image of the integrated circuit.
[0012] In one embodiment of the present disclosure, rounding a target corner in a layout outline in a test image to obtain a rounded image includes:
[0013] In the layout outline in the test image, an adjacent corner corresponding to the target corner is determined, where the adjacent corner is the corner with the smallest adjacent distance between the vertex in the layout outline and the vertex of the target corner;
[0014] If the adjacent distance is less than a preset photolithography process length threshold, the target corner is rounded using the adjacent distance as the rounding radius to obtain a rounded image;
[0015] If the adjacent distance is greater than or equal to the photolithography process length threshold, the photolithography process length threshold is used as the fillet radius to round the target corner to obtain a rounded image.
[0016] In one embodiment of the present disclosure, performing roughness adjustment on a layout outline in a rounded corner processed image to obtain a roughness adjusted image includes:
[0017] Obtain the distance r between the target pixel in the layout outline in the rounded image and the edge of the layout outline closest to the target pixel;
[0018] based on Get pixel position offset c (r) , where rms is the preset root mean square surface roughness, ξ is the preset autocorrelation length, a is the preset roughness index, and e is a natural constant;
[0019] Determine a pixel offset direction of the target pixel, where the pixel offset direction points from the pixel position of the target pixel to a projection point of the target pixel on the edge of the layout contour closest to the target pixel;
[0020] Obtaining a roughness adjustment pixel position based on a pixel position of a target pixel, a pixel position offset c(r), and a pixel offset direction;
[0021] The pixel position of the target pixel in the rounding process image is set as the roughness adjustment pixel position to obtain the roughness adjustment image.
[0022] In one embodiment of the present disclosure, adding grayscale value intensity background information to the roughness-adjusted image to obtain the grayscale-adjusted image includes:
[0023] Get the minimum distance r from the target pixel to the edge of the layout contour in the roughness adjustment image E And the preset gray value attenuation pixel step r t ;
[0024] based on Get the adjusted grayscale value C(rE), where e is a natural constant, b is the preset grayscale attenuation coefficient, and C G is the preset maximum grayscale threshold, C E is the preset minimum grayscale threshold;
[0025] The grayscale value of the target pixel in the roughness adjustment image is set to the adjustment grayscale value C(rE) to obtain a grayscale adjustment image.
[0026] In one embodiment of the present disclosure, adding noise information to a grayscale adjusted image to obtain a synthetic scanning electron microscope image of an integrated circuit includes:
[0027] based on Get the noise grayscale value C n (i, j), where (i, j) is the pixel coordinate of the target pixel in the grayscale adjusted image, C s (i, j) is the grayscale value of the target pixel in the grayscale adjustment image, Q G is the preset Gaussian noise coefficient, Q P is the preset Poisson noise coefficient, R(i,j) is a random number that conforms to the Gaussian distribution and corresponds to the target pixel;
[0028] Set the grayscale value of the target pixel in the grayscale adjustment image to the noise grayscale value C n (i,j) to obtain the integrated circuit composite SEM image.
[0029] In one embodiment of the present disclosure, the layout parameters include at least one of the parameters of the layout design minimum unit, the layout geometry category, the layout size, and the layout capture window.
[0030] In a second aspect, an embodiment of the present disclosure provides a device for generating a synthetic scanning electron microscope image of an integrated circuit, comprising:
[0031] a parameter acquisition module configured to acquire layout parameters and determine a test image according to the layout parameters, wherein the test image includes a layout matching the layout parameters;
[0032] a rounding processing module configured to round target corners in the layout outline in the test image to obtain a rounded corner processed image, wherein the target corners are other corners in the layout outline except the corners generated by intercepting the test image;
[0033] a roughness adjustment module configured to perform roughness adjustment on the layout outline in the rounded corner processed image to obtain a roughness adjusted image;
[0034] a grayscale adjustment module configured to add grayscale value intensity background information to the roughness-adjusted image to obtain a grayscale-adjusted image;
[0035] The noise adding module is configured to add noise information to the grayscale adjusted image to obtain a synthetic scanning electron microscope image of the integrated circuit.
[0036] In one embodiment of the present disclosure, the rounded corner processing module is specifically configured to:
[0037] In the layout outline in the test image, an adjacent corner corresponding to the target corner is determined, where the adjacent corner is the corner with the smallest adjacent distance between the vertex in the layout outline and the vertex of the target corner;
[0038] If the adjacent distance is less than a preset photolithography process length threshold, the target corner is rounded using the adjacent distance as the rounding radius to obtain a rounded image;
[0039] If the adjacent distance is greater than or equal to the photolithography process length threshold, the photolithography process length threshold is used as the fillet radius to round the target corner to obtain a rounded image.
[0040] In one embodiment of the present disclosure, the roughness adjustment module is specifically configured to:
[0041] Obtain the distance r between the target pixel in the layout outline in the rounded image and the edge of the layout outline closest to the target pixel;
[0042] based on Get pixel position offset c (r) , where rms is the preset root mean square surface roughness, ξ is the preset autocorrelation length, a is the preset roughness index, and e is a natural constant;
[0043] Determine a pixel offset direction of the target pixel, where the pixel offset direction points from the pixel position of the target pixel to a projection point of the target pixel on the edge of the layout contour closest to the target pixel;
[0044] Obtaining a roughness adjustment pixel position based on a pixel position of a target pixel, a pixel position offset c(r), and a pixel offset direction;
[0045] The pixel position of the target pixel in the rounding process image is set as the roughness adjustment pixel position to obtain the roughness adjustment image.
[0046] In one embodiment of the present disclosure, the grayscale adjustment module is specifically configured to:
[0047] Get the minimum distance r from the target pixel to the edge of the layout contour in the roughness adjustment image E And the preset gray value attenuation pixel step r t ;
[0048] based on Get the adjusted grayscale value C(rE), where e is a natural constant, b is the preset grayscale attenuation coefficient, and C G is the preset maximum grayscale threshold, C E is the preset minimum grayscale threshold;
[0049] The grayscale value of the target pixel in the roughness adjustment image is set to the adjustment grayscale value C(rE) to obtain a grayscale adjustment image.
[0050] In one embodiment of the present disclosure, the noise adding module is specifically configured to:
[0051] based on Get the noise grayscale value C n (i, j), where (i, j) is the pixel coordinate of the target pixel in the grayscale adjusted image, C s (i, j) is the grayscale value of the target pixel in the grayscale adjustment image, Q G is the preset Gaussian noise coefficient, Q P is the preset Poisson noise coefficient, R(i,j) is a random number that conforms to the Gaussian distribution and corresponds to the target pixel;
[0052] Set the grayscale value of the target pixel in the grayscale adjustment image to the noise grayscale value C n (i,j) to obtain the integrated circuit composite SEM image.
[0053] In one embodiment of the present disclosure, the layout parameters include at least one of the parameters of the layout design minimum unit, the layout geometry category, the layout size, and the layout capture window.
[0054] In a third aspect, an embodiment of the present disclosure provides an electronic device comprising a memory and a processor, wherein the memory is used to store one or more computer instructions, and wherein the one or more computer instructions are executed by the processor to implement a method as described in any one of the first aspects.
[0055] In a fourth aspect, an embodiment of the present disclosure provides a computer-readable storage medium having computer instructions stored thereon, which, when executed by a processor, implement the method as described in any one of the first aspects.
[0056] According to the technical solution provided by the embodiment of the present disclosure, by obtaining layout parameters and determining a test image based on the layout parameters, the target corners in the layout outline in the test image are rounded to obtain a rounded image; the roughness of the layout outline in the rounded image is adjusted to obtain a roughness-adjusted image; grayscale value intensity background information is added to the roughness-adjusted image to obtain a grayscale-adjusted image; and noise information is added to the grayscale-adjusted image to obtain a synthetic SEM image of the integrated circuit. Through the above solution, it can be ensured that the rounded corners and roughness of the layout outline in the synthetic SEM image of the integrated circuit are relatively close to the rounded corners and roughness of the layout outline in the SEM image obtained by random inspection of wafer products by CDSEM in reality, and it can also be ensured that the grayscale value intensity background and noise information of the synthetic SEM image of the integrated circuit are relatively similar to those of the real SEM image, so that the obtained synthetic SEM image of the integrated circuit is more realistic, so that some research projects can be analyzed based on the synthetic SEM image of the integrated circuit without using CDSEM, thereby accelerating the progress of the research project and reducing the cost of the research project.
[0057] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS
[0058] Other features, objectives and advantages of the present disclosure will become more apparent through the following detailed description of non-limiting embodiments in conjunction with the accompanying drawings. In the accompanying drawings:
[0059] Figure 1 A flow chart of a method for generating a synthetic SEM image of an integrated circuit according to an embodiment of the present disclosure is shown.
[0060] Figure 2 A schematic diagram illustrating a test image according to an embodiment of the present disclosure.
[0061] Figure 3 A schematic diagram illustrating a test image according to an embodiment of the present disclosure.
[0062] Figure 4 Schematic diagram showing an image with rounded corners according to an embodiment of the present disclosure
[0063] Figure 5 A schematic diagram illustrating a roughness-adjusted image according to an embodiment of the present disclosure.
[0064] Figure 6 A schematic diagram illustrating a grayscale adjusted image according to an embodiment of the present disclosure.
[0065] Figure 7 A schematic diagram illustrating a composite SEM image of an integrated circuit according to an embodiment of the present disclosure.
[0066] Figure 8 A structural block diagram of a device for generating a synthetic scanning electron microscope image of an integrated circuit according to an embodiment of the present disclosure is shown.
[0067] Figure 9 A structural block diagram of an electronic device according to an embodiment of the present disclosure is shown.
[0068] Figure 10 A schematic diagram showing the structure of a computer system suitable for implementing the method according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION
[0069] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement them. In addition, for the sake of clarity, parts not related to the description of the exemplary embodiments are omitted in the accompanying drawings.
[0070] In the present disclosure, it should be understood that terms such as "include" or "have" are intended to indicate the presence of features, numbers, steps, actions, components, parts, or combinations thereof disclosed in the present specification, and are not intended to exclude the possibility that one or more other features, numbers, steps, actions, components, parts, or combinations thereof exist or are added.
[0071] It should also be noted that, in the absence of conflict, the embodiments and features of the embodiments of the present disclosure may be combined with each other. The present disclosure will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.
[0072] In this disclosure, if it involves operations of obtaining user information or user data or displaying user information or user data to others, such operations are all authorized and confirmed by the user, or actively selected by the user.
[0073] In recent years, with the advancement of semiconductor manufacturing processes, the use of CDSEM to measure and inspect products has become increasingly important.
[0074] However, the applicant discovered that SEM images require extensive CDSEM work. Because CDSEM is expensive and takes a long time to produce, high-quality imaging significantly increases this time, making the collection of large numbers of SEM images unsustainable and impossible to obtain in a short period of time. Consequently, in some research projects, obtaining sufficient SEM images for analysis is difficult, slowing the progress of the research project.
[0075] In order to solve the above problems, the present disclosure provides a method, device, equipment and medium for generating a synthetic scanning electron microscope image of an integrated circuit.
[0076] According to the technical solution provided by the embodiment of the present disclosure, by obtaining layout parameters and determining a test image based on the layout parameters, the target corners in the layout outline in the test image are rounded to obtain a rounded image; the roughness of the layout outline in the rounded image is adjusted to obtain a roughness-adjusted image; grayscale value intensity background information is added to the roughness-adjusted image to obtain a grayscale-adjusted image; and noise information is added to the grayscale-adjusted image to obtain a synthetic SEM image of the integrated circuit. Through the above solution, it can be ensured that the rounded corners of the layout and the roughness of the layout outline in the synthetic SEM image of the integrated circuit are relatively close to the rounded corners and the roughness of the layout outline in the real SEM image obtained by random inspection of wafer products by real CDSEM, and it can also be ensured that the grayscale value intensity background and noise information of the synthetic SEM image of the integrated circuit are relatively similar to those of the real SEM image, so that the obtained synthetic SEM image of the integrated circuit is more realistic, so that some research projects can be analyzed based on the synthetic SEM image of the integrated circuit without using CDSEM, thereby accelerating the progress of the research project and reducing the cost of the research project.
[0077] Figure 1 FIG. 1 is a flow chart showing a method for generating a synthetic SEM image of an integrated circuit according to an embodiment of the present disclosure. Figure 1 As shown, the method for generating a synthetic SEM image of an integrated circuit includes the following steps S101-S105:
[0078] In step S101, layout parameters are obtained, and a test image is determined according to the layout parameters;
[0079] Wherein, the test image includes a layout matching the layout parameters;
[0080] In one embodiment of the present disclosure, the layout parameters include at least one of the parameters of the layout design minimum unit, the layout geometry category, the layout size, and the layout capture window.
[0081] The minimum unit of layout design can be understood as the smallest counting unit when designing the layout. For example, the minimum unit of layout design can be 1000dbu decibel voltage unit.
[0082] The layout geometry category can be used to indicate which type of geometry the layout outline belongs to. For example, the layout geometry category can include a rectangle, a square, a polygon surrounded only by broken lines, a shape surrounded by broken lines and curves, etc.
[0083] The size of a layout can be used to indicate the length of an edge, the curvature of an edge, the angle between edges, etc. It can also be used to indicate the size of the area where the layout is located, for example, the layout is located within a 1um*1um square.
[0084] The parameters of the layout capture window may include the magnification of the layout capture window, etc. For example, the magnification of the layout capture window is 100k.
[0085] For example, Figure 2 Schematic diagram of a test image according to an embodiment of the present disclosure is shown. Figure 2 As shown, in test image 201, test image 202 and test image 203, the layout outline 200 is a rectangle that does not include a square; in test image 204, the layout outline 200 is a square; in test image 205, test image 206 and test image 207, the layout outline 200 is a polygon surrounded by broken lines; in test image 208, the layout outline 200 is a figure surrounded by broken lines and curves.
[0086] In step S102, a target corner in the layout outline of the test image is rounded to obtain a rounded image;
[0087] The target corners are all corners in the layout outline except the corners generated by intercepting the test image;
[0088] In one embodiment of the present disclosure, all corners among the corners of the layout outline that coincide with the edge of the test image capture range can be determined as corners generated by capturing the test image, and some corners among the corners of the layout outline that coincide with the edge of the test image capture range can be randomly selected to be determined as corners generated by capturing the test image, or some corners among the corners of the layout outline that coincide with the edge of the test image capture range can be selected based on the input corner indication information to be determined as corners generated by capturing the test image.
[0089] In one embodiment of the present disclosure, rounding the target corners in the layout outline in the test image can be understood as rounding the target corners based on a preset rounding radius; it can also be understood as rounding the target corners by randomly selecting a rounding radius within a preset rounding radius range.
[0090] For example, Figure 3 A schematic diagram showing a test image according to an embodiment of the present disclosure, Figure 4 Schematic diagram showing a rounded corner image according to an embodiment of the present disclosure. Figure 3 as well as Figure 4 As shown, in the layout outline of test image 301, the target corners include corners 302 to 309. By rounding corners 302 to 309, a rounded corner processed image 401 can be obtained. In the layout outline of rounded corner processed image 401, corners 402 to 409 are rounded corners.
[0091] In step S103, the roughness of the layout outline in the rounded corner processed image is adjusted to obtain a roughness adjusted image;
[0092] In one embodiment of the present disclosure, adjusting the roughness of the layout outline in the rounded corner processed image can be understood as adjusting the positions of pixels in the layout outline so that the layout outline after the roughness adjustment appears rough and non-smooth.
[0093] For example, Figure 5 Schematic diagram showing a roughness adjustment image according to an embodiment of the present disclosure. Figure 4 as well as Figure 5 As shown, the roughness of the layout outline 400 of the rounded corner processed image 401 is adjusted to obtain a roughness adjusted image 501 . The outline of the layout outline 500 of the roughness adjusted image 501 presents a rough and non-smooth effect.
[0094] In step S104, grayscale value intensity background information is added to the roughness-adjusted image to obtain a grayscale-adjusted image;
[0095] For example, Figure 6 FIG. 1 is a schematic diagram showing a grayscale adjustment image according to an embodiment of the present disclosure. Figure 5 as well as Figure 6 As shown, by adding grayscale value intensity background information to the roughness adjusted image 501 , a grayscale adjusted image 601 can be obtained.
[0096] In step S105 , noise information is added to the grayscale adjusted image to obtain a synthetic SEM image of the integrated circuit.
[0097] In one embodiment of the present disclosure, adding noise information to the grayscale-adjusted image can be understood as adding at least one of Poisson noise and Gaussian noise to the grayscale-adjusted image. Poisson noise can be understood as noise caused by random fluctuations in the electron beam in the primary electron beam of a scanning electron microscope, i.e., electron beam shot noise, while Gaussian noise can be understood as shot noise of the microscope's electronics.
[0098] For example, Figure 7 Schematic diagram showing a composite SEM image of an integrated circuit according to an embodiment of the present disclosure. Figure 6 as well as Figure 7 As shown, by adding noise information to the grayscale adjusted image 601 , a synthetic SEM image 701 of the integrated circuit can be obtained.
[0099] According to the technical solution provided by the embodiment of the present disclosure, by obtaining layout parameters and determining a test image based on the layout parameters, the target corners in the layout outline in the test image are rounded to obtain a rounded image; the roughness of the layout outline in the rounded image is adjusted to obtain a roughness-adjusted image; grayscale value intensity background information is added to the roughness-adjusted image to obtain a grayscale-adjusted image; and noise information is added to the grayscale-adjusted image to obtain a synthetic SEM image of the integrated circuit. Through the above solution, it can be ensured that the rounded corners of the layout and the roughness of the layout outline in the synthetic SEM image of the integrated circuit are relatively close to the rounded corners and the roughness of the layout outline in the real SEM image obtained by random inspection of wafer products by real CDSEM, and it can also be ensured that the grayscale value intensity background and noise information of the synthetic SEM image of the integrated circuit are relatively similar to those of the real SEM image, so that the obtained synthetic SEM image of the integrated circuit is more realistic, so that some research projects can be analyzed based on the synthetic SEM image of the integrated circuit without using CDSEM, thereby accelerating the progress of the research project and reducing the cost of the research project.
[0100] In one embodiment of the present disclosure, rounding a target corner in a layout outline in a test image to obtain a rounded image includes:
[0101] In the layout outline in the test image, an adjacent corner corresponding to the target corner is determined, where the adjacent corner is the corner with the smallest adjacent distance between the vertex in the layout outline and the vertex of the target corner;
[0102] If the adjacent distance is less than a preset photolithography process length threshold, the target corner is rounded using the adjacent distance as the rounding radius to obtain a rounded image;
[0103] If the adjacent distance is greater than or equal to the photolithography process length threshold, the photolithography process length threshold is used as the fillet radius to round the target corner to obtain a rounded image.
[0104] According to the technical solution provided by the embodiment of the present disclosure, the adjacent corner corresponding to the target corner is determined in the layout contour in the test image, and when the adjacent distance is less than a preset lithography process length threshold, the target corner is rounded with the adjacent distance as the rounding radius, thereby ensuring that the target corner after rounding will not be distorted due to a large rounding radius; and when the adjacent distance is greater than or equal to the lithography process length threshold, the target corner is rounded with the lithography process length threshold as the rounding radius to obtain a rounded image, so that the target corner after rounding can be made closer to the corner of the layout after the actual lithography process, which helps to improve the realism of the layout contour in the integrated circuit synthetic scanning electron microscope image.
[0105] In one embodiment of the present disclosure, performing roughness adjustment on a layout outline in a rounded corner processed image to obtain a roughness adjusted image includes:
[0106] Obtain the distance r between the target pixel in the layout outline in the rounded image and the edge of the layout outline closest to the target pixel;
[0107] based on Get pixel position offset c (r) , where rms is the preset root mean square surface roughness, ξ is the preset autocorrelation length, a is the preset roughness index, and e is a natural constant;
[0108] Determine a pixel offset direction of the target pixel, where the pixel offset direction points from the pixel position of the target pixel to a projection point of the target pixel on the edge of the layout contour closest to the target pixel;
[0109] Obtaining a roughness adjustment pixel position based on a pixel position of a target pixel, a pixel position offset c(r), and a pixel offset direction;
[0110] The pixel position of the target pixel in the rounding process image is set as the roughness adjustment pixel position to obtain the roughness adjustment image.
[0111] In the above scheme, by obtaining the distance from the target pixel in the layout outline in the rounded corner processed image to the layout outline edge closest to the target pixel, and further obtaining the pixel position offset, the pixel offset direction of the target pixel is determined, and the roughness adjustment pixel position is obtained based on the pixel position, pixel position offset and pixel offset direction of the target pixel, and the pixel position of the target pixel in the rounded corner processed image is set as the roughness adjustment pixel position to obtain a roughness adjustment image. This can ensure that the roughness of the layout outline in the roughness adjustment image is closer to the roughness of the layout outline after being processed by the photolithography process in reality, which helps to improve the realism of the layout outline in the integrated circuit synthetic scanning electron microscope image.
[0112] In one embodiment of the present disclosure, adding grayscale value intensity background information to the roughness-adjusted image to obtain the grayscale-adjusted image includes:
[0113] Get the minimum distance r from the target pixel to the edge of the layout contour in the roughness adjustment image E And the preset gray value attenuation pixel step r t ;
[0114] based on Get the adjusted grayscale value C(rE), where e is a natural constant, b is the preset grayscale attenuation coefficient, and C G is the preset maximum grayscale threshold, C E is the preset minimum grayscale threshold;
[0115] The grayscale value of the target pixel in the roughness adjustment image is set to the adjustment grayscale value C(rE) to obtain a grayscale adjustment image.
[0116] In the above scheme, by obtaining the minimum distance from the target pixel to the edge of the layout contour in the roughness adjustment image and the preset grayscale value attenuation pixel step, and further obtaining the adjusted grayscale value, the grayscale value of the target pixel in the roughness adjustment image is set to the adjusted grayscale value to obtain a grayscale adjustment image. This can ensure that the grayscale of the pixel in the grayscale adjustment image is relatively close to the grayscale of the pixel in the scanning electron microscope image obtained by CDSEM random inspection of wafer products in reality, which helps to improve the realism of the synthetic scanning electron microscope image of the integrated circuit.
[0117] In one embodiment of the present disclosure, adding noise information to a grayscale adjusted image to obtain a synthetic scanning electron microscope image of an integrated circuit includes:
[0118] based on Get the noise grayscale value C n (i, j), where (i, j) is the pixel coordinate of the target pixel in the grayscale adjusted image, C s (i, j) is the grayscale value of the target pixel in the grayscale adjustment image, Q G is the preset Gaussian noise coefficient, Q P is the preset Poisson noise coefficient, R(i,j) is a random number that conforms to the Gaussian distribution and corresponds to the target pixel;
[0119] Set the grayscale value of the target pixel in the grayscale adjustment image to the noise grayscale value C n (i,j) to obtain the integrated circuit composite SEM image.
[0120] In one implementation of the present disclosure, Q G Can be preset to 10, Q P Can be preset to 42.
[0121] In the above scheme, by obtaining the noise grayscale value and setting the grayscale value of the target pixel in the grayscale adjustment image to the noise grayscale value, a synthetic scanning electron microscope image of the integrated circuit can be obtained. Poisson noise and Gaussian noise can be superimposed on the image, so that the noise in the synthetic scanning electron microscope image of the integrated circuit is closer to the noise in the scanning electron microscope image obtained by random inspection of wafer products by CDSEM in reality, thereby improving the realism of the synthetic scanning electron microscope image of the integrated circuit.
[0122] Figure 8 A structural block diagram of a device for generating a synthetic scanning electron microscope image of an integrated circuit according to an embodiment of the present disclosure is shown.
[0123] The device may be implemented as part or all of an electronic device through software, hardware, or a combination of both.
[0124] like Figure 8 As shown, the integrated circuit synthetic scanning electron microscope image generating device 800 includes:
[0125] The parameter acquisition module 801 is configured to acquire layout parameters and determine a test image according to the layout parameters, wherein the test image includes a layout that matches the layout parameters;
[0126] A corner rounding module 802 is configured to round target corners in the layout outline of the test image to obtain a corner rounding image, where the target corners are corners in the layout outline other than corners generated by intercepting the test image.
[0127] The roughness adjustment module 803 is configured to perform roughness adjustment on the layout outline in the rounded corner processed image to obtain a roughness adjusted image;
[0128] A grayscale adjustment module 804 is configured to add grayscale value intensity background information to the roughness adjusted image to obtain a grayscale adjusted image;
[0129] The noise adding module 805 is configured to add noise information to the grayscale adjusted image to obtain a synthetic SEM image of the integrated circuit.
[0130] In one embodiment of the present disclosure, the rounded corner processing module 802 is specifically configured to:
[0131] In the layout outline in the test image, an adjacent corner corresponding to the target corner is determined, where the adjacent corner is the corner with the smallest adjacent distance between the vertex in the layout outline and the vertex of the target corner;
[0132] If the adjacent distance is less than a preset photolithography process length threshold, the target corner is rounded using the adjacent distance as the rounding radius to obtain a rounded image;
[0133] If the adjacent distance is greater than or equal to the photolithography process length threshold, the photolithography process length threshold is used as the fillet radius to round the target corner to obtain a rounded image.
[0134] In one embodiment of the present disclosure, the roughness adjustment module 803 is specifically configured to:
[0135] Obtain the distance r between the target pixel in the layout outline in the rounded image and the edge of the layout outline closest to the target pixel;
[0136] based on Get pixel position offset c (r), where rms is the preset root mean square surface roughness, ξ is the preset autocorrelation length, a is the preset roughness index, and e is a natural constant;
[0137] Determine a pixel offset direction of the target pixel, where the pixel offset direction points from the pixel position of the target pixel to a projection point of the target pixel on the edge of the layout contour closest to the target pixel;
[0138] Obtaining a roughness adjustment pixel position based on a pixel position of a target pixel, a pixel position offset c(r), and a pixel offset direction;
[0139] The pixel position of the target pixel in the rounding process image is set as the roughness adjustment pixel position to obtain the roughness adjustment image.
[0140] In one embodiment of the present disclosure, the grayscale adjustment module 804 is specifically configured to:
[0141] Get the minimum distance r from the target pixel to the edge of the layout contour in the roughness adjustment image E And the preset gray value attenuation pixel step r t ;
[0142] based on Get the adjusted grayscale value C(rE), where e is a natural constant, b is the preset grayscale attenuation coefficient, and C G is the preset maximum grayscale threshold, C E is the preset minimum grayscale threshold;
[0143] The grayscale value of the target pixel in the roughness adjustment image is set to the adjustment grayscale value C(rE) to obtain a grayscale adjustment image.
[0144] In one embodiment of the present disclosure, the noise adding module 805 is specifically configured to:
[0145] based on Get the noise grayscale value C n (i, j), where (i, j) is the pixel coordinate of the target pixel in the grayscale adjusted image, C s (i, j) is the grayscale value of the target pixel in the grayscale adjustment image, Q G is the preset Gaussian noise coefficient, Q P is the preset Poisson noise coefficient, R(i,j) is a random number that conforms to the Gaussian distribution and corresponds to the target pixel;
[0146] Set the grayscale value of the target pixel in the grayscale adjustment image to the noise grayscale value C n (i,j) to obtain the integrated circuit composite SEM image.
[0147] In one embodiment of the present disclosure, the layout parameters include at least one of the parameters of the layout design minimum unit, the layout geometry category, the layout size, and the layout capture window.
[0148] According to the technical solution provided by the embodiment of the present disclosure, by obtaining layout parameters and determining a test image based on the layout parameters, the target corners in the layout outline in the test image are rounded to obtain a rounded image; the roughness of the layout outline in the rounded image is adjusted to obtain a roughness-adjusted image; grayscale value intensity background information is added to the roughness-adjusted image to obtain a grayscale-adjusted image; and noise information is added to the grayscale-adjusted image to obtain a synthetic SEM image of the integrated circuit. Through the above solution, it can be ensured that the rounded corners of the layout and the roughness of the layout outline in the synthetic SEM image of the integrated circuit are relatively close to the rounded corners and the roughness of the layout outline in the real SEM image obtained by random inspection of wafer products by real CDSEM, and it can also be ensured that the grayscale value intensity background and noise information of the synthetic SEM image of the integrated circuit are relatively similar to those of the real SEM image, so that the obtained synthetic SEM image of the integrated circuit is more realistic, so that some research projects can be analyzed based on the synthetic SEM image of the integrated circuit without using CDSEM, thereby accelerating the progress of the research project and reducing the cost of the research project.
[0149] The present disclosure also discloses an electronic device, Figure 9 A structural block diagram of an electronic device according to an embodiment of the present disclosure is shown.
[0150] like Figure 9 As shown, the electronic device includes a memory and a processor, wherein the memory is used to store one or more computer instructions, wherein the one or more computer instructions are executed by the processor to implement the method according to an embodiment of the present disclosure.
[0151] Figure 10 A schematic diagram showing the structure of a computer system suitable for implementing the method according to an embodiment of the present disclosure is shown.
[0152] like Figure 10 As shown, the computer system includes a processing unit, which can execute the various methods in the above-mentioned embodiments according to a program stored in a read-only memory (ROM) or a program loaded from a storage portion into a random access memory (RAM). In the RAM, various programs and data required for the operation of the computer system are also stored. The processing unit, ROM, and RAM are connected to each other via a bus. An input / output (I / O) interface is also connected to the bus.
[0153] The following components are connected to the I / O interface: an input part including a keyboard, a mouse, etc.; an output part including a cathode ray tube (CRT), a liquid crystal display (LCD), a speaker, etc.; a storage part including a hard disk, etc.; and a communication part including a network interface card such as a LAN card, a modem, etc. The communication part performs a communication process via a network such as the Internet. The drive is also connected to the I / O interface as needed. Removable media, such as magnetic disks, optical disks, magneto-optical disks, semiconductor memories, etc., are installed on the drive as needed so that the computer program read therefrom is installed into the storage part as needed. Among them, the processing unit can be implemented as a processing unit such as a CPU, a GPU, a TPU, an FPGA, an NPU, etc.
[0154] In particular, according to embodiments of the present disclosure, the methods described above can be implemented as computer software programs. For example, embodiments of the present disclosure include a computer program product comprising a computer program tangibly embodied on a machine-readable medium, the computer program comprising program code for executing the methods described above. In such embodiments, the computer program can be downloaded and installed from a network via a communication component and / or installed from a removable medium.
[0155] The flowcharts and block diagrams in the accompanying drawings illustrate the possible implementation architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, program segment or part of code, and the module, program segment or part of code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or can be implemented using a combination of dedicated hardware and computer instructions.
[0156] The units or modules involved in the embodiments described in this disclosure may be implemented by software or programmable hardware. The units or modules described may also be provided in a processor, and the names of these units or modules do not, in certain circumstances, constitute limitations on the units or modules themselves.
[0157] As another aspect, the present disclosure further provides a computer-readable storage medium. This computer-readable storage medium may be included in the electronic device or computer system described in the above embodiments, or may be a standalone computer-readable storage medium not incorporated into the device. The computer-readable storage medium stores one or more programs, which are used by one or more processors to execute the methods described in the present disclosure.
[0158] The above description is merely a preferred embodiment of the present disclosure and an illustration of the technical principles employed. Those skilled in the art should understand that the scope of the invention herein is not limited to the technical solutions formed by the specific combination of the above-mentioned technical features, but also encompasses other technical solutions formed by any combination of the above-mentioned technical features or their equivalents without departing from the inventive concept. For example, a technical solution formed by replacing the above-mentioned features with (but not limited to) technical features having similar functions disclosed in this disclosure.
Claims
1. A method for generating a synthetic scanning electron microscope image of an integrated circuit, characterized in that: include: Acquiring layout parameters, and determining a test image according to the layout parameters, wherein the test image includes a layout matching the layout parameters; performing rounding processing on target corners in the layout outline in the test image to obtain a rounded corner processed image, wherein the target corners are other corners in the layout outline except the corners generated by intercepting the test image; Performing roughness adjustment on the layout outline in the rounded corner processed image to obtain a roughness adjusted image; adding grayscale value intensity background information to the roughness-adjusted image to obtain a grayscale-adjusted image; adding noise information to the grayscale adjusted image to obtain a synthetic scanning electron microscope image of the integrated circuit; The step of adjusting the roughness of the layout outline in the rounded corner processed image to obtain a roughness adjusted image includes: Obtain the distance r between the target pixel in the layout outline in the rounded image and the edge of the layout outline closest to the target pixel; Based on c(r)=rms 2 *e -(r / ξ)2a r obtains the pixel position offset c(r), where rms is the preset root mean square surface roughness, ξ is the preset autocorrelation length, a is the preset roughness index, and e is a natural constant; Determining a pixel offset direction of a target pixel, where the pixel offset direction points from a pixel position of the target pixel to a projection point of the target pixel on an edge of a layout contour closest to the target pixel; Obtaining a roughness adjustment pixel position based on a pixel position of a target pixel, the pixel position offset c(r), and the pixel offset direction; The pixel position of the target pixel in the rounded corner processed image is set as the roughness adjusted pixel position to obtain a roughness adjusted image.
2. The method for generating a synthetic SEM image of an integrated circuit according to claim 1, wherein: The rounding of the target corners in the layout outline in the test image to obtain a rounded image includes: In the layout outline in the test image, determining an adjacent corner corresponding to the target corner, the adjacent corner being a corner with a minimum adjacent distance between a vertex in the layout outline and a vertex of the target corner; If the adjacent distance is less than a preset photolithography process length threshold, rounding the target corner with the adjacent distance as the rounding radius to obtain the rounded image; If the adjacent distance is greater than or equal to the photolithography process length threshold, the target corner is rounded using the photolithography process length threshold as the rounding radius to obtain the rounded image.
3. The method for generating a synthetic SEM image of an integrated circuit according to claim 1, wherein: Adding grayscale value intensity background information to the roughness-adjusted image to obtain a grayscale-adjusted image includes: Get the minimum distance r from the target pixel to the edge of the layout outline in the roughness adjustment image E And the preset gray value attenuation pixel step r t ; based on Get the adjusted grayscale value C(rE), where e is a natural constant, b is the preset grayscale attenuation coefficient, and C G is the preset maximum grayscale threshold, C E is the preset minimum grayscale threshold; The grayscale value of the target pixel in the roughness adjustment image is set as the adjustment grayscale value C(rE) to obtain the grayscale adjustment image.
4. The method for generating a synthetic SEM image of an integrated circuit according to claim 1, wherein: Adding noise information to the grayscale adjusted image to obtain a synthetic SEM image of the integrated circuit includes: based on Get the noise grayscale value C n (i, j), where (i, j) is the pixel coordinate of the target pixel in the grayscale adjusted image, C s (i, j) is the grayscale value of the target pixel in the grayscale adjustment image, Q G is the preset Gaussian noise coefficient, Q P is the preset Poisson noise coefficient, R(i,j) is a random number that conforms to the Gaussian distribution and corresponds to the target pixel; The grayscale value of the target pixel in the grayscale adjustment image is set to the noise grayscale value C n (i, j) to obtain a synthetic SEM image of the integrated circuit.
5. The method for generating a synthetic SEM image of an integrated circuit according to any one of claims 1 to 4, characterized in that: The layout parameters include at least one of the parameters of the layout design minimum unit, the layout geometric figure category, the layout size, and the layout capture window.
6. A device for generating a synthetic scanning electron microscope image of an integrated circuit, characterized in that: include: a parameter acquisition module configured to acquire layout parameters and determine a test image according to the layout parameters, wherein the test image includes a layout matching the layout parameters; a rounding processing module configured to round target corners in the layout outline in the test image to obtain a rounded corner processed image, wherein the target corners are other corners in the layout outline except the corners generated by intercepting the test image; a roughness adjustment module configured to perform roughness adjustment on the layout outline in the rounded corner processed image to obtain a roughness adjusted image; a grayscale adjustment module configured to add grayscale value intensity background information to the roughness-adjusted image to obtain a grayscale-adjusted image; a noise adding module configured to add noise information to the grayscale adjusted image to obtain a synthetic SEM image of the integrated circuit; The roughness adjustment module is specifically configured as follows: Obtain the distance r between the target pixel in the layout outline in the rounded image and the edge of the layout outline closest to the target pixel; Based on c(r)=rms 2 *e -(r / ξ)2a r obtains the pixel position offset c(r), where rms is the preset root mean square surface roughness, ξ is the preset autocorrelation length, a is the preset roughness index, and e is a natural constant; Determining a pixel offset direction of a target pixel, where the pixel offset direction points from a pixel position of the target pixel to a projection point of the target pixel on an edge of a layout contour closest to the target pixel; Obtaining a roughness adjustment pixel position based on a pixel position of a target pixel, the pixel position offset c(r), and the pixel offset direction; The pixel position of the target pixel in the rounded corner processed image is set as the roughness adjusted pixel position to obtain a roughness adjusted image.
7. The integrated circuit synthetic scanning electron microscope image generating device according to claim 6, characterized in that: The rounded corner processing module is specifically configured as follows: In the layout outline in the test image, determining an adjacent corner corresponding to the target corner, the adjacent corner being a corner with a minimum adjacent distance between a vertex in the layout outline and a vertex of the target corner; If the adjacent distance is less than a preset photolithography process length threshold, rounding the target corner with the adjacent distance as the rounding radius to obtain the rounded image; If the adjacent distance is greater than or equal to the photolithography process length threshold, the target corner is rounded using the photolithography process length threshold as the rounding radius to obtain the rounded image.
8. The integrated circuit synthetic scanning electron microscope image generating device according to claim 6, characterized in that: The grayscale adjustment module is specifically configured to: Get the minimum distance r from the target pixel to the edge of the layout outline in the roughness adjustment image E And the preset gray value attenuation pixel step r t ; based on Get the adjusted grayscale value C(rE), where e is a natural constant, b is the preset grayscale attenuation coefficient, and C G is the preset maximum grayscale threshold, C E is the preset minimum grayscale threshold; The grayscale value of the target pixel in the roughness adjustment image is set as the adjustment grayscale value C(rE) to obtain the grayscale adjustment image.
9. The integrated circuit synthetic scanning electron microscope image generating device according to claim 6, characterized in that: The noise adding module is specifically configured as follows: based on Get the noise grayscale value C n (i, j), where (i, j) is the pixel coordinate of the target pixel in the grayscale adjusted image, C s (i, j) is the grayscale value of the target pixel in the grayscale adjustment image, Q G is the preset Gaussian noise coefficient, Q P is the preset Poisson noise coefficient, R(i,j) is a random number that conforms to the Gaussian distribution and corresponds to the target pixel; The grayscale value of the target pixel in the grayscale adjustment image is set to the noise grayscale value C n (i, j) to obtain a synthetic SEM image of the integrated circuit.
10. The integrated circuit synthetic scanning electron microscope image generating device according to any one of claims 6 to 9, characterized in that: The layout parameters include at least one of the parameters of the layout design minimum unit, the layout geometric figure category, the layout size, and the layout capture window.
11. An electronic device, characterized in that: The method comprises a memory and a processor; wherein the memory is used to store one or more computer instructions, wherein the one or more computer instructions are executed by the processor to implement the method steps according to any one of claims 1 to 5.
12. A computer-readable storage medium having computer instructions stored thereon, characterized in that: When the computer instructions are executed by a processor, the method steps according to any one of claims 1 to 5 are implemented.
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