Display device, driving controller, and driving method of display device

Abstract

The invention relates to a display device, a driving controller, and a driving method of the display device. The display device includes a display panel including a plurality of pixels and displaying an image corresponding to each of a plurality of frames, and a driving controller receiving an image signal and driving the plurality of frames at a plurality of driving frequencies. The drive controller includes a representative frequency calculator, a compensation signal calculator, and a data compensation unit that receives an image signal and outputs a compensation data signal by adding a gradation of the image signal and a gradation value based on a data correction lookup table storing the gradation value. The brightness of the image is controlled based on the compensation signal and the compensation data signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and all benefits derived from Korean Patent Application No. 10-2023-0127019, filed on September 22, 2023, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present invention relates to a display device, and more particularly, to a display device having improved display quality, a driving controller, and a driving method of the display device. Background Art

[0004] Various electronic devices such as televisions, mobile phones, tablet computers, navigation systems, and game consoles are being developed. In particular, since portable display devices are operated by using batteries, various technologies for reducing power consumption are being developed.

[0005] Techniques for reducing power consumption include techniques for reducing the driving frequency of a display device. For example, in a specific operating environment in which a still image is displayed, the power consumption of the display device can be reduced by reducing the driving frequency. Summary of the invention

[0006] Embodiments of the present invention provide a display device having improved display quality, a driving controller, and a driving method of the display device.

[0007] According to an embodiment, a display device may include a display panel including a plurality of pixels and displaying an image corresponding to each of a plurality of frames, and a drive controller receiving an image signal and driving the plurality of frames at a plurality of drive frequencies. The drive controller may include: a representative frequency calculator outputting a representative frequency based on n drive frequencies of n frames before one of the plurality of frames; a compensation signal calculator outputting a compensation signal based on the representative frequency and the count number in the one frame; and a data compensation unit receiving the image signal and outputting a compensation data signal by adding the grayscale of the image signal and the grayscale value based on a data correction lookup table storing grayscale values, and may control the brightness of the image based on the compensation signal and the compensation data signal.

[0008] In an embodiment, a grayscale value of the grayscale of the image signal according to the representative frequency may be stored in the data correction lookup table.

[0009] In an embodiment, a grayscale value according to the grayscale of the image signal and a previous driving frequency of a frame before one of the plurality of frames may be stored in the data correction lookup table.

[0010] In an embodiment, when the previous driving frequency has a first frequency, the gray value may have a first gray value, and the compensation data signal may be output based on the first gray value. When the previous driving frequency has a second frequency higher than the first frequency, the gray value may have a second gray value, and the compensation data signal may be output based on the second gray value. The second gray value may be less than the first gray value.

[0011] In an embodiment, the data correction lookup table may be provided in plurality, and the plurality of data correction lookup tables may be provided according to a brightness value of the image signal.

[0012] In an embodiment, when the grayscale of the image signal is a grayscale that is not stored in the data correction lookup table, the data compensation unit may calculate the grayscale value by using an interpolation method.

[0013] In an embodiment, the representative frequency may be calculated based on a synchronization signal defining a start of each of the plurality of frames and a count signal obtained by counting the plurality of frames at a given cycle, and the count number may be output based on the count signal.

[0014] In an embodiment, the representative frequency calculator may include a plurality of shift registers receiving the synchronization signal and the counting signal, the plurality of shift registers may be electrically connected in series, and when one shift register among the plurality of shift registers receives the counting signal, the one shift register may transmit an output value to another shift register among the plurality of shift registers connected to the one shift register.

[0015] In an embodiment, the representative frequency may be calculated by multiplying the output values ​​of the shift registers by different weights in a one-to-one correspondence.

[0016] In an embodiment, the display device may further include a voltage generator which receives the compensation signal, generates a voltage whose voltage level is adjusted based on the compensation signal, and provides the voltage to each of the plurality of pixels.

[0017] In an embodiment, as the count number increases, the voltage level of the voltage may increase.

[0018] In an embodiment, when the driving frequency has a first frequency, the voltage may have a first voltage level, and when the driving frequency has a second frequency lower than the first frequency, the voltage may have a second voltage level higher than the first voltage level.

[0019] In an embodiment, the display device may further include a driving circuit that receives the compensation signal, generates an emission signal whose pulse width is adjusted according to the compensation signal, and provides the emission signal to each of the plurality of pixels.

[0020] In an embodiment, as the count number increases, the width of the pulse width may become narrower.

[0021] In an embodiment, the driving controller may further include a memory storing the data correction lookup table.

[0022] According to an embodiment, a drive controller may include a representative frequency calculator, a compensation signal calculator, and a data compensation unit. The drive controller may receive an image signal corresponding to each of a plurality of frames, each of which is driven at a driving frequency. The representative frequency calculator may output a representative frequency based on n driving frequencies of n frames before one of the plurality of frames. The compensation signal calculator may output a compensation signal based on the representative frequency and the number of counts in the one frame. Based on a data correction lookup table storing a grayscale value according to the grayscale of the image signal, the data compensation unit may add the grayscale of the image signal and the grayscale value to output a compensation data signal.

[0023] In an embodiment, a grayscale value of the grayscale of the image signal according to the representative frequency may be stored in the data correction lookup table.

[0024] In an embodiment, a grayscale value according to the grayscale of the image signal and a previous driving frequency of a frame before one of the plurality of frames may be stored in the data correction lookup table.

[0025] In an embodiment, when the previous driving frequency has a first frequency, the gray value may have a first gray value, and the compensation data signal may be output based on the first gray value. When the previous driving frequency has a second frequency higher than the first frequency, the gray value may have a second gray value, and the compensation data signal may be output based on the second gray value. The second gray value may be less than the first gray value.

[0026] In an embodiment, the drive controller may further include a memory configured to store the data correction lookup table.

[0027] According to an embodiment, a driving method of a display device (the display device displays an image based on an image signal corresponding to each of a plurality of frames) may include: outputting a representative frequency based on n driving frequencies of n frames before one of the plurality of frames; outputting a compensation signal based on the representative frequency and the count number in the one frame; and outputting a compensation data signal obtained by adding the grayscale of the image signal and the grayscale value of the grayscale of the image signal based on a data correction lookup table storing a grayscale value according to the grayscale of the image signal, wherein the brightness of the image can be controlled based on the compensation signal and the compensation data signal.

[0028] In an embodiment, a grayscale value of the grayscale of the image signal according to the representative frequency may be stored in the data correction lookup table.

[0029] In an embodiment, a grayscale value according to the grayscale of the image signal and a previous driving frequency of a frame before the one frame among the plurality of frames may be stored in the data correction lookup table.

[0030] In an embodiment, the output of the compensation data signal may include: when the previous driving frequency has a first frequency, outputting the compensation data signal based on a first grayscale value; when the previous driving frequency has a second frequency higher than the first frequency, outputting the compensation data signal based on a second grayscale value that the grayscale value has and is less than the first grayscale value.

[0031] In an embodiment, the driving method may further include: receiving the compensation signal; and adjusting a voltage level of a voltage to be supplied to each of the plurality of pixels based on the compensation signal.

[0032] In an embodiment, as the count number increases, the voltage level of the voltage may increase.

[0033] In an embodiment, the driving method may further include: receiving the compensation signal; and adjusting a pulse width of an emission signal to be provided to each of the plurality of pixels based on the compensation signal.

[0034] In an embodiment, as the count number increases, the width of the pulse width may become narrower. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The above and other objects and features of the present disclosure will become apparent by describing embodiments of the present disclosure in detail with reference to the accompanying drawings.

[0036] Figure 1 is a perspective view showing a display device according to an embodiment.

[0037] Figure 2 is a block diagram of a display device according to an embodiment.

[0038] Figure 3 is an equivalent circuit diagram of a pixel according to the embodiment.

[0039] Figure 4A is a timing diagram of a driving signal for driving a pixel according to an embodiment.

[0040] Figure 4B is a timing diagram of a driving signal for driving a pixel according to an embodiment.

[0041] Figure 5 is a block diagram showing a driving controller according to an embodiment.

[0042] Figure 6 is a flowchart illustrating a driving method of a display device according to an embodiment.

[0043] Figure 7 is a block diagram showing a driving controller according to an embodiment.

[0044] Figure 8 is a block diagram illustrating a representative frequency calculator according to an embodiment.

[0045] Fig. 9 is a block diagram illustrating the operation of a representative frequency calculator according to an embodiment.

[0046] Fig.10 is a bar graph showing frequency weight coefficients according to an embodiment.

[0047] Fig.11 is a block diagram illustrating a compensation signal calculator according to an embodiment.

[0048] Fig.12 is a block diagram illustrating a data compensation unit according to an embodiment.

[0049] Fig.13 is a block diagram illustrating a process of driving a display device according to an embodiment.

[0050] Fig.14A is a graph showing the G value for each grayscale according to the embodiment.

[0051] Fig. 14B is a graph showing JEITA values ​​measured for each grayscale in a low frequency period according to an embodiment.

[0052] Fig. 14C is a graph showing a JEITA value for each grayscale measured when a frequency is converted from a high frequency to a low frequency according to an embodiment.

[0053] Fig.15is a timing diagram showing how to drive the second initialization voltage according to an embodiment.

[0054] Fig.16 is a timing diagram showing how to drive a transmit signal according to an embodiment. DETAILED DESCRIPTION

[0055] In the specification, the statement that a first component (or region, layer, part or portion) is "on", "connected to" or "coupled to" a second component means that the first component is directly on / directly connected to / directly coupled to the second component, or that a third component is between the first component and the second component.

[0056] The same reference numerals refer to the same components. In addition, in the drawings, the thickness, proportion and size of the components are exaggerated in order to effectively describe the present invention. The term "and / or" includes one or more combinations, and related elements are defined in each of the combinations.

[0057] Although terms such as "first", "second", etc. may be used to describe various components, these components should not be interpreted as being limited by these terms. These terms are only used to distinguish one component from another component. For example, a first component may be referred to as a "second component" without departing from the scope and spirit of the present invention, and similarly, a second component may be referred to as a "first component". The articles "a", "an", and "the" are singular because they have a single referent, but the use of the singular form in the specification should not exclude the presence of more than one referent.

[0058] In addition, the terms "below", "beneath", "on", and "above" and the like are used to describe the relevance of components shown in the drawings. These relative conceptual terms are described based on the directions shown in the drawings. As shown in the drawings, the expressions "below", "under", "down", and "above" as spatially relative terms can be used to easily describe the relevance of one element or component to another element or component. Spatially relative terms should be understood as terms that include different directions of an element during its operation in addition to the directions shown in the drawings. Throughout the specification, the same reference numerals represent the same components.

[0059] The embodiments described in the specification will be described with reference to views that are ideal schematic diagrams of the present invention. Therefore, the form of the exemplary views can be modified according to manufacturing technology and / or allowed errors. Therefore, embodiments of the present invention are not limited to the specific forms shown, but include changes in shapes formed according to manufacturing processes. Therefore, the regions illustrated in the drawings have schematic properties, and the shapes of the regions illustrated in the drawings are provided to illustrate specific shapes of the regions and are not intended to limit the scope of the present invention.

[0060] The expression that an element or layer is "on", "connected to" or "coupled to" another element or layer means not only that the element or layer is directly on another element or layer, but also that a third layer or element may be interposed therebetween. Meanwhile, the expression that an element is "directly on" another element means that there is no third element or layer interposed therebetween. The expression "and / or" includes each of the items and all combinations of one or more items.

[0061] It will also be understood that the terms “comprises,” “including,” and “having” indicate the presence of the stated features, numbers, steps, operations, elements, components, or combinations thereof, but do not exclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, or combinations thereof.

[0062] Unless otherwise defined, all terms (including technical terms and scientific terms) used in this specification have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. In addition, unless explicitly defined herein, terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with the meaning in the context of the relevant technology, and should not be interpreted in an idealized or overly formalized meaning.

[0063] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

[0064] Figure 1 is a perspective view of a display device according to an embodiment.

[0065] In the examples and with reference to Figure 1 , the display device DD may have a shape in which a short side (or edge) extends in a first direction DR1 and a long side (or edge) extends in a second direction DR2 intersecting the first direction DR1. However, the shape of the display device DD is not limited thereto. For example, the display device DD may be implemented in various shapes.

[0066] In an embodiment, the display device DD may be a small or medium-sized electronic device such as a mobile phone, a tablet computer, a car navigation system, or a game console, as well as a large electronic device such as a television or a monitor. The above examples are provided only as embodiments, and the display device DD can be applied to any other electronic device without departing from the scope and spirit of the present invention.

[0067] In an embodiment, Figure 1As shown in FIG. 1 , the display device DD may display an image IM in a display surface FS oriented parallel to each of the first direction DR1 and the second direction DR2 so as to face a third direction DR3 intersecting the first direction DR1 and the second direction DR2. The display surface FS in which the image IM is displayed may correspond to a front surface of the display device DD.

[0068] In an embodiment, the display surface FS of the display device DD may be divided into a plurality of regions. A display area DA and a non-display area NDA may be defined in the display surface FS of the display device DD.

[0069] In an embodiment, the display area DA may be an area where an image IM is displayed, and a user may visually perceive the image IM via the display area DA. The shape of the display area DA may be substantially defined by the non-display area NDA. However, the above definition is provided as an example, and the non-display area NDA may be provided adjacent to only one side of the display area DA or may be omitted. The display device DD may include various embodiments and is not limited to any one embodiment.

[0070] In an embodiment, the non-display area NDA, which is an area adjacent to the display area DA, may be an area where the image IM is not displayed. A bezel area of ​​the display device DD may be defined by the non-display area NDA.

[0071] In an embodiment, the non-display area NDA may surround the display area DA. However, this is shown as an example. The non-display area NDA may be disposed adjacent to only a portion of a boundary of the display area DA, or may be omitted.

[0072] Figure 2 is a block diagram of a display device according to an embodiment.

[0073] In the examples and with reference to Figure 2 , the display device DD includes a main processor 10 , a display panel DP, a driving controller 100 , a data driving circuit 200 and a voltage generator 300 .

[0074] In an embodiment, the main processor 10 may be a graphics processing unit (GPU). The main processor 10 may provide the image signal RGB and the control signal CTRL to the driving controller 100. The main processor 10 may control the display operation of the display panel DP via the image signal RGB and the control signal CTRL.

[0075] In an embodiment, the display panel DP may display an image IM corresponding to each of a plurality of frames (refer to Figure 1). The display panel DP according to the embodiment may be a light-emitting display panel, but is not limited thereto. In an embodiment, the display panel DP may be an organic light-emitting display panel, a quantum dot light-emitting display panel, a micro light-emitting diode (LED) display panel, or a nano-LED display panel. The light-emitting layer of the organic light-emitting display panel may include an organic light-emitting material. The light-emitting layer of the quantum dot light-emitting display panel may include quantum dots or quantum rods, etc. The light-emitting layer of the micro-LED display panel may include micro-LEDs. The light-emitting layer of the nano-LED display panel may include nano-LEDs.

[0076] In an embodiment, the driving controller 100 may drive a plurality of frames at a plurality of driving frequencies. The driving controller 100 may receive an image signal RGB and a control signal CTRL. The driving controller 100 may generate a compensation data signal CDT by converting the data format of the image signal RGB to conform to the specification of the interface of the data driving circuit 200 and compensating the image signal RGB in the converted data format. The driving controller 100 may output a scanning control signal SCS, a data control signal DCS, an emission driving control signal ECS, a voltage control signal VCS, and a compensation signal CI.

[0077] In an embodiment, the data driving circuit 200 may receive the data control signal DCS and the compensation data signal CDT from the driving controller 100. The data driving circuit 200 may convert the compensation data signal CDT into a data voltage Vdata (refer to Figure 3 ), and the data voltage Vdata (refer to Figure 3 ) is output to each of the plurality of data lines DL1 to DLm. m is a positive integer. The data voltage Vdata (refer to Figure 3 ) may be an analog voltage corresponding to the grayscale value of the compensation data signal CDT.

[0078] In the embodiment, during the driving interval "A" (refer to Figure 4A ) period, the data driving circuit 200 may generate a data voltage Vdata (refer to Figure 3 ) is output to each of the data lines DL1 to DLm.

[0079] In an embodiment, the voltage generator 300 may receive a voltage control signal VCS and a compensation signal CI from the driving controller 100. The voltage generator 300 may generate a voltage required for the operation of the display panel DP based on the voltage control signal VCS and the compensation signal CI. The voltage generator 300 may provide a voltage to the display panel DP. In an embodiment, the voltage may include a first driving voltage ELVDD, a second driving voltage ELVSS, a first initialization voltage Vinit, a second initialization voltage Vainit, and a reference voltage Vbias.

[0080] In an embodiment, the voltage level of the first initialization voltage Vinit may be higher than the voltage level of the second initialization voltage Vainit. However, this is merely an example, and the voltage levels of the first initialization voltage Vinit and the second initialization voltage Vainit are not limited thereto. For example, the first initialization voltage Vinit may have the same voltage level as the second initialization voltage Vainit.

[0081] In an embodiment, the display panel DP may include scan lines GIL1 to GILn, GCL1 to GCLn, GWL1 to GWLn and EBL1 to EBLn, emission control lines EML11 to EML1n and EML21 to EML2n, data lines DL1 to DLm and pixels PX. n is a positive integer. The display panel DP may further include a scan driving circuit SD and an emission driving circuit EDC.

[0082] In an embodiment, the scan driving circuit SD may be disposed at a first side of the display panel DP. The scan lines GIL1 to GILn, GCL1 to GCLn, GWL1 to GWLn, and EBL1 to EBLn may extend from the scan driving circuit SD in a first direction DR1.

[0083] In an embodiment, the emission driving circuit EDC may be disposed at the second side of the display panel DP. The emission control lines EML11 to EML1n and EML21 to EML2n may extend from the emission driving circuit EDC in a direction away from the first direction DR1.

[0084] In an embodiment, the scan lines GIL1 to GILn, GCL1 to GCLn, GWL1 to GWLn, and EBL1 to EBLn and the emission control lines EML11 to EML1n and EML21 to EML2n may be arranged to be spaced apart from each other in the second direction DR2.

[0085] In an embodiment, the data lines DL1 to DLm may extend in a direction away from the second direction DR2 from the data driving circuit 200. The data lines DL1 to DLm may be arranged to be spaced apart from each other in the first direction DR1.

[0086] exist Figure 2 In the embodiment shown in , the scan drive circuit SD and the emission drive circuit EDC are arranged to face each other with the pixel PX interposed therebetween, but the present invention is not limited thereto. For example, the scan drive circuit SD and the emission drive circuit EDC may be arranged adjacent to each other on the first side or the second side of the display panel DP. In an embodiment, the scan drive circuit SD and the emission drive circuit EDC may be implemented with one circuit.

[0087] In an embodiment, a plurality of pixels PX may be electrically connected to scan lines GIL1 to GILn, GCL1 to GCLn, GWL1 to GWLn and EBL1 to EBLn, emission control lines EML11 to EML1n and EML21 to EML2n, and data lines DL1 to DLm. Each of the plurality of pixels PX may be electrically connected to four scan lines and two emission control lines. However, this is an example, and the number of lines connected to each of the plurality of pixels PX is not limited thereto.

[0088] In embodiments, the scan lines GIL1 to GILn, GCL1 to GCLn, GWL1 to GWLn, and EBL1 to EBLn may include initialization scan lines GIL1 to GILn, compensation scan lines GCL1 to GCLn, scan signal lines GWL1 to GWLn, and emission initialization scan lines EBL1 to EBLn.

[0089] In an embodiment, the emission control lines EML11 to EML1n and EML21 to EML2n may include first emission control lines EML11 to EML1n and second emission control lines EML21 to EML2n.

[0090] In an embodiment, each of the plurality of pixels PX may include a light emitting diode ED (refer to Figure 3 ) and a pixel circuit unit. The pixel circuit unit can control the light emitting diode ED (refer to Figure 3 ) launch.

[0091] In the embodiment, the light emitting diodes ED of the plurality of pixels PX (see Figure 3 ) can generate light of different colors. For example, the pixel PX may include a red pixel that generates red light, a green pixel that generates green light, and a blue pixel that generates blue light. The light-emitting diode of the red pixel, the light-emitting diode of the green pixel, and the light-emitting diode of the blue pixel may include light-emitting layers of different materials.

[0092] In an embodiment, the pixel circuit unit may include at least one transistor and at least one capacitor. This will be described later. The scan drive circuit SD and the emission drive circuit EDC may include transistors formed through the same process as the transistors of the pixel circuit unit.

[0093] In an embodiment, each of the plurality of pixels PX may receive a first driving voltage ELVDD, a second driving voltage ELVSS, a first initialization voltage Vinit, a second initialization voltage Vainit, and a reference voltage Vbias from the voltage generator 300 .

[0094] In an embodiment, the scan driving circuit SD may receive a scan control signal SCS from the driving controller 100. The scan driving circuit SD may output scan signals to the scan lines GIL1 to GILn, GCL1 to GCLn, GWL1 to GWLn, and EBL1 to EBLn in response to the scan control signal SCS.

[0095] In an embodiment, the emission driving circuit EDC may output emission signals to the emission control lines EML11 to EML1 n and EML21 to EML2 n in response to the emission driving control signal ECS from the driving controller 100 .

[0096] In an embodiment, the driving controller 100 may determine a driving frequency, and may control the data driving circuit 200 , the scan driving circuit SD, and the emission driving circuit EDC based on the determined driving frequency.

[0097] Figure 3 is an equivalent circuit diagram of a pixel according to an embodiment. Figure 3 In the description of Figure 2 The described components are labeled by like reference numerals / symbols, and thus, additional descriptions will be omitted to avoid redundancy.

[0098] In the examples and with reference to Figure 3 , the pixel PX may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a ninth transistor T9, respectively, including capacitors C1 and C2 and a light emitting diode ED. The pixel PX according to the embodiment may be referred to as having a 9T2C structure. However, this is an example, and the circuit configuration of the pixel PX according to the embodiment may be provided differently without being limited thereto. For example, the pixel PX may have a 10T2C structure.

[0099] In an embodiment, each of the first to ninth transistors T1 to T9 may be a P-type transistor having a low temperature polycrystalline silicon (LTPS) semiconductor layer. However, this is an example. In an embodiment, at least one of the first to ninth transistors T1 to T9 may be a P-type transistor, and the other transistors of the first to ninth transistors T1 to T9 may be an N-type transistor having an oxide semiconductor as a semiconductor layer.

[0100] In an embodiment, the scan lines GIL, GCL, GWL and EBL may transmit scan signals GI, GC, GW and EB, respectively. The scan lines GIL, GCL, GWL and EBL may include an initialization scan line GIL, a compensation scan line GCL, a scan signal line GWL and an emission initialization scan line EBL, respectively. The initialization scan line GIL may be initialization scan lines GIL1 to GILn (refer to Figure 2 The compensation scan line GCL may be one of the compensation scan lines GCL1 to GCLn (refer to Figure 2 ) The scanning signal line GWL may be one of the scanning signal lines GWL1 to GWLn (refer to Figure 2 ). The emission initialization scan line EBL may be one of the emission initialization scan lines EBL1 to EBLn (refer to Figure 2 )

[0101] In an embodiment, the emission control lines EML1 and EML2 may transmit emission signals EM1 and EM2, respectively. The emission control lines EML1 and EML2 may include first emission control lines EML1 and second emission control lines EML2, respectively. The first emission control line EML1 may be first emission control lines EML11 to EML1n (refer to Figure 2 ). The second emission control line EML2 may be one of the second emission control lines EML21 to EML2n (refer to Figure 2 )

[0102] In an embodiment, the data line DL may transmit a data voltage Vdata. The data voltage Vdata may have a value corresponding to the voltage input to the display device DD (refer to Figure 1 ) of the image signal RGB (refer to Figure 2 ). The first voltage line PL1 may transmit a first driving voltage ELVDD. The second voltage line PL2 may transmit a second driving voltage ELVSS. The voltage level of the first driving voltage ELVDD may be higher than the voltage level of the second driving voltage ELVSS. The first initialization voltage line VIL1 may transmit a first initialization voltage Vinit. The second initialization voltage line VIL2 may transmit a second initialization voltage Vainit. The reference voltage line VBL may transmit a reference voltage Vbias.

[0103] In an embodiment, the first capacitor C1 may be connected between the first voltage line PL1 and the first node N1.

[0104] In an embodiment, the second capacitor C2 may be connected between the first node N1 and the second node N2.

[0105] In an embodiment, the light emitting diode ED may include a first electrode electrically connected to the first voltage line PL1 via the first transistor T1, the sixth transistor T6 and the ninth transistor T9 and a second electrode connected to the second voltage line PL2. The first electrode of the light emitting diode ED may be referred to as an "anode electrode".

[0106] In an embodiment, the first transistor T1 may include a first electrode electrically connected to the first voltage line PL1 via a ninth transistor T9, a second electrode electrically connected to the first electrode of the light emitting diode ED via a sixth transistor T6, and a gate electrode connected to the second node N2. The first transistor T1 may be referred to as a "driving transistor".

[0107] In an embodiment, the second transistor T2 may include a first electrode electrically connected to the data line DL, a second electrode electrically connected to the first node N1, and a gate electrode receiving the first scan signal GW. The second transistor T2 may be referred to as a "switching transistor".

[0108] In an embodiment, the third transistor T3 may include a first electrode connected to the second node N2, a second electrode electrically connected to the second electrode of the first transistor T1, and a gate electrode receiving the compensation scan signal GC.

[0109] In an embodiment, the fourth transistor T4 may include a first electrode electrically connected to the second node N2, a second electrode electrically connected to the second initialization voltage line VIL2, and a gate electrode receiving the initialization scan signal GI.

[0110] In an embodiment, the fifth transistor T5 may include a first electrode electrically connected to the first node N1, a second electrode electrically connected to the first initialization voltage line VIL1, and a gate electrode receiving the compensation scan signal GC.

[0111] In an embodiment, the sixth transistor T6 may include a first electrode connected to the second electrode of the first transistor T1 , a second electrode connected to the first electrode of the light emitting diode ED, and a gate electrode receiving the second emission signal EM2 .

[0112] In an embodiment, the seventh transistor T7 may include a first electrode connected to the second initialization voltage line VIL2, a second electrode connected to each of the first electrode of the light emitting diode ED and the second electrode of the sixth transistor T6, and a gate electrode receiving the second scan signal EB. A voltage level of the second initialization voltage Vainit provided from the second initialization voltage line VIL2 may be lower than a voltage level of the first initialization voltage Vinit.

[0113] In an embodiment, the eighth transistor T8 may include a first electrode connected to each of the first electrode of the first transistor T1 and the second electrode of the ninth transistor T9 , a second electrode connected to the reference voltage line VBL, and a gate electrode receiving the second scan signal EB.

[0114] In an embodiment, according to the hysteresis characteristic of the first transistor T1, the driving current of the first transistor T1 determined by the data voltage Vdata applied in the current frame may be affected by the data voltage Vdata applied in the previous frame. However, when the reference voltage Vbias is applied to the first electrode of the first transistor T1 via the eighth transistor T8, the brightness deviation caused by the hysteresis characteristic of the first transistor T1 can be controlled. Therefore, when the display device DD (reference voltage Vbias) is Figure 1 ) displays the image IM (refer to Figure 1 ), a phenomenon such as flickering can be controlled. This may refer to providing a display device DD with improved display quality (refer to Figure 1 ).

[0115] In an embodiment, the ninth transistor T9 may include a first electrode connected to the first voltage line PL1 , a second electrode connected to the first electrode of the first transistor T1 , and a gate electrode receiving the first emission signal EM1 .

[0116] Figure 4A and Figure 4B is a timing diagram of a driving signal for driving a pixel according to an embodiment. Figure 4A An example in which the driving frequency is 120 Hz (Hertz) is shown, and Figure 4B An example in which the driving frequency is 48 Hz is shown.

[0117] In the examples and with reference to Figures 2 to 4B , the driving controller 100 may support a variable frequency mode. The main processor 10 may provide the image signal RGB at a variable frame rate per frame. The driving controller 100 supporting the variable frequency mode may provide the compensation data signal CDT to the data driving circuit 200 in synchronization with the variable frame rate, and may allow the image IM to be displayed at a variable frame rate (refer to Figure 1 ).

[0118] In an embodiment, the scan driving circuit SD may drive a plurality of frames at a plurality of driving frequencies, respectively. When the scan signal output from the scan driving circuit SD is input to each pixel PX, the light emitting diode ED of each pixel PX may emit light, in which case the frequency at which the compensation data signal CDT is written may be referred to as a "driving frequency".

[0119] In an embodiment, the display panel DP may display an image IM in each frame period (refer to Figure 1). One frame period (marked as "1 frame" in the drawings) may include a driving interval "A" and at least one scanning interval "B". Each of the driving interval "A" and the scanning interval "B" may correspond to a period of about 2.1ms (milliseconds). Each of the driving interval "A" and the scanning interval "B" may have a frequency of about 480Hz. However, this is an example, and the period of each of the driving interval "A" and the scanning interval "B" is not limited thereto. For example, each of the driving interval "A" and the scanning interval "B" may correspond to a period of about 4.2ms.

[0120] In an embodiment, during the driving interval 'A', the scan signal lines GWL1 to GWLn, the compensation scan lines GCL1 to GCLn, the initialization scan lines GIL1 to GILn, the emission control lines EML11 to EML1n and EML21 to EML2n, and the emission initialization scan lines EBL1 to EBLn may be sequentially scanned.

[0121] In an embodiment, each of the scanning signals GI, GC, GW and EB and the emission signal EM may have a high level during a given period, and may have a low level during a given period. In an embodiment, when the relevant signal has a low level, the P-type transistor is turned on. In an embodiment of the present disclosure, a description will be given below when the first transistor T1 to the ninth transistor T9 included in the pixel PX are P-type transistors. The period in which the emission signal EM is at a high level may be referred to as a "non-emission period", and the period in which the emission signal EM is at a low level may be referred to as an "emission period".

[0122] In an embodiment, the transmission signal EM may be a first transmission signal EM1 (see Figure 3 ) and the second transmission signal EM2 (reference Figure 3 ).

[0123] In the examples and with reference to Figure 4A When the main processor 10 generates a frame whose scanning rate is 120 Hz, the scanning driving circuit SD and the emission driving circuit EDC may be controlled so that one driving interval "A" and three scanning intervals "B" are included in one frame. In this embodiment, the display panel DP may operate at a driving frequency of 120 Hz.

[0124] In the examples and with reference to Figure 4B When the main processor 10 generates a frame whose scanning rate is 48 Hz, the scanning driving circuit SD and the emission driving circuit EDC may be controlled so that one driving interval "A" and nine scanning intervals "B" are included in one frame. In this embodiment, the display panel DP may operate at a driving frequency of 48 Hz.

[0125] However, this is an example, and the operation of the display panel DP according to the embodiment is not limited thereto. In the embodiment, when the main processor 10 generates a frame whose scanning rate is 240 Hz, the scanning driving circuit SD and the emission driving circuit EDC may be controlled so that one driving interval "A" and one scanning interval "B" are included in one frame. In this embodiment, the display panel DP may operate at a driving frequency of 240 Hz.

[0126] According to an embodiment, the display device DD can synchronize the timing of generating the frame of the main processor 10 and the timing of outputting the frame of the display panel DP. The display device DD can adjust the driving frequency of the display panel DP via iterations of the scanning interval "B". That is, the number of scanning intervals "B" can be changed according to the driving frequency. The display panel DP can operate at a variable frequency. In an embodiment, the display panel DP can be referred to as operating in a variable frequency mode. For example, in a specific operating environment in which a still image is displayed, the power consumption of the display device DD can be reduced by reducing the driving frequency of the display device DD. Therefore, a display device DD with reduced power consumption can be provided.

[0127] Figure 5 is a block diagram showing a drive controller according to an embodiment, and Figure 6 is a flowchart illustrating a driving method of a display device according to an embodiment.

[0128] In the examples and with reference to Figure 2 , Figure 5 and Figure 6 , the driving controller 100 may receive the image signal RGB and the control signal CTRL from the main processor 10. The driving controller 100 may include a compensation signal output unit CO, a data compensation unit 130, and a memory 140.

[0129] In an embodiment, the compensation signal output unit CO may include a representative frequency calculator 110 and a compensation signal calculator 120 .

[0130] In an embodiment, the representative frequency calculator 110 may receive the image signal RGB and the control signal CTRL. The representative frequency calculator 110 may output a representative frequency FI based on the driving frequency of "a" frames before one of the multiple frames (S100). Herein, "a" may be a positive integer.

[0131] In an embodiment, the compensation signal calculator 120 may receive a representative frequency FI. The compensation signal calculator 120 may output a compensation signal CI based on the representative frequency FI and the count number in a frame (S200). The count number may refer to the number of times a signal is repeated in a given cycle in a frame. The compensation signal calculator 120 may output a compensation signal CI based on a voltage correction lookup table VLUT. This will be described later.

[0132] According to an embodiment, the compensation signal CI may be calculated based on the driving frequency of "a" frames before one frame among a plurality of frames. That is, the compensation signal calculator 120 may output the compensation signal CI in consideration of the influence of the accumulated variable driving frequency. The voltage generator 300 may provide a voltage to the display panel DP based on the compensation signal CI. The display panel DP may drive a plurality of pixels PX based on a voltage to which the influence of the accumulated variable driving frequency is applied. The display device DD may improve the brightness deviation of the display panel DP. Therefore, a display device DD having improved display quality may be provided.

[0133] In an embodiment, the data compensation unit 130 may receive the image signal RGB and the control signal CTRL. The data compensation unit 130 may receive the data correction lookup table DLUT in which the grayscale value is stored. The data compensation unit 130 may output the compensated data signal CDT obtained by adding the grayscale and grayscale value of the image signal RGB based on the data correction lookup table DLUT (S300).

[0134] In an embodiment, a plurality of lookup tables may be stored in the memory 140. The plurality of lookup tables may include a data correction lookup table DLUT and a voltage correction lookup table VLUT. The data correction lookup table DLUT may be provided to the data compensation unit 130. The voltage correction lookup table VLUT may be provided to the compensation signal calculator 120.

[0135] In the embodiment, the previous driving frequency PF of a frame before one of the plurality of frames (refer to Fig.12 ) can be stored in the data correction lookup table DLUT. The gray value can be an experimental value measured through an experiment. This will be described later. The previous driving frequency PF can be generated based on at least one of the image signal RGB and the control signal CTRL.

[0136] In an embodiment, the data correction lookup table DLUT may be provided in plurality according to the brightness value of the image signal RGB.

[0137] In an embodiment, the display panel DP may be driven by the compensation signal CI and the compensation data signal CDT. The image IM (refer to Figure 1)'s brightness (S400).

[0138] Figure 7 is a block diagram showing a drive controller according to an embodiment. Figure 7 In the description of Figure 5 The same components as those described are marked by the same reference numerals / symbols, and thus, additional descriptions will be omitted to avoid redundancy.

[0139] In the examples and with reference to Figure 2 and Figure 7 , the driving controller 100 - 1 may include a compensation signal output unit CO, a data compensation unit 130 - 1 , and a memory 140 .

[0140] In an embodiment, the data compensation unit 130-1 may receive the image signal RGB and the representative frequency FI. The data compensation unit 130-1 may receive the data correction lookup table DLUT-1 in which the grayscale values ​​are stored. The data correction lookup table DLUT-1 may include grayscale values ​​according to the representative frequency FI and the grayscale of the image signal RGB.

[0141] In an embodiment, the data compensation unit 130 - 1 may output a compensated data signal CDT- 1 obtained by adding grayscale and grayscale values ​​of the image signal RGB based on the data correction lookup table DLUT- 1 .

[0142] Figure 8 is a block diagram illustrating a representative frequency calculator according to an embodiment.

[0143] Reference Figure 5 and Figure 8 The control signal CTRL may include a synchronization signal Sync and a count signal CYC. The synchronization signal Sync and the count signal CYC may be provided to the representative frequency calculator 110. The representative frequency FI may be calculated based on the synchronization signal Sync and the count signal CYC.

[0144] In an embodiment, the synchronization signal Sync may be activated at the start time point of each frame, and the start time point of each frame may be determined. The synchronization signal Sync may include a vertical synchronization signal. Figure 5 ) can be based on the scanning signal GW (refer to Figure 4A ) instead of a vertical synchronization signal, but the present invention is not limited to this.

[0145] In an embodiment, the count signal CYC may be provided at a given cycle in one frame. Figure 5 ) can be based on the transmitted signal EM (refer to Figure 4A) instead of the counting signal CYC, but the present invention is not limited to this.

[0146] In an embodiment, the representative frequency calculator 110 may include a shift register unit 111 , a weight multiplication unit 112 , a frequency calculation unit 113 , and a representative frequency output unit 114 .

[0147] In an embodiment, the shift register unit 111 may receive a synchronization signal Sync and a count signal CYC. The shift register unit 111 may include a 0th shift register SR0 to a kth shift register SRk, respectively. Herein, "k" may be 128. However, this is an example, and the number of shift registers included in the shift register unit 111 is not limited thereto. For example, "k" may be 16.

[0148] In an embodiment, the 0th to kth shift registers SR0 to SRk of the shift register unit 111 may be connected in series, respectively. For example, the 0th shift register SR0 may be connected to the second shift register SR1, and the second shift register SR1 may be connected to the third shift register SR2.

[0149] In an embodiment, when one of the shift registers SR0 to SRk of the shift register unit 111 receives the count signal CYC, the one shift register may output an output value to another shift register connected to the one shift register. For example, when the synchronization signal Sync having a value of "1" is provided to the 0th shift register SR0, the value "1" may be stored in the 0th shift register SR0. Thereafter, when the count signal CYC is provided to the 0th shift register SR0, the 0th shift register SR0 may provide the output value "1" stored therein to the second shift register SR1.

[0150] In an embodiment, the weight multiplication unit 112 may be connected to the shift register unit 111. The weight multiplication unit 112 may include first to i-th weight multipliers MP0 to MPi, respectively. The number of weight multipliers included in the weight multiplication unit 112 may be equal to the number of shift registers included in the shift register unit 111.

[0151] In an embodiment, the first weight multiplier MP0 may multiply the output value of the 0th shift register SR0 and the first frequency weight coefficient C[0] and may output a first calculated value.

[0152] In an embodiment, the second weight multiplier MP1 may multiply the output value of the second shift register SR1 and the second frequency weight coefficient C[1], and may output a second calculated value.

[0153] In an embodiment, the third weight multiplier MP2 may multiply the output value of the third shift register SR2 and the third frequency weight coefficient C[2], and may output a third calculated value.

[0154] In an embodiment, the weight multiplication unit 112 may provide the frequency calculation unit 113 with a calculation value obtained by multiplying the output value of the shift register unit 111 by different weights in a one-to-one correspondence.

[0155] In an embodiment, the frequency calculation unit 113 may be connected to the weight multiplication unit 112. The frequency calculation unit 113 may add the calculated values ​​to output the output frequency PFI.

[0156] In an embodiment, the representative frequency output unit 114 may be connected to the frequency calculation unit 113. The representative frequency output unit 114 may output the representative frequency FI based on the output frequency PFI and the synchronization signal Sync. The representative frequency output unit 114 may output the output frequency PFI calculated immediately before the start of each frame as the representative frequency FI.

[0157] Fig. 9 is a block diagram illustrating the operation of a representative frequency calculator according to an embodiment, and Fig.10 is a bar graph showing frequency weight coefficients according to an embodiment.

[0158] In an embodiment, Fig. 9 and Fig.10 The shift register unit 111 is shown in FIG. Figure 8 ) respectively include examples of the 0th shift register SR0 to the 16th shift register SR15. Fig. 9 1 to 14th frames FP1 to FP14 are respectively shown as examples.

[0159] In the examples and with reference to Figures 8 to 10 The synchronization signal Sync may be a vertical synchronization signal Sync. The vertical synchronization signal Sync may be activated at a start time point of each of the frames FP1 to FP14, and may determine a start time point of each of the frames FP1 to FP14. An activation period of the vertical synchronization signal Sync may vary depending on a frame rate.

[0160] In an embodiment, the counting signal CYC may be an emission signal EM (see Figure 4A ). The count signal CYC may be provided to be repeated every given cycle.

[0161] In the examples and with reference to Fig. 9, "W / H" may refer to input of the synchronization signal Sync according to the count signal CYC. "W" may refer to that the synchronization signal Sync has a value of "1", and "H" may refer to that the synchronization signal Sync has a value of "0". The value of "W / H" may be a value input to the 0th shift register SR0.

[0162] In an embodiment, the count number Cycle_cnt may indicate a value obtained by counting the number of iterations of the count signal CYC in one frame starting from 0. For example, the count number Cycle_cnt may be 0 or 1 in the first frame FP1, and the count number Cycle_cnt may be 0, 1, 2, or 3 in the tenth frame FP10. The count number Cycle_cnt may be 0, 1, or 2 in the fourteenth frame FP14.

[0163] In an embodiment, the driving frequency DF may indicate the driving frequency of each of the first frame FP1 to the fourteenth frame FP14, respectively. For example, the driving frequency DF of each of the first frame FP1 to the eighth frame FP8 may be 240 Hz, the driving frequency DF of each of the ninth frame FP9 to the eleventh frame FP11 may be 120 Hz, and the driving frequency DF of each of the twelfth frame FP12 to the fourteenth frame FP14 may be 160 Hz. That is, the display panel DP may be operated at a variable frequency.

[0164] In an embodiment, when the synchronization signal Sync and the count signal CYC are input, the count number Cycle_cnt may be "0", and the value "1" may be input to the 0th shift register SR0. Thereafter, when the count signal CYC is input without the input of the synchronization signal Sync, the count number Cycle_cnt may be "1", and the 0th shift register SR0 may output the output value "1" to the second shift register SR1. The value "1" thus output may be input to the second shift register SR1. Because the synchronization signal Sync is not input to the 0th shift register SR0, the value "0" may be input. The second shift register SR1 may output the stored value to the third shift register SR2.

[0165] In an embodiment, that is, when the count signal CYC is input, the (n-1)th shift register may output the (n-1)th value to the nth shift register. In this case, the nth shift register may output the nth value stored therein to the (n+1)th shift register, and the (n-1)th value may be stored in the nth shift register. In an embodiment, "n" is a natural number greater than 2.

[0166] In an embodiment, the input value of the synchronization signal Sync provided according to the previous count signal CYC may be stored in the 0th shift register SR0 to the 16th shift register SR15, respectively, as many as the number of shift registers included in the shift register unit 111. For example, the input value of the current synchronization signal Sync may be stored in the 0th shift register SR0. The input value of the synchronization signal Sync provided according to the count signal CYC one cycle ago may be stored in the second shift register SR1. The input value of the synchronization signal Sync provided according to the count signal CYC two cycles ago may be stored in the third shift register SR2.

[0167] In an embodiment, the current value and the previous value of the synchronization signal Sync may be accumulated and stored in the shift register unit 111 .

[0168] In an embodiment, the weight multiplication unit 112 may multiply the value stored in the shift register unit 111 by the frequency weight coefficient MI in a one-to-one correspondence. As the number of values ​​of the shift register multiplied by the frequency weight coefficient MI becomes larger, the frequency weight coefficient MI may become smaller.

[0169] In an embodiment, the frequency weight coefficient MI may include a first frequency weight coefficient C[0] to a sixteenth frequency weight coefficient C

[15] , respectively. As the frequency weight coefficient C[0] moves toward the sixteenth frequency weight coefficient C

[15] , the frequency weight coefficient MI may decrease. For example, the first frequency weight coefficient C[0] may have a value of 100. The second frequency weight coefficient C[1] may have a value of 60. The third frequency weight coefficient C[2] may have a value of 36.

[0170] According to an embodiment, the driving frequency DF may have a great influence on the previous driving frequency. The representative frequency calculator 110 may assign the first frequency weight coefficient C[0] having a larger value to the previous driving frequency. The representative frequency calculator 110 may assign the sixteenth frequency weight coefficient C

[15] having a smaller value to the previous driving frequency over time. According to the above description, a display device DD (refer to FIG. 1 ) having improved reliability can be provided. Figure 1 ).

[0171] In an embodiment, when the count number Cycle_cnt is 3 in the ninth frame FP9, "0" may be stored in the 0th shift register SR0. "0" may be stored in the second shift register SR1. "0" may be stored in the third shift register SR2. "1" may be stored in the fourth shift register SR3. "0" may be stored in the fifth shift register SR4. "1" may be stored in the sixth shift register SR5. "0" may be stored in the seventh shift register SR6. "1" may be stored in the eighth shift register SR7. "0" may be stored in the ninth shift register SR8. "1" may be stored in the tenth shift register SR9. "0" may be stored in the eleventh shift register SR10. "1" may be stored in the twelfth shift register SR11. "0" may be stored in the thirteenth shift register SR12. "1" may be stored in the fourteenth shift register SR13. "0" may be stored in the fifteenth shift register SR14. "1" may be stored in the sixteenth shift register SR15.

[0172] In an embodiment, the weight multiplication unit 112 may multiply the value stored in the 0th shift register SR0 by the first frequency weight coefficient C[0]. The weight multiplication unit 112 may multiply the value stored in the second shift register SR1 by the second frequency weight coefficient C[1]. The weight multiplication unit 112 may multiply the value stored in the third shift register SR2 by the third frequency weight coefficient C[2]. The weight multiplication unit 112 may multiply the value stored in the fourth shift register SR3 by the fourth frequency weight coefficient C[3]. The weight multiplication unit 112 may multiply the value stored in the fifth shift register SR4 by the fifth frequency weight coefficient C[4]. The weight multiplication unit 112 may multiply the value stored in the sixth shift register SR5 by the sixth frequency weight coefficient C[5]. The weight multiplication unit 112 may multiply the value stored in the seventh shift register SR6 by the seventh frequency weight coefficient C[6]. The weight multiplication unit 112 may multiply the value stored in the eighth shift register SR7 by the eighth frequency weight coefficient C[7]. The weight multiplication unit 112 may multiply the value stored in the ninth shift register SR8 by the ninth frequency weight coefficient C[8]. The weight multiplication unit 112 may multiply the value stored in the tenth shift register SR9 by the tenth frequency weight coefficient C[9]. The weight multiplication unit 112 may multiply the value stored in the eleventh shift register SR10 by the eleventh frequency weight coefficient C

[10] . The weight multiplication unit 112 may multiply the value stored in the twelfth shift register SR11 by the twelfth frequency weight coefficient C

[11] . The weight multiplication unit 112 may multiply the value stored in the thirteenth shift register SR12 by the thirteenth frequency weight coefficient C

[12] . The weight multiplication unit 112 may multiply the value stored in the fourteenth shift register SR13 by the fourteenth frequency weight coefficient C

[13] . The weight multiplication unit 112 may multiply the value stored in the fifteenth shift register SR14 by the fifteenth frequency weight coefficient C

[14] . The weight multiplication unit 112 may multiply the value stored in the sixteenth shift register SR15 by the sixteenth frequency weight coefficient C

[15] .

[0173] In an embodiment, the frequency calculation unit 113 may calculate the output frequency PFI by adding calculated values ​​obtained by multiplying the output value of the shift register unit 111 by different weights in a one-to-one correspondence. In this case, the output frequency PFI may have a value of 65.

[0174] In an embodiment, since the output frequency PFI is a frequency calculated immediately before the start of the tenth frame FP10, a value of 65 may be output as the representative frequency FI of the tenth frame FP10.

[0175] In an embodiment, the display device DD may be driven by using a variable driving frequency (see Figure 2 ). The change of the driving frequency may cause the display panel DP (refer to Figure 2 ) is a brightness difference of light emitted by the display panel DP (refer to FIG. 1 ). In an embodiment, the representative frequency calculator 110 may calculate the representative frequency FI by accumulating previous driving frequencies by using the shift register unit 111. The weight multiplication unit 112 may control the degree of consideration of the accumulated driving frequencies by using weights, and may calculate the representative frequency FI. The drive controller 100 may output a frequency for controlling the display panel DP (refer to FIG. 1 ) by using the optimally calculated representative frequency FI. Figure 2 ) is a signal of the brightness of the light emitted. Therefore, a display device DD (refer to Figure 1 ).

[0176] Fig.11 is a block diagram illustrating a compensation signal calculator according to an embodiment.

[0177] Reference Figures 8 to 11 The compensation signal calculator 120 may receive the representative frequency FI, the synchronization signal Sync and the count signal CYC. In addition, the compensation signal calculator 120 may also receive the voltage correction lookup table VLUT (refer to Figure 5 ).

[0178] In an embodiment, the compensation signal calculator 120 may include a counter 121 , a first compensation value calculator 122 , and a first interpolator 123 .

[0179] In an embodiment, the counter 121 may receive a synchronization signal Sync and a count signal CYC. The counter 121 may output a count number Cycle_cnt based on the synchronization signal Sync and the count signal CYC. The count number Cycle_cnt may indicate a value obtained by counting the number of iterations of the count signal CYC in one frame starting from "0". One frame may be defined based on the synchronization signal Sync. For example, a case where the synchronization signal Sync has a value of "1" may be defined as a start time point of a frame.

[0180] In an embodiment, the first compensation value calculator 122 may receive the representative frequency FI and the count number Cycle_cnt. The first compensation value calculator 122 may receive the representative frequency FI and the count number Cycle_cnt from the memory 140 (refer to Figure 5 )Receive voltage correction lookup table VLUT.

[0181] In an embodiment, the voltage correction lookup table VLUT may include a plurality of correction values ​​a0 to d. The compensation signal calculator 120 may output the compensation signal CI based on the plurality of correction values ​​a0 to d.

[0182] In an embodiment, Fig.11, an example in which the count number Cycle_cnt has a value of 0 to 31 is shown, but the present invention is not limited thereto.

[0183] In an embodiment, when the representative frequency FI is greater than or equal to the reference value, the correction values ​​a0 to c31 defined for each count number Cycle_cnt at the representative frequency FI may have at least two different values. When the representative frequency FI output from the representative frequency calculator 110 has a value of 138, the first correction value a0 corresponding to the count number Cycle_cnt of 0 and the second correction value a31 corresponding to the count number Cycle_cnt of 31 may be different from each other. For example, when the compensation signal CI controls the reference voltage Vbias (reference Figure 2 ), the first correction value a0 may have a value that allows the compensation signal CI to reduce the reference voltage Vbias (reference Figure 2 ) is controlled to a value of 6.00V (volts), and the second correction value a31 may have a value that allows the compensation signal CI to reduce the reference voltage Vbias (reference voltage Vbias) to 6.00V (volts). Figure 2 ) is controlled to a value of 7.30V.

[0184] In an embodiment, the reference value may be 40. However, this is an example, and a given value may be variously provided by a user, and is not limited thereto.

[0185] In an embodiment, when the representative frequency FI is less than the reference value, at the representative frequency FI, the third correction value "d" may have a consistent value. For example, when the representative frequency FI output from the representative frequency calculator 110 is 36, the third correction value "d" may be fixed and may be output as the compensation signal CI. For example, when the compensation signal CI controls the reference voltage Vbias (reference Figure 2 ), the third correction value "d" may have a value that allows the compensation signal CI to reduce the reference voltage Vbias (reference Figure 2 ) is controlled to a value of approximately 7.00V.

[0186] In an embodiment, when the third correction value "d" is less than or equal to the first correction value a0, the count number Cycle_cnt may be counted when the display panel DP (refer to Figure 2 ) increases, and therefore, the light waveform may increase. This may cause brightness deviation, that is, a flickering phenomenon may occur. For example, the low frequency may be about 30 Hz. However, in an embodiment, a reference voltage Vbias determined differently according to a representative frequency FI and a count number Cycle_cnt may be provided to a plurality of pixels PX (refer to Figure 2 The third correction value "d" may be greater than the first correction value a0. The compensation signal output unit CO (refer to Figure 5) can define the third correction value "d" so that a display panel DP suitable for driving at a low frequency is provided (refer to Figure 2 ) is the reference voltage Vbias (refer to Figure 2 ). Flickering that can be caused when driving a plurality of pixels PX at a low frequency can be improved. Therefore, a display device DD with improved display quality can be provided (refer to Figure 1 ).

[0187] In the embodiment, assuming that the representative frequency calculator 110 and the compensation signal calculator 120 do not perform compensation, when the driving frequency DF is converted from a high frequency to a low frequency, the display panel DP (refer to Figure 2 ) may appear a phenomenon of brightness increase in the light waveform. When the driving frequency DF changes, a brightness deviation may occur in the light waveform. In addition, the brightness deviation of the light waveform may occur differently depending on the accumulated driving frequency. For example, when changing from a frame of about 240Hz to a frame of about 30Hz once, a brightness deviation of about 4.3% may occur. When a frame becomes a frame of about 30Hz after two frames of about 240Hz, a brightness deviation of about 6.2% may occur. When a frame becomes a frame of about 30Hz after four frames of about 240Hz, a brightness deviation of about 8.0% may occur. When a frame becomes a frame of about 30Hz after six frames of about 240Hz, a brightness deviation of about 9.8% may occur. In this way, a flicker phenomenon may occur. However, according to an embodiment, when the driving frequency DF changes, the representative frequency calculator 110 may calculate the representative frequency FI, and the compensation signal calculator 120 may output the compensation signal CI based on the representative frequency FI. Compensation can be performed via the compensation signal CI so that the light waveform is uniform. That is, even if the brightness deviation occurs differently depending on the accumulated driving frequency, the brightness can be uniformly maintained by outputting the compensation signal CI based on the representative frequency FI. Therefore, a display device DD with improved display quality can be provided (refer to Figure 1 ).

[0188] In an embodiment, by using an interpolation method, the first interpolator 123 may calculate the compensation signal CI based on the correction values ​​a0 to d received from the first compensation value calculator 122. In an embodiment, the interpolation method may include a linear interpolation method. The linear interpolation method may be a method of calculating the compensation signal CI corresponding to the representative frequency FI based on two coordinate values ​​consisting of the representative frequency FI and the correction value (e.g., at least two of a0 to d) under the condition of the same count signal CYC, and the compensation signal CI calculated in this way may be located between the two coordinate values. However, this is an example, and the first interpolator 123 according to the embodiment may selectively use various methods as a method for calculating the compensation signal CI.

[0189] In an embodiment, when the representative frequency FI output from the representative frequency calculator 110 has a value of 65 and the count number Cycle_cnt is 2, the first compensation value calculator 122 may output a correction value to the first interpolator 123 based on the representative frequency FI and the count number Cycle_cnt set adjacent to the representative frequency FI of 65. That is, the first compensation value calculator 122 may output correction values ​​b2 and c2 located at the third row (Cycle_cnt=2) and the second column (FI=72) of the voltage correction lookup table VLUT and the third row (Cycle_cnt=2) and the third column (FI=45) of the voltage correction lookup table VLUT, respectively. The first interpolator 123 may output the compensation signal CI by linearly interpolating the correction values ​​b2 and c2.

[0190] According to an embodiment, the representative frequency calculator 110 may output a representative frequency FI in consideration of a plurality of accumulated driving frequencies. The compensation signal calculator 120 may output a compensation signal CI based on the representative frequency FI. Instead of providing a voltage correction lookup table VLUT for all accumulated driving frequencies, one lookup table may be defined based on the calculated representative frequency FI. That is, since it is not necessary to include a voltage correction table corresponding to the display device DD (refer to FIG. 1 ), the compensation signal calculator 120 may output a compensation signal CI based on the representative frequency FI. Figure 1 ), so no additional memory is required. Therefore, there is no need for an area in which an additional memory is provided, and the non-display area NDA (refer to Figure 1 ) can be reduced in area. In addition, by outputting the compensation signal CI by using a lookup table and the first interpolator 123, power consumption can be reduced. According to the above description, a display device DD (refer to Figure 1 ).

[0191] Fig.12 is a block diagram illustrating a data compensation unit according to an embodiment.

[0192] In the examples and with reference to Fig.12 The data compensation unit 130 may receive the image signal RGB and the previous driving frequency PF. The previous driving frequency PF may refer to the driving frequency of a frame before one of the plurality of frames. The data compensation unit 130 may output the compensation data signal CDT based on the image signal RGB in units of frames.

[0193] In an embodiment, the data compensation unit 130 may include a second correction value calculator 131 and a second interpolator 132 .

[0194] In an embodiment, the second correction value calculator 131 may receive the previous driving frequency PF and the image signal RGB. The second correction value calculator 131 may receive the previous driving frequency PF and the image signal RGB from the memory 140 (refer to Figure 5)Receive data correction lookup table DLUT.

[0195] In an embodiment, the data correction lookup table DLUT may include a plurality of grayscale values ​​e0 to gk according to the previous driving frequency PF and the grayscale of the image signal RGB. In this case, "k" may be an integer of 6 or more. The second correction value calculator 131 may output a compensation data signal CDT based on the plurality of grayscale values ​​e0 to gk. The compensation data signal CDT may correspond to a value obtained by adding the grayscale of the image signal RGB to a relevant grayscale value among the plurality of grayscale values ​​e0 to gk.

[0196] In an embodiment, when the previous driving frequency PF has a first frequency and the grayscale of the image signal RGB has a first grayscale, the grayscale value may have a first grayscale value g0. In an embodiment, the compensation data signal CDT may be output based on the first grayscale value g0. For example, when the first frequency is about 30 Hz and the first grayscale is 255G, the first grayscale value g0 may be about +14.

[0197] In an embodiment, when the previous driving frequency PF has a second frequency higher than the first frequency and the grayscale of the image signal RGB has a first grayscale, the grayscale value may have a second grayscale value e0 different from the first grayscale value g0. In this case, the compensation data signal CDT may be output based on the second grayscale value e0. The second grayscale value e0 may be less than the first grayscale value g0. For example, when the second frequency is about 120 Hz, the second grayscale value e0 may be about +7.

[0198] In an embodiment, when the previous driving frequency PF has a first frequency and the grayscale of the image signal RGB is a second grayscale lower than the first grayscale, the grayscale value may have a third grayscale value gk. In this case, the compensation data signal CDT may be output based on the third grayscale value gk. For example, when the second grayscale is 11G, the third grayscale value gk may be about +3.

[0199] That is, in the data correction lookup table DLUT, as the frequency becomes relatively high, each of the plurality of gray values ​​e0 to gk becomes relatively small, as the frequency becomes relatively low, each of the plurality of gray values ​​e0 to gk becomes relatively large, as the grayscale becomes high, each of the plurality of gray values ​​e0 to gk becomes large, and as the grayscale becomes low, each of the plurality of gray values ​​e0 to gk becomes small. However, this is an example, and each of the plurality of gray values ​​e0 to gk according to the embodiment may be provided differently without being limited thereto. For example, the gray values ​​g0, g1, g2, g3, g4, gk-1, and gk corresponding to the previous driving frequency PF of about 30 Hz may have values ​​of about +14, about +12, about +11, about +7, about +6, about +2, and about +3, respectively.

[0200] In an embodiment, when the previous driving frequency PF is higher than about 120 Hz, the second correction value calculator 131 may output a gray value of "0". The data compensation unit 130 may convert the image signal RGB into a data signal without compensation. That is, the compensated data signal CDT may have the same value as the data signal obtained by converting the image signal RGB. Fig.12 An example in which about 120 Hz is the highest frequency is shown in FIG. 4 , but the data correction lookup table DLUT according to the embodiment may be variously provided without being limited thereto.

[0201] In an embodiment, the G value between high frequency and low frequency can be measured to evaluate the display device DD (refer to Figure 1 ) performance. In this case, the G value may be a value obtained by dividing the brightness value corresponding to the case of driving at about 240 Hz by the brightness value corresponding to the case of driving at about 30 Hz. This will be described later.

[0202] In the embodiment, assuming that the data compensation unit 130 does not perform compensation, when the display device DD (refer to Figure 1 ) When displaying an image with a low grayscale, a large brightness difference may occur at different driving frequencies. Therefore, when the driving frequency changes, flickering may occur. However, according to an embodiment, a compensation data signal CDT obtained by correcting the grayscale of the image signal RGB through the data compensation unit 130 may be output. The display device DD (refer to Figure 1 ) at low frequencies. Display device DD (refer to Figure 1 ) can be improved. Therefore, a display device DD with improved display quality can be provided (refer to Figure 1 ).

[0203] In an embodiment, by using an interpolation method, the second interpolator 132 may calculate the compensation data signal CDT based on the grayscale values ​​e0 to gk received from the second correction value calculator 131. For example, the interpolation method may include a linear interpolation method. That is, when the grayscale of the image signal RGB is a grayscale not stored in the data correction lookup table DLUT, the compensation data signal CDT may be calculated by using an interpolation method.

[0204] Fig.13 is a block diagram illustrating a process of driving a display device according to an embodiment.

[0205] In the examples and with reference to Figure 2 , Figure 5 , Fig.12 and Fig.13In the variable frequency mode, the driving frequency DF may be switched. The driving frequency DF may be switched from a first frequency to a second frequency. For example, the first frequency may be about 240 Hz, and the second frequency may be about 30 Hz.

[0206] After the driving frequency DF is switched from the first frequency to the second frequency, a given frame may be referred to as a 'switch period TRS'.

[0207] In an embodiment, the display device DD may operate in a stable period STB after the transition period TRS. In the stable period STB, the driving frequency DF may be the second frequency.

[0208] In an embodiment, the driving controller 100 may include a compensation signal output unit CO and a data compensation unit 130. The compensation signal output unit CO may include a representative frequency calculator 110 and a compensation signal calculator 120.

[0209] In an embodiment, the representative frequency calculator 110 may output the representative frequency FI based on 'a' driving frequencies DF of a frame before one frame among a plurality of frames.

[0210] In an embodiment, the compensation signal calculator 120 may output the compensation signal CI based on the representative frequency FI and the count number Cycle_cnt in one frame.

[0211] In an embodiment, the compensation signal output unit CO may output the compensation signal CI in units of a count number Cycle_cnt.

[0212] In an embodiment, the voltage generator 300 may generate a voltage to be provided to the first transistor T1 (refer to Figure 3 ). The voltage generator 300 may control the level of the reference voltage Vbias based on the compensation signal CI.

[0213] In an embodiment, as the count number Cycle_cnt increases, the voltage level of the reference voltage Vbias may increase.

[0214] In an embodiment, as the driving frequency DF increases, the maximum value of the voltage level of the reference voltage Vbias may decrease. For example, when the driving frequency DF has a first frequency, the reference voltage Vbias may have a first voltage level V1. For example, the first voltage level V1 may be about 6V. When the driving frequency DF has a second frequency lower than the first frequency, the reference voltage Vbias may have a second voltage level V2 higher than the first voltage level V1. For example, the second voltage level V2 may be about 7V.

[0215] In an embodiment, as the representative frequency FI increases, the average value of the voltage level of the reference voltage Vbias may decrease. The brightness of the plurality of pixels PX of the display panel DP may be controlled by the reference voltage Vbias.

[0216] In an embodiment, the data compensation unit 130 may output a compensated data signal CDT obtained by adding the grayscale and grayscale value of the image signal RGB based on the data correction lookup table DLUT storing the grayscale value.

[0217] In an embodiment, assuming that the grayscale of the image signal RGB is about 87G, when the previous driving frequency PF is about 240Hz, the compensation data signal CDT may be output without compensation. The compensation data signal CDT may include a first data signal D0. For example, the first data signal D0 may be a data signal converted based on the image signal RGB. When the previous driving frequency PF has a second frequency lower than the first frequency, the second correction value calculator 131 may output a grayscale value g4. The second frequency may be about 30Hz. The compensation data signal CDT may be output based on the grayscale value g4. The compensation data signal CDT may include a second data signal D1. For example, the second data signal D1 may have a value obtained by adding the grayscale value g4 and a data signal converted based on the image signal RGB. The first data signal D0 may be different from the second data signal D1.

[0218] In an embodiment, the data compensation unit 130 may output the compensated data signal CDT in units of frames.

[0219] In an embodiment, the brightness of the plurality of pixels PX of the display panel DP may be controlled by the compensation data signal CDT.

[0220] According to an embodiment, the representative frequency calculator 110 may output a representative frequency FI in consideration of the accumulated driving frequency. The compensation signal calculator 120 may output an optimal compensation signal CI based on the representative frequency FI. Each of the plurality of pixels PX of the display panel DP may emit light based on a reference voltage Vbias controlled by the compensation signal CI. The data compensation unit 130 may output an optimal compensation data signal CDT in consideration of the grayscale of the image signal RGB and the previous driving frequency PF. Each of the plurality of pixels PX of the display panel DP may emit light based on a data voltage Vdata controlled by the compensation data signal CDT. That is, the image IM (refer to Figure 1 ) brightness. The display device DD can provide a uniform light waveform LV regardless of changes in the driving frequency DF. Therefore, a display device DD whose display quality is improved can be provided.

[0221] According to another embodiment, similar to Figure 7In the driving controller 100-1, assuming that the data compensation unit 130-1 outputs a gray value based on the representative frequency FI instead of the previous driving frequency PF, when the grayscale of the image signal RGB is about 87G and the representative frequency FI is about 120Hz, the second correction value calculator 131 may output a gray value of e4. The compensated data signal CDT-1 may be output based on the gray value of e4. Thereafter, when the representative frequency FI is about 60Hz, the second correction value calculator 131 may output a gray value of f4. The compensated data signal CDT-1 may be output based on the gray value of f4. Thereafter, when the representative frequency FI is about 30Hz, the second correction value calculator 131 may output a gray value of g4. The compensated data signal CDT-1 may be output based on the gray value of g4.

[0222] Fig.14A is a graph showing the G value for each grayscale according to the embodiment.

[0223] exist Fig.14A In the figure, the horizontal axis represents the image signal RGB (refer to Figure 2 )’s grayscale, and the vertical axis represents the G value.

[0224] The G value may be defined by Equation 1 below.

[0225] [Equation 1]

[0226] G value = (LUM (high frequency) - LUM (low frequency)) / LUM (high frequency)

[0227] Referring to the above equation 1, LUM (high frequency) represents the display panel DP driven at the first frequency among the variable driving frequencies (refer to Figure 2 ), and LUM (low frequency) indicates that the display panel DP is driven at a second frequency lower than the first frequency among the variable driving frequencies (refer to Figure 2 ) brightness. The unit of G value can be %. Fig.14A , the first frequency may correspond to approximately 240 Hz and the second frequency may correspond to approximately 30 Hz.

[0228] In the examples and with reference to Figure 2 , Figure 5 and Fig.14A , the first graph S1a, the second graph S2a, and the third graph S3a may be graphs showing G values ​​of the display panel according to the comparative example.

[0229] In an embodiment, the first graph S1 a may show a G value of each grayscale of a display device driven by using a driving controller that does not include the compensation signal output unit CO and the data compensation unit 130 .

[0230] In an embodiment, the second graph S2a may show a G value of each grayscale of a display device driven by using a driving controller not including the data compensation unit 130 and controlling the reference voltage Vbias at a low frequency to have the same voltage level as a high frequency.

[0231] In an embodiment, the third graph S3 a may show a G value of each grayscale of a display device driven by using a driving controller not including the data compensation unit 130 .

[0232] In an embodiment, the fourth graph S4 a may be a graph showing a G value for each grayscale of the display device DD to which the driving controller 100 is applied.

[0233] In an embodiment, as the display quality of the display device DD is improved, the G value may be close to about 0.0%. For example, when the G value is between about -4.0% and about 4.0%, the display device DD may be determined to be good.

[0234] In an embodiment, when the grayscale of the image signal RGB is approximately 11G, the G value of the first graph S1a may be approximately 0.6%, the G value of the second graph S2a may be approximately -0.2%, the G value of the third graph S3a may be approximately 10.1%, and the G value of the fourth graph S4a may be approximately 1.0%.

[0235] In the embodiment, the display device DD including the driving controller 100 may improve the G value. Therefore, the display device DD having improved display quality may be provided.

[0236] In an embodiment, the F value between high frequency and low frequency may be measured to evaluate the display device DD (refer to Figure 1 ) performance. The F value can be defined by the following equation 2.

[0237] [Equation 2]

[0238] F value = (LUM (high frequency, 255G) - LUM (low frequency, 255G)) / (high frequency - low frequency)

[0239] Referring to the above equation 2, LUM (high frequency, 255G) represents when the display panel DP (refer to Figure 2 ) corresponds to the luminance of the grayscale of 255G when the display panel DP (refer to Figure 2 ) corresponds to a luminance of a grayscale of 255G when driven at a second frequency lower than the first frequency among the variable driving frequencies, and (high frequency - low frequency) may refer to a value obtained by subtracting the second frequency from the first frequency. The first frequency may correspond to about 240 Hz, and the second frequency may correspond to about 30 Hz.

[0240] In an embodiment, the F value measured from a display device that does not include the data compensation unit 130 and controls the reference voltage Vbias at a low frequency to have the same voltage level as a high frequency may be about 0.019. The brightness difference corresponding to the F value of about 0.019 may be about 4.0 nits.

[0241] In an embodiment, an F value measured from the display device DD including the driving controller 100 may be about 0.002. A luminance difference corresponding to the F value of about 0.002 may be about 0.4 nit.

[0242] According to an embodiment, the F value of the display panel DP may be about 0.002. Compared with a comparative example in which the data compensation unit 130 is not included and the reference voltage Vbias is controlled to have the same voltage level at a low frequency as at a high frequency, the F value may be improved. Therefore, a display device DD having improved display quality may be provided.

[0243] Fig. 14B is a graph showing JEITA values ​​measured for each grayscale in a low frequency period according to an embodiment.

[0244] exist Fig. 14B In the figure, the horizontal axis represents the image signal RGB (refer to Figure 2 ), and the vertical axis represents the JEITA value measured in the low frequency period. For example, the low frequency period can be defined as a stable period STB (refer to Fig.13 The JEITA method flicker measurement method can be used to quantitatively evaluate the display device DD (refer to Figure 1 ) flicker level. JEITA method flicker may be a method of quantitatively measuring flicker defined by the Japan Electronics and Information Technology Industries Association. JEITA value may be a value measured in dB (decibel) by using the JEITA method flicker measurement method.

[0245] Reference Figure 2 , Figure 5 and Fig. 14B , the first graph S1b, the second graph S2b, and the third graph S3b may be graphs showing JEITA values ​​of the display panel according to the comparative example of the present disclosure.

[0246] The first graph S1b may show a JEITA value of each grayscale of a display device driven by a driving controller that does not include the compensation signal output unit CO and the data compensation unit 130 of the present disclosure.

[0247] The second graph S2b may show a JEITA value of each grayscale of a display device driven by a driving controller using the data compensation unit 130 not including the present disclosure and controlling the reference voltage Vbias at a low frequency to have the same voltage level as that at a high frequency.

[0248] In the second graph S2b, the grayscale corresponding to the JEITA value of -55.0 dB or less may range from 255G to 87G.

[0249] The third graph S3 b may show a JEITA value of each grayscale of a display device driven by a driving controller that does not include the data compensation unit 130 of the present disclosure.

[0250] The fourth graph S4b may be a graph showing the JEITA value of each grayscale of the display device DD to which the driving controller 100 of the present disclosure is applied.

[0251] As the display quality of the display device DD improves, the JEITA value may become smaller. For example, when the JEITA value is less than -45.0 dB, the display device DD may be determined to be good.

[0252] For example, when the grayscale of the image signal RGB is 11G, the JEITA value of the first graph S1b may be -38.9dB, the JEITA value of the second graph S2b may be -36.5dB, the JEITA value of the third graph S3b may be -47.0dB, and the JEITA value of the fourth graph S4b may be -49.5dB.

[0253] The display device DD including the driving controller 100 of the present disclosure can improve flicker in a low frequency period. Therefore, a display device DD having improved display quality can be provided.

[0254] In the fourth graph S4b, the grayscale corresponding to the JEITA value of -55.0 dB or less may range from 255G to 23G.

[0255] According to the present disclosure, compared with a comparative example in which the data compensation unit 130 is not included and the reference voltage Vbias is controlled to have the same voltage level at a low frequency as at a high frequency, the range of grayscales corresponding to the JEITA value of -55.0 dB or less can be wider. The display device DD including the drive controller 100 of the present disclosure can improve flickering in a low frequency period. Therefore, a display device DD having improved display quality can be provided.

[0256] Fig. 14C is a graph showing a JEITA value for each grayscale measured when a frequency is converted from a high frequency to a low frequency according to an embodiment of the present disclosure.

[0257] exist Fig. 14C In the figure, the horizontal axis represents the image signal RGB (refer to Figure 2 ), and the vertical axis represents the JEITA value measured when the frequency is converted from a high frequency to a low frequency. For example, a period in which the frequency is converted from a high frequency to a low frequency may be defined as a conversion period TRS (refer to Fig.13 ).

[0258] Reference Figure 2 , Figure 5 and Fig. 14C , the first graph S1c, the second graph S2c, and the third graph S3c may be graphs showing JEITA values ​​of the display panel according to the comparative example of the present disclosure.

[0259] The first graph S1c may show a JEITA value of each grayscale of a display device driven by a driving controller that does not include the compensation signal output unit CO and the data compensation unit 130 of the present disclosure.

[0260] The second graph S2c may show a JEITA value of each grayscale of a display device driven by using a driving controller not including the data compensation unit 130 of the present disclosure and controlling the reference voltage Vbias at a low frequency to have the same voltage level as that at a high frequency.

[0261] In the second graph S2c, the average value of the JEITA value in the range of grayscales from 87G to 255G may be -48.5dB.

[0262] The third graph S3 c may show a JEITA value of each grayscale of a display device driven by a driving controller using the data compensation unit 130 not including the present disclosure.

[0263] The fourth graph S4c may be a graph showing the JEITA value of each grayscale of the display device DD to which the driving controller 100 of the present disclosure is applied.

[0264] For example, when the grayscale of the image signal RGB is 11G, the JEITA value of the first graph S1c may be -36.5dB, the JEITA value of the second graph S2c may be -37.8dB, the JEITA value of the third graph S3c may be -28.9dB, and the JEITA value of the fourth graph S4c may be -46.0dB.

[0265] The display device DD including the driving controller 100 of the present disclosure can improve flicker in a low frequency period. Therefore, a display device DD having improved display quality can be provided.

[0266] In the fourth graph S4c, an average value of the JEITA value in the range of grayscales from about 87G to about 255G may be about -60.7 dB.

[0267] According to an embodiment, compared with a comparative example in which the data compensation unit 130 is not included and the reference voltage Vbias is controlled to have the same voltage level at a low frequency as at a high frequency, the average value of the JEITA value in the range of grayscales from about 87G to about 255G can be smaller. As the display quality of the display device DD is improved, the JEITA value can be reduced. The display device DD including the drive controller 100 can improve flickering in a low frequency period. Therefore, a display device DD having improved display quality can be provided.

[0268] According to an embodiment, the driving controller 100 may include a representative frequency calculator 110, a compensation signal calculator 120, and a data compensation unit 130. In a display device DD including the driving controller 100, all of a G value measured in a low frequency period, a JEITA value, and a JEITA value measured when a frequency is converted from a high frequency to a low frequency may be improved. Therefore, a display device DD having improved display quality may be provided.

[0269] Fig.15 is a timing diagram showing how to drive the second initialization voltage according to an embodiment. Fig.15 It is shown that when the frequency changes from about 240 Hz to about 30 Hz, Fig.13 The second initialization voltage Vainit in the frame (refer to Figure 2 ) level.

[0270] In the examples and with reference to Figure 2 , Figure 3 , Figure 5 and Fig.15 , the voltage generator 300 may generate a second initialization voltage Vainit to be supplied to the second electrode of the fourth transistor T4. The voltage generator 300 may control the level of the second initialization voltage Vainit based on the compensation signal CI. Fig.13 Differently, the compensation signal CI can be used to control the second initialization voltage Vainit instead of the reference voltage Vbias.

[0271] In an embodiment, when the representative frequency FI has a value of about 40 or more, the level of the second initialization voltage Vainit may decrease as the count number Cycle_cnt increases. For example, in the case of a frame whose frequency changes from about 240 Hz to about 30 Hz, the second initialization voltage Vainit corresponding to the count number Cycle_cnt of "0" may have a first level V1a, and the second initialization voltage Vainit corresponding to the count number Cycle_cnt of "7" may have a second level V2a. The brightness of the plurality of pixels PX of the display panel DP may be controlled by the second initialization voltage Vainit.

[0272] According to an embodiment, the representative frequency calculator 110 may output a representative frequency FI in consideration of the accumulated driving frequency. The compensation signal calculator 120 may output an optimal compensation signal CI based on the representative frequency FI. Each of the plurality of pixels PX of the display panel DP may emit light based on the second initialization voltage Vainit controlled by the compensation signal CI. The display device DD may provide a uniform light waveform regardless of the change in the driving frequency DF. Therefore, a display device DD having improved display quality may be implemented.

[0273] Fig.16 is a timing diagram showing how to drive a transmit signal according to an embodiment. Fig.16 It shows that when the frequency changes from about 240 Hz to about 30 Hz, Fig.13 The transmitted signal EM in the frame (refer to Figure 4A ) level.

[0274] In the examples and with reference to Figure 2 , Figure 3 , Figure 5 and Fig.16 , the emission driving circuit EDC may receive the compensation signal CI. The compensation signal CI is provided to the voltage generator 300 to control the reference voltage Vbias. Figure 2 and Fig.13 Differently, the compensation signal CI according to the embodiment may be provided to the emission driving circuit EDC to control the emission signals EM1 and EM2.

[0275] In an embodiment, the emission driving circuit EDC may receive the emission driving control signal ECS and the compensation signal CI from the driving controller 100 .

[0276] In an embodiment, the transmission signal correction lookup table may be stored in the memory 140, and the first compensation value calculator 122 (refer to Fig.11 ) can receive the transmission signal correction lookup table from memory 140.

[0277] In an embodiment, the emission driving circuit EDC may generate an emission signal EM. The emission driving circuit EDC may control the pulse width of the emission signal EM to be provided to the gate electrode of the ninth transistor T9 based on the compensation signal CI. However, this is an example, and the emission signal EM according to the embodiment may refer to at least one of the first emission signal EM1 and the second emission signal EM2. The pulse width may refer to a period in which the emission signal EM is applied.

[0278] In an embodiment, when the representative frequency FI has a value of about 40 or more, the pulse width of the emission signal EM may decrease as the count number Cycle_cnt increases. For example, in the case of a frame whose frequency changes from about 240 Hz to about 60 Hz, the emission signal EM corresponding to the count number Cycle_cnt of "0" may have a first pulse width W1, and the emission signal EM corresponding to the count number Cycle_cnt of "7" may have a second pulse width W2. When the representative frequency FI is about 100, the first pulse width W1 may be greater than the second pulse width W2. The brightness of the plurality of pixels PX of the display panel DP may be controlled by the pulse width of the emission signal EM.

[0279] According to an embodiment, the representative frequency calculator 110 may output a representative frequency FI in consideration of the accumulated driving frequency. The compensation signal calculator 120 may output an optimal compensation signal CI based on the representative frequency FI. Each of the plurality of pixels PX of the display panel DP may emit light based on an emission signal EM controlled by the compensation signal CI. The display device DD may provide a uniform light waveform regardless of a change in the driving frequency DF. Therefore, a display device DD having improved display quality may be implemented.

[0280] In an embodiment and according to the above description, the drive controller may include a representative frequency calculator, a compensation signal calculator, and a data compensation unit. The representative frequency calculator may output a representative frequency in consideration of the accumulated driving frequency. The compensation signal calculator may output an optimal compensation signal based on the representative frequency. Each of the plurality of pixels of the display panel may emit light based on a reference voltage controlled by a compensation signal. The data compensation unit may output an optimal compensation data signal in consideration of the grayscale of the image signal and the previous driving frequency. Each of the plurality of pixels of the display panel may emit light based on a data voltage controlled by a compensation data signal. That is, the brightness of the image may be controlled based on the compensation signal and the compensation data signal. The display device may provide a uniform light waveform regardless of changes in the driving frequency. Therefore, a display device with improved display quality may be provided.

[0281] In the embodiment, also in the display device including the driving controller, all of the G value measured in the low frequency period, the JEITA value, and the JEITA value when the frequency is switched from high frequency to low frequency can be improved. Therefore, a display device with improved display quality can be provided.

[0282] Although the present invention has been described with reference to the embodiments of the present invention, various changes and modifications can be made to the present invention without departing from the spirit and scope of the present invention, which is obvious to those skilled in the art. In addition, the embodiments or parts of the embodiments can be combined in whole or in part without departing from the scope of the present invention.

Claims

1. A display device, wherein: The display device comprises: a display panel comprising a plurality of pixels, wherein the display panel is configured to display an image corresponding to each of the plurality of frames; and a driving controller configured to receive an image signal and drive the plurality of frames at a plurality of driving frequencies, Wherein, the drive controller comprises: a representative frequency calculator configured to output a representative frequency based on n driving frequencies of n frames before one frame among the plurality of frames; a compensation signal calculator configured to output a compensation signal based on the representative frequency and the number of counts in the one frame; and a data compensation unit configured to receive the image signal and output a compensated data signal by adding the grayscale value of the image signal to the grayscale value based on a data correction lookup table storing grayscale values, Wherein, the brightness of the image is controlled based on the compensation signal and the compensation data signal.

2. The display device according to claim 1, wherein: Grayscale values ​​of the grayscale according to the representative frequency and the image signal are stored in the data correction lookup table.

3. The display device according to claim 1, wherein: A grayscale value according to the grayscale of the image signal and a previous driving frequency of a frame before the one frame among the plurality of frames is stored in the data correction lookup table.

4. The display device according to claim 3, wherein: When the previous driving frequency has a first frequency, the grayscale value has a first grayscale value, and the compensation data signal is output based on the first grayscale value, When the previous driving frequency has a second frequency higher than the first frequency, the gray value has a second gray value, and the compensation data signal is output based on the second gray value, and The second grayscale value is smaller than the first grayscale value.

5. The display device according to claim 1, wherein: The data correction lookup table includes a plurality of data correction lookup tables, and The plurality of data correction lookup tables are provided according to the brightness value of the image signal.

6. The display device according to claim 1, wherein: When the grayscale of the image signal is a grayscale not stored in the data correction lookup table, the data compensation unit calculates the grayscale value by using an interpolation method.

7. The display device according to claim 1, wherein: calculating the representative frequency based on a synchronization signal defining a start of each of the plurality of frames and a count signal obtained by counting the plurality of frames at a given cycle, and Wherein, the count number is output based on the count signal.

8. The display device according to claim 7, wherein: The representative frequency calculator includes a plurality of shift registers receiving the synchronization signal and the count signal, wherein the plurality of shift registers are electrically connected in series, and When one shift register among the plurality of shift registers receives the counting signal, the one shift register transmits the output value to another shift register among the plurality of shift registers connected to the one shift register.

9. The display device according to claim 8, wherein: The representative frequency is calculated by multiplying a plurality of output values ​​of the plurality of shift registers by different weights in a one-to-one correspondence.

10. The display device according to claim 1, wherein: The display device further includes: A voltage generator is configured to receive the compensation signal, generate a voltage whose voltage level is adjusted based on the compensation signal, and provide the voltage to each of the plurality of pixels.

11. The display device according to claim 10, wherein: As the count number increases, the voltage level of the voltage increases.

12. The display device according to claim 10, wherein: When the driving frequency has a first frequency, the voltage has a first voltage level, and When the driving frequency has a second frequency lower than the first frequency, the voltage has a second voltage level higher than the first voltage level.

13. The display device according to claim 1, wherein: The display device further includes: A driving circuit is configured to receive the compensation signal, generate an emission signal whose pulse width is adjusted according to the compensation signal, and provide the emission signal to each of the plurality of pixels.

14. The display device according to claim 13, wherein: As the count number increases, the width of the pulse width becomes narrower.

15. The display device according to claim 1, wherein: The drive controller also includes: A memory configured to store the data correction lookup table.

16. A drive controller, wherein: The drive controller comprises: Representative frequency calculator, compensation signal calculator and data compensation unit, wherein the driving controller receives an image signal corresponding to each of a plurality of frames, each of the plurality of frames being driven at a driving frequency, wherein the representative frequency calculator outputs the representative frequency based on n driving frequencies of n frames before one frame among the plurality of frames, wherein the compensation signal calculator outputs a compensation signal based on the representative frequency and the number of counts in the one frame, and Wherein, based on a data correction lookup table storing a grayscale value according to the grayscale of the image signal, the data compensation unit adds the grayscale of the image signal and the grayscale value to output a compensated data signal.

17. The drive controller according to claim 16, wherein: Grayscale values ​​of the grayscale according to the representative frequency and the image signal are stored in the data correction lookup table.

18. The drive controller according to claim 16, wherein: A grayscale value according to the grayscale of the image signal and a previous driving frequency of a frame before the one frame is stored in the data correction lookup table.

19. The drive controller according to claim 18, wherein: When the previous driving frequency has a first frequency, the grayscale value has a first grayscale value, and the compensation data signal is output based on the first grayscale value, wherein when the previous driving frequency has a second frequency higher than the first frequency, the grayscale value has a second grayscale value, and the compensation data signal is output based on the second grayscale value, and The second grayscale value is smaller than the first grayscale value.

20. The drive controller according to claim 18, wherein: The drive controller also includes: A memory configured to store the data correction lookup table.

21. A method for driving a display device, wherein: The display device displays an image based on an image signal corresponding to each of a plurality of frames, and the driving method includes: outputting a representative frequency based on n driving frequencies of n frames before one frame among the plurality of frames; outputting a compensation signal based on the representative frequency and the number of counts in the one frame; outputting a compensation data signal obtained by adding the grayscale of the image signal and the grayscale value according to the grayscale of the image signal based on a data correction lookup table storing a grayscale value according to the grayscale of the image signal, Wherein, the brightness of the image is controlled based on the compensation signal and the compensation data signal.

22. The driving method according to claim 21, wherein: Grayscale values ​​of the grayscale according to the representative frequency and the image signal are stored in the data correction lookup table.

23. The driving method according to claim 21, wherein: A grayscale value according to the grayscale of the image signal and a previous driving frequency of a frame before the one frame among the plurality of frames is stored in the data correction lookup table.

24. The driving method according to claim 23, wherein: The output of the compensation data signal comprises: outputting the compensation data signal based on a first grayscale value when the previous driving frequency has a first frequency; When the previous driving frequency has a second frequency higher than the first frequency, the compensation data signal is output based on the gray value having a second gray value smaller than the first gray value.

25. The driving method according to claim 21, wherein: The driving method further includes: receiving the compensation signal; and A voltage level of a voltage to be supplied to each of the plurality of pixels is adjusted based on the compensation signal.

26. The driving method according to claim 25, wherein: As the count number increases, the voltage level of the voltage increases.

27. The driving method according to claim 21, wherein: The driving method further includes: receiving the compensation signal; and A pulse width of an emission signal to be provided to each of the plurality of pixels is adjusted based on the compensation signal.

28. The driving method according to claim 27, wherein: As the count number increases, the width of the pulse width becomes narrower.

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