Multiplexer, driving chip and display device

Abstract

The invention provides a multiplexer, a driving chip and a display device, the multiplexer comprises a plurality of selection paths located between an input end and a plurality of output ends, each selection path comprises a first switch tube, the first end and the second end of the first switch tube are respectively connected with the input end and the output end, the control end receives a selection control signal, and the first switch tube is connected with the input end and the output end of the first switch tube; the switch-on and switch-off of the selection path are controlled; the energy storage unit is connected to the control end of the first switching tube, collects and stores charges before the control end is converted from the high level to the low level, and releases the charges to the control end before the control end is converted from the low level to the high level; and the switch unit controls transfer of charges between the energy storage unit and the control end through on and off of the switch unit. According to the multiplexer and the application thereof, through the arrangement of the switch unit and the energy storage unit, charges at the control end of the first switch tube are stored and reused, the turn-on and turn-off speed of the first switch tube is increased, and the effect of saving electricity is achieved while the response speed is increased.

Description

Technical Field

[0001] The present application relates to the field of display driving technology, and in particular to a multiplexer, a driving chip and a display device. Background Art

[0002] The display device generally includes a display panel, a gate driver and a source driver. The display panel includes a pixel array, and each unit in the pixel array includes a sub-pixel unit. The gate driver is connected to the sub-pixel units of the corresponding rows via a plurality of scan lines, and is used to provide a driving voltage in a scanning manner, so as to select the sub-pixel units of different rows in an image frame cycle. The source driver is connected to the sub-pixel units of the corresponding columns via a plurality of data lines, and is used to provide pixel data to the plurality of sub-pixel units of each column when the plurality of thin film transistors of each row are selected. In the selected state, the source driver applies the grayscale voltage to the sub-pixel unit via the data line to realize the control of the display screen. The control can be realized in the above manner for both OLED type display devices and LED type display devices.

[0003] In order to save the number of output buffers at the output end of the source driver, multiple MUXs (multiplexers or multiplexers) are set between the output buffers and the data lines. Through MUX, one output buffer can control the data reception of multiple data lines. In the MUX circuit, the transistor needs to be turned on and off by selecting a signal to realize the conduction and disconnection of the selected path, which will increase power consumption, and its conduction impedance is large, which reduces the charging speed. Summary of the invention

[0004] In order to solve the above technical problems, the present application provides a multiplexer, a driving chip and a display device.

[0005] According to one aspect of the present invention, a multiplexer is provided, comprising an input terminal and a plurality of output terminals, wherein a selection path is formed between each output terminal and the input terminal, and each selection path comprises: a first switch tube, wherein a first terminal and a second terminal of the first switch tube are respectively connected to the input terminal and the output terminal, and a control terminal of the first switch tube receives a selection control signal, and controls the on and off of the selection path according to the selection control signal; an energy storage unit, connected to the control terminal of the first switch tube, collecting and storing charges at the control terminal before the control terminal of the first switch tube changes from a high level to a low level, and releasing charges to the control terminal of the first switch tube before the control terminal changes from a low level to a high level; and a switch unit, connected to the control terminal of the first switch tube, controlling the transfer of charges between the energy storage unit and the control terminal by turning on and off itself.

[0006] Optionally, the first switch tube includes a PMOS tube or an NMOS tube, and the first switch tube is alternately turned on and off according to the control of the selection control signal.

[0007] Optionally, the switch unit includes: a first switch, connected between the control end of the first switch tube and the energy storage unit, to control the transfer of charge; and a second switch, connected between the control end of the first switch tube and the supply end of the selection control signal, to control the moment when the selection control signal is provided to the control end to control the conduction and shutdown of the first switch tube, wherein the switching state of the first switch is opposite to the switching state of the second switch.

[0008] Optionally, when the first switch is turned on and the selection control signal changes from invalid to valid, the charge at the control end of the first switch tube is collected and stored; when the first switch is turned on and the selection control signal changes from valid to invalid, the stored charge is released to the control end of the first switch tube; and during the period when the first switch is turned off, the selection control signal is transmitted to the control end of the first switch tube through the second switch, and the turning on and off of the first switch tube is controlled by the selection control signal. When the selection control signal is invalid, the first switch tube is turned off, and when the selection control signal is valid, the first switch tube is turned on.

[0009] Optionally, the first switch tube is a PMOS tube, and when the control end of the first switch tube is at a high level, the PMOS tube is disconnected, and before the high level of the control end of the PMOS tube is changed to a low level, the first switch is controlled to be turned on and the second switch is disconnected, and part of the charge at the control end of the PMOS tube is transferred to the energy storage unit; when the control end of the first switch tube is at a low level, the PMOS tube is turned on, and before the low level of the control end of the PMOS tube is changed to a high level, the first switch is controlled to be turned on and the second switch is disconnected, and the charge on the energy storage unit is transferred to the control end of the PMOS tube.

[0010] Optionally, the first switch tube is an NMOS tube. When the control end of the first switch tube is at a high level, the NMOS tube is turned on. Before the high level of the control end of the NMOS tube is changed to a low level, the first switch is controlled to be turned on and the second switch is turned off, and part of the charge at the control end of the NMOS tube is transferred to the energy storage unit; when the control end of the first switch tube is at a low level, the NMOS tube is turned off. Before the low level of the control end of the NMOS tube is changed to a high level, the first switch is controlled to be turned on and the second switch is turned off, and the charge on the energy storage unit is transferred to the control end of the NMOS tube.

[0011] Optionally, the energy storage unit includes a capacitor, and the capacitor is connected between the first switch and a ground terminal.

[0012] Optionally, each of the selection paths further includes a second switch tube, a first end and a second end of the second switch tube are respectively connected to the input end and the output end, a control end of the second switch tube is connected to the control end of the first switch tube through the first switch, and the energy storage unit includes the control end of the second switch tube.

[0013] Optionally, each of the selection paths further includes: a third switch, the control end of the second switch tube receives an inverted signal of the selection control signal through the third switch, and the second switch tube is turned on and off synchronously with the first switch tube.

[0014] Optionally, the first switch tube is one of a PMOS tube and an NMOS tube, and the second switch tube is the other of a PMOS tube and an NMOS tube.

[0015] According to another aspect of the present invention, a driving chip is provided, comprising: a source driver, which provides pixel data according to image data and transmits data with data lines of a display area; and the above-mentioned multiplexer, wherein the source driver is connected to a plurality of the data lines through the multiplexer, and a pixel array of the display area is controlled through the plurality of the data lines.

[0016] Optionally, the driver chip includes a display driver chip and a touch and display driver integrated chip.

[0017] According to another aspect of the present invention, there is provided a display device, comprising: a display panel, the display panel comprising a pixel array and a plurality of data lines, the pixel array comprising a plurality of columns of sub-pixel units, each data line being connected to a column of sub-pixel units; and the above-mentioned multiplexer, the input end of the multiplexer being connected to a source driver, the output end of the multiplexer being connected to the plurality of data lines, the pixel array being controlled via the plurality of data lines, wherein the source driver and the multiplexer are integrated in the same chip and are located outside the display panel.

[0018] The beneficial effects of this application include at least:

[0019] The embodiment of the present application provides a multiplexer, a driver chip and a display device. By setting a switch unit and an energy storage unit in each selection path of the multiplexer, the switch unit controls the connection path between the energy storage unit and the first switch tube, and controls the signal reception of the control end of the first switch tube, while the energy storage unit realizes the collection and reuse of the charge at the control end of the first switch tube. Through the operation of the switch unit, the charge at the control end of the first switch tube is collected and stored before the control end of the first switch tube changes from a high level to a low level, and the charge is released to the control end of the first switch tube before the control end of the first switch tube changes from a low level to a high level, thereby reducing the electric energy required to drive the first switch tube. Thereby, the cyclic collection and utilization of charge is realized, energy recovery is realized, and the effect of power saving is achieved.

[0020] Furthermore, the first switch tube includes a PMOS tube or an NMOS tube, and the energy storage unit may include a capacitor or a gate of a second switch tube connected in parallel with the first switch tube, so that different forms of multiplexers can be provided. When the capacitor is selected as the energy storage unit, the charge storage effect is good and the performance is stable. When the gate of the second switch tube is selected as the energy storage unit, the circuit is simple, the occupied area is small, and the cost is low. Further, when the gate of the second switch tube is selected as the energy storage unit, the second switch tube is turned on synchronously with the first switch tube, that is, the second switch tube and the first switch tube jointly control the conduction and disconnection of the selection path, which can reduce the conduction impedance. The second switch tube has the function of storing charge while realizing the conduction control, which further optimizes the performance of the multiplexer.

[0021] It should be noted that the above general description and the following detailed description are merely exemplary and explanatory and do not limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A schematic diagram showing the application of a multiplexer in a display device is shown;

[0023] Figure 2 Shows Figure 1 Schematic diagram of waveforms of various signals in the multiplexer;

[0024] Figure 3 A circuit diagram of a multiplexer according to a first embodiment of the present invention is shown;

[0025] Figure 4 Shows Figure 3 Schematic diagram of waveforms of various signals in the multiplexer;

[0026] Figure 5 shows a circuit diagram of a multiplexer according to a second embodiment of the present invention;

[0027] Figure 6 Shows Figure 5Schematic diagram of waveforms of various signals in the multiplexer;

[0028] Figure 7 A schematic diagram of a driving chip and a display device according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0029] In order to facilitate understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. The drawings provide preferred embodiments of the present application. However, the present application can be implemented in different forms and is not limited to the embodiments described herein.

[0030] References to "one embodiment" or "some embodiments" etc. described in this specification mean that a particular feature, structure or characteristic described in conjunction with the embodiment is included in one or more embodiments of the present application. Thus, the statements "in one embodiment", "in some embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in another way. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in another way. "Multiple" means two or more than two.

[0031] In addition, the same figure marks in the figures represent the same or similar structures, and thus their repeated description will be omitted. That is, the various parts in this specification are described in a combination of parallel and progressive manners, and each part focuses on the differences from other parts. The same or similar parts between the various parts can be referenced to each other.

[0032] Figure 1 shows a schematic diagram of the application of a multiplexer in a display device, Figure 2 Shows Figure 1 Schematic diagram of the waveforms of each signal in the multiplexer.

[0033] like Figure 1As shown, the display device includes a pixel array 10, a source driver 20 and a plurality of multiplexers 30. Since the present embodiment focuses on the function and use of the multiplexer, a series of devices such as a gate driver, a timing controller and an interface unit are omitted in the figure. In the present embodiment, the pixel array 10 includes a plurality of sub-pixel units 11, each of which can be displayed as one of a plurality of primary colors, and the primary colors can include at least one of red, green, blue and white. For example, a column of pixel units composed of red pixels and blue pixels and a column of pixel units composed of green pixels are alternately distributed, and each column of pixel units is connected to the source driver 20 via a data line (S1-S6). The source driver 20 is used to provide pixel data O1, O2, O3..., and drive the pixel units of the corresponding column via the data line. The output end of the source driver 20 is connected to an output buffer circuit 42, and the output buffer circuit 42 includes a plurality of buffers to realize processing such as amplification of pixel data. A plurality of multiplexers 30 are also provided between the output buffer circuit 42 and the data line. The multiplexer is, for example, 1:2, ie, one input terminal and two output terminals, so that the number of buffers can be half of that of the data line, thus saving a large number of buffers.

[0034] Each multiplexer 30 includes two transistors, such as transistor P1 and transistor P2, which are connected to data lines S1 and S2 respectively as two selection paths. The multiplexer 30 receives selection signals MUX1 and MUX2 through an external output buffer circuit 41, and controls the on and off of the internal transistors P1 and P2 respectively through the selection signals MUX1 and MUX2, that is, controls the on and off of the two selection paths. The circuit structures and connection methods of other multiplexers are similar and are not described here one by one.

[0035] pass Figure 2 It can be seen that the selection signals MUX1 and MUX2 are basically in opposite states. When the selection signal MUX1 is at a low level, the voltage Vgp at the control end of the transistor P1 is pulled to a low level, and the selection path is turned on. When the selection signal MUX2 is at a high level, the voltage Vgp at the control end of the transistor P1 is pulled to a high level, and the selection path is turned off. When the selection signal MUX2 is at a high level, the voltage Vgp at the control end of the transistor P1 is pulled to a high level, and the selection path is turned off. When the selection signal MUX1 is at a low level, the path where the transistor P2 is turned on. Thus, the pixel data O1 is provided to the data lines S1 and S2 in a time-sharing manner to drive the pixel units of the corresponding columns. Figure 2 In the process, the signal MUX1 needs to be selected each time to pull up or down the voltage of the control terminal of the transistor, which consumes a lot of electric energy, and the electric energy cannot be recycled, resulting in a great waste.

[0036] The present invention improves the multiplexer and proposes Figure 3-Figure 7A multiplexer, a driving chip and a display device using the same are described in detail below with reference to the accompanying drawings.

[0037] Figure 3 FIG. 4 shows a circuit diagram of a multiplexer according to a first embodiment of the present invention, Figure 4 Shows Figure 3 Schematic diagram of the waveforms of each signal in the multiplexer.

[0038] like Figure 3 As shown, the multiplexer 210 of this embodiment is replaced Figure 1 The multiplexer 30 in the embodiment is not described here. The same parts are not introduced here. The multiplexer 210 of this embodiment includes an input terminal and multiple output terminals, and two output terminals are taken as an example here. There is a selection path between each output terminal and the input terminal, and this embodiment includes two selection paths (selection path 220 and selection path 230). Each selection path includes a first switch tube, a switch unit 221 and an energy storage unit 222. Taking the selection path 220 as an example, the first end and the second end of the first switch tube P1 are respectively connected to the input terminal and the output terminal, and the control end of the first switch tube P1 receives the selection control signal (MUX1), and controls the conduction and shutdown of the selection path 220 according to the selection control signal (MUX1). The energy storage unit 222 is connected to the control end of the first switch tube P1, collects and stores the charge of the control end before the control end of the first switch tube P1 changes from a high level to a low level, and releases the charge to the control end of the first switch tube P1 before the control end of the first switch tube P1 changes from a low level to a high level. Thus, before the level of the control end of the first switch tube needs to be lowered, its charge is first transferred away, and before the level of the control end of the first switch tube needs to be raised, its charge is first replenished, thereby reducing the electric energy required to drive the first switch tube. The switch unit 221 is connected to the control end of the first switch tube P1, and controls the transfer of charge between the energy storage unit 222 and the control end of the first switch tube P1 by its own conduction and disconnection. The first switch tube includes a PMOS tube or an NMOS tube, which is alternately turned on and off according to the control of the selection control signal MUX1, and transfers charge before turning off again after turning on, or before turning on again after turning off. When a PMOS tube is used as the first switch tube, its control end receives Figure 2 The MUX1 in the circuit is used as the selection control signal. When the NMOS tube is used as the first switch tube, its control terminal receives Figure 2 The inverted signal of MUX1 is used as the selection control signal. Figure 3 In the figure, a PMOS tube is used as the first switch tube as an example, but an NMOS tube can also be used as the first switch tube.

[0039] Furthermore, in this embodiment, the switch unit 221 includes a first switch K1 and a second switch K2, and the first switch K1 is connected between the control end of the first switch tube P1 and the energy storage unit 222 to control the transfer of charge. The second switch K2 is connected between the control end of the first switch tube P1 and the supply end of the selection control signal MUX1 to control the moment when the selection control signal MUX1 is provided to the control end of the first switch tube P1 to control the on and off of the first switch tube P1. The switch state of the first switch K1 is opposite to the switch state of the second switch K2, that is, when the first switch K1 is turned on, the second switch K2 is turned off, and when the first switch K1 is turned off, the second switch K2 is turned on, which can be achieved by the switch control signals corresponding to the two switches respectively. When the first switch K1 is turned on and the selection control signal MUX1 changes from invalid to valid, the charge at the control end of the first switch tube P1 is collected and stored; when the first switch K1 is turned on and the selection control signal MUX1 changes from valid to invalid, the stored charge is released to the control end of the first switch tube P1, the first switch tube P1 is turned off when the selection control signal MUX1 is invalid, and the first switch tube P1 is turned on when the selection control signal MUX1 is valid. During the period when the first switch K1 is turned off, the selection control signal MUX1 is transmitted to the control end of the first switch tube P1 through the second switch K2, and the first switch tube P1 is turned on and off by the selection control signal MUX1.

[0040] Specifically, Figure 3In the embodiment, the first switch tube is a PMOS tube. When the control end of the first switch tube P1 is at a high level, it is disconnected. After it is stable, before the high level of the control end of the PMOS tube is changed to a low level, the first switch K1 is turned on and the second switch K2 is turned off by the switch control signals RE and REB, and part of the charge on the control end of the PMOS tube is transferred to the energy storage unit 222. After that, the first switch K1 is turned off and the second switch K2 is turned on. The control signal MUX1 is selected to pull the control end of the PMOS tube to a low level. Since part of the charge has been transferred to the energy storage unit 222, it is easy to lower the level of the control end of the first switch tube P1, and less electric energy is consumed. When the control end of the first switch tube P1 is at a low level, it is turned on. After it is stable, before the low level of the control end of the PMOS tube is changed to a high level, the first switch K1 is turned on and the second switch K2 is turned off by the switch control signals RE and REB, and the charge on the energy storage unit 222 is transferred to the control end of the PMOS tube. Thus, after the first switch K1 is turned off and the second switch K2 is turned on, the control signal MUX1 is selected to pull the control end of the PMOS tube to a high level, and the control end can be quickly pulled high. Similarly, when the first switch tube is an NMOS tube, the NMOS tube is turned on when the control end of the first switch tube is at a high level, and before the high level of the control end of the NMOS tube is changed to a low level, the first switch K1 is controlled to be turned on and the second switch K2 is turned off so that part of the charge at the control end of the NMOS tube is transferred to the energy storage unit 222; and when the control end of the first switch tube is at a low level, the NMOS tube is turned off, and before the low level of the control end of the NMOS tube is changed to a high level, the first switch K1 is controlled to be turned on and the second switch K2 is turned off so that the charge on the energy storage unit 222 is transferred to the control end of the NMOS tube. Thus, the collection and reuse of charges can be realized, that is, the recycling of charges can be realized, and the effect of power saving can be achieved.

[0041] Furthermore, in this embodiment, the energy storage unit 222 includes a capacitor connected between the first switch K1 and the ground terminal, and the type and quantity of the capacitor can be determined according to actual conditions. Using a capacitor to implement the energy storage unit can make the charge be collected and released faster, and the performance is higher.

[0042] like Figure 4As shown, before time t1, the selection control signal MUX1 is at a high level, the switch control signal RE is at a low level, the switch control signal REB is at a high level, the first switch K1 is disconnected, the second switch K2 is turned on, the level of the control end of the first switch tube P1 is pulled up, and the transistor is in the off state. At time t1, the switch control signal RE is at a high level, the switch control signal REB is at a low level, the first switch K1 is turned on, the second switch K2 is disconnected, and the charge at the control end of the first switch tube P1 begins to be partially transferred to the capacitor, and the voltage on the capacitor is Vc when it is stable. After time t1 and before time t2, the selection control signal MUX1 jumps to a low level. At time t2, the switch control signal RE is at a low level, the switch control signal REB is at a high level, the first switch K1 is disconnected, the second switch K2 is turned on, the level of the control end of the first switch tube P1 is pulled down, and the transistor is in the on state. At time t3, the switch control signal RE is at a high level, the switch control signal REB is at a low level, the first switch K1 is turned on, the second switch K2 is turned off, and the charge on the capacitor begins to transfer to the control end of the first switch tube P1. After time t3 and before time t4, the selection control signal MUX1 jumps to a high level. At time t4, the switch control signal RE is at a low level, the switch control signal REB is at a high level, the first switch K1 is turned off, the second switch K2 is turned on, the level of the control end of the first switch tube P1 is pulled high, and the transistor is in the off state. The above process is repeated to achieve repeated recycling of charge.

[0043] Figure 5 shows a circuit diagram of a multiplexer according to a second embodiment of the present invention, Figure 6 Shows Figure 5 Schematic diagram of the waveforms of each signal in the multiplexer.

[0044] like Figure 5 As shown, the multiplexer of this embodiment also includes two or more selection paths, each of which includes a first switch tube, a switch unit and an energy storage unit. Taking the selection path 220 as an example, it includes a first switch tube P1, a switch unit 221 and an energy storage unit 222. The switch unit 221 includes a first switch K1 and a second switch K2. Figure 3The same parts are not repeated. The difference is that, in this embodiment, the selection path 220 also includes a second transistor N1, the first end and the second end of the second switch tube N1 are connected to the input end and the output end respectively, the control end of the second switch tube N1 is connected to the control end of the first switch tube P1 through the first switch K1, and the control end of the second switch tube N1 serves as an energy storage unit 222. Charge is transferred between the control end of the first switch tube and the control end of the second switch tube. In addition, the second switch tube N1 can also control the on and off of the selection path, that is, the second switch tube N1 is synchronously turned on and off with the first switch tube P1, which can reduce the on-resistance. Furthermore, the switch unit 221 also includes a third switch K3, and the control end of the second switch tube N1 receives the inverted signal of the selection control signal MUX1 through the third switch K3. For example, the selection control signal MUX1 is connected to the control end of the second transistor N1 through the third switch K3 after passing through the inverter. The third switch K3 receives the same switch control signal REB as the second switch K2, and is synchronously turned on and off.

[0045] In this embodiment, the types of the first switch tube and the second transistor are opposite, that is, the first switch tube is one of the PMOS tube and the NMOS tube, and the second switch tube is the other of the PMOS tube and the NMOS tube. Here, the first switch tube P1 is taken as a PMOS tube and the second switch tube N1 is an NMOS tube. Of course, the NMOS tube can also be regarded as the first switch tube N1, and the PMOS tube can be regarded as the second switch tube P1. Then, the charge at the control end of the first switch tube can be transferred to the control end of the second switch tube, and the charge at the control end of the second switch tube can also be transferred to the control end of the first switch tube. That is, with any one of the switch tubes as the first switch tube, the control end of the other switch tube can be regarded as an energy storage unit, and the charge is transferred between the control ends of the two switch tubes, and the driving power when the two switch tubes are turned on can be reduced. The following is combined with Figure 6 The waveform diagram is used to illustrate.

[0046] like Figure 6As shown, before time t1, the selection control signal MUX1 is at a high level, the switch control signal RE is at a low level, the switch control signal REB is at a high level, the first switch K1 is disconnected, the second switch K2 and the third switch K3 are turned on, the level of the control end of the first switch tube P1 is pulled up, and the level of the control end of the second switch tube N1 is pulled down, and both the PMOS tube and the NMOS tube are in the off state. At time t1, the switch control signal RE is at a high level, the switch control signal REB is at a low level, the first switch K1 is turned on, the second switch K2 and the third switch K3 are disconnected, and the charge at the control end of the first switch tube P1 begins to be partially transferred to the control end of the second switch tube N1, and the potentials of the two are the same. After time t1 and before time t2, the selection control signal MUX1 jumps to a low level. At time t2, the switch control signal RE is at a low level, the switch control signal REB is at a high level, the first switch K1 is turned off, the second switch K2 and the third switch K3 are turned on, the level of the control end of the first switch tube P1 is pulled down and the level of the control end of the second switch tube N1 is pulled up, the PMOS tube and the NMOS tube are both in the on state, and the selection path 220 is turned on. In this process, due to the transfer of charge, the potentials of the control ends of the two transistors are at an intermediate potential, so that the transistors can be turned on quickly, and the selection control signal MUX1 only needs to drive the potential of the control end from the intermediate potential to a high level, or from the intermediate potential to a low level, saving a lot of electric energy and achieving the purpose of power saving. Afterwards, at time t3, the switch control signal RE is at a high level, the switch control signal REB is at a low level, the first switch K1 is turned on, the second switch K2 and the third switch K3 are turned off, and the charge on the control end of the second switch tube N1 begins to transfer to the control end of the first switch tube P1, and the two stop when their potentials reach the same, and both are at an intermediate potential. After time t3 and before time t4, the selection control signal MUX1 jumps to a high level. At time t4, the switch control signal RE is at a low level, the switch control signal REB is at a high level, the first switch K1 is disconnected, the second switch K2 and the third switch K3 are turned on, the level of the control end of the first switch tube P1 is pulled up from the middle potential, the level of the control end of the second switch tube N1 is pulled down from the middle potential, the PMOS tube and the NMOS tube are both in the off state, and the selection path 220 is turned off. In this process, the potentials of the two control ends are at the middle potential, which can be quickly pulled up or down to achieve a fast response. The selection control signal MUX1 only needs to drive the potential of the control end from the middle potential to a high level, or from the middle potential to a low level, saving a lot of electric energy. The above process is then repeated to achieve repeated recycling of charges.

[0047] In this embodiment, the second switch tube can not only be used as an energy storage unit to store charge, but also as a conduction control unit for the selection path, making it easier to turn on and off the two switch tubes, and reducing the conduction impedance on the selection path. Selecting the second switch tube to replace the capacitor can reduce the circuit area, reduce costs, and reduce the conduction impedance, making it easier to turn on and off the selection path, and improving the response speed.

[0048] Figure 7 A schematic diagram of a driving chip and a display device according to an embodiment of the present invention is shown.

[0049] The multiplexer of this embodiment can also be integrated into a driver chip, such as Figure 7 As shown, the driver chip 200 includes a source driver 201, an output selection circuit 202 and a timing controller 203. In some embodiments, it may also include a gate driver 204. The driver chip 200 is located outside the display panel 100. The output selection circuit 202 includes Figure 3-Figure 6 Any multiplexer shown. The source driver 201 provides pixel data Data according to the image data, and transmits data with the data lines of the display area. The output end of the source driver 201 is connected to multiple data lines S1, S2...Sm via the output selection circuit 202, and the pixel array of the display area 100 is controlled through the multiple data lines. The gate driver 204 is connected to the pixel array of the display area 100 through multiple scan lines G1, G2...Gn. The driver chip can be a display driver chip used in a display device, or the driver chip can be a touch and display driver integrated chip, that is, a TDDI (Touch and Display Driver Integration) chip.

[0050] The present embodiment also provides a display device, which includes a display panel and a driver chip 200, wherein the driver chip 200 is located outside the display panel. The display panel includes a display area 100 and a plurality of data lines, wherein the display area 100 includes a pixel array, wherein the pixel array includes a plurality of columns of sub-pixel units, and each data line is connected to a column of sub-pixel units. A sub-pixel unit 101 is shown in the figure, and the actual sub-pixel units 101 are arranged in an array.

[0051] The multiplexer and the driver chip and display device using the same of the embodiment of the present invention store and reuse the charge at the control end of the first switch tube by setting the switch unit and the energy storage unit, thereby achieving power saving while improving the response speed.

[0052] Finally, it should be noted that: Obviously, the above embodiments are only examples for clearly explaining the present application, and are not intended to limit the implementation methods. For ordinary technicians in the relevant field, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived from this are still within the scope of protection of the present application.

Claims

1. A multiplexer comprising an input terminal and a plurality of output terminals, each output terminal being connected to the input terminal by a selection path, wherein: Each of the selected paths comprises: a first switch tube, wherein a first end and a second end of the first switch tube are respectively connected to the input end and the output end, and a control end of the first switch tube receives a selection control signal, and controls the on and off of the selection path according to the selection control signal; an energy storage unit connected to the control end of the first switch tube, collecting and storing charges at the control end before the control end changes from a high level to a low level, and releasing the charges to the control end of the first switch tube before the control end changes from a low level to a high level; and The switch unit is connected to the control end of the first switch tube, and controls the transfer of charge between the energy storage unit and the control end of the first switch tube by turning itself on and off.

2. The multiplexer according to claim 1, wherein: The first switch tube includes a PMOS tube or an NMOS tube, and the first switch tube is alternately turned on and off according to the control of the selection control signal.

3. The multiplexer according to claim 1, wherein: The switch unit comprises: a first switch connected between the control end of the first switch tube and the energy storage unit to control the transfer of charge; and a second switch connected between the control terminal of the first switch tube and the supply terminal of the selection control signal, controlling the moment when the selection control signal is provided to the control terminal of the first switch tube to control the on and off of the first switch tube, The switching state of the first switch is opposite to the switching state of the second switch.

4. The multiplexer according to claim 3, wherein: When the first switch is turned on and the selection control signal changes from invalid to valid, collecting and storing the charge at the control end of the first switch tube; When the first switch is turned on and the selection control signal changes from valid to invalid, releasing the stored charge to the control end of the first switch tube; During the period when the first switch is turned off, the selection control signal is transmitted to the control end of the first switch tube through the second switch, and the first switch tube is turned on and off by the selection control signal. When the selection control signal is invalid, the first switch tube is turned off, and when the selection control signal is valid, the first switch tube is turned on.

5. The multiplexer according to claim 3, wherein: The first switch tube is a PMOS tube, and the PMOS tube is disconnected when the control terminal of the first switch tube is at a high level. Before the high level of the control terminal of the PMOS tube changes to a low level, the first switch is controlled to be turned on and the second switch is turned off, and part of the charge at the control terminal of the PMOS tube is transferred to the energy storage unit; The PMOS tube is turned on when the control end of the first switch tube is at a low level, and the first switch is controlled to be turned on and the second switch is turned off before the low level of the control end of the PMOS tube is changed to a high level, and the charge on the energy storage unit is transferred to the control end of the PMOS tube.

6. The multiplexer according to claim 3, wherein: The first switch tube is an NMOS tube, and the NMOS tube is turned on when the control terminal of the first switch tube is at a high level. Before the high level of the control terminal of the NMOS tube changes to a low level, the first switch is controlled to be turned on and the second switch is turned off, and part of the charge at the control terminal of the NMOS tube is transferred to the energy storage unit; When the control end of the first switch tube is at a low level, the NMOS tube is turned off. Before the low level of the control end of the NMOS tube changes to a high level, the first switch is controlled to be turned on and the second switch is turned off, and the charge on the energy storage unit is transferred to the control end of the NMOS tube.

7. The multiplexer according to any one of claims 3 to 6, wherein: The energy storage unit includes a capacitor connected between the first switch and a ground terminal.

8. The multiplexer according to any one of claims 3 to 6, wherein: Each of the selection paths further comprises: A second switch tube, wherein the first end and the second end of the second switch tube are respectively connected to the input end and the output end, the control end of the second switch tube is connected to the control end of the first switch tube through the first switch, and the energy storage unit includes the control end of the second switch tube.

9. The multiplexer according to claim 8, wherein: Each of the selection paths further comprises: The third switch, the control end of the second switch tube receives the inverted signal of the selection control signal through the third switch, and the second switch tube is turned on and off synchronously with the first switch tube.

10. The multiplexer according to claim 9, wherein: The first switch tube is one of a PMOS tube and an NMOS tube, and the second switch tube is the other of a PMOS tube and an NMOS tube.

11. A driver chip, wherein: include: A source driver provides pixel data according to image data and performs data transmission with the data lines of the display area; as well as According to the multiplexer according to any one of claims 1-10, the source driver is connected to the plurality of data lines through the multiplexer, and the pixel array of the display area is controlled through the plurality of data lines.

12. The driver chip according to claim 11, wherein: The driving chip includes a display driving chip and a touch control and display driving integrated chip.

13. A display device, wherein: include: A display panel, the display panel comprising a pixel array and a plurality of data lines, the pixel array comprising a plurality of columns of sub-pixel units, each data line being connected to a column of sub-pixel units; as well as The multiplexer according to any one of claims 1 to 10, wherein the input end of the multiplexer is connected to a source driver, the output end of the multiplexer is connected to a plurality of the data lines, and the pixel array is controlled through the plurality of the data lines. The source driver and the multiplexer are integrated in the same chip and are located outside the display panel.

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