Memory device

Abstract

The invention relates to a divisional application of which the application number is 2021111607662. The invention discloses a memory device which comprises a first chip and a second chip, the first chip comprises a first memory array and a second memory array, the first memory array comprises at least one first memory block, and the second memory array comprises at least one second memory block. The first storage array comprises at least one first storage block, the first storage block comprises a plurality of first word lines extending in the first direction and a plurality of first bit lines extending in the second direction, and the second storage array comprises at least one second storage block; a first global bit line sub-decoder block is located in a first overlook projection area formed by a first storage block, and a second global bit line sub-decoder block is located in a second overlook projection area formed by a second storage block, so that the occupied area after a first chip and a second chip are stacked can be reduced; and therefore, the occupied area of the memory device is reduced, and the minimum size of the memory device can be realized.

Description

[0001] This application is a divisional application of the invention patent with application number "2021111607662", application date "2021.09.30", and name "Memory device and preparation method thereof". Technical Field

[0002] The present application relates to the field of storage technology, and in particular to a storage device and a method for preparing the same. Background Art

[0003] like Figure 1 As shown, the memory device in the conventional technical solution includes a plurality of memory blocks 510, a plurality of local bit line decoders 520, a plurality of word line decoders 540, a plurality of global bit line decoders 530 and other circuits 550, wherein the construction areas of the memory blocks 510, the construction areas of the local bit line decoders 520, the construction areas of the word line decoders 540, the construction areas of the global bit line decoders 530 and the construction areas of the other circuits 550 do not overlap with each other, for example, the construction area of ​​the local bit line decoders 520 is located on one side of the construction area of ​​the corresponding memory blocks 510, the word line decoders 540 are located on the other side of the construction area of ​​the corresponding local bit line decoders 520 and / or the construction area of ​​the memory blocks 510, and the construction area of ​​the global bit line decoder 530 is located between the construction area of ​​the corresponding local bit line decoders 520 and the construction area of ​​the global bit line decoder 530.

[0004] Specifically, Figure 2 As shown, along a certain direction, the storage blocks 510 and the local bit line decoders 520 are arranged alternately in sequence, and the last local bit line decoder 520 is followed by the global bit line decoder 530 and multiple sense amplifiers 551 in sequence. A word line decoder 540 is arranged on the other side of each storage block 510. Each local bit line decoder 520 is electrically connected to the corresponding storage block 510 and the global bit line decoder 530, and the output end of the global bit line decoder 530 is electrically connected to the corresponding multiple sense amplifiers 551. Similarly, Figure 2 The structural areas of the storage blocks 510, the structural areas of the local bit line decoders 520, the structural areas of the global bit line decoders 530, the structural areas of the sense amplifiers 551, and the structural areas of the word line decoders 540 do not overlap with each other.

[0005] As such, the storage device in the above-mentioned conventional technical solution needs to occupy a relatively large space to integrate the above-mentioned various structures, which is not conducive to minimizing the size of the storage device.

[0006] It should be noted that the above introduction to the background technology is only for the purpose of facilitating a clear and complete understanding of the technical solution of the present application. Therefore, it cannot be considered that the above technical solution is well known to those skilled in the art simply because it appears in the background technology of the present application. Summary of the invention

[0007] The present application provides a memory device and a method for preparing the same, so as to alleviate the technical problem that the memory device needs to occupy a large area.

[0008] In a first aspect, the present application provides a memory device, which includes a first chip and a second chip, the first chip includes a first memory array and a second memory array, the first memory array includes at least one first memory block, the first memory block includes a plurality of first word lines extending along a first direction and a plurality of first bit lines extending along a second direction, the second memory array includes at least one second memory block, the second memory block includes a plurality of second word lines extending along the first direction and a plurality of second bit lines extending along the second direction; the second chip is stacked on the first chip along a third direction, the second chip includes a logic control circuit, the logic control circuit includes a first global bit line A sub-decoder and a second global bit line sub-decoder, the first global bit line sub-decoder is electrically connected to at least one first storage block, the second global bit line sub-decoder is electrically connected to at least one second storage block, the second chip has a first top-view projection area of ​​the first storage block and a second top-view projection area of ​​the second storage block; the first global bit line sub-decoder block formed by the first global bit line sub-decoder is located in the first top-view projection area, and the second global bit line sub-decoder block formed by the second global bit line sub-decoder is located in the second top-view projection area; and in the second direction, the second top-view projection area and the first top-view projection area are arranged in sequence.

[0009] In some of the embodiments, in the second direction, the first top-view projection area and the second top-view projection area are adjacent.

[0010] In some embodiments, in the first direction, the length of the first global bit line sub-decoder block is less than or equal to the length of the first top-view projection area; in the first direction, the length of the second global bit line sub-decoder block is less than or equal to the length of the second top-view projection area.

[0011] In some of the embodiments, in the first direction, the length of the first top-view projection area is equal to the length of the second top-view projection area.

[0012] In some of the embodiments, the logic control circuit also includes a sensing amplifier circuit, which is electrically connected to the output end of the first global bit line sub-decoder and the output end of the second global bit line sub-decoder, and the sensing amplifier circuit block formed by the sensing amplifier circuit is located in the first top-view projection area and / or the second top-view projection area.

[0013] In some embodiments, the sensing amplifier circuit includes a first sensing amplifier sub-circuit and a second sensing amplifier sub-circuit, the first sensing amplifier sub-circuit is electrically connected to the output end of the first global bit line sub-decoder, and the first sensing amplifier sub-circuit block formed by the first sensing amplifier sub-circuit is located in the first top-view projection area; the second sensing amplifier sub-circuit is electrically connected to the output end of the second global bit line sub-decoder, and the second sensing amplifier sub-circuit block formed by the second sensing amplifier sub-circuit is located in the second top-view projection area.

[0014] In some embodiments, the logic control circuit also includes a first local bit line sub-decoder, the first local bit line sub-decoder includes a first local bit line decoding unit and a second local bit line decoding unit electrically connected to the first global bit line sub-decoder, a first local bit line decoding unit block formed by the first local bit line decoding unit and a second local bit line decoding unit block formed by the second local bit line decoding unit are both located within the first top-view projection area; in the second direction, the first global bit line sub-decoder block is located between the first local bit line decoding unit block and the second local bit line decoding unit block.

[0015] In some embodiments, the local bit line decoder also includes a second local bit line sub-decoder, the second local bit line sub-decoder includes a third local bit line decoding unit and a fourth local bit line decoding unit electrically connected to the second global bit line sub-decoder, the third local bit line decoding unit block formed by the third local bit line decoding unit and the fourth local bit line decoding unit block formed by the fourth local bit line decoding unit are both located in the second top-view projection area, and in the second direction, the second global bit line sub-decoder block is located between the fourth local bit line decoding unit block and the third local bit line decoding unit block.

[0016] In some embodiments, in the second direction, the fourth local bit line decoding unit block, the third local bit line decoding unit block, the second local bit line decoding unit block and the first local bit line decoding unit block are arranged in sequence; in the second direction, the distance from the first global bit line sub-decoder block to the second local bit line decoding unit block is smaller than the distance from the first global bit line sub-decoder block to the first local bit line decoding unit block; in the second direction, the distance from the second global bit line sub-decoder block to the third local bit line decoding unit block is smaller than the distance from the second global bit line sub-decoder block to the fourth local bit line decoding unit block.

[0017] In some embodiments, the logic control circuit also includes a first word line decoding unit and a second word line decoding unit, the first word line decoding unit is electrically connected to the first storage block, and a first word line decoding unit block formed by the first word line decoding unit is located in the first top-view projection area; the second word line decoding unit is electrically connected to the first storage block, and a second word line decoding unit block formed by the second word line decoding unit is located in the first top-view projection area; wherein, in the first direction, the projection of the first word line decoding unit block and the projection of the second word line decoding unit block at least partially overlap; and the first word line decoding unit block and the second word line decoding unit block are both located between the first global bit line sub-decoder block and the first local bit line decoding unit block.

[0018] In some of the embodiments, in a first direction, the first sense amplifier sub-circuit block is located between the first word line decoding unit block and the second word line decoding unit block; and in a second direction, the first sense amplifier sub-circuit block is located between the first global bit line sub-decoder block and the first local bit line decoding unit block.

[0019] In some embodiments, in the first direction, a projection of the first sense amplifier sub-circuit block at least partially overlaps with a projection of the first word line decoding unit block and / or a projection of the second word line decoding unit block.

[0020] In some embodiments, in the second direction, a projection of the first sense amplifier sub-circuit block does not overlap with a projection of the first word line decoding unit block and / or a projection of the second word line decoding unit block.

[0021] In some of the embodiments, the logic control circuit further includes a third word line decoding unit and a fourth word line decoding unit, the third word line decoding unit is electrically connected to the second storage block, and a third word line decoding unit block formed by the third word line decoding unit is located within the second top-view projection area; the fourth word line decoding unit is electrically connected to the second storage block, and a fourth word line decoding unit block formed by the fourth word line decoding unit is located within the second top-view projection area; wherein, in the first direction, the projection of the third word line decoding unit block at least partially overlaps with the projection of the fourth word line decoding unit block; and the third word line decoding unit block and the fourth word line decoding unit block are both located between the second global bit line sub-decoder block and the fourth local bit line decoding unit block.

[0022] In some embodiments, the first chip includes N memory blocks arranged in sequence along the second direction, the first memory array includes M memory blocks, and the second memory array includes NM memory blocks, wherein M is less than N, and M and N are both positive integers; the first top-view projection area is the projection area of ​​the Mth memory block on the second chip, and the second top-view projection area is the projection area of ​​the M+1th memory block on the second chip; the first global bit line sub-decoder is electrically connected to at least one of the first local bit line decoding unit to the 2Mth local bit line decoding unit, and the second global bit line sub-decoder is electrically connected to at least one of the 2M+1th local bit line decoding unit to the 2Nth local bit line decoding unit.

[0023] In some embodiments, M is equal to N / 2 after rounding; and the second global bit line sub-decoder block, the 2M+1 local bit line decoding unit block formed by the 2M+1 local bit line decoding unit, the 2M local bit line decoding unit block formed by the 2M local bit line decoding unit, and the first global bit line sub-decoder block are arranged adjacent to each other in sequence along the second direction.

[0024] In some of the embodiments, the memory device further includes a plurality of first routings and a plurality of second routings, the plurality of first routings being electrically connected to the first global bit line sub-decoder and the first local bit line decoding unit to the 2Mth local bit line decoding unit; the plurality of second routings being electrically connected to the second global bit line sub-decoder and the 2M+1th local bit line decoding unit to the 2Nth local bit line decoding unit.

[0025] In some embodiments, in the second direction, a projection of the second sense amplifier sub-circuit block does not overlap with a projection of the third word line decoding unit block and / or a projection of the fourth word line decoding unit block.

[0026] In a second aspect, the present application provides a method for preparing a memory device, which includes: constructing a first memory array and a second memory array on a first chip, the first memory array including at least one first memory block, the first memory block including a plurality of first word lines extending in a first direction and a plurality of first bit lines extending in a second direction, the second memory array including at least one second memory block, the second memory block including a plurality of second word lines extending in the first direction and a plurality of second bit lines extending in the second direction; constructing a logic control circuit on a second chip, the logic control circuit including a first global bit line sub-decoder and a second global bit line sub-decoder, the first global bit line The sub-decoder is electrically connected to at least one first storage block, the second global bit line sub-decoder is electrically connected to at least one second storage block, the second chip has a first top-view projection area of ​​the first storage block and a second top-view projection area of ​​the second storage block; the first global bit line sub-decoder block formed by the first global bit line sub-decoder is located in the first top-view projection area, and the second global bit line sub-decoder block formed by the second global bit line sub-decoder is located in the second top-view projection area; and in the second direction, the second top-view projection area and the first top-view projection area are arranged in sequence; and the second chip is stacked on top of the first chip along the third direction.

[0027] In some of the embodiments, the preparation method further includes: constructing a sensing amplifier circuit in a logic control circuit; electrically connecting the sensing amplifier circuit to an output end of a first global bit line sub-decoder and an output end of a second global bit line sub-decoder; and configuring the sensing amplifier circuit to form a sensing amplifier circuit block located within the first top-view projection area and / or the second top-view projection area.

[0028] In some of the embodiments, the preparation method also includes: constructing a first sensing amplifier sub-circuit and a second sensing amplifier sub-circuit in the sensing amplifier circuit; electrically connecting the first sensing amplifier sub-circuit and the output end of the first global bit line sub-decoder, and electrically connecting the second sensing amplifier sub-circuit and the output end of the second global bit line sub-decoder; and configuring the first sensing amplifier sub-circuit block formed by the first sensing amplifier sub-circuit to be located in the first top-view projection area, and configuring the second sensing amplifier sub-circuit block formed by the second sensing amplifier sub-circuit to be located in the second top-view projection area.

[0029] The memory device and preparation method provided in the present application can reduce the occupied area of ​​the first chip and the second chip after stacking by constructing a first global bit line sub-decoder block located in a first top-view projection area formed by a first memory block and a second global bit line sub-decoder block located in a second top-view projection area formed by a second memory block, thereby reducing the occupied area of ​​the memory device and contributing to minimizing the size of the memory device.

[0030] Based on the arrangement of the decoder being completely within the projection range and the stacked structure of the two chips, the decoder can be vertically connected to the storage array without the need for additional horizontal wiring, so no wiring space is required between the two sub-modules, which can further reduce the area of ​​the first chip and the second chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0032] Figure 1 A schematic diagram of the distribution of the structures of various parts in a storage device provided by a conventional technical solution.

[0033] Figure 2 Another schematic diagram of the distribution of the various parts of the storage device provided by the traditional technical solution.

[0034] Figure 3 A schematic diagram of the structural distribution of a storage device provided in an embodiment of the present application.

[0035] Figure 4 A schematic diagram of another structural distribution of a storage device provided in an embodiment of the present application.

[0036] Figure 5 for Figure 3 Schematic diagram of the structural distribution of the first sensing amplifier sub-circuit.

[0037] Figure 6 for Figure 5 Schematic diagram of the structural distribution of the second sensing amplifier sub-circuit.

[0038] Figure 7 A schematic flow chart of a method for preparing a storage device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0039] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0040] In the description of the present disclosure, the word line decoder is also described as X-DEC, and the bit line decoder can be described as a bit line selector, a bit line multiplexer or a Y-MUX, which is used to locate the majority of memory cells in the memory array for further reading and writing operations on the memory cells.

[0041] In the description of the present disclosure, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicating the orientation or position relationship indicated are all based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of simplifying the description of the present disclosure, rather than indicating or implying that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. In addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of the present disclosure, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0042] In the description of the present disclosure, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or can communicate with each other; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can be the internal connection of two components or the interaction relationship between two components. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0043] In the present disclosure, unless otherwise clearly specified and limited, a first feature being “above” or “below” a second feature may include the first feature being in direct contact with the second feature, or may include the first feature being in contact with the second feature not being in direct contact but being in contact through a third feature other than the first feature. Moreover, a first feature being “above”, “above”, and “above” a second feature may include the first feature being directly above and obliquely above the second feature, or may simply mean that the first feature is higher in level than the second feature. A first feature being “below”, “below”, and “below” a second feature may include the first feature being directly below and obliquely below the second feature, or may simply mean that the first feature is lower in level than the second feature.

[0044] See also Figures 3 to 7 ,like Figure 3As shown, this embodiment provides a memory device, which includes a first chip 100 and a second chip 200. The first chip 100 includes a first memory array 10A and a second memory array 10B. The first memory array 10A includes at least one first memory block. The first memory block 11 includes a plurality of first word lines extending along a first direction DR1 and a plurality of first bit lines extending along a second direction DR2. The second memory array 10B includes at least one second memory block. The second memory block includes a plurality of second word lines extending along the first direction DR1 and a plurality of second bit lines extending along the second direction DR2. The second chip 200 includes a logic control circuit. The logic control circuit includes a first global bit line sub-circuit. Decoder 21 and a second global bit line sub-decoder 22, the first global bit line sub-decoder 21 is electrically connected to at least one first storage block 11, and the second global bit line sub-decoder 22 is electrically connected to at least one second storage block; the second chip 200 has a first top-view projection area of ​​a first storage block and a second top-view projection area of ​​a second storage block; the first global bit line sub-decoder block formed by the first global bit line sub-decoder 21 is located in the first top-view projection area, and the second global bit line sub-decoder block formed by the second global bit line sub-decoder 22 is located in the second top-view projection area; and in the second direction DR2, the second top-view projection area and the first top-view projection area are arranged in sequence.

[0045] It can be understood that the memory device provided in this embodiment can reduce the occupied area of ​​the first chip 100 and the second chip 200 after being stacked by constructing a first global bit line sub-decoder block located in a first top-view projection area formed by the first memory block and a second global bit line sub-decoder block located in a second top-view projection area formed by the second memory block, thereby reducing the occupied area of ​​the memory device and contributing to minimizing the size of the memory device.

[0046] The logic control circuit includes a global bit line decoder 20 , and the global bit line decoder 20 includes a first global bit line sub-decoder 21 and a second global bit line sub-decoder 22 .

[0047] It should be noted that at least partial overlap in the present application may be partial overlap or full overlap. The first storage block may be any storage block in the first storage array 10A, for example, any one of the first storage block 11 to the Mth storage block 12. Specifically, the first storage block may be the Mth storage block 12. The second storage block may be any storage block in the second storage array 10B, for example, any one of the M+1th storage block 13 to the Nth storage block 14. Specifically, the second storage block may be the M+1th storage block 13. Wherein, M and N are both positive integers, and N is greater than M.

[0048] The first direction DR1 may be an extending direction of a word line, the second direction DR2 may be an extending direction of a bit line, and the third direction DR3 may be a thickness direction of the memory device.

[0049] In one embodiment, in the second direction DR2, the first top-view projection area and the second top-view projection area are adjacent. Adjacent means that the edges of the two projection areas are connected or close to each other. It can be understood that, in this way, the spatial distribution between the first global bit line sub-decoder 21, the second global bit line sub-decoder 22 and the sense amplifier circuit 50 can be more compact, which is convenient for the first global bit line sub-decoder 21 and the second global bit line sub-decoder 22 to share the same sense amplifier circuit 50, and can also reduce the electrical transmission distance from the sense amplifier circuit 50 to the first global bit line sub-decoder 21 and the second global bit line sub-decoder 22.

[0050] In one embodiment, in the first direction DR1, the length of the first global bit line sub-decoder block is less than or equal to the length of the first top-view projection area; in the first direction DR1, the length of the second global bit line sub-decoder block is less than or equal to the length of the second top-view projection area.

[0051] In one embodiment, in the first direction DR1, the length of the first top-view projection area is equal to the length of the second top-view projection area.

[0052] In one embodiment, the logic control circuit further includes a sense amplifier circuit 50, the sense amplifier circuit 50 is electrically connected to the output end of the first global bit line sub-decoder 21 and the output end of the second global bit line sub-decoder 22, and the sense amplifier circuit block formed by the sense amplifier circuit 50 is located in the first top view projection area and / or the second top view projection area. It can be understood that the memory device provided in this embodiment can further reduce the occupied area of ​​the first chip 100 and the second chip 200 after stacking by constructing the sense amplifier circuit block to be located in the first top view projection area and / or the second top view projection area, thereby reducing the occupied area of ​​the memory device and helping to minimize the size of the memory device; and shorten the distance between the sense amplifier circuit 50 and the two global bit line sub-decoders, thereby reducing the delay.

[0053] It should be noted that, in this embodiment, the first memory array 10A and the second memory array 10B can share the same sense amplifier circuit 50 .

[0054] like Figure 4As shown, in one embodiment, the sense amplifier circuit 50 includes a first sense amplifier sub-circuit 51, a second sense amplifier sub-circuit 52, a third sense amplifier sub-circuit 53 and a fourth sense amplifier sub-circuit 54. The output end of the first global bit line sub-decoder 21 is electrically connected to the first sense amplifier sub-circuit 51 and the second sense amplifier sub-circuit 52. The first sense amplifier sub-circuit block formed by the first sense amplifier sub-circuit 51 and the second sense amplifier sub-circuit block formed by the second sense amplifier sub-circuit 52 are both located in the first top-view projection area; the output end of the second global bit line sub-decoder 22 is electrically connected to the third sense amplifier sub-circuit 53 and the fourth sense amplifier sub-circuit 54. The third sense amplifier sub-circuit block formed by the third sense amplifier sub-circuit 53 and the fourth sense amplifier sub-circuit block formed by the fourth sense amplifier sub-circuit 54 are both located in the second top-view projection area.

[0055] It can be understood that in this embodiment, the first memory array 10A is electrically connected to the first sense amplifier sub-circuit 51 and the second sense amplifier sub-circuit 52 through the first global bit line sub-decoder 21, and the second memory array 10B is electrically connected to the third sense amplifier sub-circuit 53 and the fourth sense amplifier sub-circuit 54 through the second global bit line sub-decoder 22. Each memory array can use a set of sense amplifier sub-circuits separately, so that the bit line read operation of each memory array can be independently implemented.

[0056] In one embodiment, the logic control circuit further includes a local bit line decoder 30, the local bit line decoder 30 includes a first local bit line sub-decoder 30A, the first local bit line sub-decoder 30A is electrically connected to the first global bit line sub-decoder 21, the first local bit line sub-decoder 30A includes a first local bit line decoding unit 31 and a second local bit line decoding unit 32, a first local bit line decoding unit block formed by the first local bit line decoding unit 31 and a second local bit line decoding unit block formed by the second local bit line decoding unit 32 are both located within the first top-view projection area; in the second direction DR2, the first global bit line sub-decoder block is located between the first local bit line decoding unit block and the second local bit line decoding unit block.

[0057] It can be understood that the memory device provided in this embodiment can further reduce the occupied area of ​​the first chip 100 and the second chip 200 after being stacked by constructing the first local bit line decoding unit block and the second local bit line decoding unit block within the first top-view projection area, thereby reducing the occupied space of the memory device and helping to minimize the size of the memory device.

[0058] In some embodiments, the first global bit line sub-decoder block, the first local bit line decoding unit block and / or the second local bit line decoding unit block may be located in different layers of the same chip, and the first global bit line sub-decoder block may also at least partially overlap with the first local bit line decoding unit block and / or the second local bit line decoding unit block in the third direction DR3.

[0059] In some embodiments, the first global bit line sub-decoder block is located between the first local bit line decoding unit block and the second local bit line decoding unit block, and the first global bit line sub-decoder block does not overlap with the first local bit line decoding unit block and / or the second local bit line decoding unit block.

[0060] It should be noted that, in the present embodiment, each first storage block is electrically connected to a corresponding local bit line sub-decoder. For example, the first storage block 11 can be electrically connected to the first local bit line decoding unit 31 and the second local bit line decoding unit 32, the local bit line decoder 30 further includes the Mth local bit line sub-decoder 30B, the Mth local bit line sub-decoder 30B includes the 2M-1th local bit line decoding unit 33 and the 2Mth local bit line decoding unit 34, and the Mth storage block 12 can be electrically connected to the 2M-1th local bit line decoding unit 33 and the 2Mth local bit line decoding unit 34. Among them, the first storage block can be any storage block from the first storage block 11 to the Mth storage block 12. When the first storage block is the Mth storage block 12, the first local bit line decoding unit can be the 2M-1th local bit line decoding unit 33; the second local bit line decoding unit can be the 2Mth local bit line decoding unit 34. Similarly, the second storage block may be any one of the (M+1)th storage block 13 to the (N)th storage block 14 .

[0061] In one embodiment, the local bit line decoder 30 further includes a second local bit line sub-decoder 30C, which is electrically connected to the second global bit line sub-decoder 22. The second local bit line sub-decoder 30C includes a third local bit line decoding unit 35 and a fourth local bit line decoding unit 36. The third local bit line decoding unit block formed by the third local bit line decoding unit 35 and the fourth local bit line decoding unit block formed by the fourth local bit line decoding unit 36 ​​are both located within the second top-view projection area. In the second direction DR2, the second global bit line sub-decoder block is located between the fourth local bit line decoding unit block and the third local bit line decoding unit block.

[0062] It should be noted that, in this embodiment, each second storage block is electrically connected to a corresponding local bit line sub-decoder. For example, the second storage block can be electrically connected to the third local bit line decoding unit 35 and the fourth local bit line decoding unit 36, the second local bit line sub-decoder 30C can be the M+1th local bit line sub-decoder 30C, the M+1th local bit line sub-decoder 30C includes the 2M+1th local bit line decoding unit 35 and the 2M+2nd local bit line decoding unit 36, and the M+1th storage block 13 can be electrically connected to the 2M+1th local bit line decoding unit 35 and the 2M+ 2N-1 local bit line decoding unit 37 and 2N local bit line decoding unit 38. The N storage block 14 may be electrically connected to the 2N-1 local bit line decoding unit 37 and the 2N local bit line decoding unit 38.

[0063] In one of the embodiments, in the second direction DR2, the fourth local bit line decoding unit block, the third local bit line decoding unit block, the second local bit line decoding unit block and the first local bit line decoding unit block are arranged in sequence; in the second direction DR2, the distance from the first global bit line sub-decoder block to the second local bit line decoding unit block is smaller than the distance from the first global bit line sub-decoder block to the first local bit line decoding unit block; in the second direction DR2, the distance from the second global bit line sub-decoder block to the third local bit line decoding unit block is smaller than the distance from the second global bit line sub-decoder block to the fourth local bit line decoding unit block.

[0064] In one embodiment, the logic control circuit further includes a first word line decoding unit 41 and a second word line decoding unit 42, the first word line decoding unit 41 is electrically connected to the first storage block 11, and a first word line decoding unit block formed by the first word line decoding unit 41 is located in the first top view projection area; the second word line decoding unit 42 is electrically connected to the first storage block 11, and a second word line decoding unit block formed by the second word line decoding unit 42 is located in the first top view projection area; wherein, in the first direction DR1, the projection of the first word line decoding unit block and the projection of the second word line decoding unit block at least partially overlap; and the first word line decoding unit block and the second word line decoding unit block are both located between the first global bit line sub-decoder block and the first local bit line decoding unit block (such as Figure 4 , when M is 1 and N is 2).

[0065] It can be understood that the memory device provided in this embodiment can further reduce the occupied area of ​​the first chip 100 and the second chip 200 after being stacked by constructing the first word line decoding unit block formed by the first word line decoding unit 41 and the second word line decoding unit block formed by the second word line decoding unit 42 to be located within the first top view projection area, thereby reducing the occupied space of the memory device and helping to minimize the size of the memory device.

[0066] In some embodiments, the first word line decoding unit block and the second word line decoding unit block are both located between the first global bit line sub-decoder block and the second local bit line decoding unit block, and the first word line decoding unit block does not overlap with the first global bit line sub-decoder block and / or the second local bit line decoding unit block, and the second word line decoding unit block does not overlap with the first global bit line sub-decoder block and / or the second local bit line decoding unit block. The first word line decoding unit block also does not overlap with the second word line decoding unit block.

[0067] It should be noted that, in the present embodiment, the logic control circuit includes a word line decoder 40, the word line decoder 40 includes at least one word line sub-decoder, the word line sub-decoder may include two word line decoding units, in some embodiments, any storage block is configured with one or two corresponding word line decoding units, for example, the first word line sub-decoder 40A includes a first word line decoding unit 41 and a second word line decoding unit 42, the first storage block 11 is electrically connected to the first word line decoding unit 41 and the second word line decoding unit 42, the Mth word line sub-decoder 40B includes a 2M-1th word line decoding unit 43 and a 2Mth word line decoding unit 44, The Mth word line decoding unit 44, the Mth storage block 12 is electrically connected to the 2M-1 word line decoding unit 43 and the 2M word line decoding unit 44, the M+1th word line sub-decoder 40C includes the 2M+1th word line decoding unit 45 and the 2M+2th word line decoding unit 46, the M+1th storage block 13 is electrically connected to the 2M+1th word line decoding unit 45 and the 2M+2th word line decoding unit 46, the Nth word line sub-decoder 40D includes the 2N-1 word line decoding unit 47 and the 2N word line decoding unit 48, and the Nth storage block 14 is electrically connected to the 2N-1 word line decoding unit 47 and the 2N word line decoding unit 48.

[0068] In one embodiment, in the first direction DR1, the first sense amplifier sub-circuit block is located between the first word line decoding unit block and the second word line decoding unit block; and in the second direction DR2, the first sense amplifier sub-circuit block is located between the first global bit line sub-decoder block and the first local bit line decoding unit block.

[0069] It can be understood that in this embodiment, the first sense amplifier sub-circuit block does not overlap with the first word line decoding unit block and / or the second word line decoding unit block. Similarly, the first sense amplifier sub-circuit block does not overlap with the first global bit line sub-decoder block and / or the first local bit line decoding unit block.

[0070] In one embodiment, in the first direction DR1, the projection of the first sense amplifier sub-circuit block at least partially overlaps with the projection of the first word line decoding unit block and / or the projection of the second word line decoding unit block.

[0071] In one embodiment, in the second direction DR2, the projection of the first sense amplifier sub-circuit block does not overlap with the projection of the first word line decoding unit block and / or the projection of the second word line decoding unit block.

[0072] In one embodiment, the second chip 200 further includes a plurality of first routing lines 61 , and the plurality of first routing lines 61 are electrically connected to the first global bit line sub-decoder 21 and the first to 2M-th local bit line decoding units 31 to 34 .

[0073] In one embodiment, the second chip 200 further includes a plurality of second traces 62 , and the plurality of second traces 62 are electrically connected to the second global bit line sub-decoder 22 and the 2M+1th local bit line decoding unit 35 to the 2Nth local bit line decoding unit 38 .

[0074] Among them, the first routing line 61 and the second routing line 62 can both be global bit lines. This setting is equivalent to dividing the storage blocks into two groups (the first storage array 10A and the second storage array 10B), the first storage block 11 to the Mth storage block 12 are the first group of storage blocks (the first storage array 10A), and the M+1th storage block 13 to the Nth storage block 14 are the second group of storage blocks (the second storage array 10B). The first routing line 61 electrically connects the first group of storage blocks to the first global bit line sub-decoder 21, and the second routing line 62 electrically connects the second group of storage blocks to the second global bit line sub-decoder 22. This way of grouping the storage blocks, in conjunction with the three-dimensional bonding process (i.e., stacking / bonding the second chip 200 to the first chip 100 in the third direction), can comprehensively shorten the connection between each storage block and the global decoder / global bit line decoder 20, and also reduce the connection between the global decoder / global bit line decoder 20 and the local decoder / local bit line decoder 30, so that the chip delay is greatly reduced.

[0075] In one embodiment, the second chip 200 further includes a plurality of third traces 71 , and the plurality of third traces 71 are electrically connected to the first global bit line sub-decoder 21 and the sense amplifier circuit 50 .

[0076] In one embodiment, the second chip 200 further includes a plurality of fourth traces 72 , and the plurality of fourth traces 72 are electrically connected to the second global bit line sub-decoder 22 and the sense amplifier circuit 50 .

[0077] Among them, Figure 5 As shown, the first sense amplifier sub-circuit 51 may include a plurality of sense amplifiers arranged along a first direction DR1, for example, sense amplifier 51A, sense amplifier 51B, sense amplifier 51C, sense amplifier 51D, etc. The second sense amplifier sub-circuit 52 may also include a plurality of sense amplifiers arranged along the first direction DR1, for example, sense amplifier 52A, sense amplifier 52B, sense amplifier 52C, sense amplifier 52D, etc. The first direction DR1 may be a bit line arrangement direction of the first memory array 10A or the second memory array 10B.

[0078] Among them, Figure 6 As shown, the third sense amplifier sub-circuit 53 may include a plurality of sense amplifiers arranged along the first direction DR1, for example, sense amplifier 53A, sense amplifier 53B, sense amplifier 53C, sense amplifier 53D, etc. The fourth sense amplifier sub-circuit 54 may also include a plurality of sense amplifiers arranged along the first direction DR1, for example, sense amplifier 54A, sense amplifier 54B, sense amplifier 54C, sense amplifier 54D, etc.

[0079] In one embodiment, the Nth memory block 14 to the first memory block 11 are sequentially arranged along the second direction DR2 , and the second direction DR2 may be a word line arrangement direction of the first memory array 10A or the second memory array 10B.

[0080] In one embodiment, the first chip 100 and the second chip 200 overlap or stack along a third direction DR3. It can be understood that the third direction DR3 may be a thickness direction of the first chip 100 and the second chip 200 after being stacked.

[0081] In one embodiment, the logic control circuit further includes a third word line decoding unit and a fourth word line decoding unit, the third word line decoding unit is electrically connected to the second storage block, and a third word line decoding unit block formed by the third word line decoding unit is located within the second top-view projection area; the fourth word line decoding unit is electrically connected to the second storage block, and a fourth word line decoding unit block formed by the fourth word line decoding unit is located within the second top-view projection area; wherein, in the first direction DR1, the projection of the third word line decoding unit block at least partially overlaps with the projection of the fourth word line decoding unit block; and the third word line decoding unit block and the fourth word line decoding unit block are both located between the second global bit line sub-decoder block and the fourth local bit line decoding unit block.

[0082] In one embodiment, in the first direction DR1, the second sense amplifier sub-circuit block is located between the third word line decoding unit block and the fourth word line decoding unit block; and in the second direction DR2, the second sense amplifier sub-circuit block is located between the second global bit line sub-decoder block and the fourth local bit line decoding unit block.

[0083] In one embodiment, in the first direction DR1, the projection of the second sense amplifier sub-circuit block at least partially overlaps with the projection of the third word line decoding unit block and / or the projection of the fourth word line decoding unit block.

[0084] In one embodiment, in the second direction DR2, the projection of the second sense amplifier sub-circuit block does not overlap with the projection of the third word line decoding unit block and / or the projection of the fourth word line decoding unit block.

[0085] It should be noted that the projection of the second sense amplifier sub-circuit block does not overlap with the projection of the third word line decoding unit block and / or the projection of the fourth word line decoding unit block. This means that along the second direction, the second sense amplifier sub-circuit block may have a projection of the second sense amplifier sub-circuit block, the third word line decoding unit block may have a projection of the third word line decoding unit block, and the fourth word line decoding unit block may have a projection of the fourth word line decoding unit block; and in the second direction, the projection of the second sense amplifier sub-circuit block does not overlap with the projection of the third word line decoding unit block and / or the projection of the fourth word line decoding unit block on any plane perpendicular to the second direction.

[0086] In one embodiment, the first chip 100 includes N storage blocks arranged in sequence along the second direction DR2, the first storage array 10A includes M storage blocks, and the second storage array 10B includes NM storage blocks, wherein M is less than N, and both M and N are positive integers; the first top-view projection area is the projection area of ​​the Mth storage block 12 on the second chip 200, and the second top-view projection area is the projection area of ​​the M+1th storage block 13 on the second chip 200; the first global bit line sub-decoder 21 is electrically connected to at least one of the first local bit line decoding unit 31 to the 2Mth local bit line decoding unit 34, and the second global bit line sub-decoder 22 is electrically connected to at least one of the 2M+1th local bit line decoding unit 35 to the 2Nth local bit line decoding unit 38.

[0087] In one embodiment, M is equal to N / 2 after rounding; and the second global bit line sub-decoder block, the 2M+1 local bit line decoding unit block formed by the 2M+1 local bit line decoding unit 35, the 2M local bit line decoding unit block formed by the 2M local bit line decoding unit 34, and the first global bit line sub-decoder block are arranged adjacent to each other in sequence along the second direction DR2.

[0088] In one embodiment, the memory device further includes a plurality of first routing lines 61 and a plurality of second routing lines 62, wherein the plurality of first routing lines 61 are electrically connected to the first global bit line sub-decoder 21 and the first local bit line decoding unit 31 to the 2Mth local bit line decoding unit 34; and the plurality of second routing lines 62 are electrically connected to the second global bit line sub-decoder 22 and the 2M+1th local bit line decoding unit 35 to the 2Nth local bit line decoding unit 38.

[0089] In one embodiment, in the second direction DR2, the projection of the second sense amplifier sub-circuit block does not overlap with the projection of the third word line decoding unit block and / or the projection of the fourth word line decoding unit block.

[0090] like Figure 7 As shown, in one embodiment, this embodiment provides a method for preparing a memory device, which includes the following steps:

[0091] Step S10: construct a first memory array and a second memory array on a first chip, the first memory array includes at least one first memory block, the first memory block includes a plurality of first word lines extending along a first direction and a plurality of first bit lines extending along a second direction, the second memory array includes at least one second memory block, the second memory block includes a plurality of second word lines extending along the first direction and a plurality of second bit lines extending along the second direction.

[0092] Step S20: construct a logic control circuit on the second chip, the logic control circuit includes a first global bit line sub-decoder and a second global bit line sub-decoder, the first global bit line sub-decoder is electrically connected to at least one first storage block, the second global bit line sub-decoder is electrically connected to at least one second storage block, the second chip has a first top-view projection area of ​​the first storage block and a second top-view projection area of ​​the second storage block; the first global bit line sub-decoder block formed by the first global bit line sub-decoder is located in the first top-view projection area, and the second global bit line sub-decoder block formed by the second global bit line sub-decoder is located in the second top-view projection area; and in the second direction, the second top-view projection area and the first top-view projection area are arranged in sequence.

[0093] And step S30: stacking the second chip on the first chip along the third direction.

[0094] It can be understood that the preparation method provided in this embodiment can reduce the occupied area of ​​the first chip and the second chip after stacking by constructing a first global bit line sub-decoder block located in a first top-view projection area formed by the first storage block and a second global bit line sub-decoder block located in a second top-view projection area formed by the second storage block, thereby reducing the occupied area of ​​the storage device and helping to minimize the size of the storage device.

[0095] In one embodiment, the preparation method further includes: constructing a sensing amplifier circuit in a logic control circuit; electrically connecting the sensing amplifier circuit to an output end of a first global bit line sub-decoder and an output end of a second global bit line sub-decoder; and configuring the sensing amplifier circuit block formed by the sensing amplifier circuit to be located within the first top-view projection area and / or the second top-view projection area.

[0096] In one embodiment, the preparation method further includes: constructing a first sense amplifier sub-circuit and a second sense amplifier sub-circuit in the sense amplifier circuit; electrically connecting the first sense amplifier sub-circuit and the output end of the first global bit line sub-decoder, and electrically connecting the second sense amplifier sub-circuit and the output end of the second global bit line sub-decoder; and configuring the first sense amplifier sub-circuit block formed by the first sense amplifier sub-circuit to be located in the first top-view projection area, and configuring the second sense amplifier sub-circuit block formed by the second sense amplifier sub-circuit to be located in the second top-view projection area.

[0097] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0098] The storage device and the preparation method thereof provided in the embodiments of the present application are introduced in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solution and the core idea of ​​the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A storage device, characterized in that: include: A first chip, the first chip comprising a first memory array and a second memory array, the first memory array comprising at least one first memory block, the first memory block comprising a plurality of first word lines extending along a first direction and a plurality of first bit lines extending along a second direction, the second memory array comprising at least one second memory block, the second memory block comprising a plurality of second word lines extending along the first direction and a plurality of second bit lines extending along the second direction; A second chip is stacked on top of the first chip along a third direction, the second chip includes a logic control circuit, the logic control circuit includes a first global bit line sub-decoder and a second global bit line sub-decoder, the first global bit line sub-decoder is electrically connected to the at least one first storage block, the second global bit line sub-decoder is electrically connected to the at least one second storage block, the second chip has a first top-view projection area of ​​the first storage block and a second top-view projection area of ​​the second storage block; the first global bit line sub-decoder block formed by the first global bit line sub-decoder is located in the first top-view projection area, and the second global bit line sub-decoder block formed by the second global bit line sub-decoder is located in the second top-view projection area.

2. The memory device according to claim 1, wherein: In the second direction, the first overhead projection area and the second overhead projection area are adjacent to each other.

3. The memory device according to claim 2, wherein: In the first direction, the length of the first global bit line sub-decoder block is less than or equal to the length of the first top-view projection area; in the first direction, the length of the second global bit line sub-decoder block is less than or equal to the length of the second top-view projection area.

4. The memory device according to claim 3, wherein: In the first direction, the length of the first top-view projection area is equal to the length of the second top-view projection area.

5. The memory device according to claim 1, wherein: The logic control circuit also includes: The sense amplifier circuit is electrically connected to the output end of the first global bit line sub-decoder and the output end of the second global bit line sub-decoder, and the sense amplifier circuit block formed by the sense amplifier circuit is located in the first top-view projection area and / or the second top-view projection area.

6. The memory device according to claim 5, characterized in that The inductive amplifier circuit comprises: A first sense amplifier sub-circuit is electrically connected to an output terminal of the first global bit line sub-decoder, wherein a first sense amplifier sub-circuit block formed by the first sense amplifier sub-circuit is located within the first top-view projection area; and The second sense amplifier sub-circuit is electrically connected to the output end of the second global bit line sub-decoder. The second sense amplifier sub-circuit block formed by the second sense amplifier sub-circuit is located in the second top-view projection area.

7. The memory device according to any one of claims 1 to 6, characterized in that: The logic control circuit also includes: A first local bit line sub-decoder, the first local bit line sub-decoder includes a first local bit line decoding unit and a second local bit line decoding unit electrically connected to the first global bit line sub-decoder, a first local bit line decoding unit block formed by the first local bit line decoding unit and a second local bit line decoding unit block formed by the second local bit line decoding unit are both located within the first top-view projection area; in the second direction, the first global bit line sub-decoder block is located between the first local bit line decoding unit block and the second local bit line decoding unit block.

8. The memory device according to claim 7, wherein: The local bit line decoder further comprises: A second local bit line sub-decoder, the second local bit line sub-decoder includes a third local bit line decoding unit and a fourth local bit line decoding unit electrically connected to the second global bit line sub-decoder, a third local bit line decoding unit block formed by the third local bit line decoding unit and a fourth local bit line decoding unit block formed by the fourth local bit line decoding unit are both located within the second top-view projection area, and in the second direction, the second global bit line sub-decoder block is located between the fourth local bit line decoding unit block and the third local bit line decoding unit block.

9. The memory device according to claim 8, wherein: In the second direction, the fourth local bit line decoding unit block, the third local bit line decoding unit block, the second local bit line decoding unit block and the first local bit line decoding unit block are arranged in sequence; in the second direction, the distance from the first global bit line sub-decoder block to the second local bit line decoding unit block is smaller than the distance from the first global bit line sub-decoder block to the first local bit line decoding unit block; in the second direction, the distance from the second global bit line sub-decoder block to the third local bit line decoding unit block is smaller than the distance from the second global bit line sub-decoder block to the fourth local bit line decoding unit block.

10. The memory device according to claim 7, wherein: The logic control circuit also includes: A first word line decoding unit is electrically connected to the first storage block, and a first word line decoding unit block formed by the first word line decoding unit is located in the first top-view projection area; A second word line decoding unit is electrically connected to the first storage block, and a second word line decoding unit block formed by the second word line decoding unit is located in the first top-view projection area; Among them, in the first direction, the projection of the first word line decoding unit block and the projection of the second word line decoding unit block at least partially overlap; and the first word line decoding unit block and the second word line decoding unit block are both located between the first global bit line sub-decoder block and the first local bit line decoding unit block.

11. The memory device according to claim 10, wherein: In the first direction, the first sense amplifier sub-circuit block is located between the first word line decoding unit block and the second word line decoding unit block; and in the second direction, the first sense amplifier sub-circuit block is located between the first global bit line sub-decoder block and the first local bit line decoding unit block.

12. The memory device according to claim 11, wherein: In the first direction, a projection of the first sense amplifier sub-circuit block at least partially overlaps with a projection of the first word line decoding unit block and / or a projection of the second word line decoding unit block.

13. The memory device according to claim 12, wherein: In the second direction, the projection of the first sense amplifier sub-circuit block does not overlap with the projection of the first word line decoding unit block and / or the projection of the second word line decoding unit block.

14. The memory device according to claim 8, wherein: The logic control circuit also includes: A third word line decoding unit is electrically connected to the second storage block, and a third word line decoding unit block formed by the third word line decoding unit is located in the second top-view projection area; a fourth word line decoding unit, electrically connected to the second storage block, wherein a fourth word line decoding unit block formed by the fourth word line decoding unit is located in the second top-view projection area; Among them, in the first direction, the projection of the third word line decoding unit block and the projection of the fourth word line decoding unit block at least partially overlap; and the third word line decoding unit block and the fourth word line decoding unit block are both located between the second global bit line sub-decoder block and the fourth local bit line decoding unit block.

15. The memory device according to claim 14, wherein: The first chip includes N storage blocks arranged in sequence along the second direction, the first storage array includes M storage blocks, and the second storage array includes NM storage blocks, wherein M is less than N, and both M and N are positive integers; The first top-view projection area is a projection area of ​​the Mth storage block on the second chip, and the second top-view projection area is a projection area of ​​the M+1th storage block on the second chip; The first global bit line sub-decoder is electrically connected to at least one of the first to 2M local bit line decoding units, and the second global bit line sub-decoder is electrically connected to at least one of the 2M+1 to 2N local bit line decoding units.

16. The memory device according to claim 15, wherein: M is equal to N / 2 after rounding; and the second global bit line sub-decoder block, the 2M+1 local bit line decoding unit block formed by the 2M+1 local bit line decoding unit, the 2M local bit line decoding unit block formed by the 2M local bit line decoding unit and the first global bit line sub-decoder block are arranged adjacent to each other in sequence along the second direction.

17. The memory device according to claim 16, wherein: The storage device further comprises: a plurality of first routing lines, the plurality of first routing lines being electrically connected to the first global bit line sub-decoder and the first local bit line decoding unit to the 2Mth local bit line decoding unit; and A plurality of second routing lines are electrically connected to the second global bit line sub-decoder and the 2M+1th local bit line decoding unit to the 2Nth local bit line decoding unit.

18. The memory device according to claim 17, wherein: In the second direction, the projection of the second sense amplifier sub-circuit block does not overlap with the projection of the third word line decoding unit block and / or the projection of the fourth word line decoding unit block.

19. A storage device, characterized in that: include: A first chip, the first chip comprising a first memory array and a second memory array, the first memory array comprising at least one first memory block, the first memory block comprising a plurality of first word lines extending along a first direction and a plurality of first bit lines extending along a second direction, the second memory array comprising at least one second memory block, the second memory block comprising a plurality of second word lines extending along the first direction and a plurality of second bit lines extending along the second direction; The second chip is stacked on top of the first chip along a third direction, and the second chip has a first overhead projection area of ​​the first storage block and a second overhead projection area of ​​the second storage block; the second chip includes a logic control circuit, and the logic control circuit includes an inductive amplifier circuit. The inductive amplifier circuit block formed by the inductive amplifier circuit is located in the first overhead projection area and / or the second overhead projection area.

20. The memory device according to claim 19, wherein: In the second direction, the first overhead projection area and the second overhead projection area are adjacent to each other.

21. The memory device according to claim 20, wherein: In the first direction, the length of the first global bit line sub-decoder block is less than or equal to the length of the first top-view projection area; in the first direction, the length of the second global bit line sub-decoder block is less than or equal to the length of the second top-view projection area.

22. The memory device according to claim 21, wherein: In the first direction, the length of the first top-view projection area is equal to the length of the second top-view projection area.

23. The memory device according to claim 19, wherein: The inductive amplifier circuit comprises: A first sense amplifier sub-circuit is electrically connected to an output terminal of the first global bit line sub-decoder, wherein a first sense amplifier sub-circuit block formed by the first sense amplifier sub-circuit is located within the first top-view projection area; and The second sense amplifier sub-circuit is electrically connected to the output end of the second global bit line sub-decoder. The second sense amplifier sub-circuit block formed by the second sense amplifier sub-circuit is located in the second top-view projection area.

24. The storage device according to any one of claims 19 to 23, characterized in that: The logic control circuit also includes: A first local bit line sub-decoder, the first local bit line sub-decoder includes a first local bit line decoding unit and a second local bit line decoding unit electrically connected to the first global bit line sub-decoder, a first local bit line decoding unit block formed by the first local bit line decoding unit and a second local bit line decoding unit block formed by the second local bit line decoding unit are both located within the first top-view projection area; in the second direction, the first global bit line sub-decoder block is located between the first local bit line decoding unit block and the second local bit line decoding unit block.

25. The memory device according to claim 24, wherein: The local bit line decoder further comprises: A second local bit line sub-decoder, the second local bit line sub-decoder includes a third local bit line decoding unit and a fourth local bit line decoding unit electrically connected to the second global bit line sub-decoder, a third local bit line decoding unit block formed by the third local bit line decoding unit and a fourth local bit line decoding unit block formed by the fourth local bit line decoding unit are both located within the second top-view projection area, and in the second direction, the second global bit line sub-decoder block is located between the fourth local bit line decoding unit block and the third local bit line decoding unit block.

26. The memory device according to claim 25, characterized in that In the second direction, the fourth local bit line decoding unit block, the third local bit line decoding unit block, the second local bit line decoding unit block and the first local bit line decoding unit block are arranged in sequence; in the second direction, the distance from the first global bit line sub-decoder block to the second local bit line decoding unit block is smaller than the distance from the first global bit line sub-decoder block to the first local bit line decoding unit block; in the second direction, the distance from the second global bit line sub-decoder block to the third local bit line decoding unit block is smaller than the distance from the second global bit line sub-decoder block to the fourth local bit line decoding unit block.

27. The memory device according to claim 24, wherein: The logic control circuit also includes: A first word line decoding unit is electrically connected to the first storage block, and a first word line decoding unit block formed by the first word line decoding unit is located in the first top-view projection area; A second word line decoding unit is electrically connected to the first storage block, and a second word line decoding unit block formed by the second word line decoding unit is located in the first top-view projection area; Among them, in the first direction, the projection of the first word line decoding unit block and the projection of the second word line decoding unit block at least partially overlap; and the first word line decoding unit block and the second word line decoding unit block are both located between the first global bit line sub-decoder block and the first local bit line decoding unit block.

28. The memory device according to claim 27, wherein: In the first direction, the first sense amplifier sub-circuit block is located between the first word line decoding unit block and the second word line decoding unit block; and in the second direction, the first sense amplifier sub-circuit block is located between the first global bit line sub-decoder block and the first local bit line decoding unit block.

29. The memory device according to claim 28, wherein: In the first direction, a projection of the first sense amplifier sub-circuit block at least partially overlaps with a projection of the first word line decoding unit block and / or a projection of the second word line decoding unit block.

30. The memory device according to claim 29, wherein: In the second direction, the projection of the first sense amplifier sub-circuit block does not overlap with the projection of the first word line decoding unit block and / or the projection of the second word line decoding unit block.

31. The memory device according to claim 25, wherein: The logic control circuit also includes: A third word line decoding unit is electrically connected to the second storage block, and a third word line decoding unit block formed by the third word line decoding unit is located in the second top-view projection area; a fourth word line decoding unit, electrically connected to the second storage block, wherein a fourth word line decoding unit block formed by the fourth word line decoding unit is located in the second top-view projection area; Among them, in the first direction, the projection of the third word line decoding unit block and the projection of the fourth word line decoding unit block at least partially overlap; and the third word line decoding unit block and the fourth word line decoding unit block are both located between the second global bit line sub-decoder block and the fourth local bit line decoding unit block.

32. The memory device according to claim 31, wherein: The first chip includes N storage blocks arranged in sequence along the second direction, the first storage array includes M storage blocks, and the second storage array includes NM storage blocks, wherein M is less than N, and both M and N are positive integers; The first top-view projection area is a projection area of ​​the Mth storage block on the second chip, and the second top-view projection area is a projection area of ​​the M+1th storage block on the second chip; The first global bit line sub-decoder is electrically connected to at least one of the first to 2M local bit line decoding units, and the second global bit line sub-decoder is electrically connected to at least one of the 2M+1 to 2N local bit line decoding units.

33. The memory device according to claim 32, wherein: M is equal to N / 2 after rounding; and the second global bit line sub-decoder block, the 2M+1 local bit line decoding unit block formed by the 2M+1 local bit line decoding unit, the 2M local bit line decoding unit block formed by the 2M local bit line decoding unit and the first global bit line sub-decoder block are arranged adjacent to each other in sequence along the second direction.

34. The memory device according to claim 33, wherein: The storage device further comprises: a plurality of first routing lines, the plurality of first routing lines being electrically connected to the first global bit line sub-decoder and the first local bit line decoding unit to the 2Mth local bit line decoding unit; and A plurality of second routing lines are electrically connected to the second global bit line sub-decoder and the 2M+1th local bit line decoding unit to the 2Nth local bit line decoding unit.

35. The memory device according to claim 34, wherein: In the second direction, the projection of the second sense amplifier sub-circuit block does not overlap with the projection of the third word line decoding unit block and / or the projection of the fourth word line decoding unit block.

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