Semiconductor package including insulating material

Abstract

A semiconductor package includes: a redistribution structure including a redistribution layer including copper (Cu) and an insulating layer surrounding the redistribution layer; a semiconductor chip mounted on the redistribution structure and including a connection pad; an internal connection terminal between the redistribution structure and the semiconductor chip and electrically connecting the redistribution layer to the connection pad; an external connection terminal attached under the redistribution structure and electrically connected to the redistribution layer; and a sealing material configured to surround the semiconductor chip and the internal connection terminal on the redistribution structure. The insulating layer comprises an insulating material having a TC index K of 20 to 100 according to the formula: [TC index] # imgabs0 #

Description

Technical Field

[0001] The inventive concept relates to a semiconductor package, and more particularly, to a semiconductor package including an insulating material forming a redistribution structure. Background Art

[0002] Recently, the demand for portable electronic devices in the electronic product market has increased rapidly, and as a result, there is a continuous need to miniaturize and reduce the weight of electronic components mounted on portable electronic devices. Although the overall thickness of semiconductor packages is decreasing in order to miniaturize and lighten electronic components, the demand for increased memory capacity continues to increase. Therefore, wafer-level packaging has been used to efficiently arrange semiconductor chips within the limited structure of a semiconductor package. Summary of the invention

[0003] The inventive concept relates to a semiconductor package having improved reliability by forming an insulating layer included in a redistribution structure of an insulating material capable of preventing or reducing physical damage.

[0004] Problems to be solved by the technical idea of ​​the present inventive concept are not limited to the above-mentioned problems, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

[0005] According to some aspects of the present inventive concept, a semiconductor package is provided, the semiconductor package comprising: a first redistribution structure, the first redistribution structure comprising: a plurality of first redistribution patterns, the plurality of first redistribution patterns having a plurality of first bottom surface connection pads and a plurality of first top surface connection pads; and a first redistribution insulation layer, the first redistribution insulation layer surrounding the plurality of first redistribution patterns; a first semiconductor chip, the first semiconductor chip being mounted in a first chip mounting area on the first redistribution structure; a plurality of first solder bumps, the plurality of first solder bumps being attached to the plurality of first bottom surface connection pads below the first redistribution structure; a second redistribution structure, the second redistribution structure being located on the first semiconductor chip and the first redistribution structure, and comprising: a plurality of second redistribution patterns, the plurality of second redistribution patterns having a plurality of second bottom a surface connection pad and a plurality of second top surface connection pads; and a second redistribution insulating layer, the second redistribution insulating layer surrounding the plurality of second redistribution patterns; a second semiconductor chip, the second semiconductor chip being mounted in a second chip mounting region on the second redistribution structure; a plurality of second solder bumps, the plurality of second solder bumps being attached to the plurality of second top surface connection pads between the second redistribution structure and the second semiconductor chip; a plurality of conductive pillars, the plurality of conductive pillars surrounding the first semiconductor chip and connecting some of the plurality of first top surface connection pads to some of the plurality of second bottom surface connection pads; and a sealing material, the sealing material being configured to fill a space between the first redistribution structure and the second redistribution structure and surrounding the plurality of conductive pillars and the first semiconductor chip. Each of the plurality of first redistribution patterns and the plurality of second redistribution patterns is formed of a conductive material, and wherein each of the first redistribution insulating layer and the second redistribution insulating layer is formed of an insulating material satisfying the following TC index K of 20 to 100.

[0006] [TC Index]

[0007]

[0008] Among them, U T is the toughness of the insulating material, α 1 refers to the thermal expansion coefficient of the insulating material, α 2 refers to the coefficient of thermal expansion of the conductive material surrounded by the insulating material, ΔT refers to the temperature change, and E refers to the elastic modulus of the insulating material.

[0009] According to some aspects of the present inventive concept, there is provided a semiconductor package, the semiconductor package comprising: a redistribution structure, the redistribution structure comprising a redistribution layer including copper (Cu) and an insulating layer surrounding the redistribution layer; a semiconductor chip, the semiconductor chip being mounted on the redistribution structure and comprising a connection pad; an internal connection terminal, the internal connection terminal being located between the redistribution structure and the semiconductor chip and being configured to electrically connect the redistribution layer to the connection pad; an external connection terminal, the external connection terminal being attached below the redistribution structure and being electrically connected to the redistribution layer; and a sealing material, the sealing material being configured to surround the semiconductor chip and the internal connection terminal on the redistribution structure. The insulating layer is formed of an insulating material satisfying the following TC index K of 20 to 100.

[0010] [TC Index]

[0011]

[0012] Among them, U T Refers to the toughness of the insulating material, α 1 Refers to the thermal expansion coefficient of the insulating material, α 2 refers to the thermal expansion coefficient of copper (Cu), ΔT refers to the temperature change, and E refers to the elastic modulus of the insulating material.

[0013] According to some aspects of the present inventive concept, there is provided a semiconductor package, the semiconductor package comprising: a redistribution structure, the redistribution structure comprising: a first insulating layer; at least one second insulating layer, the at least one second insulating layer being located on the first insulating layer; and a plurality of redistribution layers, the plurality of redistribution layers being located on the first insulating layer and the at least one second insulating layer, the plurality of redistribution layers being configured to be electrically connected to each other, each of the plurality of redistribution layers comprising a conductive material; a semiconductor chip, the semiconductor chip being mounted on the redistribution structure and comprising a connection pad; an internal connection terminal, the internal connection terminal being located between the redistribution structure and the semiconductor chip and being configured to electrically connect the plurality of redistribution layers to the connection pad; an external connection terminal, the external connection terminal being attached under the redistribution structure and being electrically connected to the plurality of redistribution layers; and a sealing material, the sealing material being configured to surround the semiconductor chip and the internal connection terminal on the redistribution structure. Each of the first insulating layer and the at least one second insulating layer is formed of an insulating material satisfying the following TC index K of 20 to 100.

[0014] [TC Index]

[0015]

[0016] U T Refers to the toughness of the insulating material, α 1 Refers to the thermal expansion coefficient of the insulating material, α 2 refers to the thermal expansion coefficient of the conductive material surrounded by the insulating material, ΔT refers to the temperature change, E refers to the elastic modulus of the insulating material, and d 1 is the vertical distance from the bottom surface of the semiconductor chip to the top surface of the external connection terminal, and d 2 It refers to the vertical distance from the bottom surface of the semiconductor chip to the bottom surface of the first insulating layer or the second insulating layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0018] Figure 1 is a cross-sectional view showing main components of a semiconductor package according to some example embodiments;

[0019] Figure 2 It shows Figure 1 An enlarged cross-sectional view of a portion AA;

[0020] Figure 3 It is shown Figure 2 Scanning electron micrograph of the peripheral area of ​​the metal under bump;

[0021] Figures 4 to 6 is a graph showing crack occurrence degrees according to various physical properties of an insulating material of an insulating layer included in a redistribution structure;

[0022] Figure 7 is a cross-sectional view showing main components of a semiconductor package according to some example embodiments;

[0023] Figure 8 It shows Figure 7 An enlarged cross-sectional view of part BB;

[0024] Fig. 9 is a flowchart illustrating a method of manufacturing a semiconductor package according to some example embodiments;

[0025] Figures 10 to 22 are cross-sectional views illustrating a method of manufacturing a semiconductor package according to some example embodiments in process order; and

[0026] Fig.23 is a block diagram schematically illustrating a configuration of a semiconductor package according to some example embodiments. DETAILED DESCRIPTION

[0027] Hereinafter, example embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

[0028] Figure 1 is a cross-sectional view illustrating main components of a semiconductor package 1000 according to some example embodiments. Figure 2 It shows Figure 1 An enlarged cross-sectional view of portion AA. Figure 3 It is shown Figure 2 Scanning electron micrograph of the peripheral area of ​​the underbump metal.

[0029] refer to Figures 1 to 3 The semiconductor package 1000 may include a first semiconductor chip 100, a plurality of conductive pillars 200 arranged around the first semiconductor chip 100, a first redistribution structure 300 arranged under the first semiconductor chip 100, a second redistribution structure 400 arranged above the first semiconductor chip 100, and a second semiconductor chip 500 arranged above the second redistribution structure 400.

[0030] The semiconductor package 1000 may have a package-on-package (PoP) structure. For example, the semiconductor package 1000 may include a fan-out semiconductor package in which the horizontal width and the horizontal area of ​​the first redistribution structure 300 are greater than the horizontal width and the horizontal area of ​​the first semiconductor chip 100. In some example embodiments, the semiconductor package 1000 may include a fan-out wafer level package (FOWLP) or a fan-out panel level package (FOPLP).

[0031] In some example embodiments, the first redistribution structure 300 and the second redistribution structure 400 may be formed by a redistribution process. Here, the first redistribution structure 300 and the second redistribution structure 400 may be referred to as a lower redistribution structure and an upper redistribution structure, respectively.

[0032] The first redistribution structure 300 may include a first redistribution insulating layer 310 and a plurality of first redistribution patterns 330. The first redistribution insulating layer 310 may surround the plurality of first redistribution patterns 330. In some example embodiments, the first redistribution structure 300 may include a plurality of stacked first redistribution insulating layers 310. For example, the plurality of first redistribution insulating layers 310 may sequentially include a first insulating layer 312, a second insulating layer 314, and a third insulating layer 316. However, the inventive concept is not limited thereto. The first insulating layer 312, the second insulating layer 314, and the third insulating layer 316 may be formed of the same material or different materials. The first redistribution insulating layer 310 may be formed of, for example, a photo-imageable dielectric (PID) material. For example, at least one of the first insulating layer 312, the second insulating layer 314, and the third insulating layer 316 may include an insulating material having a different K value of the following TC index 1 or TC index 2, which will be described in detail later. In some example embodiments, each of the first insulating layer 312 , the second insulating layer 314 , and the third insulating layer 316 (and additional insulating layers in, for example, the first redistribution insulating layer 310 ) may have a thickness of about or exactly 3 μm to about or exactly 10 μm.

[0033] The plurality of first redistribution patterns 330 may include a plurality of first redistribution line patterns 332 and a plurality of first redistribution paths 334. The plurality of first redistribution patterns 330 may include, for example, a metal such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), or ruthenium (Ru) and / or an alloy thereof. However, the inventive concept is not limited thereto.

[0034] The plurality of first redistribution line patterns 332 may be arranged on at least one of the top surface and the bottom surface of the first redistribution insulation layer 310. For example, when the first redistribution structure 300 includes a plurality of stacked first redistribution insulation layers 310, the plurality of first redistribution line patterns 332 may be arranged on the top surface of the uppermost first redistribution insulation layer 310 and the bottom surface of the lowermost first redistribution insulation layer 310, and between adjacent first redistribution insulation layers 310.

[0035] The plurality of first redistribution vias 334 may penetrate the first redistribution insulating layer 310 to be connected to some of the plurality of first redistribution line patterns 332. In some example embodiments, each of the plurality of first redistribution vias 334 may have a tapered shape extending from bottom to top with an increasing horizontal width.

[0036] In some example embodiments, some of the plurality of first redistribution line patterns 332 may be formed together with some of the plurality of first redistribution vias 334 so as to be integrated. For example, the first redistribution line pattern 332 and the first redistribution via 334 contacting the bottom surface of the first redistribution line pattern 332 may be formed together so as to be integrated.

[0037] Among the plurality of first redistribution patterns 330, some first redistribution patterns arranged adjacent to the bottom surface of the first redistribution structure 300 may be referred to as a plurality of first bottom surface connection pads 330P1, and some first redistribution patterns arranged adjacent to the top surface of the first redistribution structure 300 may be referred to as a plurality of first top surface connection pads 330P2. That is, the plurality of first bottom surface connection pads 330P1 may include some first redistribution line patterns arranged adjacent to the bottom surface of the first redistribution structure 300 among the plurality of first redistribution line patterns 332, and the plurality of first top surface connection pads 330P2 may include some first redistribution line patterns arranged adjacent to the top surface of the first redistribution structure 300 among the plurality of first redistribution line patterns 332.

[0038] A plurality of external connection terminals 600 may be attached to the plurality of first bottom surface connection pads 330P1. The plurality of external connection terminals 600 may connect the semiconductor package 1000 to the outside. In some example embodiments, the plurality of external connection terminals 600 may include solder bumps or solder balls. In some example embodiments, the plurality of chip connection members 130 may be attached to some of the plurality of first top surface connection pads 330P2, and the plurality of conductive pillars 200 may be attached to other first top surface connection pads of the plurality of first top surface connection pads 330P2.

[0039] In some example embodiments, a plurality of under bump metallizations (UBMs) may be arranged between the plurality of first bottom surface connection pads 330P1 and the plurality of external connection terminals 600. That is, a plurality of under bump metallizations (UBMs) may be arranged below the plurality of first bottom surface connection pads 330P1, and a plurality of external connection terminals 600 may be arranged below the plurality of under bump metallizations (UBMs). Therefore, the plurality of under bump metallizations (UBMs) may be arranged to protrude downward from the lowermost surface of the first redistribution insulating layer 310.

[0040] In some example embodiments, the plurality of external connection terminals 600 may be attached to some of the plurality of first bottom surface connection pads 330P1, and the passive elements 610 may be attached to others of the plurality of first bottom surface connection pads 330P1.

[0041] A plurality of external connection terminals 600 may be formed on the top surface of the first redistribution structure 300. The plurality of external connection terminals 600 may include, for example, solder balls, conductive bumps, conductive paste, a ball grid array (BGA), a lead grid array (LGA), a pin grid array (PGA), or a combination thereof.

[0042] The passive element 610 may include at least one selected from a resistor, a capacitor, an inductor, a thermistor, an oscillator, a ferrite bead, an antenna, and a varistor. For example, the passive element 610 may include a multilayer ceramic capacitor (MLCC), a low inductance chip capacitor (LICC), a land side capacitor (LSC), or an integrated passive device (IPD). However, the inventive concept is not limited thereto.

[0043] The outer underfill layer 650 may surround the sidewalls of the solder bumps 630 disposed under the passive component 610, and may fill the gap between the solder bumps 630 adjacent to each other. In the process of electrically connecting the passive component 610 to the solder bumps 630, a gap may be formed between the passive component 610 and the solder bumps 630. Because the gap may cause a problem in the reliability of the connection between the passive component 610 and the solder bumps 630, the outer underfill layer 650 may be injected and cured to strengthen the connection.

[0044] The passive component 610 is more stably fixed to the solder bump 630 by the external underfill layer 650 , and the passive component 610 may not be electrically separated from the solder bump 630 despite the difference in thermal expansion coefficient between the passive component 610 and the solder bump 630 .

[0045] A plurality of first top surface connection pads 330P2 may be arranged on the top surface of the first redistribution insulation layer 310. For example, when the first redistribution structure 300 includes a plurality of stacked first redistribution insulation layers 310, the plurality of first top surface connection pads 330P2 may be arranged on the top surface of the uppermost first redistribution insulation layer 310.

[0046] At least one first semiconductor chip 100 may be mounted on the first redistribution structure 300. That is, the first semiconductor chip 100 may include a single chip or a plurality of chips. The first semiconductor chip 100 may include a semiconductor substrate 110 having an active surface and an inactive surface facing each other, a semiconductor device 112 formed on the active surface of the semiconductor substrate 110, and a plurality of chip pads 120 arranged on the first surface of the first semiconductor chip 100. For example, the first semiconductor chip 100 may have a thickness 100T of about or exactly 150 μm to about or exactly 1500 μm.

[0047] Here, the first surface and the second surface of the first semiconductor chip 100 face each other, and the second surface of the first semiconductor chip 100 refers to an inactive surface of the semiconductor substrate 110. Since the active surface of the semiconductor substrate 110 is adjacent to the first surface of the first semiconductor chip 100, illustrations distinguishing the active surface of the semiconductor substrate 110 and the first surface of the first semiconductor chip 100 are omitted.

[0048] In some example embodiments, the first semiconductor chip 100 has a face-down arrangement in which the first surface faces the first redistribution structure 300, and the first semiconductor chip 100 may be mounted on a top surface of the first redistribution structure 300. In this case, the first surface of the first semiconductor chip 100 may be referred to as a bottom surface of the first semiconductor chip 100, and the second surface of the first semiconductor chip 100 may be referred to as a top surface of the first semiconductor chip 100.

[0049] A plurality of chip connection members 130 may be between a plurality of chip pads 120 of the first semiconductor chip 100 and some of the first top surface connection pads 330P2 of the first redistribution structure 300. For example, each of the plurality of chip connection members 130 may be a solder ball or a microbump. The first semiconductor chip 100 may be electrically connected to a plurality of first redistribution patterns 330 of the first redistribution structure 300 through a plurality of chip connection members 130. The plurality of chip connection members 130 may include a plurality of bump layers 132 arranged on the plurality of chip pads 120 and a plurality of internal connection terminals 134 covering the plurality of bump layers 132. The plurality of chip connection members 130 may be formed of, for example, Cu, Al, silver (Ag), Sn, gold (Au) and / or solder. However, the inventive concept is not limited thereto.

[0050] The semiconductor substrate 110 may include, for example, a semiconductor material such as silicon (Si) or germanium (Ge). Alternatively, the semiconductor substrate 110 may include a compound semiconductor material such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). The semiconductor substrate 110 may include a well doped with impurities, which is a conductive region. The semiconductor substrate 110 may have various device isolation structures such as a shallow trench isolation (STI) structure.

[0051] A semiconductor device 112 including a plurality of individual devices of different types may be formed on an active surface of the semiconductor substrate 110. The plurality of individual devices may be electrically connected to a conductive region of the semiconductor substrate 110. The semiconductor device 112 may also include a conductive wiring or a conductive plug that electrically connects the plurality of individual devices to the conductive region of the semiconductor substrate 110. In addition, each of the plurality of individual devices may be electrically separated from other adjacent individual devices by an insulating layer.

[0052] In some example embodiments, the first semiconductor chip 100 may include a logic element. For example, the first semiconductor chip 100 may include a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, or an application processor (AP) chip. In some example embodiments, when the semiconductor package 1000 includes a plurality of first semiconductor chips 100, one of the plurality of first semiconductor chips 100 may include a CPU chip, a GPU chip, or an AP chip, and another first semiconductor chip may include a storage semiconductor chip including a memory device.

[0053] For example, the memory device may include a nonvolatile memory device such as a flash memory, a phase change random access memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FeRAM), or a resistive random access memory (RRAM). In some example embodiments, the memory device may include a volatile memory device such as a dynamic random access memory (DRAM) or a static random access memory (SRAM).

[0054] The second redistribution structure 400 may include a second redistribution insulation layer 410 and a plurality of second redistribution patterns 430. The second redistribution insulation layer 410 may surround the plurality of second redistribution patterns 430. In some example embodiments, the second redistribution structure 400 may include a plurality of stacked second redistribution insulation layers 410. For example, the plurality of second redistribution insulation layers 410 may sequentially include a fourth insulation layer 412, a fifth insulation layer 414, and a sixth insulation layer 416. However, the inventive concept is not limited thereto. The fourth insulation layer 412, the fifth insulation layer 414, and the sixth insulation layer 416 may be formed of the same material or different materials. The second redistribution insulation layer 410 may be formed of, for example, a PID material. For example, at least one of the fourth insulation layer 412, the fifth insulation layer 414, and the sixth insulation layer 416 may include an insulating material having a different K value of the following TC index 1 or TC index 2, which will be described in detail later. In some example embodiments, the fourth insulating layer 412 , the fifth insulating layer 414 , and the sixth insulating layer 416 (and additional insulating layers in, for example, the plurality of second redistribution insulating layers 410 ) each have a thickness of about or exactly 3 μm to about or exactly 10 μm.

[0055] In some example embodiments, the second redistribution structure 400 may include a plurality of stacked second redistribution insulation layers 410. The plurality of second redistribution patterns 430 may include a plurality of second redistribution line patterns 432 and a plurality of second redistribution vias 434. The plurality of second redistribution patterns 430 may include a metal or a metal alloy. In some example embodiments, the plurality of second redistribution patterns 430 may be formed by stacking a metal or a metal alloy on a seed layer.

[0056] The plurality of second redistribution line patterns 432 may be arranged on at least one of the top surface and the bottom surface of the second redistribution insulation layer 410. For example, when the second redistribution structure 400 includes a plurality of stacked second redistribution insulation layers 410, the plurality of second redistribution line patterns 432 may be arranged on the top surface of the uppermost second redistribution insulation layer 410 and the bottom surface of the lowermost second redistribution insulation layer 410, and between adjacent second redistribution insulation layers 410.

[0057] Among the plurality of second redistribution patterns 430, some second redistribution patterns arranged adjacent to the bottom surface of the second redistribution structure 400 may be referred to as a plurality of second bottom surface connection pads 430P1, and some second redistribution patterns arranged adjacent to the top surface of the second redistribution structure 400 may be referred to as a plurality of second top surface connection pads 430P2. That is, the plurality of second bottom surface connection pads 430P1 may include some second redistribution line patterns arranged adjacent to the bottom surface of the second redistribution structure 400 among the plurality of second redistribution line patterns 432, and the plurality of second top surface connection pads 430P2 may include some second redistribution line patterns arranged adjacent to the top surface of the second redistribution structure 400 among the plurality of second redistribution line patterns 432. In some example embodiments, the plurality of second bottom surface connection pads 430P1 may be arranged adjacent to some second redistribution vias adjacent to the bottom surface of the second redistribution structure 400 among the plurality of second redistribution vias 434.

[0058] The second semiconductor chip 500 may include a second semiconductor device 512 and a plurality of second pads 530. The second semiconductor chip 500 may be electrically connected to the second redistribution structure 400 through a plurality of internal connection terminals 550 interposed between the plurality of second pads 530 and the plurality of second top surface connection pads 430P2. The second semiconductor chip 500 may be mounted on the second redistribution structure 400 so that the plurality of second pads 530 face the second redistribution structure 400.

[0059] In some example embodiments, the second semiconductor chip 500 may be electrically connected to the plurality of first redistribution patterns 330 of the first redistribution structure 300 through the plurality of internal connection terminals 550 attached to the plurality of second pads 530 , the plurality of second redistribution patterns 430 , and the plurality of conductive pillars 200 .

[0060] In some example embodiments, the second semiconductor device 512 may include a memory device. For example, the memory device may include a nonvolatile memory device such as a flash memory, a PRAM, an MRAM, a FeRAM, or an RRAM. In some example embodiments, the memory device may include a volatile memory device such as a DRAM or an SRAM.

[0061] A plurality of second bottom surface connection pads 430P1 may be arranged on the bottom surface of the second redistribution insulation layer 410. For example, when the second redistribution structure 400 includes a plurality of stacked second redistribution insulation layers 410, the plurality of second bottom surface connection pads 430P1 may be arranged on the bottom surface of the lowermost second redistribution insulation layer 410.

[0062] A plurality of second top surface connection pads 430P2 may be arranged on the top surface of the second redistribution insulation layer 410. For example, when the second redistribution structure 400 includes a plurality of stacked second redistribution insulation layers 410, the plurality of second top surface connection pads 430P2 may be arranged on the top surface of the uppermost second redistribution insulation layer 410.

[0063] The plurality of second redistribution vias 434 may penetrate the second redistribution insulating layer 410 to be connected to some of the plurality of second redistribution line patterns 432. In some example embodiments, some of the plurality of second redistribution line patterns 432 may be formed together with some of the plurality of second redistribution vias 434 so as to be integrated. For example, the second redistribution line pattern 432 and the second redistribution via 434 contacting the bottom surface of the second redistribution line pattern 432 may be formed together so as to be integrated.

[0064] In some example embodiments, each of the plurality of second redistribution passages 434 may have a tapered shape extending from top to bottom with a reduced horizontal width. That is, the plurality of first redistribution passages 334 and the plurality of second redistribution passages 434 extend in the same direction with a reduced horizontal width. However, the inventive concept is not limited thereto.

[0065] Herein, the first redistribution insulating layer 310, the first redistribution pattern 330, the first redistribution line pattern 332, and the first redistribution path 334 may be referred to as a first insulating layer, a first wiring pattern, a first wiring line pattern, and a first wiring path, respectively. Herein, the second redistribution insulating layer 410, the second redistribution pattern 430, the second redistribution line pattern 432, and the second redistribution path 434 may be referred to as a second insulating layer, a second wiring pattern, a second wiring line pattern, and a second wiring path, respectively.

[0066] An encapsulant 250 may surround the first semiconductor chip 100 on the top surface of the first redistribution structure 300. The encapsulant 250 may fill the space between the first redistribution structure 300 and the second redistribution structure 400. For example, the encapsulant 250 may include a molding member including an epoxy mold compound (EMC). The encapsulant 250 may also include a filler.

[0067] In some example embodiments, an internal underfill layer 150 surrounding the plurality of chip connection members 130 may be interposed between the first semiconductor chip 100 and the first redistribution structure 300. In some example embodiments, the internal underfill layer 150 may fill the space between the first semiconductor chip 100 and the first redistribution structure 300, and may partially cover the lower side of the first semiconductor chip 100. The internal underfill layer 150 may be formed by, for example, a capillary underfill process, and may be formed of, for example, epoxy resin or the like.

[0068] In some example embodiments, side surfaces of the first redistribution structure 300 , side surfaces of the sealing material 250 , and side surfaces of the second redistribution structure 400 may be aligned with each other in a vertical direction so as to be coplanar.

[0069] The plurality of conductive pillars 200 may penetrate the sealing material 250 to electrically connect the first redistribution structure 300 to the second redistribution structure 400. The sealing material 250 may surround the plurality of conductive pillars 200.

[0070] The plurality of conductive pillars 200 may be interposed between the first redistribution structure 300 and the second redistribution structure 400 and spaced apart from the first semiconductor chip 100 in a horizontal direction. For example, the plurality of conductive pillars 200 may be spaced apart from the first semiconductor chip 100 in a horizontal direction and may be arranged around the first semiconductor chip 100 in an outer region of the first redistribution structure 300.

[0071] The plurality of conductive pillars 200 may be interposed between the plurality of first top surface connection pads 330P2 and the plurality of second bottom surface connection pads 430P1. The bottom surfaces of the plurality of conductive pillars 200 may contact the plurality of first top surface connection pads 330P2 of the first redistribution structure 300 to be electrically connected to the plurality of first redistribution patterns 330, and the top surfaces of the plurality of conductive pillars 200 may contact the plurality of second bottom surface connection pads 430P1 of the second redistribution structure 400 to be electrically connected to the plurality of second redistribution patterns 430. In some example embodiments, the plurality of conductive pillars 200 may include Cu or a Cu alloy. However, the inventive concept is not limited thereto.

[0072] Bottom surfaces of the plurality of conductive pillars 200 may contact top surfaces of the plurality of first top surface connection pads 330P2, respectively. Top surfaces of the plurality of conductive pillars 200 may contact bottom surfaces of the plurality of second bottom surface connection pads 430P1, respectively.

[0073] Recently, the demand for portable electronic devices in the electronic product market has increased rapidly, and as a result, there is a continuous need to miniaturize and reduce the weight of electronic components mounted on portable electronic devices. Although the overall thickness of semiconductor packages is decreasing in order to miniaturize and lighten electronic components, the demand for increased storage capacity continues to increase. Therefore, fan-out wafer-level packaging is applied to effectively arrange the first semiconductor chip 100 in a limited structure of the semiconductor package 1000.

[0074] According to the heat dissipation of the first semiconductor chip 100 in the limited structure of the semiconductor package 1000, in the first redistribution structure 300 constituting the fan-out type wafer level package, due to the difference in thermal expansion coefficients between the first redistribution insulation layer 310 as an insulating material and the first redistribution pattern 330 as a conductive material, cracks may occur in the first redistribution insulation layer 310 having relatively low strength.

[0075] Similarly, in the second redistribution structure 400 constituting the fan-out wafer level package, cracks may occur in the second redistribution insulation layer 410 having relatively low strength due to the difference in thermal expansion coefficients between the second redistribution insulation layer 410 as an insulating material and the second redistribution pattern 430 as a conductive material.

[0076] In this manner, in order to solve the problem of cracks, the first redistribution insulating layer 310 and the second redistribution insulating layer 410 are formed of various insulating materials. However, due to different characteristics of various materials forming the semiconductor package 1000, it is difficult to identify problems in advance.

[0077] Therefore, in some example embodiments, a new TC index for minimizing the problem of cracks by applying a highly reliable insulating material to the first and second redistribution insulating layers 310 and 410 may be used.

[0078] In some example embodiments, each of the first redistribution insulating layer 310 and the second redistribution insulating layer 410 may include an insulating material having K of 20 or more satisfying the following TC index 1.

[0079] [TC Index 1]

[0080]

[0081] Among them, U T Refers to the toughness of the insulating material, α 1 Refers to the thermal expansion coefficient of the insulating material, α 2 refers to the coefficient of thermal expansion of a conductive material surrounded by an insulating material, ΔT refers to the temperature change, and E refers to Young's modulus, which is the elastic modulus of the insulating material.

[0082] According to some example embodiments, when each of the first and second redistribution insulating layers 310 and 410 is formed of an insulating material and each of the first and second redistribution patterns 330 and 430 is formed of a conductive material, cracks are significantly reduced by a TC index of 1.

[0083] Here, the insulating material may include, for example, a photoimageable dielectric (PID) material or a photosensitive polyimide (PSPI). In addition, the PID material may include, for example, any one selected from polyhydroxystyrene (PHS), polybenzoxazole (PBO), and polyimide (PI). In addition, PI may include a negative photosensitive insulating material or a positive photosensitive insulating material. However, the insulating material is not limited to the above materials.

[0084] Here, the conductive material forming each of the first redistribution pattern 330 and the second redistribution pattern 430 may include, for example, a metal such as Cu, Al, W, Ti, Ta, In, Mo, Mn, Co, Sn, Ni, Mg, Re, Be, Ga, or Ru or an alloy thereof. However, the inventive concept is not limited thereto. In general, each of the first redistribution pattern 330 and the second redistribution pattern 430 may include Cu.

[0085] Here, U T Can be about or exactly 1mJ / mm 3 To about or exactly 110mJ / mm 3 , α 1 can be about or exactly 40 ppm / °C to about or exactly 70 ppm / °C, α 2 It may be about or exactly 16.7 ppm / °C, which is the thermal expansion coefficient of Cu, ΔT may be about or exactly 175°C or about or exactly 215°C, and E may be about or exactly 2 GPa to about or exactly 4 GPa.

[0086] The value of ΔT may vary under stress conditions and extreme conditions. For example, stress conditions refer to temperature characteristic tests performed according to a temperature change from about or exactly -55°C to about or exactly 120°C, and extreme conditions refer to temperature characteristic tests performed according to a temperature change from about or exactly -65°C to about or exactly 150°C.

[0087] In some example embodiments, each of the first redistribution insulating layer 310 and the second redistribution insulating layer 410 may include an insulating material having K of 20 or more satisfying the following TC index 2.

[0088] [TC Index 2]

[0089]

[0090] Among them, U T Refers to the toughness of the insulating material, α 1 Refers to the thermal expansion coefficient of the insulating material, α 2 refers to the thermal expansion coefficient of the conductive material surrounded by the insulating material, ΔT refers to the temperature change, E refers to the elastic modulus of the insulating material, and d 1 is the vertical distance from the bottom surface of the semiconductor chip to the top surface of the external connection terminal, and d 2 It refers to the vertical distance from the bottom surface of the semiconductor chip to the bottom surface of the first insulating layer 312 or the second insulating layer 314. Here, when the insulating material includes a plurality of insulating layers, d 2 May refer to the bottom surface in each insulating layer.

[0091] For example, in Figure 2 Medium, d 1 represents the vertical distance from the bottom surface of the first semiconductor chip 100 to the top surface of the external connection terminal 600, d 2 represents a vertical distance from the bottom surface of the first semiconductor chip 100 to the bottom surface of the first insulating layer 312, and d 3 represents the vertical distance from the bottom surface of the first semiconductor chip 100 to the bottom surface of the second insulating layer 314. That is, in TC index 2, d 2 Can be d 3 replace.

[0092] [Table 1]

[0093]

[0094] *At -55°C

[0095] In some example embodiments, according to Table 1 and Figure 3 , it can be noted that in the insulating material satisfying TC Index 2 with K of 20 or more (e.g., about or exactly 20 to about or exactly 100), the occurrence of cracks is reduced. Thus, it can be noted that in the insulating material satisfying TC Index 2 with K of 40 or more (e.g., about or exactly 40 to about or exactly 100), the occurrence of cracks is significantly reduced.

[0096] If the insulating material is selected based on K according to the TC index 2, it can be concluded that it is desirable to use the negative photosensitive PI. That is, it can be noted that the negative photosensitive PI is a material forming each of the first redistribution insulating layer 310 and the second redistribution insulating layer 410 and has high reliability.

[0097] In this manner, through the quantized values ​​of various materials forming the first redistribution structure 300 and the second redistribution structure 400 , K according to a TC index (TC index 1 and TC index 2 are hereinafter collectively referred to as a TC index) may be obtained.

[0098] As a result, the reliability of the semiconductor package 1000 conceived according to the present invention is improved by forming the first redistribution insulation layer 310 included in the first redistribution structure 300 and the second redistribution insulation layer 410 included in the second redistribution structure 400 from an insulating material (e.g., an optimal insulating material) that can prevent or reduce physical damage while taking into account various physical properties according to the TC index.

[0099] Figures 4 to 6 is a graph showing a degree of crack occurrence according to various physical properties of an insulating material forming an insulating layer included in a redistribution structure.

[0100] refer to Figures 4 to 6 , respectively showing the crack occurrence rate according to elongation, the crack occurrence rate according to fracture resistance, and the crack occurrence rate according to the TC index in accordance with the present inventive concept.

[0101] exist Figure 4 In the embodiment of the present invention, the elongation is measured under the condition that the insulating material is about -55°C (the lowest temperature under stress conditions). Examining the crack occurrence rate according to the elongation, it can be noted that the crack occurrence rate significantly decreases as the elongation (which is a physical property of the insulating material) increases. That is, when the elongation (unit: %) is about or exactly 2%, about or exactly 18%, about or exactly 40%, the crack occurrence frequency (unit: %) is measured to be about or exactly 100%, about or exactly 0% to about or exactly 8%, and about or exactly 0%.

[0102] exist Figure 5 In the test, the fracture resistance is measured under the condition that the insulating material is about -55°C (the lowest temperature under stress conditions). Examining the crack occurrence rate according to the fracture resistance, it can be noted that the crack occurrence rate decreases significantly as the fracture resistance (which is a physical property of the insulating material) increases. That is, when the fracture resistance (unit: mJ / mm 3 ) is approximately or exactly 0 mJ / mm 3 , about or exactly 200000mJ / mm 3 , and approximately or exactly 1080000mJ / mm 3 When , the crack occurrence frequency (unit: %) is about or exactly 100%, about or exactly 0% to about or exactly 10%, about or exactly 0%. Here, fracture resistance can be applied as a physical property that is substantially the same as toughness.

[0103] exist Figure 6, the TC index according to the present invention is measured under the condition that the insulating material is about -55°C (the lowest temperature under stress conditions). The crack occurrence rate is examined according to the TC index of the present invention, and it can be noted that the crack occurrence rate is significantly reduced as the TC index of the insulating material according to the present invention increases. That is, when the TC index (unit: arbitrary unit) according to the present invention is about or exactly 8%, about or exactly 19%, and about or exactly 39%, the crack occurrence frequency (unit: %) is measured to be about or exactly 0% to about or exactly 6%, about or exactly 0% to about or exactly 8%, and about or exactly 0%.

[0104] That is, by forming the first redistribution insulating layer 310 included in the first redistribution structure 300 and the second redistribution insulating layer 410 included in the second redistribution structure 400 from an insulating material (e.g., an optimal insulating material) that can prevent or reduce physical damage in consideration of various physical properties according to the TC index, the semiconductor package 1000 (refer to Figure 1 ) reliability.

[0105] Figure 7 is a cross-sectional view illustrating main components of a semiconductor package 1100 according to some example embodiments. Figure 8 It shows Figure 7 An enlarged cross-sectional view of portion BB.

[0106] Most of the components and materials forming the semiconductor package 1100 described below are similar to those previously described in Figures 1 to 3 Therefore, for convenience, the differences from the semiconductor package 1000 described above are mainly described.

[0107] refer to Figure 7 and Figure 8 , the semiconductor package 1100 may include a first semiconductor chip 100 , a first redistribution structure 300 disposed under the first semiconductor chip 100 , and a sealing material 250 surrounding the first semiconductor chip 100 on a top surface of the first redistribution structure 300 .

[0108] The semiconductor package 1100 may include a fan-out type semiconductor package in which the horizontal width and horizontal area of ​​the first redistribution structure 300 are greater than those of the first semiconductor chip 100. In some example embodiments, the semiconductor package 1100 may include a fan-out type wafer level package or a fan-out type panel level package.

[0109] The first redistribution structure 300 may include a first redistribution insulation layer 310 and a plurality of first redistribution patterns 330. The first redistribution insulation layer 310 may surround the plurality of first redistribution patterns 330. In some example embodiments, the first redistribution structure 300 may include a plurality of stacked first redistribution insulation layers 310. For example, the plurality of first redistribution insulation layers 310 may sequentially include a first insulation layer 312, a second insulation layer 314, and a third insulation layer 316. However, the inventive concept is not limited thereto. The first redistribution insulation layer 310 may be formed of, for example, a PID material.

[0110] The plurality of first redistribution patterns 330 may include a plurality of first redistribution line patterns 332 and a plurality of first redistribution vias 334. The plurality of first redistribution line patterns 332 may be arranged on at least one of the top surface and the bottom surface of the first redistribution insulation layer 310. The plurality of first redistribution vias 334 may penetrate the first redistribution insulation layer 310 to be connected to some of the plurality of first redistribution line patterns 332.

[0111] Among the multiple first redistribution patterns 330, some first redistribution patterns arranged adjacent to the bottom surface of the first redistribution structure 300 can be referred to as a plurality of first bottom surface connecting pads 330P1, and some first redistribution patterns arranged adjacent to the top surface of the first redistribution structure 300 can be referred to as a plurality of first top surface connecting pads 330P2.

[0112] A plurality of external connection terminals 600 may be attached to the plurality of first bottom surface connection pads 330P1. The plurality of external connection terminals 600 may connect the semiconductor package 1100 to the outside.

[0113] In some example embodiments, a plurality of under bump metallurgy (UBM)s may be disposed between the plurality of first bottom surface connection pads 330P1 and the plurality of external connection terminals 600. That is, a plurality of under bump metallurgy (UBM)s may be disposed below the plurality of first bottom surface connection pads 330P1, and a plurality of external connection terminals 600 may be disposed below the plurality of under bump metallurgy (UBM)s.

[0114] In some example embodiments, the plurality of external connection terminals 600 may be attached to some of the plurality of first bottom surface connection pads 330P1, and the passive elements 610 may be attached to others of the plurality of first bottom surface connection pads 330P1.

[0115] At least one first semiconductor chip 100 may be mounted on the first redistribution structure 300. That is, the first semiconductor chip 100 may include a single chip or a plurality of chips. The first semiconductor chip 100 may include a semiconductor substrate 110 having an active surface and an inactive surface facing each other, a semiconductor device 112 formed on the active surface of the semiconductor substrate 110, and a plurality of chip pads 120 arranged on the first surface of the first semiconductor chip 100.

[0116] The plurality of chip connection members 130 may be interposed between the plurality of chip pads 120 of the first semiconductor chip 100 and some of the plurality of first top surface connection pads 330P2 of the first redistribution structure 300. The plurality of chip connection members 130 may include a plurality of bump layers 132 arranged on the plurality of chip pads 120 and a plurality of internal connection terminals 134 covering the plurality of bump layers 132.

[0117] The sealing material 250 may surround the first semiconductor chip 100 on the top surface of the first redistribution structure 300. The sealing material 250 may configure the exterior of the semiconductor package 1100. For example, the sealing material 250 may include a molding member including EMC. The sealing material 250 may further include a filler.

[0118] In some example embodiments, an inner underfill layer 150 surrounding the plurality of chip connection members 130 may be interposed between the first semiconductor chip 100 and the first redistribution structure 300. In some example embodiments, the inner underfill layer 150 may fill a space between the first semiconductor chip 100 and the first redistribution structure 300 and may partially cover a lower side of the first semiconductor chip 100.

[0119] In some example embodiments, the first redistribution insulating layer 310 may include an insulating material having K of 20 or more satisfying the following TC index 1.

[0120] [TC Index 1]

[0121]

[0122] Among them, U T Refers to the toughness of the insulating material, α 1 Refers to the thermal expansion coefficient of the insulating material, α 2 refers to the coefficient of thermal expansion of the conductive material surrounded by the insulating material, ΔT refers to the temperature change, and E refers to the elastic modulus of the insulating material.

[0123] In some example embodiments, when the first redistribution insulating layer 310 is formed of an insulating material and the first redistribution pattern 330 is formed of a conductive material, cracks are significantly reduced by a TC index of 1.

[0124] Here, the insulating material may include, for example, a PID material or a PSPI. In addition, the PID material may include, for example, any one selected from PHS, PBO, and PI. In addition, PI may include a negative photosensitive insulating material or a positive photosensitive insulating material. However, the insulating material is not limited to the above materials.

[0125] Here, the conductive material forming the plurality of first redistribution patterns 330 may include, for example, a metal such as Cu, Al, W, Ti, Ta, In, Mo, Mn, Co, Sn, Ni, Mg, Re, Be, Ga, or Ru or an alloy thereof. However, the inventive concept is not limited thereto. In general, the plurality of first redistribution patterns 330 may include Cu.

[0126] Here, U T Can be about or exactly 1mJ / mm 3 To about or exactly 110mJ / mm 3 , α 1 can be about or exactly 40 ppm / °C to about or exactly 70 ppm / °C, α 2 It may be about or exactly 16.7 ppm / °C, which is the thermal expansion coefficient of Cu, ΔT may be about or exactly 175°C or about or exactly 215°C, and E may be about or exactly 2 GPa to about or exactly 4 GPa.

[0127] In some example embodiments, the first redistribution insulating layer 310 may include an insulating material having K of 20 or more (eg, 20 to 100) satisfying the following TC index 2.

[0128] [TC Index 2]

[0129]

[0130] Among them, U T Refers to the toughness of the insulating material, α 1 Refers to the thermal expansion coefficient of the insulating material, α 2 refers to the thermal expansion coefficient of the conductive material surrounded by the insulating material, ΔT refers to the temperature change, E refers to the elastic modulus of the insulating material, and d 1 is the vertical distance from the bottom surface of the semiconductor chip to the top surface of the external connection terminal, and d 2 It refers to the vertical distance from the bottom surface of the semiconductor chip to the bottom surface of the first insulating layer 312 or the second insulating layer 314. Here, when the insulating material includes a plurality of insulating layers, d 2 May refer to the bottom surface in each insulating layer.

[0131] For example, in Figure 8 Medium, d1 represents the vertical distance from the bottom surface of the first semiconductor chip 100 to the top surface of the external connection terminal 600, d 2 represents a vertical distance from the bottom surface of the first semiconductor chip 100 to the bottom surface of the first insulating layer 312, and d 3 represents the vertical distance from the bottom surface of the first semiconductor chip 100 to the bottom surface of the second insulating layer 314. That is, in TC index 2, d 3 Can be d 2 replace.

[0132] As a result, the reliability of the semiconductor package 1100 according to the present invention is improved by forming the first redistribution insulating layer 310 included in the first redistribution structure 300 from an insulating material (e.g., an optimal insulating material) that can prevent or reduce physical damage while considering various physical properties according to the TC index.

[0133] Fig. 9 is a flowchart illustrating a method of manufacturing a semiconductor package according to some example embodiments.

[0134] refer to Fig. 9 , the method S1000 of manufacturing a semiconductor package may include operations S110 to S170 .

[0135] In some exemplary embodiments, the specific process order may be performed differently from the described order. For example, two processes described in succession may be performed substantially simultaneously, or may be performed in the reverse order of the described process.

[0136] The semiconductor package manufacturing method S1000 conceived according to the present invention may include: selecting an insulating material by using a TC index in operation S110; forming a first redistribution structure including the selected insulating material in operation S120; mounting a first semiconductor chip on the first redistribution structure in operation S130; forming a sealing material covering the first semiconductor chip in operation S140; forming a second redistribution structure including the selected insulating material on the sealing material in operation S150; mounting a second semiconductor chip on the second redistribution structure in operation S160; and forming each semiconductor package by cutting a substrate structure including a plurality of first semiconductor chips and a second semiconductor chip in operation S170.

[0137] Reference will be made to the later described Figures 10 to 22 Technical features of each of operations S110 to S170 are described in detail.

[0138] Figures 10 to 22are cross-sectional views illustrating a method of manufacturing a semiconductor package according to some example embodiments in process order.

[0139] refer to Fig.10 A first redistribution structure 300 including a first redistribution insulation layer 310 and a plurality of first redistribution patterns 330 including a plurality of first redistribution line patterns 332 and a plurality of first redistribution vias 334 is formed on the carrier substrate CS.

[0140] The insulating material forming the first redistribution insulating layer 310 may be selected as an insulating material (eg, an optimal insulating material) that may prevent or reduce physical damage in consideration of various physical properties of a TC index according to the inventive concept.

[0141] The carrier substrate CS may include a semiconductor substrate, a glass substrate, a ceramic substrate, or a plastic substrate. In some example embodiments, a release film may be attached to the carrier substrate CS to form the first redistribution structure 300 .

[0142] A plurality of first redistribution line patterns 332 may be formed on the carrier substrate CS. The plurality of first redistribution line patterns 332 formed on the carrier substrate CS may include a plurality of first bottom surface connection pads 330P1.

[0143] Next, after forming a first preliminary redistribution insulating layer covering the plurality of first redistribution line patterns 332 on the carrier substrate CS, a portion of the first preliminary redistribution insulating layer may be removed by an exposure process and a development process to form a first insulating layer 312 having a plurality of first via holes. The plurality of first via holes may be formed such that a horizontal width decreases from a top surface to a bottom surface of the first insulating layer 312. In some example embodiments, the plurality of first bottom surface connection pads 330P1 and a bottom surface of the first insulating layer 312 may be coplanar.

[0144] Next, after forming the first redistribution conductive layer on the second insulating layer 314, the first redistribution conductive layer may be patterned to form a plurality of first redistribution patterns 330 including a plurality of first redistribution line patterns 332 and a plurality of first redistribution vias 334. The plurality of first redistribution vias 334 of the plurality of first redistribution patterns 330 may fill the plurality of first via holes, and the plurality of first redistribution line patterns 332 of the plurality of first redistribution patterns 330 may be above the top surface of the second insulating layer 314.

[0145] Next, the first redistribution structure 300 may be formed by forming a third insulating layer 316 and a plurality of first redistribution patterns 330. The plurality of first redistribution line patterns 332 arranged on the top surface of the first redistribution structure 300 may include a plurality of first top surface connection pads 330P2. In some example embodiments, when the first redistribution insulation layer 310 sequentially includes the first insulation layer 312, the second insulation layer 314, and the third insulation layer 316, the plurality of first top surface connection pads 330P2 may include a plurality of first redistribution line patterns 332 arranged on the top surface of the third insulation layer 316.

[0146] refer to Fig.11 , a plurality of conductive pillars 200 electrically connected to the plurality of first top surface connection pads 330P2 arranged in the outer region of the first redistribution structure 300 are formed.

[0147] The plurality of conductive pillars 200 may be formed by electroplating. The plurality of conductive pillars 200 satisfying the desired shape may be formed by an exposure process and a development process using a photoresist (not shown) and a single plating process. In some example embodiments, the conductive material may include Cu or a Cu alloy. However, the inventive concept is not limited thereto.

[0148] For example, the plurality of first top surface connection pads 330P2 may function as a seed layer for forming the plurality of conductive pillars 200. That is, when the plurality of conductive pillars 200 are formed by an electroplating process, the plurality of first top surface connection pads 330P2 provide a path through which current may flow, so that the plurality of conductive pillars 200 may be formed on the plurality of first top surface connection pads 330P2.

[0149] refer to Fig.12 , a first semiconductor chip 100 including a plurality of chip pads 120 is mounted on the first redistribution structure 300 .

[0150] The first semiconductor chip 100 may be mounted on the first redistribution structure 300 such that the plurality of chip connection members 130 are interposed between the plurality of chip pads 120 and some of the plurality of first top surface connection pads 330P2 of the first redistribution structure 300 .

[0151] The first semiconductor chip 100 may be mounted on the chip mounting region of the first redistribution structure 300 and spaced apart in a horizontal direction from the plurality of conductive pillars 200. For example, a plurality of chip connection members 130 including a plurality of bump layers 132 and a plurality of internal connection terminals 134 covering the plurality of bump layers 132 may be formed on the plurality of chip pads 120 of the first semiconductor chip 100, and the first semiconductor chip 100 having the plurality of chip connection members 130 formed therein may be mounted on the first redistribution structure 300.

[0152] The inner underfill layer 150 may fill a space between the first semiconductor chip 100 and the first redistribution structure 300 . The inner underfill layer 150 may surround the plurality of chip connection members 130 .

[0153] refer to Fig.13 , forming a sealing material 250 covering the first semiconductor chip 100 and the plurality of conductive pillars 200 .

[0154] The sealing material 250 may be formed to have a top surface at a higher vertical height than top surfaces of the plurality of conductive pillars 200 so as to cover the entire top surfaces of the plurality of conductive pillars 200 .

[0155] Next, a portion of the sealing material 250 is removed so that the plurality of conductive pillars 200 are exposed. That is, the upper portion of the sealing material 250 may be partially removed by a chemical mechanical polishing (CMP) process. The sealing material 250 may include a molding member including EMC.

[0156] refer to Fig.14 A second redistribution structure 400 including a second redistribution insulation layer 410 and a plurality of second redistribution patterns 430 including a plurality of second redistribution line patterns 432 and a plurality of second redistribution vias 434 is formed on the plurality of conductive pillars 200 and the sealing material 250 .

[0157] The insulating material forming the second redistribution insulating layer 410 may be selected as an insulating material (eg, an optimal insulating material) that may prevent or reduce physical damage in consideration of various physical properties of a TC index according to the inventive concept.

[0158] After forming the second preliminary redistribution insulating layer on the plurality of conductive pillars 200 and the sealing material 250, a portion of the second preliminary redistribution insulating layer may be removed by an exposure process and a development process to form a fourth insulating layer 412 having a plurality of second via holes. In some example embodiments, the plurality of second bottom surface connection pads 430P1 and the bottom surface of the fourth insulating layer 412 may be coplanar.

[0159] The plurality of second via holes may be formed such that the horizontal width decreases from the top surface to the bottom surface of the fourth insulating layer 412. Next, after forming a second redistribution conductive layer on the fifth insulating layer 414, the second redistribution conductive layer may be patterned to form a plurality of second redistribution patterns 430 including a plurality of second redistribution line patterns 432 and a plurality of second redistribution vias 434.

[0160] The plurality of second redistribution vias 434 formed on the plurality of conductive pillars 200 may include a plurality of second bottom surface connection pads 430P1. The plurality of second redistribution vias 434 of the plurality of second redistribution patterns 430 may fill the plurality of second via holes, and the plurality of second redistribution line patterns 432 of the plurality of second redistribution patterns 430 may be above the top surface of the fifth insulating layer 414.

[0161] Next, the second redistribution structure 400 may be formed by forming a sixth insulating layer 416 and a plurality of second redistribution patterns 430. The plurality of second redistribution line patterns 432 arranged on the top surface of the second redistribution structure 400 may include a plurality of second top surface connection pads 430P2. In some example embodiments, when the second redistribution insulation layer 410 sequentially includes a fourth insulation layer 412, a fifth insulation layer 414, and a sixth insulation layer 416, the plurality of second top surface connection pads 430P2 may include a plurality of second redistribution line patterns 432 arranged on the top surface of the sixth insulation layer 416.

[0162] refer to Fig.15 , a substrate structure SS formed on a carrier substrate CS may be prepared.

[0163] For the sake of brevity, the manufacturing process of one first semiconductor chip 100 has been mainly described. However, in practice, a plurality of first semiconductor chips 100 may be arranged side by side or in a matrix on a carrier substrate CS to form a substrate structure SS. Figures 10 to 14 The manufacturing process is described in Fig.15 Part of CC.

[0164] Therefore, the manufacturing process will be described focusing on the process of manufacturing the substrate structure SS including the plurality of first semiconductor chips 100 into each semiconductor package 1000 (refer to Fig. 22 ).

[0165] refer to Fig.16 , the exposed surface of the substrate structure SS may be attached to the dicing film 10 .

[0166] The dicing film 10 may include a base layer 11, an intermediate layer 13 on the base layer 11, and an adhesive layer 15 on the intermediate layer 13. Here, the dicing film 10 may have a first diameter. The first diameter may be greater than a second diameter of the substrate structure SS. The second diameter, which is the diameter of the wafer constituting the substrate structure SS, may correspond to, for example, approximately or exactly 300 mm (or, for example, approximately or exactly 12 inches) or approximately or exactly 450 mm (or, for example, approximately or exactly 18 inches).

[0167] The exposed surface of the substrate structure SS to which the carrier substrate CS is attached may be mounted to adhere to the adhesive layer 15 of the dicing film 10. Fig.16 As shown, the edge of the adhesive layer 15 of the dicing film 10 may be fixed to the lower portion of the frame 20. The frame 20 may have a ring shape. However, the inventive concept is not limited thereto. When the substrate structure SS to which the carrier substrate CS is attached is attached to the adhesive layer 15 of the dicing film 10, the second redistribution structure 400 formed in the substrate structure SS may be attached to face the adhesive layer 15.

[0168] refer to Fig.17 , the carrier substrate CS may be separated from the substrate structure SS.

[0169] In order to separate and remove the carrier substrate CS, the laser P1 may be irradiated onto the carrier substrate CS. The bonding force between the substrate structure SS and the carrier substrate CS may be weakened by the irradiation of the laser P1, and the carrier substrate CS may be completely separated.

[0170] An adhesive layer (not shown) may be disposed between the carrier substrate CS and the substrate structure SS to facilitate separation of the carrier substrate CS. The adhesive layer may be in the form of a liquid or gel that may be easily deformed by a certain amount of heat (eg, a predetermined or desired amount of heat) caused by radiation of the laser P1.

[0171] refer to Fig.18 , a plurality of external connection terminals 600 may be attached to some of the plurality of first bottom surface connection pads 330P1, and passive elements 610 may be attached to other first bottom surface connection pads of the plurality of first bottom surface connection pads 330P1.

[0172] In order to attach the plurality of external connection terminals 600 and the passive element 610 to the plurality of first bottom surface connection pads 330P1, a reflow process may be performed. After the solder forming the plurality of external connection terminals 600 is melted by the reflow process, the solder may be arranged in a spherical shape on the plurality of first bottom surface connection pads 330P1 without collapsing due to surface tension. In some example embodiments, an intermetallic compound may be formed at the interface between the plurality of external connection terminals 600 and the plurality of first bottom surface connection pads 330P1.

[0173] Next, the space between the passive component 610 and the first redistribution structure 300 may be filled with an outer underfill layer 650. The outer underfill layer 650 may surround sidewalls of the solder bumps 630 disposed under the passive component 610 and may fill gaps between the solder bumps 630 adjacent to each other.

[0174] refer to Fig.19, various components of the first redistribution structure 300 including the substrate structure SS may be cut P2 along scribe lines DL.

[0175] Since the substrate structure SS may include a fan-out wafer level package or a fan-out panel level package, various types of material films including the first redistribution structure 300 may be cut P2 along a scribe line DL to be physically separated into individual semiconductor dies. Although only one scribe line DL is shown in the drawings, the inventive concept is not limited thereto.

[0176] refer to Fig. 20 , a pressure P3 may be provided to the bottom of the dicing film 10 to expand the surface area of ​​the dicing film 10 .

[0177] In some example embodiments, a jig (not shown) may be attached to the bottom of the dicing film 10, and the jig may be pushed upward to expand the dicing film 10. That is, a pressure P3 may be provided to the bottom of the dicing film 10.

[0178] According to the expansion of the dicing film 10, the substrate structure SS (refer to Fig.19 ) can be based on the scribe line DL (reference Fig.19 ) is physically separated into a first semiconductor die SD1 and a second semiconductor die SD2. Although only the first semiconductor die SD1 and the second semiconductor die SD2 are shown in the drawings, the number of semiconductor dies is not limited thereto.

[0179] refer to Fig.21 , the first semiconductor die SD1 may be picked up ( P4 ) from the dicing film 10 by using a pickup device.

[0180] In some example embodiments, when removing the dicing film 10 from the first semiconductor die SD1, a wet cleaning process may be performed to remove adhesive residue that may remain on the exposed surface of the dicing film 10. The wet cleaning process may be performed by using an organic solvent or an inorganic solvent depending on the material constituting the adhesive layer 15 of the dicing film 10.

[0181] refer to Fig. 22 , the second semiconductor chip 500 may be mounted to be electrically connected to the second redistribution structure 400 of the first semiconductor die SD1 .

[0182] The second semiconductor chip 500 may be mounted on the second redistribution structure 400 such that the plurality of second pads 530 face the second redistribution structure 400. The second semiconductor chip 500 may be electrically connected to the plurality of first redistribution patterns 330 of the first redistribution structure 300 through the plurality of internal connection terminals 550 attached to the plurality of second pads 530, the plurality of second redistribution patterns 430, and the plurality of conductive pillars 200. In this manner, the semiconductor package 1000 may be completed.

[0183] Fig.23 is a block diagram schematically illustrating a configuration of a semiconductor package 1200 according to some example embodiments.

[0184] refer to Fig.23 , the semiconductor package 1200 may include a micro processing unit 1210, a memory 1220, an interface 1230, a GPU 1240, a function block 1250, and a bus 1260 that connects the above components to each other.

[0185] The semiconductor package 1200 may include both the micro processing unit 1210 and the GPU 1240 , or may include only one of the two.

[0186] The microprocessing unit 1210 may include a core and a cache memory. For example, the microprocessing unit 1210 may include multiple cores. Each core in the multiple cores may have the same or different performance. In addition, each core in the multiple cores may be activated at the same time or may be activated at different times.

[0187] The memory 1220 may store the result processed by the functional block 1250 under the control of the microprocessing unit 1210. The interface 1230 may exchange information or signals with an external device. The GPU 1240 may perform a graphics function. For example, the GPU 1240 may execute a video codec or may process 3D graphics. The functional block 1250 may perform various functions. For example, when the semiconductor package 1200 includes an application processor used in a mobile device, some of the functional blocks 1250 may perform a communication function.

[0188] The semiconductor package 1200 may include the above reference Figure 1 The semiconductor package 1000 described and / or referenced Figure 7 A semiconductor package 1100 is described.

[0189] When the terms "approximately" or "substantially" are used in conjunction with a numerical value in this specification, the associated numerical value is intended to include a manufacturing or operating tolerance (e.g., ±10%) around the stated numerical value. Moreover, when the words "approximately" and "substantially" are used in conjunction with a geometric shape, it is intended that the precision of the geometric shape is not required, but the range of shapes is within the scope of the present disclosure. Further, regardless of whether a numerical value or shape is modified by "approximately" or "substantially", it should be understood that these numerical values ​​and shapes should be interpreted as including a manufacturing or operating tolerance (e.g., ±10%) around the stated numerical value or shape.

[0190] As described herein, any electronic device and / or portion thereof according to any of the example embodiments of the example embodiments may include, may be included in, and / or may be implemented by, one or more instances of a processing circuit system (such as hardware including logic circuits; a hardware / software combination, such as a processor that executes software; or any combination thereof). For example, the processing circuit system may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a graphics processing unit (CPU), an application processor (AP), a digital signal processor (DSP), a microcomputer, a field programmable gate array (FPGA) and a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), a neural network processing unit (NPU), an electronic control unit (ECU), an image signal processor (ISP), and the like. In some example embodiments, the processing circuit system may include: a non-transitory computer-readable storage device (e.g., memory), such as a DRAM device, which stores a program of instructions; and a processor (e.g., a CPU) configured to execute the program of instructions to implement the functionality and / or methods performed by some or all of any device, system, module, unit, controller, circuit, architecture and / or portion thereof according to any example embodiment and / or any portion thereof in the example embodiments.

[0191] While the inventive concepts have been particularly shown and described with reference to example embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor package, comprising: a first redistribution structure including a plurality of first redistribution patterns and a first redistribution insulating layer, the first redistribution insulating layer surrounding the plurality of first redistribution patterns, the plurality of first redistribution patterns having a plurality of first bottom surface connection pads and a plurality of first top surface connection pads; a first semiconductor chip mounted in a first chip mounting region on the first redistribution structure; a plurality of first solder bumps attached to the plurality of first bottom surface connection pads beneath the first redistribution structure; a second redistribution structure, the second redistribution structure comprising a plurality of second redistribution patterns and a second redistribution insulation layer, the second redistribution insulation layer surrounding the plurality of second redistribution patterns, the plurality of second redistribution patterns having a plurality of second bottom surface connection pads and a plurality of second top surface connection pads, the second redistribution structure being located on the first semiconductor chip and the first redistribution structure; a second semiconductor chip mounted in a second chip mounting region on the second redistribution structure; a plurality of second solder bumps attached to the plurality of second top surface connection pads between the second redistribution structure and the second semiconductor chip; a plurality of conductive pillars surrounding the first semiconductor chip and connecting some of the plurality of first top surface connection pads to some of the plurality of second bottom surface connection pads; as well as a sealing material filling a space between the first redistribution structure and the second redistribution structure and surrounding the plurality of conductive pillars and the first semiconductor chip, each of the plurality of first redistribution patterns and the plurality of second redistribution patterns comprising a conductive material, and Each of the first redistribution insulating layer and the second redistribution insulating layer includes an insulating material having a TC index K of 20 to 100 according to the following formula: [TC Index] in, U T is the toughness of the insulating material, α1 is the thermal expansion coefficient of the insulating material, α2 is the thermal expansion coefficient of the conductive material surrounded by the insulating material, ΔT is the temperature change, and E is the elastic modulus of the insulating material.

2. The semiconductor package according to claim 1, wherein: Each of the first redistribution insulating layer and the second redistribution insulating layer includes a plurality of insulating layers, and a thickness of each of the plurality of insulating layers in a vertical direction is 3 μm to 10 μm.

3. The semiconductor package according to claim 1, wherein: The insulating material includes a photoimageable dielectric material.

4. The semiconductor package according to claim 3, wherein: The photoimageable dielectric material includes any one selected from polyhydroxystyrene, polybenzoxazole, and polyimide.

5. The semiconductor package according to claim 4, wherein: The polyimide includes a negative photosensitive insulating material or a positive photosensitive insulating material.

6. The semiconductor package according to claim 1, wherein: The conductive material in each of the plurality of first redistribution patterns and the plurality of second redistribution patterns is copper.

7. The semiconductor package according to claim 1, wherein: In the temperature characteristic test of the semiconductor package, the temperature changes from -55°C to 120°C, or from -65°C to 150°C.

8. The semiconductor package according to claim 7, wherein: In the insulating material, the ΔT is 175°C or 215°C.

9. The semiconductor package according to claim 1, wherein: In the insulating material, the E is 2 GPa to 4 GPa.

10. The semiconductor package according to claim 1, wherein Each of the first redistribution insulating layer and the second redistribution insulating layer includes a plurality of insulating layers stacked in a vertical direction, and At least some of the plurality of insulating layers include insulating materials having different values ​​of the TC index K.

11. A semiconductor package, comprising: a redistribution structure comprising a redistribution layer including copper and an insulating layer surrounding the redistribution layer; a semiconductor chip mounted on the redistribution structure and comprising connection pads; an internal connection terminal located between the redistribution structure and the semiconductor chip and configured to electrically connect the redistribution layer to the connection pad; an external connection terminal attached below the redistribution structure and electrically connected to the redistribution layer; as well as A sealing material is configured to surround the semiconductor chip and the internal connection terminals on the redistribution structure, wherein the insulating layer includes an insulating material having a TC index K of 20 to 100 according to the following formula: [TC Index] in, U T is the toughness of the insulating material, α1 is the thermal expansion coefficient of the insulating material, α2 is the thermal expansion coefficient of copper, ΔT is the temperature change, and E is the elastic modulus of the insulating material.

12. The semiconductor package according to claim 11, wherein The U T 1mJ / mm 3 Up to 110mJ / mm 3 , α1 is 40ppm / ℃ to 70ppm / ℃, α2 is 16.7ppm / ℃, The ΔT is 175°C or 215°C, and The E is 2 Gpa to 4 Gpa.

13. The semiconductor package according to claim 12, wherein: The insulating layer includes a plurality of layers, and a thickness of each of the plurality of layers in a vertical direction is 3 μm to 10 μm.

14. The semiconductor package according to claim 11, wherein The insulating material includes a photoimageable dielectric material including any one selected from polyhydroxystyrene, polybenzoxazole, and polyimide.

15. The semiconductor package according to claim 11, wherein The insulating layer includes a plurality of layers stacked in a vertical direction, and At least some of the plurality of layers include insulating materials having different values ​​of the TC index K.

16. A semiconductor package, comprising: A redistribution structure, the redistribution structure comprising: a first insulating layer; at least one second insulating layer, the at least one second insulating layer being located on the first insulating layer; and a plurality of redistribution layers, the plurality of redistribution layers being located on the first insulating layer and the at least one second insulating layer, the plurality of redistribution layers being configured to be electrically connected to each other, each of the plurality of redistribution layers comprising a conductive material; a semiconductor chip mounted on the redistribution structure and comprising connection pads; an internal connection terminal located between the redistribution structure and the semiconductor chip and configured to electrically connect the plurality of redistribution layers to the connection pad; an external connection terminal attached under the redistribution structure and electrically connected to the plurality of redistribution layers; and A sealing material surrounding the semiconductor chip and the internal connection terminals on the redistribution structure, wherein each of the first insulating layer and at least one of the second insulating layers comprises an insulating material having a TC index K of 20 to 100 according to the following formula: [TC Index] in, U T is the toughness of the insulating material, α1 is the thermal expansion coefficient of the insulating material, α2 is the thermal expansion coefficient of the conductive material surrounded by the insulating material, ΔT is the temperature change, E is the elastic modulus of the insulating material, d1 is a vertical distance from the bottom surface of the semiconductor chip to the top surface of the external connection terminal, and d2 is a vertical distance from the bottom surface of the semiconductor chip to the bottom surface of the first insulating layer or the second insulating layer.

17. The semiconductor package according to claim 16, wherein: An under bump metallurgy is located in a lowermost redistribution layer among the plurality of redistribution layers, and the external connection terminal is attached to the under bump metallurgy.

18. The semiconductor package according to claim 17, wherein: The d1 is greater than or equal to the d2.

19. The semiconductor package according to claim 16, wherein: Each of the first insulating layer and at least one of the second insulating layers has a thickness in a vertical direction of 3 μm to 10 μm.

20. The semiconductor package according to claim 19, wherein The insulating material comprises a photoimageable dielectric material, the photoimageable dielectric material comprising any one selected from polyhydroxystyrene, polybenzoxazole and polyimide, and The first insulating layer and at least one of the second insulating layers include insulating materials different from each other.

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