Self-powered circuit for a switching power supply and switching power supply

Abstract

The application provides a self-powered circuit of a switching power supply and the switching power supply. The self-powered circuit comprises a first linear voltage stabilizing circuit connected between a common connection end of a main power tube and an auxiliary power tube and a power supply capacitor; a second linear voltage stabilizing circuit connected in parallel with the second linear voltage stabilizing circuit; and an adjusting circuit connected with the second linear voltage stabilizing circuit, which generates an adjusting voltage to adjust a first charging current flowing through the second linear voltage stabilizing circuit when the second linear voltage stabilizing circuit is turned on. When the switching power supply is started, the first linear voltage stabilizing circuit is turned on, and the power supply capacitor is charged. When a PWM signal generated by a control chip of the switching power supply is valid, the second linear voltage stabilizing circuit is turned on. The application can save power supply loss and optimize system EMI.

Description

Technical Field

[0001] This invention relates to the field of power electronics, and in particular to a self-powered circuit for a switching power supply and the switching power supply itself. Background Technology

[0002] By using normally-on power devices, self-starting and self-powering can be achieved relatively easily. The self-starting function can eliminate the need for additional resistor-based or high-voltage-based starting circuits, and the self-powering function can eliminate the need for auxiliary winding power supply.

[0003] like Figure 1 The diagram shows a self-powered circuit for a prior art switching power supply. Taking a flyback converter as an example, the self-powered circuit includes a main power transistor Q1 and an auxiliary power transistor Q2 connected in series. A first linear adjustment circuit (LDO1) is connected between their common connection terminal and the power supply capacitor C0. A power supply voltage VDD is generated across the power supply capacitor C0, which powers the control chip of the switching power supply. The power supply voltage VDD passes through the LDO (linear adjustment circuit) to obtain voltage VCC, which powers the drive circuit O1 of the auxiliary power transistor Q2. The drive circuit O1 receives a PWM drive signal and generates a drive signal DRV to control the on / off state of the auxiliary power transistor Q2. The signal waveform diagram of this self-powered circuit is shown below. Figure 2 As shown, during the turn-on period of power transistor Q1 and auxiliary power transistor Q2 (t1~t2), the magnetizing inductor of the flyback converter stores energy, the inductor current I_Lm rises, and the voltage Vsw at SW and the voltage drop Vds_Q2 across the auxiliary power transistor Q2 are at a low level. The control chip is powered by the supply voltage VDD, and the VDD voltage drops. During the turn-off period of power transistor Q1 and auxiliary power transistor Q2 (t2~t3), the magnetizing inductor current supplies power to the output, the inductor current I_Lm drops, and the voltage Vsw at SW is clamped to Vin + Nps * Vo, where Vin is the DC input voltage of the flyback converter, Vo is the output voltage, and Nps is the turns ratio of the transformer primary and secondary sides Nps = Np / Ns. At this time, power transistor Q1 operates in the linear region, capacitor C0 charges, and the voltage drop of power transistor Q1 is Vds_Q1 = V SW -(-Vgs_th), where Vgs_th is the threshold voltage of the D-Mode power device. Due to the voltage clamping at SW, the power transistor Q1 has relatively large losses, P = Vds_Q1 * Ivdd, where Ivdd is the average current consumed by the chip.

[0004] When power transistor Q1 and auxiliary power transistor Q2 are turned off, the supply voltage VDD originates from the voltage Vsw at SW. Vsw is a high voltage, and at this time, power transistor Q1 operates in the linear region, similar to a high-voltage LDO, which results in large power supply losses and low system efficiency. Furthermore, when auxiliary power transistor Q2 is turned on, if the switching speed is not controlled, it may cause significant electromagnetic interference (EMI). Summary of the Invention

[0005] The purpose of this invention is to provide a self-powered circuit for a high-efficiency switching power supply and the switching power supply itself, in order to solve the problems of high power loss and low system efficiency in the prior art, while also optimizing the system EMI problem.

[0006] The present invention also provides a self-powered circuit for a switching power supply, the switching power supply including an inductor, a main power transistor, and an auxiliary power transistor, wherein the inductor is connected to a first terminal of the main power transistor, and the auxiliary power transistor is connected between a second terminal of the main power transistor and a ground terminal.

[0007] A power supply capacitor is used to generate the power supply voltage for the control chip of the switching power supply.

[0008] The first linear voltage regulator circuit is connected between the common connection terminal of the main power transistor and the auxiliary power transistor and the power supply capacitor;

[0009] The second linear voltage regulator circuit is connected in parallel with the first linear voltage regulator circuit.

[0010] An adjustment circuit is connected to the second linear voltage regulator circuit. When the second linear voltage regulator circuit is turned on, the first charging current flowing through the second linear voltage regulator circuit is adjusted so that the voltage change rate of the first node between the main power transistor and the inductor reaches a preset change rate.

[0011] During the startup process of the switching power supply, the first linear voltage regulator circuit is turned on, and the power supply capacitor is charged; when the PWM signal generated by the control chip of the switching power supply is valid, the second linear voltage regulator circuit is turned on, and the power supply capacitor is charged.

[0012] Optionally, when the supply voltage reaches a first threshold, the first linear regulator circuit is turned off.

[0013] Optionally, when the second linear regulator circuit is turned on, the adjustment circuit adjusts the first charging current to a reference current so that the voltage change rate of the first node between the main power transistor and the inductor reaches a preset change rate.

[0014] Optionally, the adjustment circuit includes a first resistor connected in the charging path between the second linear voltage regulator circuit and the charging capacitor; the magnitude of the first charging current is set by setting the magnitude of the first resistor.

[0015] Optionally, the adjustment circuit further includes a sampling circuit and a first operational amplifier. When the second linear regulator circuit is turned on, the sampling circuit samples the voltage of the first resistor to obtain a voltage sampling signal.

[0016] The first operational amplifier performs operational amplification on the voltage sampling signal and the first reference voltage to obtain an adjustment voltage, and the adjustment voltage controls the magnitude of the first charging current.

[0017] Optionally, the sampling circuit is configured such that when the second linear voltage regulator circuit is turned on, the voltage at the power supply terminal is sampled to obtain a first sampling signal.

[0018] When the second linear voltage regulator circuit is turned off, the voltage at the sampling power supply terminal is used to obtain the second sampling signal.

[0019] Subtracting the first sampled signal from the second sampled signal yields a voltage sampled signal characterizing the voltage of the first resistor;

[0020] The power supply terminal is the common connection terminal between the second linear voltage regulator circuit and the first resistor.

[0021] Optionally, the first resistor and the power supply capacitor are integrated outside the control chip, while the first linear voltage regulator circuit, the second linear voltage regulator circuit, the main power transistor, and the auxiliary power transistor are integrated inside the control chip.

[0022] Optionally, the adjustment circuit includes a rate of change detection circuit for detecting the rate of change of the first node voltage to obtain a rate of change detection signal, and adjusting the first charging current according to the rate of change detection signal.

[0023] Optionally, the adjustment circuit further includes a sample-and-hold circuit and a second operational amplifier, wherein the sample-and-hold circuit samples and holds the rate of change detection signal when the second linear adjustment circuit is turned on;

[0024] The second operational amplifier performs operational amplification on the rate of change detection signal obtained from the sample-and-hold circuit and the second reference voltage to obtain the adjustment voltage, which controls the magnitude of the first charging current.

[0025] Optionally, a clamping circuit is also included, which is connected to the high-potential end of the power supply capacitor, and is used to clamp the power supply voltage at the preset value when the power supply voltage is greater than the preset value.

[0026] Optionally, when the turn-on time of the second linear voltage regulator circuit reaches a preset time, the second linear voltage regulator circuit is turned off, and the auxiliary power transistor is turned on.

[0027] Optionally, when the voltage at the first node between the main power transistor and the inductor drops to a preset voltage, the second linear regulator circuit is turned off and the auxiliary power transistor is turned on.

[0028] Optionally, the power transistor is a depletion-type transistor.

[0029] The present invention also provides a switching power supply, including a main power transistor and an inductor connected together, and any of the above-described self-powered circuits for generating the power supply voltage of the control chip of the switching power supply.

[0030] Compared with the prior art, the present invention has the following advantages: The present invention establishes two charging paths between the common connection terminal of the main power transistor and the auxiliary power transistor and the power supply capacitor. When the switching power supply is first started, the power supply capacitor is pre-charged through the first charging path; when the switching power supply is working normally, the capacitor is charged through the second charging path when the auxiliary switching transistor is turned on, so as to save turn-on losses and optimize power supply efficiency; at the same time, the charging current on the second path is controlled to control the drop slope of the voltage at the connection terminal of the inductor and the main power transistor, so as to optimize the EMI of the system. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of a self-powered circuit for a current-technical switching power supply.

[0032] Figure 2 The waveform diagram of the operation of a self-powered circuit in the prior art;

[0033] Figure 3 This is a schematic diagram of the switching power supply of the present invention;

[0034] Figure 4 This is a schematic diagram of Embodiment 1 of the adjustment circuit of the present invention;

[0035] Figure 5 This is a schematic diagram of embodiment 2 of the adjustment circuit of the present invention;

[0036] Figure 6 This is a schematic diagram of an embodiment of the second linear voltage regulator circuit of the present invention;

[0037] Figure 7 This is a waveform diagram of the self-powered circuit of the present invention. Detailed Implementation

[0038] The preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings, but the present invention is not limited to these embodiments. The present invention covers any substitutions, modifications, equivalent methods, and solutions made within the spirit and scope of the present invention.

[0039] To provide the public with a thorough understanding of the present invention, specific details are described in detail in the following preferred embodiments of the invention, but those skilled in the art can fully understand the invention without these details.

[0040] The invention is described more specifically in the following paragraphs by way of example with reference to the accompanying drawings. It should be noted that the drawings are in a simplified form and use non-precise proportions, in order to facilitate and clearly illustrate the purpose of the embodiments of the invention.

[0041] like Figure 3 The diagram illustrates the principle of the switching power supply of the present invention. A flyback converter is used as an example for explanation, but in this invention, the switching power supply is not limited to a flyback converter; it can also be a buck converter, boost converter, etc. In this embodiment, the flyback converter rectifies the AC input voltage AC to obtain a DC input voltage Vin. The main power transistor Q1 and the primary winding Np of the transformer T are connected in series, with the connection node being the first node SW. The rectifier diode D0 and the secondary winding Ns of the transformer T are connected in series. By controlling the switching state of the main power transistor Q1, the DC input voltage Vin is converted into an output voltage Vo via the transformer T. The main power transistor Q1 of this invention is a depletion-type transistor, preferably a depletion-type gallium nitride transistor, with its gate grounded. There is parasitic capacitance between the gate and drain of the main power transistor Q1, and the primary winding of the transformer T also has parasitic capacitance. There is also parasitic capacitance along the connection path between the main power transistor Q1 and the primary winding of the transformer T. These parasitic capacitances in the flyback converter are equivalent to the equivalent capacitance C shown in the diagram. EQ The flyback converter also includes an auxiliary power transistor Q2 connected to the main power transistor Q1 and its driving circuit 20, which is used to control the auxiliary power transistor Q2 to turn off according to the PWM signal.

[0042] The flyback converter also includes a self-powered circuit 10 and a drive distribution circuit 30. The drive distribution circuit 30 receives a PWM signal and generates a PWM2 signal to control the self-powered state of the self-powered circuit 10 and a PWM1 signal to provide the drive auxiliary power Q2 to the drive circuit 20. (See waveforms.) Figure 7Specifically, the self-powered circuit 10 includes a first linear regulator circuit (LDO1) 01, a second linear regulator circuit (LDO2) 02, an adjustment circuit 03, a clamping circuit 04, and a power supply capacitor C0. LDO1 and LDO2 are connected between the common connection terminal of the main power transistor Q1 and the auxiliary power transistor Q2 and the first terminal of the power supply capacitor C0. LDO1 and LDO2 are connected in parallel. The second terminal of the power supply capacitor C0 is grounded, and the power supply voltage VDD of the switching power supply is generated on the power supply capacitor C0. The clamping circuit 04 is connected to the high-potential terminal of the power supply capacitor C0 to clamp the power supply voltage VDD. The adjustment circuit 03 is connected to LDO2 and receives the PWM1 signal to control the operating state of LDO2. The power supply capacitor C0 is typically integrated externally to the control chip, while the other components of the power supply circuit 10 are integrated internally.

[0043] Furthermore, after the switching power supply starts up, LDO1 turns on, and the main power transistor Q2 is a normally on device. The voltage Vsw at the first node SW between the main power transistor Q1 and the magnetizing inductor LM charges the power supply capacitor C0 through the main power transistor Q2 and LDO1. The supply current flowing through LDO1 is I. LDO1The supply voltage VDD generated across the power supply capacitor C0 rises. When VDD reaches the chip's startup voltage, the chip powers on and generates a PWM signal. When VDD reaches the first threshold VDD1 (greater than or equal to the chip's startup voltage), LDO1 is cut off. LDO1 ensures that the supply voltage VDD is not lower than the set first threshold VDD1, guaranteeing the chip's normal startup. By setting LDO1, it remains in standby mode. During chip startup, light load, or dynamic operation, the charging circuit containing LDO1 automatically charges, ensuring the chip is always powered and preventing power loss. Furthermore, because LDO1 can charge in standby mode, the capacitance of the power supply capacitor C0 can be set relatively small, still meeting power requirements. After the chip is powered on, it generates a PWM signal. When the PWM signal switches from low to high, LDO2 turns on, and the voltage Vsw continues to charge the power supply capacitor C0 through the main power transistor Q2 and LDO2. The supply voltage VDD on the power supply capacitor C0 continues to rise. In one optional mode, after LDO2 has been on for a period of time, LDO2 is controlled to turn off, and the auxiliary power transistor Q2 is turned on. The on-time of LDO2 can be controlled according to the falling slope of the voltage Vsw. In another optional mode, when the voltage Vsw drops to a preset value, which represents the voltage Vsw dropping close to its trough, LDO2 is controlled to turn off, and the auxiliary power transistor is turned on. By controlling the turn-off time of LDO2, the magnitude of the supply voltage VDD is controlled to avoid the supply voltage VDD being too large or too small, thus avoiding insufficient power supply or low power supply efficiency. This invention charges the power supply capacitor C0 after the PWM signal is valid, so the Vsw voltage will not be too high, the power supply loss is small, and the high loss caused by the large voltage Vsw charging the capacitor C0 during the auxiliary power transistor's turn-off period is avoided. Furthermore, to prevent the supply voltage VDD from being charged too high or becoming overvoltage, the clamping circuit 04 is used to clamp the supply voltage VDD to the second threshold when the supply voltage VDD is greater than the second threshold.

[0044] Furthermore, since dVsw / dt=(I LM -I1) / C EQ Where Vsw is the voltage at the first node, I LM To fix the excitation inductor current, C EQ As an equivalent parasitic capacitance, I1 is the current flowing through the main power transistor Q1. Therefore, the rate of change of the first node voltage Vsw can be adjusted by adjusting the current flowing through the main power transistor Q1. Furthermore, when LDO2 is turned on, the adjustment circuit 03 generates an adjustment signal VM1 to adjust the supply current I flowing through LDO2. LDO2 This, in turn, adjusts the current I1 flowing through the main power transistor Q1, thereby increasing the current I flowing through the LDO2. LDO2By reaching the reference current, the current I1 flowing through the main power transistor Q1 reaches the expected current, which in turn causes the rate of change of the first node voltage Vsw to reach the expected rate of change. This optimizes the system's EMI performance and prevents the first node voltage Vsw from dropping too quickly, which would result in poor EMI performance and damage to the switching power devices. Based on the above analysis, the self-powered scheme of this invention not only saves power supply losses but also optimizes the system's EMI.

[0045] like Figure 4 The diagram illustrates the schematic of Embodiment 1 of the adjustment circuit 03 of the present invention. It includes a first resistor R1 connected between LDO1, LDO2, and the power supply capacitor C0. Preferably, the first resistor R1 and the power supply capacitor C0 are located externally to the chip. The common connection terminal of the first resistor R1 and LDO1 / LDO2 is the power supply pin of the control chip, outputting a power supply voltage VDD. When LDO2 is turned on, the power supply current I flowing through LDO2 can be adjusted by adjusting the value of the first resistor R1. LDO2 This adjusts the rate of change of the voltage Vsw flowing through the first node to optimize the system's EMI performance. Optionally, the adjustment circuit 03 also includes a sampling circuit 301 and a first operational amplifier 302. The sampling circuit 301 samples the voltage across the first resistor R1 to obtain a sampling signal VS. The first operational amplifier 302 amplifies the sampling signal VS and the reference signal Vref to generate an adjustment signal VM1. This adjustment signal VM1 is used to control the current I flowing through LDO2. LDO2 The size of the sampling circuit 301 is further specified. The sampling circuit 301 includes a logic circuit 3011, a first sampling circuit 3012, a second sampling circuit 3013, and a subtractor 3014. The logic circuit 3011 receives the PWM2 signal and can also receive a PWM signal. When the PWM2 signal is valid, indicating that the power supply capacitor C0 is charging, the logic circuit 3011 outputs a control signal tr1 to control the first sampling circuit 3012 to sample the VDD voltage to obtain the first sampling signal VDD1. When the PWM2 signal is invalid, indicating that the power supply capacitor C0 is not charging and LDO2 is turned off, the logic circuit 3011 outputs... Control signal tr2 controls the second sampling circuit 3032 to sample the VDD voltage to obtain the second sampling signal VDD2. Subtractor 3014 subtracts the first sampling signal VDD1 and the second sampling signal VDD2 to obtain the sampling signal VS representing the battery voltage. Furthermore, when capacitor C0 is charging, the supply voltage VDD is equal to the voltage across capacitor C0 plus the voltage across resistor R1. When capacitor C0 is not charging, the supply voltage VDD is equal to the voltage across capacitor C0. Assuming that the voltage across capacitor C0 does not change much before and after charging, and that when LDO2 is turned on, the charging current I... LDO2 Once the expected reference current is reached, the difference VS between the first sampling signal VDD1 and the second sampling signal VDD2 can characterize the voltage across the LDO2 turn-on resistor R1.

[0046] like Figure 5 The diagram illustrates the schematic of Embodiment 2 of the adjustment circuit 03 of the present invention, including a sampling circuit 303, a sample-and-hold circuit 301, and a second operational amplifier 302. The sampling circuit 303 samples the rate of change of the first node voltage Vsw to obtain a sampling signal VS1. Optionally, the sampling circuit 303 includes a capacitor C301 and a resistor R301 connected in series. The voltage at the common connection terminal of the capacitor C301 and the resistor R301 is the sampling signal VS1. The sample-and-hold circuit 301 receives the PWM2 signal. When the PWM2 signal is valid, i.e., when the LDO2 is charging, the sampling signal VS1 is sampled and held to obtain a holding signal V1. The second operational amplifier 302 amplifies the reference signal Vref and the holding signal V1 to obtain an adjustment voltage, which is used to control the conduction current of the LDO, thereby adjusting the rate of change of the first node voltage Vsw to optimize EMI.

[0047] like Figure 6 The diagram illustrates the schematic of the second linear voltage regulator circuit (LDO2) of the present invention, including a regulating transistor M201, a current mirror 201, and a diode D1. The anode of diode D1 is connected to the common connection terminal of the main power transistor Q1 and the auxiliary power transistor Q2 (the voltage at this terminal is Vd2). The cathode of diode D1 is connected to one end of the current mirror 201. The input terminal of the current mirror 201 is connected to the regulating transistor M201, and the output terminal of the current mirror is connected to the high potential terminal of the power supply capacitor C0. The control terminal of the regulating transistor M201 receives the regulating voltage VM1 output by the regulating circuit 03, and controls the current flowing through the regulating transistor M201, i.e., the input current of the current mirror 201, according to the regulating voltage VM1. The output current of the current mirror 201 is the charging current of the power supply capacitor C0, i.e., the current I. LDO2 The output current of the current mirror 201 is proportional to the input current, preferably 1:1. The LDO2 adjusts the charging current I supplied to the power supply capacitor C0 according to the magnitude of the adjustment voltage VM1. LDO2 The magnitude of the voltage is adjusted, thereby regulating the rate of change of the first node voltage Vsw to adjust the switching speed of the main power transistor Q1, thus optimizing the system's EMI and preventing damage to power devices.

[0048] like Figure 7 The diagram shown illustrates the operating waveforms of the self-powered circuit of this invention. Figure 3 The schematic circuit diagram illustrates the waveform: The drive distribution circuit 30 distributes the PWM signal to generate PWM1 and PWM2 signals. During the time period t1-t3, the PWM signal is active. During the active PWM period t1-t2, PWM2 is active, controlling LDO2 to conduct, and the current I on LDO2... LDO2As capacitor C0 charges, the supply voltage VDD rises, the magnetizing inductor Lm charges, and the magnetizing inductor current ILM rises. The voltage Vds_Q2 across the auxiliary power transistor Q2 drops to the Miller plateau voltage of the main power transistor Q1, and the first node voltage Vsw decreases. At time t2, the supply voltage VDD rises to the second threshold VDD2, and the first node voltage Vsw drops to its lowest point. During the time interval t2-t3, PWM1 is active, PWM2 is inactive, the auxiliary power transistor Q2 is turned on, LDO2 is short-circuited and cut off, and the current I on LDO2... LDO2 With the voltage at node 0, the first node voltage Vsw remains at its lowest point. Due to the reduced supply voltage VDD, the voltage Vds_Q2 across the auxiliary power transistor Q2 drops to its lowest point, charging the magnetizing inductor and increasing the magnetizing inductor current ILm. The waveform shows that after the inductor current ILm drops to its lowest point and the PWM becomes effective, but before the auxiliary power transistor Q2 turns on, power is supplied to the supply capacitor C0 through LDO2, and the parasitic capacitance C... EQ The energy from the previous stage is used to charge the power supply capacitor C0, which can save some power supply losses. Additionally, it avoids the significant losses caused by the high voltage Vsw charging capacitor C0, thus optimizing power supply efficiency. Furthermore, by adjusting the current I of LDO2... LDO2 The descent rate of Vsw can be adjusted to optimize system EMI.

[0049] Although the embodiments are described and illustrated separately above, some common technologies are involved. Those skilled in the art can replace and integrate them between the embodiments. If there is any content not explicitly described in one embodiment, then another embodiment that is described can be referred to.

[0050] The embodiments described above do not constitute a limitation on the scope of protection of this technical solution. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the above embodiments should be included within the scope of protection of this technical solution.

Claims

1. A self-powered circuit for a switching power supply, the switching power supply comprising an inductor, a main power transistor, and an auxiliary power transistor, wherein the inductor is connected to a first terminal of the main power transistor, and the auxiliary power transistor is connected between a second terminal of the main power transistor and a ground terminal, characterized in that: include, A power supply capacitor is used to generate the power supply voltage for the control chip of the switching power supply. The first linear voltage regulator circuit is connected between the common connection terminal of the main power transistor and the auxiliary power transistor and the power supply capacitor; The second linear voltage regulator circuit is connected in parallel with the first linear voltage regulator circuit. An adjustment circuit is connected to the second linear voltage regulator circuit. When the second linear voltage regulator circuit is turned on, the first charging current flowing through the second linear voltage regulator circuit is adjusted so that the voltage change rate of the first node between the main power transistor and the inductor reaches a preset change rate. During the startup process of the switching power supply, the first linear voltage regulator circuit is turned on, and the power supply capacitor is charged; when the PWM signal generated by the control chip of the switching power supply is valid, the second linear voltage regulator circuit is turned on, and the power supply capacitor is charged.

2. The self-powered circuit according to claim 1, characterized in that: When the supply voltage reaches the first threshold, the first linear regulator circuit is turned off.

3. The self-powered circuit according to claim 1, characterized in that: When the second linear regulator circuit is turned on, the adjustment circuit adjusts the first charging current to the reference current so that the voltage change rate of the first node between the main power transistor and the inductor reaches the preset change rate.

4. The self-powered circuit according to claim 1, characterized in that: The adjustment circuit includes a first resistor connected in the charging path between the second linear voltage regulator circuit and the power supply capacitor; the magnitude of the first charging current is set by setting the magnitude of the first resistor.

5. The self-powered circuit according to claim 4, characterized in that: The adjustment circuit further includes a sampling circuit and a first operational amplifier. When the second linear voltage regulator circuit is turned on, the sampling circuit samples the voltage of the first resistor to obtain a voltage sampling signal. The first operational amplifier performs operational amplification on the voltage sampling signal and the first reference voltage to obtain an adjustment voltage, and the adjustment voltage controls the magnitude of the first charging current.

6. The self-powered circuit according to claim 5, characterized in that: The sampling circuit is configured such that when the second linear voltage regulator circuit is turned on, the voltage at the sampling power supply terminal is used to obtain a first sampling signal. When the second linear voltage regulator circuit is turned off, the voltage at the sampling power supply terminal is used to obtain the second sampling signal. Subtracting the first sampled signal from the second sampled signal yields a voltage sampled signal characterizing the voltage of the first resistor; The power supply terminal is the common connection terminal between the second linear voltage regulator circuit and the first resistor.

7. The self-powered circuit according to claim 5, characterized in that: The first resistor and the power supply capacitor are integrated outside the control chip, while the first linear voltage regulator circuit, the second linear voltage regulator circuit, the main power transistor, and the auxiliary power transistor are integrated inside the control chip.

8. The self-powered circuit according to claim 1, characterized in that: The adjustment circuit includes a rate of change detection circuit, which is used to detect the rate of change of the first node voltage to obtain a rate of change detection signal, and adjust the first charging current according to the rate of change detection signal.

9. The self-powered circuit according to claim 8, characterized in that: The adjustment circuit further includes a sample-and-hold circuit and a second operational amplifier. When the second linear voltage regulator circuit is turned on, the sample-and-hold circuit samples and holds the rate of change detection signal. The second operational amplifier performs operational amplification on the rate of change detection signal obtained from the sample-and-hold circuit and the second reference voltage to obtain an adjustment voltage, which controls the magnitude of the first charging current.

10. The self-powered circuit according to claim 1, characterized in that: It also includes a clamping circuit, which is connected to the high-potential end of the power supply capacitor, and is used to clamp the power supply voltage at the preset value when the power supply voltage is greater than the preset value.

11. The self-powered circuit according to claim 1, characterized in that: When the turn-on time of the second linear voltage regulator circuit reaches the preset time, the second linear voltage regulator circuit is turned off, and the auxiliary power transistor is turned on.

12. The self-powered circuit according to claim 1, characterized in that: When the voltage at the first node between the main power transistor and the inductor drops to a preset voltage, the second linear regulator circuit is turned off, and the auxiliary power transistor is turned on.

13. The self-powered circuit according to claim 1, characterized in that: The power transistor is a depletion-type transistor.

14. A switching power supply, comprising a main power transistor and an inductor connected in series, characterized in that: The self-powered circuit according to any one of claims 1-13 is used to generate the power supply voltage of the control chip of the switching power supply.

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