LLR and partial sum updating method and device in SSCL decoding

Abstract

The invention discloses an LLR and partial sum updating method in SSCL decoding, which comprises the following steps: selecting an f function or a g function according to a bit value corresponding to a current level in f / g control signals of a current decoding node, and calculating and judging an LLR sequence required by the current decoding node; l LLR values with the minimum absolute values in the LLR sequence are selected; carrying out expansion decoding judgment on the current decoding node to obtain an expansion decoding path sequence; calculating a final candidate decoding path by using the current existing extended decoding path sequence; calculating the f / g control signal of the next node according to the node length of the current decoding node and the f / g control signal; updating the part and sequence of each candidate decoding path of the next node by using the final candidate decoding path sequence and the f / g control signal of the next node; the invention further discloses an LLR and partial sum updating device in SSCL decoding. According to the technical scheme of the invention, the calculation speed of the update control of the LLR and the partial sum can be effectively improved, and the hardware resource consumption of the decoder is reduced.

Description

Technical Field

[0001] The invention belongs to the field of communication technology, and in particular relates to a method and device for updating LLR and partial sum in SSCL decoding. Background Art

[0002] With the continuous development of information and communication technology, people have higher and higher requirements for the reliability and fault tolerance of communication systems. Polar code, as a new type of coding method, is a coding scheme that has been proven to reach the channel capacity limit through rigorous mathematical methods. It has the advantages of simple decoding and excellent performance, and has been widely used in communication systems. The simplified serial cancellation list (SSCL) decoding algorithm of polar code reconstructs the codewords to be decoded according to multiple node types, which changes the decoding method from the traditional single-bit decision to a one-time multi-bit decision. This multi-bit node-by-node decoding method allows the decoder to terminate the iterative calculation of the LLR in advance at a higher log-likelihood ratio (LLR) level, and directly obtain the bit estimates of multiple codewords, thereby eliminating redundant calculations, greatly increasing the decoding efficiency of the decoder, and causing almost no loss in error performance. However, since the lengths of various nodes are different, the distribution levels of the nodes are also different, resulting in the number of LLR iterations and the update and interpretation of partial sums having a very high complexity. This makes it difficult to achieve low hardware area and high throughput for the SSCL decoding algorithm, thus limiting the application of the SSCL decoder. Summary of the invention

[0003] In order to solve the above problems existing in the prior art, the present invention proposes a method and device for updating LLR and partial sum in SSCL decoding, so as to improve the throughput of the SSCL decoder and reduce its hardware area.

[0004] A method for updating LLR and partial sum in SSCL decoding of the present invention comprises:

[0005] Step 1: According to the current decoding node node i+1 f / g control signal CTRL i+1 Corresponding to the bit value of the current level, select the f function or the g function to calculate the LLR sequence required to determine the current decoding node;

[0006] Step 2: Select L LLR values ​​with the smallest absolute values ​​in the LLR sequence, and obtain a position index sequence I of the L LLR values ​​with the smallest absolute values ​​in the LLR sequence;

[0007] Step 3: Perform extended decoding judgment on the current decoding node to obtain an extended decoding path sequence codewords_pm;

[0008] Step 4: Calculate the final candidate decoding path using the currently available extended decoding path sequence;

[0009] Step 5: Calculate the f / g control signal of the next node according to the node length and f / g control signal of the current decoding node;

[0010] Step 6: Using the final candidate decoding path sequence and the f / g control signal of the next node, update the partial sum sequence of each candidate decoding path of the next node;

[0011] Step seven, perform CRC check on each candidate decoding path in the final candidate decoding path sequence; if the CRC check result of any candidate decoding path is 0, select the candidate decoding path with a CRC check result of 0 as the final decoding path; if the CRC check results of all candidate decoding paths are not 0, select the candidate decoding path with the smallest path metric value as the final decoding path.

[0012] Furthermore, the step 1 includes:

[0013] If the jth bit of the control signal of the current decoding node f / g is 0, the LLR sequence of the next level is calculated using the f function and the LLR sequence of the current level;

[0014]

[0015] If the jth bit of the control signal of the current decoding node f / g is 1, the LLR sequence of the next level is calculated using the g function and the LLR sequence of the current level;

[0016]

[0017] The calculated LLR sequence of the next level is used as the LLR sequence of the current level, and this step is repeated until the LLR sequence R of the level where the current decoding node is located is obtained. n ;

[0018] in, is the qth LLR value of level j+1; is the qth LLR value of level j; is the first LLR values, level j represents the current level; ps q is the partial sum corresponding to the qth LLR value of level j.

[0019] Furthermore, the step 4 includes:

[0020] Among the existing extended decoding paths, select L extended decoding paths with the smallest path metric values ​​as candidate decoding paths;

[0021] For the candidate decoding paths, perform steps 1 to 4 respectively to obtain a sequence of all extended decoding paths Decode_path;

[0022] Select the L extended decoding paths with the smallest path metric value in Decode_path as the final candidate decoding path sequence Decode_path final .

[0023] Furthermore, the step five includes:

[0024] According to node i+1 The node length B i+1 , get CTRL i+1 The effective field temp;

[0025]

[0026] Fill the right side of temp with 0 to make its bit width log2N, and get CTRL i+2 ;

[0027]

[0028] Among them, CTRL i+1 is the f / g control signal of the current decoding node, CTRL i+2 is the f / g control signal of the next decoding node; N is the length of the word to be decoded; CTRL i+1 [log2N:1] means taking CTRL i+1 bit log2N in to bit 1, and so on.

[0029] Furthermore, the step six includes:

[0030] Calculate the partial sum sequence PSUM of the next decoding node i+2 ;

[0031]

[0032] According to the node length B i+2 and CTRL i+2 Update control signal PSUM_Valid for calculating partial sums i+2 ;

[0033]

[0034] According to the PSUM_Valid i+2 , update the PSUM i+2 ;

[0035]

[0036] n={1,2,…,log2N}

[0037] Among them, ps n is the partial sum result of level n, For ps n The generator matrix is ​​num, num is the latest decoded num decoding bits; N is the length of the word to be decoded.

[0038] An LLR and partial sum updating device in SSCL decoding of the present invention comprises:

[0039] A node information acquisition module is used for the decoder to obtain a codeword sequence A to be decoded and an LLR sequence R1 of level 1 from the channel;

[0040] LLR calculation module is used to calculate the current decoding node node i+1 f / g control signal CTRL i+1 Corresponding to the bit value of the current level, select the f function or the g function to calculate the LLR sequence required to determine the current decoding node;

[0041] LLR selection module, used to select R n The L LLR values ​​with the smallest absolute values ​​are obtained in R n Position index sequence I in

[0042] Expand the decoding path calculation module to calculate the current decoding node node i+1 Perform extended decoding judgment and obtain node i+1 The extended decoding path sequence codewords_pm;

[0043] The candidate decoding path selection module is used to calculate the final candidate decoding path Decode_path using the currently available extended decoding path sequence codewords_pm final ;

[0044] f / g control signal update module, used to update the current decoding node node i+1 The node length and CTRL i+1 , calculate the f / g control signal CTRL of the next node i+2 ;

[0045] Partial and updated module for utilizing Decode_path final and CTRL i+2 Update the partial sum sequence PSUM of each candidate decoding path for the next node i+2 ;

[0046] The final decoding path selection module is used to select the final candidate decoding path sequence Decode_path final Perform CRC check on each candidate decoding path in to obtain the final decoding path;

[0047] If the CRC check result of a candidate decoding path is 0, the candidate decoding path with the CRC check result of 0 is selected as the final decoding path; if the CRC check results of all candidate decoding paths are not 0, the candidate decoding path with the smallest path metric value is selected as the final decoding path.

[0048] Furthermore, the LLR calculation module includes:

[0049] Control signal judgment unit, used to judge node i+1 The f and g operation control signal CTRL i+1 Whether the j-th bit of is 0; if so, the LLR sequence of the next level is calculated by the f calculation unit, otherwise, the LLR sequence of the next level is calculated by the g calculation unit;

[0050] An f calculation unit, used for calculating the LLR sequence of the next level by using the f function and the LLR sequence of the current level;

[0051]

[0052] A g calculation unit, used for calculating the LLR sequence of the next level by using the g function and the LLR sequence of the current level;

[0053]

[0054] in, is the qth LLR value of level j+1; is the qth LLR value of level j; is the first LLR values, level j represents the current level; ps q is the partial sum corresponding to the qth LLR value of level j.

[0055] Furthermore, the candidate decoding path selection module includes:

[0056] A candidate decoding path selection unit is used to select L extended decoding paths with the smallest path metric values ​​from the existing extended decoding paths as candidate decoding paths, and send them to the LLR calculation module to perform extended decoding to obtain a candidate decoding path sequence Decode_path;

[0057] The final candidate path acquisition unit is used to select L extended decoding paths with the smallest path metric value in Decode_path as the final candidate decoding path sequence Decode_path final .

[0058] Furthermore, the control signal update module of f and g includes:

[0059] Valid field acquisition unit, used to obtain the valid field according to the node i+1 The node length B i+1 , get CTRL i+1 The effective field temp;

[0060]

[0061] The control signal update unit is used to pad the right side of temp with 0 to make its bit width log2N and obtain CTRL i+2 ;

[0062]

[0063] Among them, CTRL i+1 is the f / g control signal of the current decoding node, CTRL i+2 is the f / g control signal of the next decoding node; N is the length of the word to be decoded; CTRL i+1 [log2N:1] means taking CTRL i+1 bit log2N in to bit 1, and so on.

[0064] Further, the part and update module include:

[0065] Partial sum sequence calculation unit, used to calculate the partial sum sequence PSUM of the next node i+2 ;

[0066]

[0067] The effective signal calculation unit is used to calculate the effective signal according to the node length B. i+2 And the control signal CTRL i+2 Update control signal PSUM_Valid for calculating partial sums i+2 ;

[0068]

[0069] section and update unit for the PSUM_Valid i+2 , update the PSUM i+2 ;

[0070]

[0071] n={1,2,…,log2N}

[0072] Among them, ps n is the partial sum result of level n, For ps n The generator matrix is ​​num, num is the latest decoded num decoding bits; N is the length of the word to be decoded.

[0073] In the technical solution of the present invention, the effective rules of decoding are used to control according to the control signals of the f function and the g function and the node length. The operation control signals of the f function and the g function are obtained by using the a priori known node length. According to the control signal, the single-bit value of the corresponding position is used to determine whether the calculation of each LLR level uses the f function and the g function; the effective rules of decoding are used to control whether the partial sum data of each level is updated to the current new value or maintained as the old value according to the control signals of the f function and the g function and the node length. The above update control method of LLR and partial sum data only involves simple operations such as AND, OR, and addition of single-bit data, and the related update control signals can form a unique hot code, so that the selection structure only needs to compare one bit, thereby speeding up the execution speed of the hardware, improving the calculation speed of the update control of LLR and partial sum, reducing the hardware resource consumption of the decoder, and improving the throughput of the decoder. BRIEF DESCRIPTION OF THE DRAWINGS

[0074] Figure 1 It is a schematic diagram of the binary tree structure of the codeword to be decoded in the technical solution of the present invention;

[0075] Figure 2 is a flow chart of a method according to a specific embodiment 1 of the present invention;

[0076] Figure 3 It is a schematic diagram of the structure of the device of specific embodiment 2 of the present invention; DETAILED DESCRIPTION

[0077] In order to better illustrate the technical solution of the present invention, the specific implementation manner of the present invention is described in detail below with reference to the accompanying drawings.

[0078] In the following specific embodiments of the present invention, the length of the codeword to be decoded of the polar code obtained from the channel is N. The codeword to be decoded contains two types of information bits and frozen bits. The frozen bits are directly judged as 0 according to the a priori known position sequence; the information bits need to be judged according to the corresponding LLR values. Figure 2 As shown in FIG. 1 , the calculation of the LLR value is performed in a hierarchical manner. The hierarchical level is determined by the length of the codeword to be decoded. The polar code with a codeword length of N has a total of log2N layers of LLR value sequences. The hierarchical numbers are numbered from small to large from top to bottom. The LLR sequence of the top layer is R1 = {llr1, llr2, …, llrN}. The number of candidate lists of the SSCL decoding algorithm is L, and the codeword to be decoded contains four special nodes: R0 node, all frozen bit node; R1 node, all information bit node; REP node, the last bit is the information bit, and the rest of the bits are frozen bits; SPC node, the first bit is the frozen bit, and the rest of the bits are information bits. The above four special nodes can completely represent the codeword to be decoded. Specific embodiment 1

[0080] This embodiment is a preferred implementation of the method for updating LLR and partial sums in SSCL decoding of the present invention.

[0081] See also Figure 2 ,like Figure 2 As shown, the method of this embodiment includes:

[0082] S101, the decoder obtains a codeword sequence A to be decoded and an LLR sequence R1 of level 1 from a channel;

[0083] Α={node1,node2,…,node x}

[0084] node i ={T i ,B i}

[0085] Among them, node i represents the i-th special node, T i For node i The node type, B i For node i , x is the number of nodes contained in Α.

[0086] S102, using the f function and the g function to calculate the decision node i+1 The required LLR sequence R n ;

[0087] In this specific embodiment, this step may further include:

[0088] S1021, judge CTRL i+1 Whether the j-th bit of is 0, if yes, execute step S1022, otherwise, execute step S1023;

[0089] S1022, calculating the LLR sequence of the next level using the f function and the LLR sequence of the current level;

[0090]

[0091] Among them, CTRLi+1 For node i+1 The f and g operation control signals, is the qth LLR value of level j+1; is the qth LLR value of level j; is the first LLR value; executing step S1024;

[0092] S1023, calculating the LLR sequence of the next level by using the g function and the LLR sequence of the current level;

[0093]

[0094] Among them, ps q is the partial sum corresponding to the qth LLR value of level j.

[0095] S1024, set the level of the LLR sequence calculated in step S1022 or S1023 as the current level, and repeat steps S1021 to S1023 until node i+1 LLR sequence R at the level n ;

[0096] S103, Select R n The L LLR values ​​with the smallest absolute values ​​are obtained in R n Position index sequence I in

[0097] I={index L ,index L-1 ,…,index1}

[0098] Among them, the position indexes in I are arranged from large to small according to the absolute value of their corresponding LLR values, and index1 is the LLR value with the smallest absolute value in R n Position index in, index L The LLR value with the smallest absolute value is in R n The position index in .

[0099] S104, decode the current node node i+1 Perform extended decoding judgment and obtain node i+1 The extended decoding path sequence codewords_pm.

[0100] In this specific embodiment, this step may further include:

[0101] S1041, determine node i+1If the node type is R0, execute step S1042; if the node type is R1, execute step S1043; if the node type is SPC, execute step S1044; if the node type is REP, execute step S1045;

[0102] S1042, R n Perform extended decoding according to the R0 node method, calculate the path metric value of each extended decoding path, and obtain codewords_pm;

[0103]

[0104] α k =0

[0105] llr k ∈R n , 1≤k≤B i+1 , 0<l≤L

[0106] Among them, penalty k is the path penalty value; α k is the decision bit;

[0107] S1043, R n Perform extended decoding according to the R1 node mode and calculate the path metric value of each extended decoding path to obtain the extended decoding path sequence codewords_pm;

[0108] R n Make hard decisions and calculate their path metrics to obtain the optimal decoding path

[0109]

[0110] llr k ∈R n , 1≤k≤B i+1

[0111] According to R n performing L-1 extended decoding on the optimal decoding path to obtain L-1 extended decoding paths;

[0112] α k =~α k

[0113]

[0114] penalty k =|llr k |

[0115] llrk ∈R n , k∈I

[0116] Among them, ~ is a bit flip operation;

[0117] According to the path metric value of each decoding path Arrange the optimal decoding path and the extended decoding path in descending order to obtain codewords_pm;

[0118]

[0119] S1044, R n Perform extended decoding according to the SPC node method and calculate the path metric value of each extended decoding path to obtain codewords_pm;

[0120] R n Make hard decisions and calculate their path metrics to obtain the optimal decoding path

[0121]

[0122] llr k ∈R n , 1≤k≤B i+1

[0123] Perform verification calculation on the node codeword to obtain the verification value λ;

[0124]

[0125] If λ≠0, updating the optimal decoding path;

[0126]

[0127] According to the LLR values ​​corresponding to the position indexes in I, performing L-1 extended decoding on the optimal decoding path to obtain L-1 extended decoding paths;

[0128]

[0129] Among them, k1 and k2 are the numbers of the L-1 pairs of LLR values ​​whose sum of the absolute values ​​of the LLRs corresponding to the position indices in I is the smallest.

[0130] According to the path metric value of each decoding path Arrange the optimal decoding path and the extended decoding path in descending order to obtain codewords_pm;

[0131]

[0132] S1045, Rn Perform extended decoding according to the REP node method and calculate the path metric value of each extended decoding path to obtain codewords_pm;

[0133] Calculate the path metric PM of the candidate path with all 0 decoding 0 ;

[0134]

[0135] llr k ∈R n , 1≤k≤B i+1

[0136] Calculate the path metric PM of the candidate path with all 1 decoding 1 ;

[0137]

[0138] llr k ∈R n , 1≤k≤B i+1

[0139] getcodewords_pm;

[0140]

[0141] S1046, using the generation matrix to update each decoding path in codewords_pm;

[0142]

[0143] in, To generate the matrix, log2B is calculated from the basic matrix F. i+1 The Kronecker product of is obtained.

[0144] S105, using the currently existing extended decoding path sequence codewords_pm, calculate and obtain the final candidate decoding path;

[0145] S1051. Select L extended decoding paths with the smallest path metrics from among the existing extended decoding paths as candidate decoding paths;

[0146] S1052, executing steps S102 to S105 respectively for the candidate decoding paths to obtain a sequence Decode_path of all extended decoding paths;

[0147] Decode_path = {codewords_pm L ,codewords_pm L-1,…,codewords_pm1}

[0148] S1053, select L extended decoding paths with the smallest path metric values ​​in Decode_path as the final candidate decoding path sequence Decode_path final ;

[0149] S106, according to the current decoding node node i+1 The node length and control signal CTRL i+1 , calculate the control signal CTRL of the next node i+2 ;

[0150] In this specific embodiment, this step may further include:

[0151] According to node i+1 B i+1 , get CTRL i+1 The effective field temp;

[0152]

[0153] Among them, CTRL i+1 [log2N:1] means taking CTRL i+1 bit log2N in to bit 1, and so on.

[0154] Fill the right side of temp with 0 to make its bit width log2N, and get CTRL i+2 ;

[0155]

[0156] S107, using Decode_path final and CTRL i+2 Update the partial sum sequence PSUM of each candidate decoding path for the next node i+2 ;

[0157] In this specific embodiment, this step may further include:

[0158] S1071. Calculate the partial sum sequence PSUM of the next node i+2 ;

[0159]

[0160] Among them, ps n is the partial sum result of level n, For ps n The generator matrix of , num is the num decoded bits decoded most recently;

[0161] S1072, according to the node length B i+2 And the control signal CTRL i+2 Update control signal PSUM_Valid for calculating partial sums i+2 ;

[0162]

[0163] S1073, according to the PSUM_Valid i+2 , update the PSUM i+2 ;

[0164]

[0165] n={1,2,…,log2N}

[0166] Repeat steps S102 to S107 until all nodes are decoded;

[0167] S108, respectively decode the final candidate decoding path sequence Decode_path final Perform CRC check on each candidate decoding path in to obtain the final decoding path;

[0168] If the CRC check result of a candidate decoding path is 0, the candidate decoding path with the CRC check result of 0 is selected as the final decoding path; if the CRC check results of all candidate decoding paths are not 0, the candidate decoding path with the smallest path metric value is selected as the final decoding path.

[0169] In this specific embodiment, the specific calculation method of the CRC check of this step can use the public CRC check method such as the paper "Optimized FPGA Implementation of the CRC Using Parallel Pipelining Architecture" published in the "2019 International Conference on Advanced Science and Engineering" in 2019. Specific embodiment 2

[0171] This embodiment is a preferred implementation of the LLR and partial sum updating device in SSCL decoding of the present invention.

[0172] See also Figure 3 ,like Figure 3 As shown, the device of this embodiment includes:

[0173] A node information acquisition module is used for the decoder to obtain a codeword sequence A to be decoded and an LLR sequence R1 of level 1 from the channel;

[0174] Α={node1,node2,…,node x}

[0175] node i ={T i ,B i}

[0176] Among them, node i represents the i-th special node, T i For node i The node type, B i For node i , x is the number of nodes contained in Α.

[0177] LLR calculation module, used to calculate the decision node using f function and g function i+1 The required LLR sequence R n ;

[0178] In this specific embodiment, this module may further include:

[0179] Control signal judgment unit, used to judge node i+1 The f and g operation control signal CTRL i+1 Whether the j-th bit of is 0; if so, the LLR sequence of the next level is calculated by the f calculation unit, otherwise, the LLR sequence of the next level is calculated by the g calculation unit;

[0180] An f calculation unit, used for calculating the LLR sequence of the next level by using the f function and the LLR sequence of the current level;

[0181]

[0182] in, is the qth LLR value of level j+1; is the qth LLR value of level j; is the first LLR values;

[0183] A g calculation unit, used for calculating the LLR sequence of the next level by using the g function and the LLR sequence of the current level;

[0184]

[0185] Among them, ps q is the partial sum corresponding to the qth LLR value of level j.

[0186] LLR selection module, used to select R n The L LLR values ​​with the smallest absolute values ​​are obtained in R n Position index sequence I in

[0187] I={index L ,index L-1 ,…,index1}

[0188] Among them, the position indexes in I are arranged from large to small according to the absolute value of their corresponding LLR values, and index1 is the LLR value with the smallest absolute value in R n Position index in, index L The LLR value with the smallest absolute value is in R n The position index in .

[0189] Expand the decoding path calculation module to calculate the current decoding node node i+1 Perform extended decoding judgment and obtain node i+1 The extended decoding path sequence codewords_pm.

[0190] In this specific embodiment, this module may further include:

[0191] A decoding type selection unit, used to determine the node type of the current decoding node, and select a corresponding extended decoding mode according to the node type;

[0192] The R0 node decoding unit is used to n Perform extended decoding according to the R0 node method, calculate the path metric value of each extended decoding path, and obtain codewords_pm;

[0193]

[0194] α k =0

[0195] llr k ∈R n , 1≤k≤B i+1 , 0<l≤L

[0196] Among them, penalty k is the path penalty value; α k is the decision bit;

[0197] The R1 node decoding unit is used to nPerform extended decoding according to the R1 node mode and calculate the path metric value of each extended decoding path to obtain the extended decoding path sequence codewords_pm;

[0198] R n Make hard decisions and calculate their path metrics to obtain the optimal decoding path

[0199]

[0200] llr k ∈R n , 1≤k≤B i+1

[0201] According to R n performing L-1 extended decoding on the optimal decoding path to obtain L-1 extended decoding paths;

[0202] α k =~α k

[0203]

[0204] penalty k =|llr k |

[0205] llr k ∈R n , k∈I

[0206] Among them, ~ is a bit flip operation;

[0207] According to the path metric value of each decoding path Arrange the optimal decoding path and the extended decoding path in descending order to obtain codewords_pm;

[0208]

[0209] The SPC node decoding unit is used to decode R n Perform extended decoding according to the SPC node method and calculate the path metric value of each extended decoding path to obtain codewords_pm;

[0210] R n Make hard decisions and calculate their path metrics to obtain the optimal decoding path

[0211]

[0212]

[0213] llr k ∈R n , 1≤k≤B i+1

[0214] Perform verification calculation on the node codeword to obtain the verification value λ;

[0215]

[0216] If λ≠0, updating the optimal decoding path;

[0217]

[0218] According to the LLR values ​​corresponding to the position indexes in I, performing L-1 extended decoding on the optimal decoding path to obtain L-1 extended decoding paths;

[0219]

[0220] Among them, k1 and k2 are the numbers of the L-1 pairs of LLR values ​​whose sum of the absolute values ​​of the LLRs corresponding to the position indices in I is the smallest.

[0221] According to the path metric value of each decoding path Arrange the optimal decoding path and the extended decoding path in descending order to obtain codewords_pm;

[0222]

[0223] REP node decoding unit is used to n Perform extended decoding according to the REP node method and calculate the path metric value of each extended decoding path to obtain codewords_pm;

[0224] Calculate the path metric PM of the candidate path with all 0 decoding 0 ;

[0225]

[0226] llr k ∈R n , 1≤k≤B i+1

[0227] Calculate the path metric PM of the candidate path with all 1 decoding 1 ;

[0228]

[0229] llr k ∈R n , 1≤k≤B i+1

[0230] getcodewords_pm;

[0231]

[0232] A decoding path updating unit, used for updating each decoding path in codewords_pm;

[0233]

[0234] in, To generate the matrix, log2B is calculated from the basic matrix F. i+1 The Kronecker product of is obtained.

[0235] The candidate decoding path selection module is used to calculate the final candidate decoding path Decode_path using the currently available extended decoding path sequence codewords_pm final ;

[0236] In this specific embodiment, this module may further include:

[0237] A candidate decoding path selection unit is used to select L extended decoding paths with the smallest path metric values ​​from the existing extended decoding paths as candidate decoding paths, and send them to the LLR calculation module to perform extended decoding to obtain a candidate decoding path sequence Decode_path;

[0238] Decode_path = {codewords_pm L ,codewords_pm L-1 ,…,codewords_pm1}

[0239] The final candidate path acquisition unit is used to select L extended decoding paths with the smallest path metric value in Decode_path as the final candidate decoding path sequence Decode_path final ;

[0240] f / g control signal update module, used to update the current decoding node node i+1 The node length and CTRL i+1 , calculate the CTRL of the next node i+2 ;

[0241] In this specific embodiment, this module may further include:

[0242] Valid field acquisition unit, used to obtain the valid field according to the node i+1 B i+1 , get CTRL i+1The effective field temp;

[0243]

[0244] Among them, CTRL i+1 [log2N:1] means taking CTRL i+1 bit log2N in to bit 1, and so on.

[0245] The control signal update unit is used to pad the right side of temp with 0 to make its bit width log2N and obtain CTRL i+2 ;

[0246]

[0247] Partial and update module, using Decode_path final and CTRL i+2 Update the partial sum sequence PSUM of each candidate decoding path for the next node i+2 ;

[0248] In this specific embodiment, this module may further include:

[0249] Partial sum sequence calculation unit, used to calculate the partial sum sequence PSUM of the next node i+2 ;

[0250]

[0251]

[0252] Among them, ps n is the partial sum result of level n, For ps n The generator matrix of , num is the num decoded bits decoded most recently;

[0253] The effective signal calculation unit is used to calculate the effective signal according to the node length B. i+2 And the control signal CTRL i+2 Update control signal PSUM_Valid for calculating partial sums i+2 ;

[0254]

[0255] section and update unit for the PSUM_Valid i+2 , update the PSUM i+2 ;

[0256]

[0257] n={1,2,…,log2N}

[0258] The final decoding path selection module is used to select the final candidate decoding path sequence Decode_path final Perform CRC check on each candidate decoding path in to obtain the final decoding path;

[0259] If the CRC check result of a candidate decoding path is 0, the candidate decoding path with the CRC check result of 0 is selected as the final decoding path; if the CRC check results of all candidate decoding paths are not 0, the candidate decoding path with the smallest path metric value is selected as the final decoding path.

[0260] In this specific embodiment, the specific calculation method of the CRC check of this module can use the public CRC check method such as the paper "Optimized FPGA Implementation of the CRC Using Parallel Pipelining Architecture" published in the "2019 International Conference on Advanced Science and Engineering" in 2019.

[0261] In the above specific embodiment of the present invention, the a priori known node length is first used to calculate the f and g operation control signals of the current decoding node, and the partial sums of each level are updated according to the f and g control signals and the node length. In the technical scheme of the specific embodiment of the present invention, the update control method of LLR and partial sum data only involves single-bit AND, OR, and simple addition operations. The relevant update control signals can simply form a unique hot code, so that the selection structure only needs to compare one bit, thereby further accelerating the execution speed of the hardware. Through the technical scheme of the present invention, the calculation speed of the update control of LLR and partial sum is improved, the hardware resource consumption of the decoder is reduced, and the throughput of the decoder is improved.

[0262] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention can be modified or replaced by equivalents without departing from the purpose and scope of the technical solutions of the present invention, which should be included in the scope of the claims of the present invention.

Claims

1. A method for updating LLR and partial sum in SSCL decoding, characterized in that: include: Step 1: According to the current decoding node node i+1 f / g control signal CTRL i+1 Corresponding to the bit value of the current level, select the f function or the g function to calculate the LLR sequence required to determine the current decoding node; Step 2: Select L LLR values ​​with the smallest absolute values ​​in the LLR sequence, and obtain a position index sequence I of the L LLR values ​​with the smallest absolute values ​​in the LLR sequence; Step 3: Perform extended decoding judgment on the current decoding node to obtain an extended decoding path sequence codewords_pm; Step 4: Calculate the final candidate decoding path using the currently available extended decoding path sequence; Step 5: Calculate the f / g control signal of the next node according to the node length and f / g control signal of the current decoding node; Step 6: Using the final candidate decoding path sequence and the f / g control signal of the next node, update the partial sum sequence of each candidate decoding path of the next node.

2. The method according to claim 1, characterized in that: The step one comprises: If the jth bit of the control signal of the current decoding node f / g is 0, the LLR sequence of the next level is calculated using the f function and the LLR sequence of the current level; If the jth bit of the control signal of the current decoding node f / g is 1, the LLR sequence of the next level is calculated using the g function and the LLR sequence of the current level; The calculated LLR sequence of the next level is used as the LLR sequence of the current level, and this step is repeated until the LLR sequence R of the level where the current decoding node is located is obtained. n ; in, is the qth LLR value of level j+1; is the qth LLR value of level j; is the first LLR values, level j represents the current level; ps q is the partial sum corresponding to the qth LLR value of level j.

3. The method according to claim 2, characterized in that The fourth step comprises: Among the existing extended decoding paths, select L extended decoding paths with the smallest path metric values ​​as candidate decoding paths; For the candidate decoding paths, perform steps 1 to 4 respectively to obtain a sequence of all extended decoding paths Decode_path; Select the L extended decoding paths with the smallest path metric value in Decode_path as the final candidate decoding path sequence Decode_path final .

4. The method according to claim 3, characterized in that The step five comprises: According to node i+1 The node length B i+1 , get CTRL i+1 The effective field temp; Fill the right side of temp with 0 to make its bit width log2N, and get CTRL i+2 ; Among them, CTRL i+1 is the f / g control signal of the current decoding node, CTRL i+2 is the f / g control signal of the next decoding node; N is the length of the word to be decoded; CTRL i+1 [log2N:1] means taking CTRL i+1 bit log2N in to bit 1, and so on.

5. The method according to claim 4, characterized in that Step six shown includes: Calculate the partial sum sequence PSUM of the next decoding node i+2 ; According to the node length B i+2 and CTRL i+2 Update control signal PSUM_Valid for calculating partial sums i+2 ; According to the PSUM_Valid i+2 , update the PSUM i+2 ; n={1,2,…,log2N} Among them, ps n is the partial sum result of level n, For ps n The generator matrix of , num is the num decoded bits decoded most recently; {α num ,α num-1 ,…,α1} are the decision bits in codewords_pm, and N is the length of the codeword to be decoded.

6. An apparatus for updating LLR and partial sums in SSCL decoding, characterized in that: include: A node information acquisition module is used for the decoder to obtain a codeword sequence A to be decoded and an LLR sequence R1 of level 1 from the channel; LLR calculation module is used to calculate the current decoding node node i+1 f / g control signal CTRL i+1 Corresponding to the bit value of the current level, select the f function or the g function to calculate the LLR sequence required to determine the current decoding node; LLR selection module, used to select R n The L LLR values ​​with the smallest absolute values ​​are obtained in R n Position index sequence I in Expand the decoding path calculation module to calculate the current decoding node node i+1 Perform extended decoding judgment and obtain node i+1 The extended decoding path sequence codewords_pm; The candidate decoding path selection module is used to calculate the final candidate decoding path Decode_path using the currently available extended decoding path sequence codewords_pm final ; f / g control signal update module, used to update the current decoding node node i+1 The node length and CTRL i+1 , calculate the f / g control signal CTRL of the next node i+2 ; Partial and updated module for utilizing Decode_path final and CTRL i+2 Update the partial sum sequence PSUM of each candidate decoding path for the next node i+2 .

7. The device according to claim 6, characterized in that The LLR calculation module comprises: Control signal judgment unit, used to judge node i+1 The f and g operation control signal CTRL i+1 Whether the j-th bit of is 0; if so, the LLR sequence of the next level is calculated by the f calculation unit, otherwise, the LLR sequence of the next level is calculated by the g calculation unit; An f calculation unit, used for calculating the LLR sequence of the next level by using the f function and the LLR sequence of the current level; A g calculation unit, used for calculating the LLR sequence of the next level by using the g function and the LLR sequence of the current level; in, is the qth LLR value of level j+1; is the qth LLR value of level j; is the first LLR values, level j represents the current level; ps q is the partial sum corresponding to the qth LLR value of level j.

8. The device according to claim 7, characterized in that The candidate decoding path selection module comprises: A candidate decoding path selection unit is used to select L extended decoding paths with the smallest path metric values ​​from the existing extended decoding paths as candidate decoding paths, and send them to the LLR calculation module to perform extended decoding to obtain a candidate decoding path sequence Decode_path; The final candidate path acquisition unit is used to select L extended decoding paths with the smallest path metric value in Decode_path as the final candidate decoding path sequence Decode_path final .

9. The device according to claim 8, characterized in that The f / g control signal updating module comprises: Valid field acquisition unit, used to obtain the valid field according to the node i+1 The node length B i+1 , get CTRL i+1 The effective field temp; The control signal update unit is used to pad the right side of temp with 0 to make its bit width log2N and obtain CTRL i+2 ; Among them, CTRL i+1 is the f / g control signal of the current decoding node, CTRL i+2 is the f / g control signal of the next decoding node; N is the length of the word to be decoded; CTRL i+1 [log2N:1] means taking CTRL i+1 bit log2N in to bit 1, and so on.

10. The device according to claim 9, characterized in that The parts and update modules include: Partial sum sequence calculation unit, used to calculate the partial sum sequence PSUM of the next node i+2 ; The effective signal calculation unit is used to calculate the effective signal according to the node length B. i+2 And the control signal CTRL i+2 Update control signal PSUM_Valid for calculating partial sums i+2 ; section and update unit for the PSUM_Valid i+2 , update the PSUM i+2 ; n={1,2,…,log2N} Among them, ps n is the partial sum result of level n, For ps n The generator matrix is ​​num, num is the latest decoded num decoding bits; N is the length of the word to be decoded.

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