Integrated optical Reed-Muller code decoder chip and photoelectric system

Abstract

The invention discloses an integrated optical Reed-Muller code decoder chip and a photoelectric system, the chip comprises an RM code dimension reduction calculation unit, the RM code dimension reduction calculation unit is configured to receive an input optical signal and an electric control signal and calculate and generate a first intermediate optical signal and a second intermediate optical signal, and the RM code dimension reduction calculation unit comprises a beam splitter, a beam combiner and a dimension reduction calculation assembly; the dimension reduction calculation assembly comprises an optical splitter, a sum and difference calculation unit, an optical path selection unit, a nonlinear calculation unit, an optical phase shifter and an optical coupler; the optical low-dimension low-order RM code decoding unit is configured to receive the first intermediate optical signal or the second intermediate optical signal and the electric control signal, calculate a low-order low-dimension RM code decoding likelihood result and output the low-order low-dimension RM code decoding likelihood result as an optical signal; compared with traditional electronic calculation, the integrated optical Reed-Muller code decoder chip and the photoelectric system are higher in speed and lower in energy consumption.

Description

Technical Field

[0001] The present invention relates to the technical field of optical communication systems, and in particular to an integrated optical Reed-Muller code decoder chip and an optoelectronic system. Background Art

[0002] Optical communication technology, especially fiber-optic communication, plays a pivotal role in global data transmission, carrying more than 85% of data traffic. As the cornerstone of high-speed backbone network communications and the essential infrastructure of large-scale data center clusters, optical communication technology is essential to the operation of the modern information society. Similar to classical digital communication systems, optical communication systems are inevitably affected by various interference factors such as noise and dispersion during signal transmission. In order to effectively combat these interferences, optical communication systems use a variety of technologies including channel equalization and channel coding. Among these technologies, channel coding, also known as forward error correction coding, is particularly important because of its key role in improving the reliability of signal transmission. At present, channel coding technology is mainly implemented through silicon digital chip technology to ensure the accuracy and integrity of data transmission.

[0003] Compared with electronic computing, photonic computing has the advantages of high speed, low energy consumption, and high parallelism. At the same time, photons have the characteristics of propagation and computing. The propagation process itself does not generate Joule heat and is close to zero power consumption, which meets the high speed and low energy consumption requirements of the channel coding decoder. At the same time, benefiting from the mature CMOS process, silicon-based photonic technology has the advantages of high integration and mature manufacturing process. In addition, in the optical communication scenario, the decoder module is moved forward and the received optical signal is directly error-corrected and decoded before the photoelectric conversion, which can better utilize the phase information in the optical signal and improve the decoding performance. Therefore, the use of optical computing to implement the decoding module of error correction coding in optical communication can give full play to the advantages of high speed, high bandwidth and low energy consumption of optical computing, replace the existing circuit implementation scheme, and is one of the ways to break through the bottleneck of high-speed optical communication signal processing.

[0004] Reed-Muller code is a classic error correction code, defined by two parameters r and m, denoted as RM(r, m). Where 0≤r≤m, the code length is 2 m , the dimension is The minimum Hamming distance is d min =2 m-r RM codes are well-known for their simple construction and rich structural characteristics, suitable for different channel conditions, and have low complexity in both encoding and decoding.

[0005] The Dumer decoding algorithm is an algorithm for decoding Reed-Muller codes. It is a recursive algorithm, and the key to the decoding algorithm is to recursively decompose the RM code until a low-order RM code is reached that can be decoded using a fast Hadamard transform or maximum likelihood decoding decoder. This recursive approach enables the algorithm to efficiently handle high-order RM codes while maintaining low complexity. Summary of the invention

[0006] The purpose of this section is to summarize some aspects of embodiments of the present invention and briefly introduce some preferred embodiments. Some simplifications or omissions may be made in this section and the specification abstract and the invention title of this application to avoid blurring the purpose of this section, the specification abstract and the invention title, and such simplifications or omissions cannot be used to limit the scope of the present invention.

[0007] In view of the above problems existing in the existing integrated optical Reed-Muller code decoder chip and optoelectronic system, the present invention is proposed.

[0008] Therefore, the object of the present invention is to provide an integrated optical Reed-Muller code decoder chip and optoelectronic system with higher speed and lower energy consumption.

[0009] To solve the above technical problems, the present invention provides the following technical solutions: an integrated optical Reed-Muller code decoder chip, characterized in that: it includes an RM code dimensionality reduction calculation unit, configured to receive an input optical signal and an electrical control signal, calculate and generate a first intermediate optical signal and a second intermediate optical signal, the RM code dimensionality reduction calculation unit includes a beam splitter, a beam combiner and a dimensionality reduction calculation component; the dimensionality reduction calculation component includes an optical splitter, a sum and difference calculation unit, an optical path selection unit, a nonlinear calculation unit, an optical phase shifter and an optical coupler; an optical low-dimensional low-order RM code decoding unit, configured to receive the first intermediate optical signal or the second intermediate optical signal and the electrical control signal, calculate the low-order low-dimensional RM code decoding likelihood result and output it as an optical signal.

[0010] As a preferred solution of the integrated optical Reed-Muller code decoder chip and optoelectronic system of the present invention, wherein: the beam splitter is configured to receive an input optical signal, split the optical signal into groups of two and input them into the dimension reduction computing component array;

[0011] The beam combiner is configured to receive the optical signal output by the dimension reduction computing component array, and to organize and combine the optical signals into two groups of optical signals, namely, the first intermediate optical signal and the second intermediate optical signal;

[0012] The dimension reduction calculation component is configured to receive two optical signals, calculate the log-likelihood ratio of the low-dimensional low-order RM code after dimension reduction according to the RM code decoding algorithm, and then output two optical signals, which respectively correspond to the log-likelihood ratios of the corresponding bits of the two RM codes after dimension reduction.

[0013] As a preferred embodiment of the integrated optical Reed-Muller code decoder chip and optoelectronic system of the present invention, wherein: the optical splitter is configured to split an input optical signal into two input photon signals with equal optical intensities, and input the two input photon signals into the corresponding upper-branch waveguide and lower-branch waveguide respectively;

[0014] The sum-difference calculation unit is formed by combining a 2×2 multimode interferometer and an optical phase shifter, and is configured to input two optical signals and generate two output optical signals, which are respectively the calculation results of the sum and difference of the two input signals;

[0015] The optical path selection unit consists of an optical switch, inputs two optical signals, and determines the output port of the optical signal according to the input electrical control signal;

[0016] The non-linear calculation unit is formed by combining a Mach-Zehnder coupler, a Mach-Zehnder interferometer and a microring resonator, realizes the softplus non-linear activation function operation, and is configured to input two optical signals, and the two output optical signals are respectively the non-linear calculation results of the input signals;

[0017] The optical coupler is configured to receive three optical signal inputs, and the output optical signal is the coupling result of the input signals.

[0018] As a preferred embodiment of the integrated optical Reed-Muller code decoder chip and optoelectronic system of the present invention, wherein: the optical low-dimensional low-order RM code decoding unit adopts the following steps:

[0019] (1) Specify m, r, and start decoding RM(m, r)

[0020] (2) Judge whether m and r satisfy the recursive stop condition. If so, go to (3); if not, go to (4);

[0021] (3) If r = 1 or m = r is satisfied, the recursive stop condition is met, and the decoding result c is obtained by using the FHT decoding algorithm or the ML decoding algorithm;

[0022] (4) If 1 < r < m, then adopt the recursive calculation method of calculating LLR of RM(m - 1, r - 1) → decoding RM(m - 1, r - 1) and going to (1) to obtain the codeword v → updating the LLR of RM(m - 1, r) → decoding RM(m - 1, r) and going to (1) to obtain the codeword u;

[0023] (5) Form the final decoding result c = (u, u + v).

[0024] As a preferred embodiment of the integrated optical Reed-Muller code decoder chip and optoelectronic system of the present invention, wherein: the integrated optical Reed-Muller code decoder chip further includes a photodetector;

[0025] The photodetector is communicatively connected to the optical low-dimensional low-order RM code decoding unit (200), and is configured to receive the output optical signal and perform photoelectric conversion on the output optical signal.

[0026] As a preferred solution of the integrated optical Reed-Muller code decoder chip and optoelectronic system of the present invention, it includes: an electrical processor; the electrical processor is communicatively connected to the integrated optical Reed-Muller decoder chip and is configured to input an electrical control signal to the integrated optical Reed-Muller decoder chip and output a decoding result; the integrated optical Reed-Muller decoder chip is configured to perform optical path selection in RM code dimensionality reduction calculation based on the electrical control signal and update the first intermediate optical signal.

[0027] As a preferred solution of the integrated optical Reed-Muller code decoder chip and optoelectronic system of the present invention, wherein: the optoelectronic system further comprises: a control signal drive;

[0028] The control signal driver is issued by the electrical processor, and the control signal driver is respectively connected to the electrical processor and the optical Reed-Muller code decoder chip, and is configured to receive and amplify the electrical control signal.

[0029] Beneficial effects of the present invention:

[0030] The integrated optical Reed-Muller code decoder chip and optoelectronic system of the present invention have faster computing speed and lower energy consumption than traditional electronic computing. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative labor. Among them:

[0032] Figure 1 The figure is a schematic diagram of the overall structure of the integrated optical Reed-Muller code decoder chip of the present invention.

[0033] Figure 2 The figure is a schematic diagram of the structure of the RM code dimensionality reduction calculation unit of the integrated optical Reed-Muller code decoder chip of the present invention.

[0034] Figure 3 The figure is a schematic diagram of the structure of the dimension reduction computing component of the integrated optical Reed-Muller code decoder chip of the present invention.

[0035] Figure 4 The figure is a schematic diagram of the structure of the sum-difference calculation unit of the integrated optical Reed-Muller code decoder chip of the present invention.

[0036] Figure 5 The figure is a schematic diagram of the structure of the optical path selection unit of the integrated optical Reed-Muller code decoder chip of the present invention.

[0037] Figure 6 The figure is a schematic diagram of the structure of the nonlinear computing unit of the integrated optical Reed-Muller code decoder chip of the present invention.

[0038] Figure 7 The schematic diagram of the structure of the optical first-order RM code decoding chip of the integrated optical Reed-Muller code decoder chip of the present invention is shown.

[0039] Figure 8 The schematic diagram of the structure of the optical m-order RM code decoding chip of the integrated optical Reed-Muller code decoder chip of the present invention is shown.

[0040] Fig. 9 The schematic diagram of the optoelectronic system structure of the integrated optical Reed-Muller code decoder chip of the present invention is shown in FIG. DETAILED DESCRIPTION

[0041] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are described in detail below in conjunction with the accompanying drawings.

[0042] In the following description, many specific details are set forth to facilitate a full understanding of the present invention, but the present invention may also be implemented in other ways different from those described herein, and those skilled in the art may make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0043] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The term "in one embodiment" that appears in different places in this specification does not necessarily refer to the same embodiment, nor does it refer to a separate or selective embodiment that is mutually exclusive with other embodiments.

[0044] Secondly, the present invention is described in detail with reference to the schematic diagram. When describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional diagrams showing the device structure will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0045] Reference Figure 1 , is an embodiment of the present invention, and provides a schematic diagram of the structure of an integrated optical Reed-Muller code decoder chip, wherein the optical RM (m, r) decoder chip includes an RM code dimensionality reduction calculation unit 100 and an optical low-dimensional low-order RM code decoding unit 200.

[0046] It should be noted that the optical RM(m,r) decoding chip has a recursive structure and exists only when 1 < r < m Figure 1 the structure shown, refer to Figure 1 , when the parameters of the optical RM(m,r) decoding chip and the optical RM(m-1,r-1) decoding chip meet the conditions, they should have a similar structure to the optical RM(m,r) decoding chip. The structures of the optical decoding chips when r = 1 and r = m will be described later. Among them, the optical decoder chip when r = 1 is called the optical first-order RM code decoder chip; the optical decoding chip when r = m is called the optical m-order RM code decoder chip.

[0047] It should be noted that the optical RM(m,r) decoding chip is a new type of decoding chip that uses optical principles for calculation and information processing. In the optical RM(m,r) decoding chip, optical signals are used as carriers of information and are processed and operated through optical devices and optical elements to achieve linear and non-linear calculations in the RM code decoding algorithm. The linear calculation of the optical RM(m,r) decoding chip refers to using optical elements to implement Hadamard matrix operations and various summation operations. Optical elements can use principles such as interference, optical arrays, and diffraction to achieve this linear calculation. Optical elements can include Mach-Zehnder interferometers 103d-2 and micro-ring resonators 103d-3, etc. The non-linear calculation of the optical RM(m,r) decoding chip refers to implementing the softplus non-linear activation function operation in the RM decoding algorithm to increase the accuracy of the decoding result.

[0048] The optical low-dimensional low-order RM code decoding unit 200 adopts the following algorithm:

[0049] (1) Specify m, r, and start decoding RM(m, r)

[0050] (2) Judge whether m, r meet the recursive stop condition. If so, go to (3); if not, go to (4);

[0051] (3) If r = 1 or m = r is satisfied, the recursive stop condition is met, and the decoding result c is obtained using the FHT decoding algorithm or the ML decoding algorithm;

[0052] (4) If 1 < r < m, then adopt the recursive calculation method of calculating the LLR of RM(m-1,r-1) → decoding RM(m-1, r-1) and then going to (1) to obtain the codeword v → updating the LLR of RM(m-1,r) → decoding RM(m-1, r) and then going to (1) to obtain the codeword u;

[0053] (5) Form the final decoding result c = (u, u + v).

[0054] Referring to a binary input memoryless channel W: {0, 1}→W, the log-likelihood ratio (LLR) of the output symbol x∈W is defined as LLR(x)=log[W(x|0) / W(x|1)]. Assume that the codeword c in RM(m, r) is sent through a binary input channel W, denote the output vector y, and denote the corresponding LLR vector L. Define vector L0 to represent the first half of L, and vector L1 to represent the second half of L. According to the Plotkin(u, u+v) structure of the RM code, the codeword c in RM(m, r) can be decomposed into two codewords, namely u in RM(m-1, r) and v in RM(m-1, r-1). Define vector L to represent the LLR corresponding to the codeword u, let vector L v represents the LLR corresponding to the codeword v. Before starting to decode the codeword v, you need to use the formula Calculate the LLR vector L from the LLR vectors L0 and L1 v . Use L v After decoding the codeword v in RM(m-1, r-1), use v together with L0 and L1 to update the LLR vector L u The update rule is as follows: for each i=(1, 2, ..., 2 m-1 ), if v i =0, then L u (i) = L0(i) + L1(i); if v i =1, then L u (i) = L0(i) - L1(i). Next, use the LLR vector L u Decode u∈RM(m-1, r). Finally, combine u and v to form the final decoding result c=(u, u+v).

[0055] In the embodiments of the present disclosure, reference Figure 1 , the RM code dimensionality reduction calculation unit 100 is configured to receive an input optical signal and an electrical control signal, and generate a first intermediate optical signal and a second intermediate optical signal. For example, the input optical signal may be a signal composed of 2^m beams of light, wherein the information carried by each beam of light corresponds to the log-likelihood ratio of one bit of information at the corresponding position in the 2^m-bit received codeword, and is also an optical signal output after being transmitted through a channel in the optical communication system. The RM code dimensionality reduction calculation unit 100 can perform linear and nonlinear operations, calculate the values ​​of 2^(m-1) log-likelihood ratios of the codeword of the RM(m,r) code reduced to the RM(m-1,r-1) code, and generate a second intermediate optical signal containing 2^(m-1) beams of light; calculate the values ​​of 2^(m-1) log-likelihood ratios of the codeword of the RM(m,r) code reduced to the RM(m-1,r) code, and generate a first intermediate optical signal containing 2^(m-1) beams of light.

[0056] When the parameters meet the conditions, the optical RM(m-1,r) decoding chip and the optical RM(m-1,r-1) decoding chip should have a similar structure to the optical RM(m,r) decoding chip. For example, when 1 < r < m-1 for the optical RM(m-1,r) decoding chip and 1 < r-1 < m-1 for the optical RM(m-1,r-1) decoding chip. They are both configured to receive an input optical signal and an electrical control signal and output an optical signal containing decoded information.

[0057] Figure 2 FIG. is a schematic structural diagram of an optional RM code dimension reduction calculation unit 100 provided by an embodiment of the present disclosure. It should be noted that the beam splitter 101 only divides the 2^m beam optical signal input in parallel into 2^(m-1) groups according to rules, and two optical signals in each group are input to the dimension reduction calculation component 103; the combiner 102 divides the received 2^m beam optical signal into two groups according to rules, with 2^(m-1) beam optical signals in each group, and outputs them as the first intermediate optical signal and the second intermediate optical signal respectively. It should also be noted that the number of dimension reduction calculation components 103 is determined by the parameters of the RM code dimension reduction calculation unit 100. Specifically, there should be 2^(m-1) dimension reduction calculation components 103 in the RM code dimension reduction calculation unit 100 for decoding RM(m,r) code.

[0058] In some embodiments of the present disclosure, referring to Figure 2 FIG. Figure 2 , the RM code dimension reduction calculation unit 100 includes a beam splitter 101, a combiner 102, and a dimension reduction calculation component 103. The beam splitter 101 is configured to receive an input optical signal and output the input signal to the dimension reduction calculation component 103 according to rules. Each dimension reduction calculation component 103, communicatively connected to the beam splitter 101, is configured to receive corresponding two optical signals and an electrical control signal, output a dimension reduction calculation result, and generate two optical signals. The combiner 102, communicatively connected to multiple dimension reduction calculation components 103, is configured to receive multiple optical signals and combine the signals into two beams to generate the first intermediate optical signal and the second intermediate optical signal.

[0059] Figure 3 FIG. is a schematic structural diagram of an optional dimension reduction calculation component provided by an embodiment of the present disclosure. It should be noted that the optical splitter 103a can be a Y-branch coupler or a multimode interference coupler. The optical coupler 103f can be a multimode interference coupler or a directional coupler. The optical phase shifter 103e can be any one of a piezoelectric optical phase shifter, an electro-optic phase shifter, or a thermo-optic phase shifter. Each branch in the dimension reduction calculation component 103 is a multimode waveguide. Referring to Figure 3, the dimension reduction calculation component 103 includes an optical splitter 103a, a sum-difference calculation unit 103b, an optical path selection unit 103c, a nonlinear calculation unit 103d, an optical phase shifter 103e, and an optical coupler 103f; the optical splitter 103a can receive an input optical signal and divide the input optical signal into two input optical signals with equal optical intensities. The connection method of the optical splitter 103a in the dimension reduction calculation component 103 is as follows: Figure 3 The optical phase shifter 103e is configured to shift the phase by -π.

[0060] refer to Figure 4 , the optical phase shifter 103e can be any one of a piezoelectric optical phase shifter, an electro-optical phase shifter or a thermo-optical phase shifter; the sum-difference calculation unit 103b includes the optical phase shifter 103e and a multi-mode interferometer. Among them, the multi-mode interferometer 331 is a 2×2 multi-mode interference coupler, and the optical phase shifter 103e is configured to be phase shifted -π / 4, -3π / 4, 0, and -π / 2 from the upper left, lower left, upper right, and lower right.

[0061] Figure 5 1 is a schematic diagram of the structure of an optional optical path selection unit provided in an embodiment of the present disclosure. It should be noted that the optical switch can be any one of an electro-optical switch and a thermo-optical switch. An optical switch is provided in the optical path selection unit 103c. The optical switch is configured to receive two input optical signals and an electrical signal, and output an optical signal. The optical switch can select an optical path for output according to different electrical signals.

[0062] Figure 61 is a schematic diagram of the structure of an optional nonlinear calculation unit 103d provided in an embodiment of the present disclosure. It should be noted that the optical phase shifter 103e and the phase shifters in the Mach-Zehnder coupler 103d-1 and the Mach-Zehnder interferometer 103d-2 can be any one of a piezoelectric optical phase shifter, an electro-optical phase shifter or a thermo-optical phase shifter. The nonlinear calculation unit 103d includes a Mach-Zehnder coupler 103d-1, a Mach-Zehnder interferometer 103d-2, a microring resonator 103d-3 and an optical phase shifter 103e. Among them, the optical phase shifter 103e is configured to shift the phase by -π. The Mach-Zehnder coupler 103d-1 may include an optical phase shifter 103e, and the phase on one arm is adjusted by the optical phase shifter 103e so that there is a phase difference between the optical signals on the two arms. The microring resonator 103d-3, coupled to the Mach-Zehnder interferometer 103d-2, is configured to utilize the free carrier dispersion effect to generate a nonlinear phase response of the upper arm optical signal. The Mach-Zehnder interferometer 103d-2 then combines the upper and lower arm optical signals to realize the softplus nonlinear activation function calculation. That is, the optical phase shifter 103e on the microring resonator 103d-3, the Mach-Zehnder interferometer 103d-2, and the Mach-Zehnder coupler 103d-1 allows the amplitude and phase bias of the device to be adjusted, thereby jointly realizing the programmability of the shape and threshold of the device's nonlinear transfer function. The nonlinearity in the microring resonator 103d-3 is complemented by the linear operation on the Mach-Zehnder interferometer 103d-2 and the Mach-Zehnder coupler 103d-1.

[0063] Figure 7 is a schematic diagram of the structure of an optional optical first-order RM code decoder chip provided in an embodiment of the present disclosure. It should be noted that the RM (m, r) code does not have a Figure 1 The structure of the Zhongguang RM (m, r) decoding chip. Figure 7 , the decoder of RM(m,r) code when r=1 involves fast Hadamard transform, that is, the input signal is multiplied by the Hadamard matrix and then output, and the output signal is the first-order RM code decoding likelihood result. The optical implementation of the matrix multiplication can be any one of a Mach-Zehnder array, a multimode interferometer array, and a microring resonator grid. In the embodiments of the present disclosure, reference Figure 7 The optical RM(m,1) decoding chip is configured to receive an input optical signal, perform matrix multiplication, and output an optical signal of the calculation result. The number of input and output signals is 2^m, and the number of rows and columns of the Hadamard matrix is ​​also 2^m.

[0064] Figure 8 is a schematic diagram of the structure of an optional optical m-order RM code decoder chip provided in an embodiment of the present disclosure. It should be noted that the RM (m, r) code does not have when r = m. Figure 1The structure of the Zhongguang RM (m, r) decoding chip. Figure 8 , when r=m, the number of information bits k of RM(m,r) code is equal to the encoded code length n, which is equivalent to no encoding. Therefore, the optical RM(m,m) decoding chip is configured to directly output without performing any operation after receiving the input signal. It should be noted that the number of input signals and the number of output signals are both 2^m.

[0065] Fig. 9 is a schematic diagram of an optional optoelectronic system provided in an embodiment of the present disclosure, with reference to Fig. 9 The optoelectronic computing system includes an electrical processor, a control signal driver, and the optical RM(m,r) decoding chip described in the above embodiment. Fig. 9 The electronic processor is configured to receive a signal containing a decoding likelihood result output by the optical RM(m,r) decoding chip, and output a decoding result and a control signal after performing a comparison operation. The control signal driver is respectively connected to the electronic processor and the optical RM(m,r) decoding chip, and is configured to receive and amplify the control signal.

[0066] In the embodiments of the present disclosure, reference Fig. 9 , the control signal can be provided by an electrical processor. The control signal is driven and amplified by the control signal and then output to the optical RM (m, r) decoding chip to control the optical path selection unit 103c in the optical RM (m, r) decoding chip to select the optical path. The electrical processor can receive the result of the likelihood calculation when decoding the first-order code after completing the decoding linear and nonlinear operations. Then, the calculation result is sampled and processed, and the control signal is output based on the output result, so that the optical path selection unit in the low-order decoder chip is controlled based on the control signal.

[0067] It is understandable that the embodiments of the present disclosure can simultaneously realize linear calculation and nonlinear calculation, thereby improving the calculation speed of the decoder chip. At the same time, both linear calculation and nonlinear calculation are realized through optical signals. Therefore, the embodiments of the present disclosure do not need to perform photoelectric conversion and electro-optical conversion on the intermediate optical signal, and only perform photoelectric conversion before transmitting the signal to the electrical processor, thereby further improving the calculation speed of the optical decoding chip.

[0068] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present invention, which should all be included in the scope of the claims of the present invention.

Claims

1. An integrated optical Reed-Muller code decoder chip, characterized in that: include, An RM code dimension reduction calculation unit (100) is configured to receive an input optical signal and an electrical control signal, and calculate and generate a first intermediate optical signal and a second intermediate optical signal, wherein the RM code dimension reduction calculation unit (100) comprises a beam splitter (101), a beam combiner (102), and a dimension reduction calculation component (103); The dimension reduction calculation component (103) comprises an optical spectrometer (103a), a sum-difference calculation unit (103b), an optical path selection unit (103c), a nonlinear calculation unit (103d), an optical phase shifter (103e) and an optical coupler (103f); The optical low-dimensional low-order RM code decoding unit (200) is configured to receive a first intermediate optical signal or a second intermediate optical signal and an electrical control signal, calculate a low-order low-dimensional RM code decoding likelihood result and output it as an optical signal.

2. The integrated optical Reed-Muller code decoder chip according to claim 1, characterized in that: The beam splitter (101) is configured to receive an input optical signal, split the optical signal into groups of two and input them into the array of the dimension reduction calculation component (103); The beam combiner (102) is configured to receive the optical signal output by the dimension reduction computing component (103) array, and to combine the optical signal into two groups of optical signals, namely the first intermediate optical signal and the second intermediate optical signal; The dimension reduction calculation component (103) is configured to receive two optical signals, calculate the log-likelihood ratio of the low-dimensional low-order RM code after dimension reduction according to the RM code decoding algorithm, and then output two optical signals, which respectively correspond to the log-likelihood ratios of the corresponding bits of the two RM codes after dimension reduction.

3. The integrated optical Reed-Muller code decoder chip according to claim 2, characterized in that: The optical splitter (103a) is configured to split the input optical signal into two input photon signals with equal optical intensities, and input the two input photon signals into the corresponding upper branch waveguide and lower branch waveguide respectively; The sum and difference calculation unit (103b) is formed by a combination of a 2×2 multi-mode interferometer and an optical phase shifter, and is configured to input two optical signals and generate two output optical signals, which are respectively the calculation results of the sum and difference of the two input signals; The optical path selection unit (103c) is composed of an optical switch, which inputs two optical signals and determines the output port of the optical signal according to the input electrical control signal; The nonlinear calculation unit (103d) is formed by combining a Mach-Zehnder coupler (103d-1), a Mach-Zehnder interferometer (103d-2) and a microring resonator (103d-3), realizes softplus nonlinear activation function operation, and is configured to input two light signals and output two light signals which are nonlinear calculation results of the input signals respectively; The optical coupler (103f) is configured to receive three optical signal inputs, and the output optical signal is the coupling result of the input signals.

4. The integrated optical Reed-Muller code decoder chip according to claim 3, characterized in that: The optical low-dimensional low-order RM code decoding unit (200) adopts the following steps: (1) Specify m, r and start decoding RM(m, r) (2) Determine whether m and r satisfy the recursive stopping condition. If so, go to (3); if not, go to (4); (3) If r=1 or m=r, the recursive stop condition is met, and the FHT decoding algorithm or the ML decoding algorithm is used to obtain the decoding result c; (4) If 1 < r < m, a recursive calculation method is adopted: calculate the LLR of RM(m - 1, r - 1) → decode RM(m - 1, r - 1) and transfer to (1) to obtain the codeword v → update the LLR of RM(m - 1, r) → decode RM(m - 1, r) and transfer to (1) to obtain the codeword u; (5) Form the final decoding result c = (u, u + v).

5. The integrated optical Reed-Muller code decoder chip according to claim 4, characterized in that: The integrated optical Reed - Muller code decoder chip further includes a photodetector; The photodetector is communicatively connected to the optical low - dimensional low - order RM code decoding unit (200), and is configured to receive the output optical signal and perform photoelectric conversion on the output optical signal.

6. An optoelectronic system using the integrated optical Reed-Muller code decoder chip as claimed in claim 5, characterized in that: It includes an electrical processor; The electrical processor is communicatively connected to the integrated optical Reed - Muller decoder chip, and is configured to input an electrical control signal to the integrated optical Reed - Muller decoder chip and output a decoding result; The integrated optical Reed - Muller decoder chip is configured to perform optical path selection in the RM code dimension reduction calculation based on the electrical control signal and update the first intermediate optical signal.

7. The photovoltaic system according to claim 6, characterized in that: The optoelectronic system further includes: a control signal driver; The control signal driver is issued by the electrical processor. The control signal driver is respectively connected to the electrical processor and the optical Reed - Muller code decoder chip, and is configured to receive and amplify the electrical control signal.

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