MIMO communication system signal detection method, circuit, device and equipment based on memristor array

Abstract

The present invention relates to a MIMO communication system signal detection method, circuit, device, and apparatus based on a memristor array, which are used in the field of wireless communication signal processing. To address the problem that existing MIMO signal detection calculation circuits based on memristor arrays are extremely sensitive to memristor conductance errors, the present invention represents the MIMO channel matrix as the product of a small-scale fading coefficient matrix and a large-scale fading coefficient matrix, transforms the matrix calculation expressions for ZF signal detection and MMSE signal detection into a new equivalent form, and uses a memristor array-based matrix calculation circuit to calculate the transformed equivalent expression to achieve signal detection. The present invention provides two memristor array-based matrix calculation circuit design schemes, two corresponding MIMO communication system signal detection devices, and three memristor array-based MIMO communication system signal detection devices. The present invention is less sensitive to memristor conductance errors and has better signal detection performance.

Description

Technical Field

[0001] The present invention relates to the fields of wireless communication signal processing and semiconductor integrated circuits, and in particular to a MIMO communication system signal detection method, circuit, device and equipment based on a memristor array. Background Art

[0002] Multiple-Input Multiple-Output (MIMO) technology is one of the core technologies of the physical layer of modern wireless communication systems. MIMO technology can more fully utilize spatial multiplexing gain, thereby significantly improving the spectral efficiency of wireless communication systems. Both the transmitter and receiver of a MIMO system include multiple antennas, so the signal received by the receiver is the superposition of the signals transmitted by all transmitting antennas. Furthermore, the received signal may be affected by other interfering signals. Signal detection technology in MIMO communication systems is a technology that determines the original signal sent by each transmitting antenna based on the received signal when the receiver knows complete or partial channel state information (CSI). The most typical MIMO signal detection technology is linear detection, including zero forcing (ZF) detection and minimum mean square error (MMSE) detection.

[0003] Matrix calculations include matrix multiplication, inversion, and other operations. Traditional digital computers need to perform a large number of floating-point addition and floating-point multiplication operations when performing matrix calculations, which has a high computational complexity. For example, the complexity of inverting an N-order matrix is ​​generally O(N 3 A memristor (including but not limited to resistive random access memory, phase change memory, and conductive bridge memory) is an electronic component whose conductance state can be modulated by applying an external stimulus. Memristors can be integrated into crossbar arrays to perform analog matrix computing. In recent years, matrix computing technology based on memristor arrays has garnered widespread attention.

[0004] According to Ohm's law and Kirchhoff's law, the vector of output current values ​​from a memristor array can be expressed as the product of a matrix of conductance values ​​of the memristors in the array and a vector of input voltage values. Therefore, by mapping the elements of the matrix to be calculated to memristor conductance values ​​and the elements of the vector to be calculated to input voltage values, the product of the matrix and vector to be calculated can be obtained by measuring the output current. This principle allows matrix-vector multiplication. "Mapping" in this process means adjusting the memristor conductance values ​​so that the conductance matrix of the memristor array and the matrix to be calculated have a linear relationship; or adjusting the input voltage values ​​so that the input voltage vector and the vector to be calculated have a linear relationship. Furthermore, by connecting the memristor array to multiple operational amplifiers in different ways, similar principles can be used to perform operations such as calculating inverse matrices and pseudo-inverse matrices.

[0005] Furthermore, traditional digital computers based on the von Neumann architecture have separate storage and computation units, and the memory write speed is slower than the CPU's computation speed, which limits CPU throughput. In contrast, matrix computations based on memristor arrays are in-memory computations, which do not require data exchange between storage and computation units. Their computation speed and energy efficiency are significantly superior to those of traditional digital computers. Therefore, memristor arrays are more suitable for large-dimensional matrix computations than traditional digital computers.

[0006] Reference 1 (P. Mannocci, E. Melacarne and D. Ielmini, "An Analogue In-Memory Ridge Regression Circuit With Application to Massive MIMO Acceleration," in IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 12, no. 4, pp. 952-962, Dec. 2022) proposes a matrix computation circuit based on a memristor array. This circuit is used to perform matrix operations in channel estimation, signal detection, and precoding in massive MIMO systems. During the computation, the circuit maps the MIMO channel matrix into the conductance matrix of the memristor array. The paper simulates the performance of ZF and regularized ZF (RZF) receivers based on this circuit. The simulation results show that, when the memristor precision is greater than or equal to 6 bits and the operational amplifier open-loop gain is greater than or equal to 60 dB, the symbol error rate performance of the ZF and RZF receivers based on this circuit is comparable to that of traditional digital computers. In addition, the energy efficiency of this circuit is 4 orders of magnitude higher than that of a commercial graphics processing unit (GPU), and the area efficiency is 3 orders of magnitude higher.

[0007] Reference 2 (P. Zuo, Z. Sun and R. Huang, "Extremely-Fast, Energy-Efficient Massive MIMO Precoding With Analog RRAM Matrix Computing," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 70, no. 7, pp. 2335-2339, July 2023) proposes a matrix computation circuit based on a memristor array for performing matrix operations in massive MIMO linear precoding. During the computation, the circuit maps the MIMO channel matrix and its Gram matrix into the conductance matrix of the memristor array. Simulation results in Reference 2 show that for a 16×128 MIMO system, the circuit can compute ZF precoding within 20 ns, two orders of magnitude faster than traditional digital methods and 50 times more energy efficient.

[0008] The actual conductance of a memristor often differs from its desired ideal conductance by a certain amount. If the values ​​of the elements in the mapped matrix vary significantly, even small conductance errors can significantly impact the representation accuracy of smaller elements, leading to significant computational errors. In multi-user MIMO systems, the transmitting antennas of user terminals are often located in different locations, resulting in elements in different columns of the channel matrix often following probability distributions with different variances. The variances of different elements of the channel matrix's Gram matrix vary even more. When using a matrix calculation circuit based on a memristor array for MIMO signal detection, the technical solution in Reference 1 requires mapping the channel matrix into the conductance matrix of the memristor array. When using a matrix calculation circuit based on a memristor array for MIMO linear precoding, the technical solution in Reference 2 requires mapping the channel matrix and its Gram matrix into the conductance matrix of the memristor array. In practical applications, the values ​​of the different elements of the mapped matrices in the two aforementioned technical solutions often vary significantly, making them highly sensitive to the conductance errors of the memristors. Even small conductance errors can severely impact the performance of both solutions. Summary of the Invention

[0009] Existing MIMO signal processing solutions based on memristor arrays are highly sensitive to memristor conductance errors; even small conductance errors can severely impact their performance. To address this issue, the present invention discloses a signal detection method, circuit, device, and apparatus for a MIMO communication system based on a memristor array. Compared to existing solutions, the present invention is less sensitive to memristor conductance errors and offers improved signal detection performance.

[0010] The present invention provides a MIMO communication system signal detection method based on a memristor array. First, a large-scale fading coefficient matrix, a small-scale fading coefficient matrix and a baseband received signal are obtained. Then, for the ZF signal detection algorithm, a matrix calculation circuit based on a memristor array is used to calculate For the MMSE signal detection algorithm, a matrix computing circuit based on a memristor array is used to calculate Among them, y is the received signal, the matrix N K Large-scale fading coefficients (power domain) between a transmit antenna and a single receive antenna array; matrix is the small-scale fading coefficient matrix between all transmit antennas and a single receive antenna array; means taking the real part of the matrix, Indicates taking the imaginary part of the matrix, (·) -1 represents matrix inversion, (·) T represents matrix transpose, diag(·) represents diagonal matrix; matrix parameter is the variance of the noise, p s is the average power of the transmitted signal. Finally, the calculation result is determined as the symbol in the modulation constellation.

[0011] Furthermore, in order to implement the above-mentioned MIMO communication system signal detection method based on memristor array proposed by the present invention, the present invention provides two circuit design schemes based on memristor array to implement the matrix calculation involved in the above-mentioned signal detection method.

[0012] The matrix calculation circuit design scheme 1 provided by the present invention includes: the calculation circuit includes a group of memristor arrays a1 connected in corresponding rows, a group of memristor arrays a2 connected in corresponding rows, a group of operational amplifiers and 2N K The equivalent conductance matrix of a set of memristor arrays a1 connected in corresponding rows is 2N K ×2N R dimensional matrix A1; the equivalent conductance matrix of a set of corresponding row-connected memristor arrays a2 is 2N K ×2N K dimensional matrix A2; a group of memristor arrays a1 connected in corresponding rows are connected to corresponding rows of a group of memristor arrays a2 connected in corresponding rows, and each row is connected to the inverting input terminal and one of the non-inverting input terminals of an operational amplifier in a group of operational amplifiers, and the non-inverting input terminal or the inverting input terminal of the operational amplifier that is not connected to the corresponding row of the memristor array is grounded; the output terminal of each operational amplifier in the group of operational amplifiers is connected to the corresponding column of a group of memristor arrays a2 connected in corresponding rows, and is also connected to the input terminal of an inverting amplifier circuit; an input voltage vector v is applied to each column of a group of memristor arrays a1 connected in corresponding rows in , in 2N K The output voltage vector v is measured at the output end of the inverting amplifier circuit out . N K 、N R The number of transmitting antennas and receiving antennas of the MIMO communication system are respectively. The group of memristor arrays connected in corresponding rows described in the present invention refers to corresponding rows connected, each column is connected with a voltage follower circuit or an analog inverter or other circuit with similar functions, and the column input voltage v in The row output current i when each row is grounded out Satisfy i out =Mv in A group of memristor arrays having a relationship, M is the equivalent conductance value matrix of the memristor arrays connected in corresponding rows.

[0013] The second matrix calculation circuit design scheme provided by the present invention includes: the calculation circuit includes a group of memristor arrays connected in corresponding rows, a group of memristor arrays connected in corresponding columns, a group of operational amplifiers 1, a group of operational amplifiers 2 and 2N K The equivalent conductance matrix of a set of memristor arrays connected in corresponding rows is 2N R ×2N K dimensional matrix B1; the equivalent conductance matrix of a set of corresponding column-connected memristor arrays 2 is 2N R ×2N K dimensional matrix B2; each row of a group of memristor arrays connected to corresponding rows is connected to one of the inverting input and non-inverting input of an operational amplifier in a group of operational amplifiers 1, and the non-inverting input or inverting input of the corresponding row of the memristor array is grounded; the output of each operational amplifier in a group of operational amplifiers 1 is connected to the corresponding row of a group of memristor arrays connected to corresponding columns, and a jumper memristor with a conductance value of δ0 is connected between the corresponding rows of the memristor arrays connected to corresponding rows; each column of a group of memristor arrays connected to corresponding columns is connected to one of the inverting input and non-inverting input of an operational amplifier in a group of operational amplifiers 2, and the non-inverting input or inverting input of the corresponding column of the memristor array is grounded; the output of each operational amplifier in a group of operational amplifiers 2 is connected to the corresponding column of the memristor arrays connected to corresponding rows, and a jumper memristor and an analog inverter are connected between the corresponding columns of the memristor arrays connected to corresponding columns, and this is marked as 2N K The conductance values ​​of the memristors connected across the resistors are The output terminal of each operational amplifier in a group of operational amplifiers 2 is simultaneously connected to the input terminal of an inverting amplifier circuit; an input current vector i is applied to each row of a group of memristor arrays connected in corresponding rows. in , in 2N K The output voltage vector v is measured at the output end of the inverting amplifier circuit out The present invention describes a group of memristor arrays connected in corresponding columns, wherein corresponding columns are connected, voltage follower circuits or analog inverters or other circuits with similar functions are connected between corresponding rows, and row input voltage v in The column output current i when each column is grounded out Satisfy i out =M T v in A group of memristor arrays having a relationship, M is an equivalent conductance value matrix of the group of memristor arrays connected in corresponding columns.

[0014] Furthermore, the present invention provides two implementations of a MIMO communication system signal detection device based on a memristor array.

[0015] The first implementation of the MIMO communication system signal detection device based on the memristor array of the present invention is as follows: the detection device is composed of a calculation circuit 1, a memristor conductance value calculation and programming module, a voltage measurement module, and a judgment module. The calculation circuit 1 refers to a circuit designed and implemented according to the matrix calculation circuit design scheme 1 provided by the present invention; the memristor conductance value calculation and programming module is used to calculate the target conductance value of the memristor in the calculation circuit 1 according to the large-scale fading coefficient matrix and the small-scale fading coefficient matrix, and to program and modify the conductance value of the memristor in the calculation circuit 1; the voltage measurement module is used to measure the output voltage of the calculation circuit 1; the judgment module is used to calculate based on the measurement result of the output voltage. or It is determined as the symbol in the modulation constellation with the closest Euclidean distance and an estimated signal is output.

[0016] The second implementation of the MIMO communication system signal detection device based on the memristor array of the present invention is as follows: the detection device is composed of a calculation circuit 2, a memristor conductance value calculation and programming module, a voltage measurement module and a judgment module. The calculation circuit 2 refers to a circuit designed and implemented according to the matrix calculation circuit design scheme 2 provided by the present invention; the memristor conductance value calculation and programming module is used to calculate the target conductance value of the memristor in the calculation circuit 2 according to the large-scale fading coefficient matrix and the small-scale fading coefficient matrix, and to program and modify the conductance value of the memristor in the calculation circuit 2; the voltage measurement module is used to measure the output voltage of the calculation circuit 2; the judgment module is used to calculate the output voltage according to the measurement result of the output voltage. or It is determined as the symbol in the modulation constellation with the closest Euclidean distance and an estimated signal is output.

[0017] Furthermore, the present invention provides three implementations of a MIMO communication system signal detection device based on a memristor array.

[0018] A first implementation of the memristor array-based MIMO communication system signal detection device of the present invention is as follows: the detection device comprises: an antenna, a radio frequency filter 1, a low-noise amplifier, a radio frequency filter 2, a mixer connected to a local oscillator, an intermediate frequency filter, an intermediate frequency amplifier, and an analog-to-digital converter, all connected in sequence; a voltage / current providing module, a channel estimation module, and a memristor array-based MIMO communication system signal detection device proposed in the present invention. The antenna, radio frequency filter 1, the low-noise amplifier, the radio frequency filter 2, the mixer connected to the local oscillator, the intermediate frequency filter, the intermediate frequency amplifier, and the analog-to-digital converter, all connected in sequence, are configured to convert radio frequency signals received by the antenna into baseband received signals in the form of digital signals and output the baseband received signals to the channel estimation module and the voltage / current providing module; the voltage / current providing module is configured to provide input voltage or input current to the MIMO communication system signal detection device; the channel estimation module is configured to calculate a large-scale fading coefficient matrix and a small-scale fading coefficient matrix based on channel estimation-related techniques and output these two matrices to the MIMO communication system signal detection device; and the MIMO communication system signal detection device is configured to calculate and output an estimated signal.

[0019] A second implementation of the memristor array-based MIMO communication system signal detection device of the present invention is: the detection device includes: an antenna, a radio frequency filter 1, a low-noise amplifier, a radio frequency filter 2, a mixer connected to a local oscillator, an intermediate frequency filter, an intermediate frequency amplifier, as well as a sampling and holding circuit, a channel estimation module and the memristor array-based MIMO communication system signal detection device proposed in the present invention. The antenna, RF filter 1, low-noise amplifier, RF filter 2, mixer connected to a local oscillator, intermediate frequency filter, and intermediate frequency amplifier connected in sequence are used to convert the RF signal received by the antenna into a baseband reception signal in the form of an analog signal and output it to the sampling and holding circuit; the sampling and holding circuit is used to sample the baseband reception signal in the form of an analog signal to obtain a voltage or current vector corresponding to the baseband reception signal, thereby providing an input voltage for the signal detection device implemented in method one or providing an input current for the signal detection device implemented in method two, and the sampling and holding circuit simultaneously outputs the voltage or current vector corresponding to the baseband reception signal to the channel estimation module; the channel estimation module is used to calculate the large-scale fading coefficient matrix and the small-scale fading coefficient matrix based on channel estimation related technologies and output these two matrices to the signal detection device; the signal detection calculation device is used to detect and output the estimated signal.

[0020] A third implementation of the memristor array-based MIMO communication system signal detection device of the present invention is: the detection device includes: an antenna, a radio frequency filter 1, a low-noise amplifier, a radio frequency filter 2, a mixer 1 connected to a local oscillator 1, an intermediate frequency filter, an intermediate frequency amplifier, and an IQ demodulation module, a channel estimation module and the memristor array-based MIMO communication system signal detection device proposed in the present invention, wherein the IQ demodulation module includes a local oscillator 2, a mixer 2, a mixer 3, a low-pass filter 1, and a low-pass filter 2. The antenna, RF filter 1, low noise amplifier, RF filter 2, mixer 1 connected to local oscillator 1, intermediate frequency filter, and intermediate frequency amplifier connected in sequence are used to convert the RF signal received by the antenna into a baseband receiving signal in the form of an analog signal and output it to the IQ demodulation module; the IQ demodulation module is used to convert the baseband receiving signal in the form of an analog signal into a voltage or current vector corresponding to the baseband receiving signal, thereby providing an input voltage for the signal detection device implemented in the first embodiment of the present invention or providing an input current for the signal detection device implemented in the second embodiment. The IQ demodulation module simultaneously outputs the voltage or current vector corresponding to the baseband receiving signal to the channel estimation module; the IQ demodulation module In the module, the local oscillator 2 generates two signals with a phase difference of 90° and inputs them into mixer 2 and mixer 3 respectively. The baseband receiving signal in the form of an analog signal is also input into mixer 2 and mixer 3 respectively. The output signals of mixer 2 and mixer 3 are input into low-pass filter 1 and low-pass filter 2 respectively. The output voltage / current of low-pass filter 1 and low-pass filter 2 is the voltage or current vector corresponding to the baseband receiving signal; the channel estimation module is used to calculate the large-scale fading coefficient matrix and the small-scale fading coefficient matrix based on channel estimation related technology and output these two matrices to the signal detection device; the signal detection calculation device is used to realize detection and output the estimated signal.

[0021] Compared with the prior art, the advantages and positive effects of the present invention are: the present invention transforms the matrix calculation expression of the ZF signal detection algorithm into The matrix calculation expression of the MMSE signal detection algorithm is transformed into Then, a matrix calculation circuit based on a memristor array is used to calculate the transformed equivalent expression, thereby realizing MIMO signal detection. In the signal detection method for a MIMO communication system based on a memristor array proposed by the present invention, the difference in the values ​​of different elements of the mapped matrix is ​​often small, so the calculation accuracy is relatively less affected by the conductance error of the memristor, thereby avoiding the problem in existing solutions that even small conductance errors can seriously affect signal detection performance. Compared with existing technical solutions, the signal detection method, circuit, device and equipment of the MIMO communication system of the present invention are less sensitive to the conductance error of the memristor and have better signal detection performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 is a flow chart of a signal detection method for a MIMO communication system based on a memristor array of the present invention;

[0023] Figure 2 is a schematic diagram of an example of a group of memristor arrays connected in corresponding rows as described in the present invention;

[0024] Figure 3 is a schematic diagram of an example of a group of memristor arrays connected in corresponding columns as described in the present invention;

[0025] Figure 4 This is a schematic diagram of a matrix calculation circuit design solution provided by the present invention;

[0026] Figure 5 This is a schematic diagram of a second matrix calculation circuit design scheme provided by the present invention;

[0027] Figure 6 This is a circuit structure diagram of a preferred embodiment of the matrix calculation circuit design solution 1 provided by the present invention;

[0028] Figure 7 This is a circuit structure diagram of a preferred embodiment of the second matrix calculation circuit design solution provided by the present invention;

[0029] Figure 8 This is a structural diagram of a MIMO communication system signal detection device based on a memristor array provided by the present invention;

[0030] Figure 9 This is a structural diagram of a second signal detection device for a MIMO communication system based on a memristor array provided by the present invention;

[0031] Figure 10 This is a flow chart of using the signal detection device provided by the present invention to perform signal detection in a MIMO communication system;

[0032] Figure 11 This is a flow chart of using the signal detection device 2 provided by the present invention to perform signal detection in a MIMO communication system;

[0033] Figure 12 1 is a structural diagram of a MIMO communication system signal detection device based on a memristor array provided by the present invention;

[0034] Figure 13 1 is a structural diagram of a second MIMO communication system signal detection device based on a memristor array provided by the present invention;

[0035] Figure 141 is a schematic diagram of the structure of a MIMO communication system signal detection device based on a memristor array provided by the present invention;

[0036] Figure 15 This is a diagram showing the detection performance simulation results of the signal detection method for a MIMO communication system based on a memristor array of the present invention. DETAILED DESCRIPTION

[0037] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0038] The present invention provides a MIMO communication system signal detection method, circuit, device and equipment based on a memristor array. The matrix calculation expressions of the existing MIMO communication system signal detection scheme based on a memristor array for the ZF and MMSE signal detection algorithms are respectively and The present invention expresses the MIMO channel matrix as the product of the small-scale fading coefficient matrix and the large-scale fading coefficient matrix, thereby transforming the matrix calculation expression into and The transformed equivalent expression is then calculated using a matrix calculation circuit based on a memristor array, thereby achieving MIMO signal detection. Compared with existing technical solutions, the present invention is less sensitive to memristor conductance errors and has better signal detection performance.

[0039] First, the calculation principle of MIMO communication system signal detection is explained, using ZF signal detection and MMSE signal detection.

[0040] Consider a system with N transmitting antennas K , the number of receiving antennas is N R For a MIMO communication system, the information transmission process of the system can be expressed as:

[0041]

[0042] in is the received signal vector, is the channel matrix, is the transmitted signal vector, is the noise signal vector.

[0043] Wireless channel fading usually includes large-scale fading and small-scale fading. Large-scale fading describes the change in signal power over a large distance between the transmitter and the receiver, mainly including path loss and shadow fading; small-scale fading describes the rapid change in signal power and frequency over a short time and small spatial scale, mainly including multipath effect and Doppler shift. Assuming that all receiving antennas are located at the same position, the large-scale fading coefficient between the same transmitting antenna and all receiving antennas is the same. Assuming NK The large-scale fading coefficients (power domain) between the transmitting antenna and the receiving antenna are but It can be expressed as:

[0044]

[0045] in This matrix is ​​called the large-scale fading coefficient matrix, and diag represents a diagonal matrix; It describes the small-scale fading coefficients between all transmit antennas and all receive antennas, which is called the small-scale fading coefficient matrix. The above formula shows that the channel matrix can be expressed as the product of the small-scale fading coefficient matrix and the large-scale fading coefficient matrix. Both can be obtained through channel estimation.

[0046] The complex model shown in formula (1) can be written in real form, that is:

[0047] y=Hs+n (3)

[0048] in means taking the real part of the matrix, It means taking the imaginary part of the matrix.

[0049] Formula (2) can also be written in real number form:

[0050] H=GΛ (4)

[0051] in

[0052] The purpose of the signal detection considered in the present invention is to calculate the estimated value of s based on y at the receiving end when the CSI is known.

[0053] The calculation formula of the ZF signal detection algorithm of the MIMO communication system is:

[0054]

[0055] The superscript T indicates transpose, and -1 indicates matrix inversion.

[0056] After expressing the channel matrix as the product of the small-scale fading coefficient matrix and the large-scale fading coefficient matrix, formula (5) can be transformed into:

[0057]

[0058] The calculation formula of the MMSE signal detection algorithm of the MIMO communication system is:

[0059]

[0060] The parameters is the variance of the noise signal, p s is the average power of the transmitted signal, and I is the unit matrix.

[0061] After expressing the channel matrix as the product of the small-scale fading coefficient matrix and the large-scale fading coefficient matrix, formula (7) can be transformed into:

[0062]

[0063] The matrix

[0064] Complete the pair or After the calculation, the result will be or The estimated signal can be obtained by judging the constellation point with the shortest Euclidean distance.

[0065] The meanings of a group of memristor arrays connected in corresponding rows, a group of memristor arrays connected in corresponding columns, and their equivalent conductance matrices described in the present invention are explained below.

[0066] When using memristor arrays for matrix calculations, it is often necessary to map the matrix being calculated into the conductance matrix of the memristor array. However, the matrix being calculated may contain negative elements, while the memristor conductance values ​​can only be positive. In this case, multiple memristor arrays can be connected and the matrix being calculated can be mapped into the equivalent conductance matrix of these memristor arrays, thus enabling calculations on matrices containing negative elements.

[0067] A group of memristor arrays can be connected in the following way: corresponding rows are connected, and voltage follower circuits or analog inverters or other circuits with similar functions are connected between corresponding columns. If an input voltage is applied to each column of a memristor array in the group, each row of the memristor array is grounded and the output current of each row is measured, assuming that the vector formed by the input voltage is v in , the vector formed by the output current is i out , the relationship between input voltage and output current is:

[0068] i out =Mv in (9)

[0069] M is the equivalent conductance matrix of the corresponding row-connected memristor array.

[0070] For example, Figure 2 An example of a memristor array connected in a row is given in the present invention. Figure 2As shown, the group of memristor arrays connected in corresponding rows includes three memristor arrays, memristor array 1, memristor array 2, and memristor array 3, as well as several voltage follower circuits and several analog inverters. Each column corresponding to memristor array 1 and memristor array 2 is connected through a voltage follower circuit, and each column corresponding to memristor array 2 and memristor array 3 is connected through an analog inverter. An input voltage v is applied to each column of memristor array 1. in Since the input and output voltages of the voltage follower circuit are equal and the input and output voltages of the analog inverter are opposite to each other, the vector formed by the voltage values ​​of each column of the memristor array 2 is also v in , the vector formed by the voltage values ​​of each column of the memristor array 3 is -v in Let M1, M2, and M3 represent the conductance matrices of memristor arrays 1, 2, and 3, respectively. The output current of this group of memristor arrays can be expressed as:

[0071] i out =(M1+M2-M3)v in (10)

[0072] therefore, Figure 2 The equivalent conductance matrix of a set of memristor arrays connected in corresponding rows is M1+M2-M3. Figure 2 This is only one example of a set of memristor arrays connected in corresponding rows as described in the present invention. Figure 2 The group of memristor arrays connected in corresponding rows shown includes three memristor arrays, a plurality of analog inverters, and a plurality of voltage follower circuits. However, the embodiment of the present invention does not impose any quantitative restrictions on the number of memristor arrays, the number of analog inverters, and the number of voltage follower circuits in a group of memristor arrays. Any group of memristor arrays in which the column input voltage and the row output current when each row is grounded satisfy the relationship shown in formula (9) can be considered as a group of memristor arrays connected in corresponding rows described in the embodiment of the present invention.

[0073] A group of memristor arrays can also be connected in the following way: corresponding columns are connected, and corresponding rows are connected through voltage follower circuits or analog inverters or other circuits with similar functions. If an input voltage is applied to each row of a memristor array in the group of memristor arrays, each column of the memristor array is grounded and the output current of each column is measured, assuming that the vector formed by the input voltage is v in , the vector formed by the output current is i out , the relationship between input voltage and output current is:

[0074] i out =M T v in (11)

[0075] M is the equivalent conductance matrix of the corresponding column-connected memristor array.

[0076] For example, Figure 3 An example of a memristor array having a set of connected columns is given in the present invention. Figure 3 As shown, the group of memristor arrays connected in corresponding columns includes three memristor arrays, memristor array 1, memristor array 2, and memristor array 3, as well as several voltage follower circuits and several analog inverters. Each row corresponding to memristor array 1 and memristor array 2 is connected through a voltage follower circuit, and each row corresponding to memristor array 2 and memristor array 3 is connected through an analog inverter. An input voltage v is applied to each row of memristor array 1. in Since the input and output voltages of the voltage follower circuit are equal and the input and output voltages of the analog inverter are opposite to each other, the vector formed by the voltage values ​​of each row of the memristor array 2 is also v in , the vector formed by the voltage values ​​of each row of the memristor array 3 is -v in Let M1, M2, and M3 represent the conductance matrices of memristor arrays 1, 2, and 3, respectively. The output current of this group of memristor arrays can be expressed as:

[0077] i out =(M1+M2-M3) T v in (12)

[0078] therefore, Figure 3 The equivalent conductance matrix of a set of memristor arrays connected in corresponding columns is M1+M2-M3. Figure 3 This is only one example of a group of memristor arrays connected in corresponding columns as described in the present invention. Figure 3 The group of memristor arrays connected in corresponding columns shown includes three memristor arrays, a plurality of analog inverters, and a plurality of voltage follower circuits. However, the embodiment of the present invention does not impose any quantitative restrictions on the number of memristor arrays, the number of analog inverters, and the number of voltage follower circuits in a group of memristor arrays. Any group of memristor arrays in which the row input voltage and the column output current when each column is grounded satisfy the relationship shown in formula (11) can be considered as a group of memristor arrays connected in corresponding columns described in the embodiment of the present invention.

[0079] It should be noted that if a group of memristor arrays includes only one memristor array, the equivalent conductance value matrix of the group of memristor arrays is the conductance value matrix of the memristor array.

[0080] Existing MIMO signal detection schemes based on memristor arrays use a matrix calculation circuit based on a memristor array to perform the matrix operation shown in formula (5) to achieve ZF detection, or perform the matrix operation shown in formula (7) to achieve MMSE detection. The present invention uses a matrix calculation circuit based on a memristor array to perform the matrix operation shown in formula (6) to achieve ZF detection, or perform the matrix operation shown in formula (8) to achieve MMSE detection.

[0081] The present invention proposes a MIMO communication system signal detection method based on a memristor array. Figure 1 shown.

[0082] Specifically, the signal detection method for a MIMO communication system based on a memristor array proposed in the present invention includes the following steps 1.1 to 1.3.

[0083] 1.1) Obtain the large-scale fading coefficient matrix, the small-scale fading coefficient matrix, and the baseband received signal.

[0084] 1.2) For the ZF signal detection algorithm, a matrix computing circuit based on a memristor array is used to calculate For the MMSE signal detection algorithm, a matrix computing circuit based on a memristor array is used to calculate

[0085] 1.3) The calculation results are determined as symbols in the modulation constellation.

[0086] Furthermore, in order to implement the above-mentioned MIMO communication system signal detection method based on memristor array proposed by the present invention, the present invention provides two circuit design schemes based on memristor array to implement the matrix calculation involved in the above-mentioned signal detection method.

[0087] The matrix calculation circuit design scheme provided by the present invention is as follows Figure 4 The circuit includes a group of memristor arrays a1 connected in corresponding rows, a group of memristor arrays a2 connected in corresponding rows, a group of operational amplifiers and 2N K The equivalent conductance matrix of a set of memristor arrays a1 connected in corresponding rows is 2N K ×2N R dimensional matrix A1; the equivalent conductance matrix of a set of corresponding row-connected memristor arrays a2 is 2N K ×2N Kdimensional matrix A2; a group of corresponding rows of connected memristor arrays a1 are connected to corresponding rows of a group of connected memristor arrays a2, and each row is connected to the inverting input and one of the non-inverting inputs of an operational amplifier in a group of operational amplifiers, and the non-inverting input or inverting input of the corresponding row of the memristor array is not connected to ground; the output of each operational amplifier in the group of operational amplifiers is connected to the corresponding column of a group of connected memristor arrays a2, and is also connected to the input of an inverting amplifier circuit; let 2N K The 2N inverting amplifier circuit is connected to the output of the operational amplifier in a group of operational amplifiers. K The conductance values ​​of the memristors are 2N K The conductance values ​​of the memristors connected across the output and inverting input of the operational amplifier in the inverting amplifier circuit are Then the amplification factor of the kth inverting amplifier circuit is ξ k / ξ′ k , let 2N K The amplification factors of the inverting amplifier circuits are That is θ k =ξ k / ξ′ k (1≤k≤2N K ). Apply input voltage vector v to each column of a set of memristor arrays a1 connected in corresponding rows. in , in 2N K The output voltage vector v is measured at the output end of the inverting amplifier circuit out .

[0088] The relationship between the output voltage vector and the input voltage vector of the circuit is:

[0089]

[0090] in

[0091] So, map y to v in , G T Map to A1, and G T G is mapped to A2, and Λ -1 Mapping to Θ, we can measure v out Get Map y to v in , G T Map to A1, and G T G+P is mapped to A2, and Λ -1 Mapping to Θ, we can measure v out Get The meaning of "mapping" in the above process is: by adjusting the conductance value of the memristor (or the input voltage value), the equivalent conductance value matrix and the corresponding mapped matrix (or the input voltage value vector and the corresponding mapped vector) satisfy a linear relationship.

[0092] Complete the pair or After the calculation, the result will be or The estimated signal can be obtained by deciding the symbol in the modulation constellation with the closest Euclidean distance.

[0093] The matrix calculation circuit design scheme 2 provided by the present invention is as follows Figure 5 The circuit includes a group of memristor arrays connected in corresponding rows, a group of memristor arrays connected in corresponding columns, a group of operational amplifiers 1, a group of operational amplifiers 2 and 2N. K The equivalent conductance matrix of a set of memristor arrays connected in corresponding rows is 2N R ×2N K dimensional matrix B1; the equivalent conductance matrix of a set of corresponding column-connected memristor arrays is 2N R ×2N K dimensional matrix B2; each row of a group of memristor arrays connected to corresponding rows is connected to one of the inverting input and non-inverting input of an operational amplifier in a group of operational amplifiers 1, and the non-inverting input or inverting input of the operational amplifier not connected to the corresponding row of the memristor array is grounded; the output of each operational amplifier in a group of operational amplifiers 1 is connected to the corresponding row of a group of memristor arrays connected to corresponding columns, and a jumper memristor with a conductance value of δ0 is connected between the corresponding rows of the memristor arrays connected to corresponding rows; each column of a group of memristor arrays connected to corresponding columns is connected to one of the inverting input and non-inverting input of an operational amplifier in a group of operational amplifiers 2, and the non-inverting input or inverting input of the operational amplifier not connected to the corresponding column of the memristor array is grounded; the output of each operational amplifier in a group of operational amplifiers 2 is connected to the corresponding column of a group of memristor arrays connected to corresponding rows, and a jumper memristor and an analog inverter are connected between the corresponding columns of the memristor arrays connected to corresponding columns. Assume that 2N K The conductance values ​​of the memristors connected across the resistors are The output of each operational amplifier in a group of operational amplifiers 2 is connected to the input of an inverting amplifier circuit at the same time. Let 2N K 2N connected to the output terminal of the operational amplifier in a group of operational amplifiers 2 in an inverting amplifier circuit K The conductance values ​​of the memristors are 2N KThe conductance values ​​of the memristors connected across the output and inverting input of the operational amplifier in the inverting amplifier circuit are Then the amplification factor of the kth inverting amplifier circuit is ξ k / ξ′ k , let 2N K The amplification factors of the inverting amplifier circuits are That is θ k =ξ k / ξ k '(1≤k≤2N K ). Apply input current vector i to each row of a group of corresponding rows of connected memristor arrays. in , in 2N K The output voltage vector v is measured at the output end of the inverting amplifier circuit out .

[0094] The relationship between the output voltage vector and the input current vector of the circuit is:

[0095]

[0096] in

[0097] Therefore, mapping y to i in , map G to B1 and B2, and transform Λ -1 Map to Θ, and make δ k =0(1≤k≤2N K ), we can measure v out Get Map y to i in , map G to B1 and B2, map P to Δ, and map Λ -1 Mapping to Θ, we can measure v out Get The meaning of "mapping" in the above process is: by adjusting the conductance value of the memristor (or the input current value), the equivalent conductance value matrix and the corresponding mapped matrix (or the input current value vector and the corresponding mapped vector) satisfy a linear relationship.

[0098] Complete the pair or After the calculation, the result will be or The estimated signal can be obtained by deciding the symbol in the modulation constellation with the closest Euclidean distance.

[0099] Preferably, an embodiment of the matrix calculation circuit design solution 1 provided by the present invention is as follows: Figure 6 shown.

[0100] Figure 6In the circuit shown, a group of memristor arrays a1 connected in corresponding rows includes memristor array 1, memristor array 2 and 2N R analog inverters, memristor array 1 and memristor array 2 are both 2N K ×2N R dimensional memristor array, assuming that the matrices composed of their conductance values ​​are C1 and C2 respectively; a group of corresponding row-connected memristor arrays a2 includes memristor array 3, memristor array 4, memristor array 5, 2N K A voltage follower circuit and a 2N K The memristor array 3 only places memristors in the diagonal position. Assume that the diagonal matrix formed by its conductance value is 2N K ×2N K Dimensional matrix C3, memristor array 4, memristor array 5 are both 2N K ×2N K dimensional memristor array, assuming that the matrices of their conductance values ​​are C4 and C5 respectively. Memristor arrays 1 and 2 are connected to an analog inverter between each corresponding column, memristor arrays 3 and 4 are connected to a voltage follower circuit between each corresponding column, and memristor arrays 4 and 5 are connected to an analog inverter between each corresponding column. A set of operational amplifiers includes 2N K The non-inverting input terminals of the operational amplifiers in a group of operational amplifiers are all grounded, and the corresponding rows of the memristor arrays 1, 2, 3, 4, and 5 are connected together, and these 2N K The rows are connected to the inverting input terminals of the operational amplifiers in the corresponding set of operational amplifiers, the output terminals of the operational amplifiers in the set of operational amplifiers are connected to the corresponding columns of the memristor array 3, and the output terminals of the operational amplifiers in the set of operational amplifiers are connected to the input terminals of an inverting amplifier circuit, with a total of 2N inverting amplifier circuits. K Assume 2N K The amplification factors of the inverting amplifier circuits are Apply input voltage vector v to each column of memristor array 1 in , in 2N K The output voltage vector v is measured at the output end of the inverting amplifier circuit out .

[0101] Figure 6 The relationship between the output voltage vector and the input voltage vector of the circuit shown is:

[0102] v out =Θ(C3+C4-C5) -1 (C1-C2)v in (15)

[0103] in

[0104] So, map y to v in , G T Mapping to C1-C2, G T G is mapped to C3+C4-C5, and Λ -1 Mapping to Θ, we can measure v out Get Map y to v in , G T Mapping to C1-C2, G T G+P is mapped to C3+C4-C5, and Λ -1 Mapping to Θ, we can measure v out Get

[0105] Complete the pair or After the calculation, the result will be or The estimated signal can be obtained by deciding the symbol in the modulation constellation with the closest Euclidean distance.

[0106] Preferably, an embodiment of the second matrix calculation circuit design scheme provided by the present invention is as follows: Figure 7 shown.

[0107] Figure 7 In the circuit shown, a group of memristor arrays connected in corresponding rows includes memristor array 1, memristor array 2 and 2N. K analog inverters, memristor array 1 and memristor array 2 are both 2N R ×2N K dimensional memristor array, assuming that the matrices formed by their conductance values ​​are D1 and D2 respectively; a group of corresponding column-connected memristor arrays includes memristor array 3, memristor array 4 and 2N R analog inverters, memristor array 3 and memristor array 4 are both 2N R ×2N K dimensional memristor array, assuming that the matrices formed by their conductance values ​​are D3 and D4 respectively; the corresponding rows of memristor arrays 1 and 2 are connected together, an analog inverter is connected between each corresponding column between memristor arrays 1 and 2, the corresponding columns of memristor arrays 3 and 4 are connected together, an analog inverter is connected between each corresponding row between memristor arrays 3 and 4; a group of operational amplifiers 1 includes 2N R Operational amplifiers, each operational amplifier has a non-inverting input terminal grounded, an inverting input terminal connected to the corresponding rows of memristor arrays 1 and 2, and an output terminal of the operational amplifier connected to the corresponding row of memristor array 3. A cross-connected memristor with a conductance value of δ0 is connected between the output terminal and the inverting input terminal of each operational amplifier. A group of operational amplifiers 2 includes 2NK operational amplifiers, where the inverting input of each operational amplifier is grounded, and the output of each operational amplifier in a group of operational amplifiers 2 is connected to the corresponding column of the memristor array 1. At the same time, a jumper memristor and an analog inverter are connected between the corresponding columns of the memristor array connected to a group of corresponding columns. Assume that the 2N K The conductance values ​​of the memristors connected across the resistors are The output terminals of the operational amplifiers in a group of operational amplifiers 2 are connected to the input terminals of an inverting amplifier circuit, and the inverting amplifier circuits are 2N in total. K Assume 2N K The amplification factors of the inverting amplifier circuits are Apply input voltage vector i to each row of memristor array 1 in , in 2N K The output voltage vector v is measured at the output end of the inverting amplifier circuit out .

[0108] Figure 7 The relationship between the output voltage and input current of the circuit shown is:

[0109] v out =Θ((D3-D4) T (D1-D2)+Δ) -1 (D3-D4) T i in (16)

[0110] in

[0111] Therefore, mapping y to i in , map G to D1-D2 and D3-D4, and map Λ -1 Map to Θ, and make δ k =0,(1≤k≤2N K ), we can measure v out Get Map y to i in , map G to D1-D2 and D3-D4, map P to Δ, and map Λ -1 Mapping to Θ, we can measure v out Get

[0112] Complete the pair or After the calculation, the result will be or The estimated signal can be obtained by deciding the symbol in the modulation constellation with the closest Euclidean distance.

[0113] Furthermore, the present invention provides two MIMO communication system signal detection devices based on memristor arrays for implementing the MIMO communication system signal detection method proposed in the present invention.

[0114] For example, the structure of the signal detection device 1 of the MIMO communication system based on the memristor array (hereinafter referred to as the signal detection device 1) of the embodiment of the present invention is as follows: Figure 8 As shown. The signal detection device 1 is composed of a calculation circuit 1, a memristor conductance value calculation and programming module, a voltage measurement module and a judgment module. The calculation circuit 1 refers to a circuit designed and implemented according to the matrix calculation circuit design scheme 1 provided by the present invention; the memristor conductance value calculation and programming module is used to calculate the target conductance value of the memristor in the calculation circuit 1 according to the large-scale attenuation coefficient matrix and the small-scale attenuation coefficient matrix, and to program and modify the conductance value of the memristor in the calculation circuit 1; the voltage measurement module is used to measure the output voltage of the calculation circuit 1, which can be an analog to digital converter (ADC) or a high-precision voltage measurement chip or other device; the judgment module is used to calculate according to the measurement result of the output voltage. or It is determined as the symbol in the modulation constellation with the closest Euclidean distance and an estimated signal is output.

[0115] For example, the structure of the second signal detection device for a MIMO communication system based on a memristor array (hereinafter referred to as the second signal detection device) according to an embodiment of the present invention is as follows: Figure 9 As shown. The signal detection device 2 is composed of a calculation circuit 2, a memristor conductance value calculation and programming module, a voltage measurement module and a judgment module. The calculation circuit 2 refers to a circuit designed and implemented according to the matrix calculation circuit design scheme 2 provided by the present invention; the memristor conductance value calculation and programming module is used to calculate the target conductance value of the memristor in the calculation circuit 2 according to the large-scale attenuation coefficient matrix and the small-scale attenuation coefficient matrix, and to program and modify the conductance value of the memristor in the calculation circuit 2; the voltage measurement module is used to measure the output voltage of the calculation circuit 2, which can be an ADC or a high-precision voltage measurement chip or other device; the judgment module is used to calculate according to the measurement result of the output voltage. or It is determined as the symbol in the modulation constellation with the closest Euclidean distance and an estimated signal is output.

[0116] For example, the flowchart of the signal detection method for the MIMO communication system proposed by the present invention using a signal detection device is shown in FIG. Figure 10 Specifically, the process of using the signal detection device 1 to implement the MIMO communication system signal detection method proposed by the present invention includes the following steps 2.1 to 2.5.

[0117] 2.1) Obtain the large-scale fading coefficient matrix, small-scale fading coefficient matrix and baseband received signal.

[0118] 2.2) Modify the conductance value of each memristor in the calculation circuit 1, including:

[0119] G T Mapping is A1, that is, using the memristor conductance value calculation and programming module to modify the conductance values ​​of the memristors in a group of corresponding rows of connected memristor array 1 in the calculation circuit 1, so that the equivalent conductance value matrix A1 of a group of corresponding rows of connected memristor array 1 satisfies:

[0120] A1=α1G T (17)

[0121] Also need to Λ -1 Mapping is Θ, that is, modifying the conductance of the memristor in each inverting amplifier circuit in the calculation circuit 1 so that the amplification factor of the inverting amplifier circuit satisfies:

[0122] Θ=α2Λ -1 (18)

[0123] If the ZF signal detection algorithm is used, G T G is mapped to A2, that is, the conductance values ​​of the memristors in a group of corresponding rows of connected memristor arrays 2 in the computing circuit 1 are modified so that the equivalent conductance value matrix A2 of a group of corresponding rows of connected memristor arrays 2 satisfies:

[0124] A2=α3G T G (19)

[0125] If the MMSE signal detection algorithm is used, G T G+P is mapped to A2, that is, the conductance values ​​of the memristors in a group of corresponding rows of connected memristor arrays 2 in the computing circuit 1 are modified so that the equivalent conductance value matrix A2 of a group of corresponding rows of connected memristor arrays 2 satisfies:

[0126] A2=α3(G T G+P) (20)

[0127] The above parameters α1, α2, α3 and the specific conductance value of the memristor are determined by the memristor conductance value calculation and programming module according to the adjustable range of the conductance value of the memristor, the value of the channel matrix, etc.

[0128] 2.3) Apply input voltage.

[0129] The baseband received signal vector y is mapped to an input voltage vector, that is, an input voltage is applied to the calculation circuit 1, and the applied input voltage satisfies:

[0130] vin =α4y (21)

[0131] The above parameter α4 is determined according to the adjustable range of the input voltage, the value of the baseband received signal vector, etc.

[0132] 2.4) Measure the output voltage.

[0133] Use the voltage measurement module to measure the output voltage v of the calculation circuit 1 out .

[0134] 2.5) The calculation results are determined as symbols in the modulation constellation.

[0135] The judgment module obtains the measurement results of the voltage measurement module and calculates according to the following formula or

[0136] If the ZF signal detection algorithm is used, then

[0137]

[0138] If the MMSE signal detection algorithm is used, then

[0139]

[0140] Next, the decision module will calculate the result or The decision is made on the symbol in the modulation constellation with the closest Euclidean distance, and the estimated signal is output.

[0141] For example, the flowchart of the signal detection method for the MIMO communication system proposed by the present invention using the signal detection device 2 is shown in FIG. Figure 11 Specifically, the process of using the second signal detection device to implement the MIMO communication system signal detection method proposed by the present invention includes the following steps 3.1 to 3.5.

[0142] 3.1) Obtain the large-scale fading coefficient matrix, small-scale fading coefficient matrix and baseband received signal.

[0143] 3.2) Modify the conductance values ​​of each memristor in the calculation circuit 2, including:

[0144] Map G to B1 and B2, that is, use the memristor conductance calculation and programming module to modify the conductance values ​​of the memristors in a group of memristor arrays connected in corresponding rows and a group of memristor arrays connected in corresponding columns in the calculation circuit 2, so that the equivalent conductance matrix B1 of the group of memristor arrays connected in corresponding rows and the equivalent conductance matrix B2 of the group of memristor arrays connected in corresponding columns satisfy:

[0145] B1=β1G (24)

[0146] B2=β2G (25)

[0147] Also need to Λ -1 Mapping is Θ, that is, modifying the conductance of the memristor in each inverting amplifier circuit in the calculation circuit 2 so that the amplification factor of the inverting amplifier circuit satisfies:

[0148] Θ=β3Λ -1 (26)

[0149] If the ZF signal detection algorithm is used, the conductance value of the memristor connected across the operational amplifier in a group of operational amplifiers 2 in the calculation circuit 2 needs to be modified so that the conductance value of the memristor connected across the operational amplifier in a group of operational amplifiers 2 is all 0, that is, δ k =0(1≤k≤2N K ).

[0150] If the MMSE signal detection algorithm is used, P needs to be mapped to Δ. That is, the conductance value of the memristor connected across the operational amplifier in a group of operational amplifiers 2 in the calculation circuit 2 is modified so that the conductance value of the memristor connected across the operational amplifier in a group of operational amplifiers 2 satisfies:

[0151] Δ=β1β2P (27)

[0152] The above parameters β1, β2, β3 and the specific conductance value of the memristor are determined by the memristor conductance value calculation and programming module according to the adjustable range of the conductance value of the memristor, the value of the channel matrix, etc.

[0153] 3.3) Apply input current.

[0154] The baseband received signal vector y is mapped to an input current vector, that is, an input current is applied to the calculation circuit 2, and the applied input current satisfies:

[0155] i in =β4y (28)

[0156] The parameter β4 is determined according to the adjustable range of the input current, the value of the baseband received signal vector, etc.

[0157] 3.4) Measure the output voltage.

[0158] Use the voltage measurement module to measure the output voltage v of the calculation circuit 2 out .

[0159] 3.5) The calculation results are determined as symbols in the modulation constellation.

[0160] The judgment module obtains the measurement results of the voltage measurement module and calculates according to the following formula or

[0161] If the ZF signal detection algorithm is used, then

[0162]

[0163] If the MMSE signal detection algorithm is used, then

[0164]

[0165] Next, the decision module will calculate the result or The symbol in the modulation constellation with the closest Euclidean distance is decided and an estimated signal is output.

[0166] Furthermore, the present invention provides three implementations of a MIMO communication system signal detection device based on a memristor array.

[0167] For example, Figure 12 This is a schematic diagram of the structure of a MIMO communication system signal detection device according to an embodiment of the present invention, comprising: an antenna, RF filter 1, a low-noise amplifier, RF filter 2, a mixer connected to a local oscillator, an intermediate frequency filter, an intermediate frequency amplifier, and an analog-to-digital converter, connected in sequence; a voltage / current supply module, a channel estimation module, and a first or second MIMO communication system signal detection device based on a memristor array according to the present invention. The functions of each module are as follows:

[0168] The antenna, RF filter 1, low-noise amplifier, RF filter 2, mixer connected to a local oscillator, intermediate frequency filter, intermediate frequency amplifier and analog-to-digital converter connected in sequence are used to convert the RF signal received by the antenna into a baseband reception signal in the form of a digital signal and output the baseband reception signal to the channel estimation module and the voltage / current providing module.

[0169] The voltage / current providing module is used to provide input voltage for signal detection device 1 or input current for signal detection device 2 based on the baseband received signal. This module can be a digital to analog converter (DAC) or an adjustable voltage source / current source chip or other device.

[0170] The channel estimation module is used to calculate the large-scale fading coefficient matrix and the small-scale fading coefficient matrix based on the channel estimation related technology, and output these two matrices to the first or second signal detection device.

[0171] The first or second signal detection calculation device of the MIMO communication system based on the memristor array is used to realize signal detection and output an estimated signal.

[0172] For example, Figure 13This is a schematic diagram of the structure of the second MIMO communication system signal detection device proposed in an embodiment of the present invention, comprising: an antenna, RF filter 1, a low-noise amplifier, RF filter 2, a mixer connected to a local oscillator, an intermediate frequency filter, an intermediate frequency amplifier, a sample-and-hold circuit, a channel estimation module, and the first or second MIMO communication system signal detection device based on a memristor array proposed in the present invention. The functions of each module are as follows:

[0173] The antenna, RF filter 1, low noise amplifier, RF filter 2, mixer connected to a local oscillator, intermediate frequency filter, and intermediate frequency amplifier connected in sequence are used to convert the RF signal received by the antenna into a baseband received signal in the form of an analog signal and output it to the sample and hold circuit.

[0174] The sampling and holding circuit is used to sample the baseband received signal in the form of an analog signal. The sampling and holding circuit can be directly used to provide input voltage for signal detection device one or input current for signal detection device two without the need for an additional voltage / current providing module. The sampling results are simultaneously output to the channel estimation module for calculating the large-scale fading coefficient matrix and the small-scale fading coefficient matrix.

[0175] The channel estimation module is used to calculate the large-scale fading coefficient matrix and the small-scale fading coefficient matrix based on the channel estimation related technology, and output these two matrices to the first or second signal detection device.

[0176] The first or second signal detection calculation device of the MIMO communication system based on the memristor array is used to realize signal detection and output an estimated signal.

[0177] For example, Figure 14 This is a schematic diagram of the structure of the MIMO communication system signal detection device proposed in an embodiment of the present invention, including: an antenna, a radio frequency filter 1, a low noise amplifier, a radio frequency filter 2, a mixer 1 connected to a local oscillator 1, an intermediate frequency filter, an intermediate frequency amplifier, an IQ demodulation module, a channel estimation module, and the first or second MIMO communication system signal detection device based on a memristor array proposed in the present invention, wherein the IQ demodulation module includes a local oscillator 2, a mixer 2, a mixer 3, a low-pass filter 1, and a low-pass filter 2. The functions of each module are as follows:

[0178] The antenna, RF filter 1, low noise amplifier, RF filter 2, mixer 1 connected to local oscillator 1, intermediate frequency filter, and intermediate frequency amplifier connected in sequence are used to convert the RF signal received by the antenna into a baseband received signal in the form of an analog signal and output it to the IQ demodulation module.

[0179] The IQ demodulation module is used to convert the baseband received signal in the form of an analog signal into a voltage or current vector corresponding to the baseband received signal, thereby providing an input voltage for signal detection device 1 or an input current for signal detection device 2. The IQ demodulation module also outputs the voltage or current vector corresponding to the baseband received signal to the channel estimation module. In the IQ demodulation module, the local oscillator 2 generates two signals with a phase difference of 90° and inputs them into mixer 2 and mixer 3 respectively. The baseband received signal in the form of an analog signal is also input into mixer 2 and mixer 3 respectively. The output signals of mixer 2 and mixer 3 are respectively input into low-pass filter 1 and low-pass filter 2. The output voltage / current of low-pass filter 1 and low-pass filter 2 is the voltage or current vector corresponding to the baseband received signal. Low-pass filter 1 and low-pass filter 2 can be directly used to provide input voltage or current for detection device 1 or 2 without the need for an additional voltage / current providing module.

[0180] Channel estimation module: Calculates the large-scale fading coefficient matrix and the small-scale fading coefficient matrix based on channel estimation related technologies, and outputs these two matrices to the first or second signal detection device.

[0181] Memristor array-based MIMO communication system signal detection computing device one or two: realizes signal detection and outputs estimated signal.

[0182] like Figure 15 Figure 2 shows the bit error rate simulation results of a signal detection method for a MIMO communication system based on a memristor array according to an embodiment of the present invention, as well as the bit error rate simulation results for MIMO signal detection using the circuit in Reference 1 and the modified circuit in Reference 2. The conductance error level in the figure refers to the ratio of the standard deviation of the memristor conductance error to the adjustable range of the memristor conductance. The simulation scenario is a 4×64 multi-user MIMO system, with signal transmitters randomly distributed within a circular cell with a radius of 150 meters. Each signal transmitter has a transmitting antenna, a transmitted signal power of 20 dBm, a carrier frequency of 2 GHz, and a modulation scheme of 64QAM. Figure 15 Simulation results show that, in the presence of conductance errors, the bit error rate (BER) for ZF or MMSE signal detection using the memristor array-based MIMO communication system signal detection method proposed in this invention is lower than the BER for ZF or MMSE signal detection using the circuit in Reference 1 or the modified circuit in Reference 2. Therefore, compared with other technical solutions, the memristor array-based MIMO communication system signal detection method proposed in this invention has superior detection performance.

[0183] Except for the technical features described in the specification, all other technical features are known to those skilled in the art. The present invention omits descriptions of well-known components and well-known technologies to avoid redundancy and unnecessary limitation of the present invention. The implementation methods described in the above embodiments do not represent all implementation methods consistent with the present application. Based on the technical solution of the present invention, various modifications or variations that can be made by those skilled in the art without creative effort are still within the scope of protection of the present invention.

Claims

1. A signal detection method for a MIMO communication system based on a memristor array, characterized in that: The method includes: First, obtain the large-scale fading coefficient matrix, small-scale fading coefficient matrix and baseband received signal, and express the MIMO channel matrix H as the product of the small-scale fading coefficient matrix G and the large-scale fading coefficient matrix Λ; suppose the number of transmitting antennas of the MIMO communication system is N K , the number of receiving antennas is N R ; Secondly, a matrix calculation circuit based on a memristor array is used to perform matrix calculations, where: If zero-forcing ZF detection is used, calculate If the minimum mean square error MMSE detection is used, calculate in, N K Large-scale fading coefficients between the transmitting antennas and a single receiving antenna; is the plural form of G, means taking the real part of the matrix, Indicates taking the imaginary part of the matrix; parameter p s is the average power of the transmitted signal, is the variance of the noise signal; (·)- 1 represents matrix inversion, (·) T represents matrix transpose, diag(·) represents diagonal matrix; Finally, the calculation results or The decision is the symbol in the modulation constellation.

2. A matrix computing circuit based on a memristor array, used in the signal detection method according to claim 1, characterized in that: The circuit is designed as follows: the circuit includes a group of memristor arrays a1 connected in corresponding rows, a group of memristor arrays a2 connected in corresponding rows, a group of operational amplifiers and 2N K Inverting amplifier circuit; the equivalent conductance matrix of a set of corresponding row-connected memristor arrays a1 is 2N K ×2N R dimensional matrix A1; the equivalent conductance matrix of a set of corresponding row-connected memristor arrays a2 is 2N K ×2N K dimensional matrix A2; a group of corresponding rows of connected memristor arrays a1 are connected to corresponding rows of a group of connected memristor arrays a2, and each row is connected to the inverting input and one of the non-inverting inputs of an operational amplifier in a group of operational amplifiers, and the non-inverting input or inverting input of the corresponding row of the memristor array is not connected to ground; the output of each operational amplifier in the group of operational amplifiers is connected to the corresponding column of a group of connected memristor arrays a2, and is also connected to the input of an inverting amplifier circuit; let 2N K The 2N inverting amplifier circuit is connected to the output of the operational amplifier in a group of operational amplifiers. K The conductance values ​​of the memristors are 2N K The conductance values ​​of the memristors connected across the output and inverting input of the operational amplifier in the inverting amplifier circuit are Then the amplification factor of the kth inverting amplifier circuit is θ k =ξ k / ξ k '(1≤k≤2N K ); Apply input voltage vector v to each column of a set of memristor arrays a1 connected in corresponding rows in , in 2N K The output voltage vector v is measured at the output end of the inverting amplifier circuit out ; The relationship between the output voltage vector and the input voltage vector of this circuit is: in In this circuit, y is mapped to v in , G T Map to A1, and G T G is mapped to A2, and Λ -1 Mapping to Θ, by measuring v out Get Map y to v in , G T Map to A1, and G T G+P is mapped to A2, and Λ -1 Mapping to Θ, by measuring v out Get A group of memristor arrays with corresponding rows connected are connected, and the column input voltage v in The row output current i when each row is grounded out Satisfy i out =Mv in Relationship, M is the equivalent conductance value matrix of the memristor array connected in the corresponding row.

3. A matrix computing circuit based on a memristor array, used in the signal detection method according to claim 1, characterized in that: The circuit is designed as follows: the circuit includes a group of memristor arrays connected in corresponding rows, a group of memristor arrays connected in corresponding columns, a group of operational amplifiers 1, a group of operational amplifiers 2 and 2N K Inverting amplifier circuit; the equivalent conductance matrix of a group of corresponding row-connected memristor arrays is 2N R ×2N K dimensional matrix B1; the equivalent conductance matrix of a set of corresponding column-connected memristor arrays is 2N R ×2N K dimensional matrix B2; each row of a group of memristor arrays connected to corresponding rows is connected to one of the inverting input and non-inverting input of an operational amplifier in a group of operational amplifiers 1, and the non-inverting input or inverting input of the operational amplifier not connected to the corresponding row of the memristor array is grounded; the output of each operational amplifier in a group of operational amplifiers 1 is connected to the corresponding row of a group of memristor arrays connected to corresponding columns, and a jumper memristor with a conductance value of δ0 is connected between the corresponding rows of the memristor arrays connected to corresponding rows; each column of a group of memristor arrays connected to corresponding columns is connected to one of the inverting input and non-inverting input of an operational amplifier in a group of operational amplifiers 2, and the non-inverting input or inverting input of the operational amplifier not connected to the corresponding column of the memristor array is grounded; the output of each operational amplifier in a group of operational amplifiers 2 is connected to the corresponding column of the memristor arrays connected to corresponding rows, and a jumper memristor and an analog inverter are connected between the corresponding columns of the memristor arrays connected to corresponding columns. Let 2N K The conductance values ​​of the memristors connected across the resistors are The output of each operational amplifier in a group of operational amplifiers 2 is connected to the input of an inverting amplifier circuit at the same time. Let 2N K 2N connected to the output terminal of the operational amplifier in a group of operational amplifiers 2 in an inverting amplifier circuit K The conductance values ​​of the memristors are 2N K The conductance values ​​of the memristors connected across the output and inverting input of the operational amplifier in the inverting amplifier circuit are Then the amplification factor of the kth inverting amplifier circuit is θ k =ξ k / ξ k '(1≤k≤2N K ); Apply input current vector i to each row of a group of corresponding row-connected memristor arrays in , in 2N K The output voltage vector v is measured at the output end of the inverting amplifier circuit out , the relationship between the output voltage vector and the input current vector of the circuit is: in In this circuit, y is mapped to i in , map G to B1 and B2, and transform Λ -1 Map to Θ, and make δ k =0(1≤k≤2N K ), by measuring v out Get Map y to i in , map G to B1 and B2, map P to Δ, and map Λ -1 Mapping to Θ, by measuring v out Get A group of memristor arrays with corresponding columns connected are connected, and the row input voltage v in The column output current i when each column is grounded out Satisfy i out =M T v in Relationship, M is the equivalent conductance value matrix of the memristor array connected to the corresponding columns of this group.

4. A matrix computing circuit based on a memristor array as claimed in claim 2, characterized in that: The circuit is implemented as follows: a group of memristor arrays a1 connected in corresponding rows includes memristor array 1, memristor array 2 and 2N R analog inverters; memristor array 1 and memristor array 2 are both 2N K ×2N R The corresponding conductance values ​​of the memristor array are C1 and C2 respectively; a group of memristor arrays a2 connected in corresponding rows includes memristor array 3, memristor array 4, memristor array 5, 2N K A voltage follower circuit and a 2N K Analog inverters; memristor array 3 places memristors only in the diagonal position, and the corresponding diagonal matrix of conductance values ​​is 2N K ×2N K dimensional matrix C3; memristor array 4 and memristor array 5 are both 2N K ×2N K dimensional memristor array, the corresponding conductance values ​​are composed of matrices C4 and C5 respectively; an analog inverter is connected between each corresponding column of memristor array 1 and memristor array 2, a voltage follower circuit is connected between each corresponding column of memristor array 3 and memristor array 4, and an analog inverter is connected between each corresponding column of memristor array 4 and memristor array 5; a set of operational amplifiers contains 2N K The non-inverting inputs of the operational amplifiers are all grounded, the corresponding rows of memristor arrays 1, 2, 3, 4, and 5 are connected together, and each row is respectively connected to the inverting input of an operational amplifier in a corresponding group of operational amplifiers, the outputs of the operational amplifiers in a group of operational amplifiers are respectively connected to the corresponding columns of memristor array 3, and the outputs of the operational amplifiers in a group of operational amplifiers are respectively connected to the input of an inverting amplifier circuit.

5. The matrix computing circuit based on a memristor array according to claim 3, wherein: The circuit is implemented as follows: a group of memristor arrays connected in corresponding rows includes memristor array 1, memristor array 2 and 2N K analog inverters; memristor array 1 and memristor array 2 are both 2N R ×2N K The corresponding conductance values ​​of the memristor array are D1 and D2 respectively; a group of memristor arrays connected in corresponding columns includes memristor array 3, memristor array 4 and 2N R analog inverters; memristor array 3 and memristor array 4 are both 2N R ×2N K dimensional memristor array, the corresponding conductance values ​​constitute the matrices D3 and D4 respectively; the corresponding rows of memristor array 1 and memristor array 2 are connected together, an analog inverter is connected between each corresponding column between memristor array 1 and memristor array 2, the corresponding columns of memristor array 3 and memristor array 4 are connected together, an analog inverter is connected between each corresponding row between memristor array 3 and memristor array 4; a group of operational amplifiers 1 includes 2N R Operational amplifiers, each operational amplifier has a non-inverting input terminal grounded, an inverting input terminal connected to the corresponding rows of memristor arrays 1 and 2, and an output terminal of the operational amplifier connected to the corresponding row of memristor array 3. A cross-connected memristor with a conductance value of δ0 is connected between the output terminal and the inverting input terminal of each operational amplifier. A group of operational amplifiers 2 includes 2N K operational amplifiers, each of which has an inverting input connected to ground; the output of each operational amplifier in a group of operational amplifiers 2 is connected to a corresponding column of the memristor array 1; and a jumper memristor and an analog inverter are connected between corresponding columns of the memristor array connected to a group of corresponding columns; the outputs of the operational amplifiers in a group of operational amplifiers 2 are respectively connected to the input of an inverting amplifier circuit.

6. A MIMO communication system signal detection device based on a memristor array, characterized in that: The device comprises a computing circuit 1, a memristor conductance value calculation and programming module, a voltage measurement module, and a judgment module; the computing circuit 1 is a matrix computing circuit based on a memristor array as described in claim 2; the memristor conductance value calculation and programming module is used to calculate the target conductance value of the memristor in the computing circuit 1 according to the large-scale attenuation coefficient matrix and the small-scale attenuation coefficient matrix, and to program and modify the conductance value of the memristor in the computing circuit 1; the voltage measurement module is used to measure the output voltage of the computing circuit 1; The decision module is used to calculate the output voltage based on the measurement results. or The calculation result is determined as the symbol in the modulation constellation with the closest Euclidean distance, and an estimated signal is obtained and output.

7. A MIMO communication system signal detection device based on a memristor array, characterized in that: The device comprises a second computing circuit, a memristor conductance value calculation and programming module, a voltage measurement module, and a judgment module; the computing circuit second is a matrix computing circuit based on a memristor array as described in claim 3; the memristor conductance value calculation and programming module is used to calculate the target conductance value of the memristor in the computing circuit second according to the large-scale attenuation coefficient matrix and the small-scale attenuation coefficient matrix, and to program and modify the conductance value of the memristor in the computing circuit second; the voltage measurement module is used to measure the output voltage of the computing circuit second; The decision module is used to calculate the output voltage based on the measurement results. or The calculation result is determined as the symbol in the modulation constellation with the closest Euclidean distance, and an estimated signal is obtained and output.

8. A MIMO communication system signal detection device based on a memristor array, characterized in that: The detection device includes: an antenna, a radio frequency filter 1, a low-noise amplifier, a radio frequency filter 2, a mixer connected to a local oscillator, an intermediate frequency filter, an intermediate frequency amplifier and an analog-to-digital converter, as well as a voltage / current providing module, a channel estimation module and a MIMO communication system signal detection device as described in claim 6 or 7, which are connected in sequence; the antenna, radio frequency filter 1, a low-noise amplifier, radio frequency filter 2, a mixer connected to a local oscillator, an intermediate frequency filter, an intermediate frequency amplifier and an analog-to-digital converter, which are connected in sequence, are used to convert the radio frequency signal received by the antenna into a baseband receiving signal in the form of a digital signal and output the baseband receiving signal to the channel estimation module and the voltage / current providing module; the voltage / current providing module is used to provide input voltage or input current for the MIMO communication system signal detection device; the channel estimation module is used to calculate a large-scale fading coefficient matrix and a small-scale fading coefficient matrix and output them to the MIMO communication system signal detection device; the MIMO communication system signal detection device calculates and outputs an estimated signal.

9. A MIMO communication system signal detection device based on a memristor array, characterized in that: The detection device includes: an antenna, a radio frequency filter 1, a low-noise amplifier, a radio frequency filter 2, a mixer connected to a local oscillator, an intermediate frequency filter and an intermediate frequency amplifier, as well as a sampling and holding circuit, a channel estimation module and a MIMO communication system signal detection device as described in claim 6 or 7, which are connected in sequence; the antenna, radio frequency filter 1, a low-noise amplifier, radio frequency filter 2, a mixer connected to a local oscillator, an intermediate frequency filter and an intermediate frequency amplifier, which are connected in sequence, are used to convert the radio frequency signal received by the antenna into a baseband received signal in the form of an analog signal and output it to the sampling and holding circuit; the sampling and holding circuit is used to sample the baseband received signal in the form of an analog signal to obtain a voltage or current vector corresponding to the baseband received signal, provide input voltage or input current for the MIMO communication system signal detection device, and the sampling and holding circuit simultaneously outputs the voltage or current vector corresponding to the baseband received signal to the channel estimation module; the channel estimation module is used to calculate a large-scale fading coefficient matrix and a small-scale fading coefficient matrix and output them to the MIMO communication system signal detection device; the MIMO communication system signal detection device calculates and outputs an estimated signal.

10. A MIMO communication system signal detection device based on a memristor array, characterized in that: The detection device includes: an antenna, a radio frequency filter 1, a low noise amplifier, a radio frequency filter 2, a mixer 1 connected to a local oscillator 1, an intermediate frequency filter and an intermediate frequency amplifier, as well as an IQ demodulation module, a channel estimation module and a MIMO communication system signal detection device as claimed in claim 6 or 7; wherein the IQ demodulation module includes a local oscillator 2, a mixer 2, a mixer 3, a low-pass filter 1, and a low-pass filter 2; the antenna, the radio frequency filter 1, the low noise amplifier, the radio frequency filter 2, the mixer 1 connected to the local oscillator 1, the intermediate frequency filter and the intermediate frequency amplifier, which are connected in sequence, are used to convert the radio frequency signal received by the antenna into a baseband reception signal in the form of an analog signal and output it to the IQ demodulation module; the IQ demodulation module is used to convert the baseband reception signal in the form of an analog signal into a voltage or current vector corresponding to the baseband reception signal, which is the voltage or current vector corresponding to the baseband reception signal. The MIMO communication system signal detection device provides an input voltage or input current, and the IQ demodulation module simultaneously outputs the voltage or current vector corresponding to the baseband received signal to the channel estimation module; in the IQ demodulation module, the local oscillator 2 generates two signals with a phase difference of 90° and inputs them into mixer 2 and mixer 3 respectively, and the baseband received signal in the form of an analog signal is also input into mixer 2 and mixer 3 respectively, and the output signals of mixer 2 and mixer 3 are input into low-pass filter 1 and low-pass filter 2 respectively, and the output voltage / current of low-pass filter 1 and low-pass filter 2 is the voltage or current vector corresponding to the baseband received signal; the channel estimation module calculates the large-scale fading coefficient matrix and the small-scale fading coefficient matrix and outputs them to the MIMO communication system signal detection device; the MIMO communication system signal detection device calculates and outputs the estimated signal.

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