Multi-master multi-slave full duplex communication protocol based on arbitration selection single-line multiplexing mechanism

Abstract

The invention provides a multi-master multi-slave full duplex communication protocol based on an arbitration selection single-line multiplexing mechanism, which comprises the following steps that: firstly, all equipment performs master-slave negotiation based on a bus, all equipment with a clock control right intention sends a section of message, the message carries a master equipment identifier, and the master equipment identifier carries a master equipment identifier; the device carrying the master device identifier participates in bus competition, broadcasts the same clock signal to all devices in the line after successful competition through the arbitration selection line, awakens all slave devices, and starts data communication, so that the communication efficiency is improved, and through a mechanism based on arbitration selection / single line multiplexing, the bus competition is reduced, the communication bandwidth is improved, the system design is simplified, and the cost is reduced. The multi-master and multi-slave system has the advantages that a complex hardware circuit is not needed, the design and implementation of the multi-master and multi-slave system are simplified, the reliability is enhanced, the reliability of communication and the accuracy of data are ensured through a multi-unit arbitration interval and a verification mechanism, multiple modes are supported, multiple data transmission modes are provided, and different application requirements are met.

Description

Technical Field

[0001] The invention mainly relates to the field of communication protocols, and in particular to a multi-master and multi-slave full-duplex communication protocol based on arbitration selection single-line multiplexing mechanism. Background Art

[0002] In modern electronic systems, multi-master and multi-slave communication is a common communication method, which is widely used in embedded systems and distributed computing environments. Traditional multi-master and multi-slave communication protocols, such as I²C and SPI, have certain limitations, such as bus contention, bandwidth limitation, and low communication efficiency. These protocols usually rely on central arbitration mechanisms or hardware circuits to handle competition between multiple master devices, resulting in increased system complexity and cost. Therefore, an efficient and reliable multi-master and multi-slave communication protocol is needed to solve these problems. Summary of the invention

[0003] 1. Problems to be solved by the invention: The present invention provides a multi-master and multi-slave full-duplex communication protocol based on arbitration selection single-line multiplexing mechanism, aiming to improve communication efficiency, reduce bus competition, simplify system design, and achieve higher communication bandwidth and reliability.

[0004] 2. Technical solution: To achieve the above object, the present invention provides a technical solution: a multi-master and multi-slave full-duplex communication protocol based on arbitration selection single-line multiplexing mechanism, comprising the following steps: In each communication cycle, the master device is dynamically determined through the arbitration selection line. The master device is responsible for controlling the global timing to ensure the order and effective transmission of the data stream, while the slave device responds according to the instructions of the master device, realizing a highly flexible master-slave role scheduling mechanism.

[0005] First, all devices conduct master-slave negotiation based on a bus. All devices that intend to control the clock send a message carrying the master device identifier. The device carrying the master device identifier participates in the bus competition. After successfully competing through the arbitration selection line, the same clock signal is broadcast to all devices in the line, waking up all slave devices and starting data communication.

[0006] The devices participating in the competition for the master device simultaneously send their own device addresses to the bus. Based on the principle of the smaller address wins, the winner of this round of arbitration selection line is selected and becomes the only master device in this round. The other master devices participating in the election are also converted into slave devices. The winner controls the subsequent clock line and sends command data to control different slave devices on the line. The slave device will give a corresponding response action after receiving the command.

[0007] After the previous round of communication ends, the loser of the previous round of master device competition in the bus starts a new round of master device competition, and the winner of the previous round withdraws from the master device competition and becomes a slave device. Then, the operations of steps 2 and 3 are implemented in a loop until all the devices participating in the first round of slave devices act as master devices and complete the "busy" cycle, that is, complete the task list of controlling the slave devices of their own devices. When all devices on the bus are in an idle state and no device controls the clock line, the communication is completely ended, and the next round of communication begins when a device continues to send a message containing the master device identifier to the bus.

[0008] The mechanism based on the smaller address wins effectively avoids conflicts between devices and ensures the priority of devices through unique addresses. In a multi-master and multi-slave structure, this mechanism can ensure that each device has an equal opportunity to control the bus, greatly improving the flexibility and scalability of the system. At the same time, this round-robin scheduling mechanism avoids a single device occupying the bus for a long time, thereby improving the load balancing capability and resource utilization efficiency of the multi-device system.

[0009] The protocol's cyclic scheduling and task switching design further optimizes communication efficiency, ensuring that each device's tasks can be completed as needed. The entire system exhibits high stability and reliability in high-concurrency scenarios and can meet the communication needs of complex application scenarios.

[0010] Furthermore, the arbitration selection line is designed based on the timing of line XOR / modulo-2 operation. Multiple master devices send arbitration signals through the selection line. Each master device pulls the selection line low to initiate arbitration. The line XOR allows multiple master devices to send signals at the same time, and finally confirms which master device wins the arbitration.

[0011] The results of modulo-2 addition and modulo-2 subtraction in the modulo-2 operation are the same and consistent with the result of the XOR operation.

[0012] Furthermore, all master devices compete, and the devices transmit addresses through the arbitration selection line. The arbitration selection line is used for arbitration, with the high bit first and the low address being the master device. In this scenario, the last two bits of the address of the competing master device are required to be programmable addresses, that is, the maximum number of competing master devices that can be mounted is 4. In other scenarios, it can also be an n-bit programmable address, and the maximum number of competing master devices that can be mounted is 2. n A competitive master device - independently designed according to the application scenario.

[0013] Furthermore, the unit arbitration interval in the arbitration selection line is determined according to a specific scenario and hardware support, as follows.

[0014] First single-bit arbitration interval: All devices send the first address bit (0) and the arbitration line remains low.

[0015] Second single-bit arbitration interval: All devices send the second address bit (0) and the arbitration line remains low.

[0016] Third single-bit arbitration interval: All devices send the third address bit (0) and the arbitration line remains low.

[0017] Fourth single-bit arbitration interval: All devices send the fourth address bit (1) and the arbitration line goes low.

[0018] Fifth single-bit arbitration interval: All devices send the fifth address bit (1) and the arbitration line remains low.

[0019] The sixth unit arbitration interval: Device A and Device B send the sixth address bit (0), Device C sends the sixth address bit (1), Device C detects that the arbitration line is at a high level, exits arbitration, and identifies through the trigger that it was Device C that triggered or other hardware circuits.

[0020] Seventh single-bit arbitration interval: Device A and Device B send the seventh address bit (1). The address bit sent by Device B is 1 and the arbitration line goes low.

[0021] The eighth unit arbitration interval: The address bit sent by device A is 0, and the address bit sent by device B is 1. Device B detects that the arbitration line is high, exits arbitration, and recognizes through the trigger that it is device B that triggers or other hardware circuits.

[0022] The arbitration link ends when the unit arbitration interval (arbitration selection line high level time > number of master devices * unit arbitration interval) is reached.

[0023] The arbitration line remains low, and device A wins. After another period of time, depending on the specific scenario, it can also be set to a unit arbitration interval to facilitate hardware redundancy design, or it can be shortened. For more efficient communication, device A pulls up the arbitration selection line.

[0024] Furthermore, after the master device is selected in the arbitration stage, the master device pulls up the arbitration line, and the steps for selecting the slave device are as follows: The M2S line sends the slave device address and waits for the slave device to respond.

[0025] Start condition: Arbitration select line is pulled low.

[0026] Send address: The master device sends an 8-bit address (0Xxx), and the M2S line transmits the address data.

[0027] Read / Write Bit: Send a 1-bit read / write bit, where 1 indicates a read operation and 0 indicates a write operation.

[0028] The operation time of the above two steps is: clock cycle / 2*number of slave devices.

[0029] The slave device sends 1 bit of data through the arbitration select line / master input slave output, where 1 means response and 0 means no response.

[0030] For the master device: Send data: The master device sends data (0Xxx), and the master output transmits data from the input line.

[0031] Receive data: The slave device sends data (0Xxx), the arbitration selection line / master input slave output transmits data.

[0032] Check bit: Send 1 check bit, where 1 means check and 0 means no check. Depending on the specific check method, the receiver can choose parity check, CRC cyclic redundancy check, Hamming code, etc.

[0033] For slave devices: Send data: Send data (0Xxx) from the device, AS / S2M transmits data.

[0034] Receive data: The master device sends data (0Xxx), and the M2S line transmits data.

[0035] Furthermore, it also includes the main mode: In master mode, the master device provides clock signals and frame synchronization signals, including arbitration start signal, arbitration end signal, communication start signal, communication end signal, etc.

[0036] Furthermore, it also includes slave mode: In slave mode, the slave device can only respond to triggers passively.

[0037] During the use of this communication protocol, a register is defined which contains the following two bits: DCSH (Datachange-samplingHigh).

[0038] DCSL (Data change-sampling low).

[0039] When DCSH=0, DCSL=0. Mode=0.

[0040] When DCSH=0, DCSL=1. Mode=1.

[0041] When DCSH=1, DCSL=0. Mode=2.

[0042] When DCSH=1, DCSL=1. Mode=3.

[0043] The clock polarity used to determine the communication mode can be changed by programming the master operation register.

[0044] This mode selects data to be broadcast to all devices on the line before selecting a slave device via the arbitration select line / master input to the slave output.

[0045] The high level is mode 0, the low level is mode 1, the rising edge is mode 2, and the falling edge is mode 3. The falling edge and low level are generated and finally pulled back to the high level. Therefore, the rising edge and falling edge are required to be greater than 3 / 8 clock cycle.

[0046] During the use of this communication protocol, a register is defined which contains the following two bits: DWH (Data Width High) DWL (Data Width Low) When DWH=0, DWL=0. DataWidth=8 bits.

[0047] When DWH=0, DWL=1, DataWidth=16 bits.

[0048] When DWH=1, DWL=0, DataWidth=32 bits.

[0049] When DWH=1, DWL=1. DataWidth=64 bits.

[0050] The data width of a frame during communication can be changed by programming the master device operation register.

[0051] 3. Beneficial effects: Compared with the prior art, the technical solution provided by the present invention has the following beneficial effects: The present invention provides a multi-master and multi-slave full-duplex communication protocol based on an arbitration selection single-line multiplexing mechanism, which improves communication efficiency. Through the arbitration selection / single-line multiplexing mechanism, bus contention is reduced, communication bandwidth is increased, system design is simplified, no complex hardware circuits are required, the design and implementation of the multi-master and multi-slave system are simplified, reliability is enhanced, and communication reliability and data accuracy are guaranteed through a multi-unit arbitration interval and a verification mechanism. Multi-modes are supported, multiple data transmission modes are provided, and different application requirements are adapted.

[0052] The present invention provides a multi-master and multi-slave full-duplex communication protocol based on arbitration selection single-line multiplexing mechanism, which effectively avoids conflicts between devices by adopting a mechanism in which the one with the smaller address wins, and ensures the priority determination of the device through a unique address. In a multi-master and multi-slave structure, this mechanism can ensure that each device has an equal opportunity to control the bus, greatly improving the flexibility and scalability of the system. At the same time, this cyclic scheduling mechanism avoids a single device occupying the bus for a long time, thereby improving the load balancing capability and resource utilization efficiency of the multi-device system. At the same time, the cyclic scheduling and task switching design of the protocol further optimizes the communication efficiency, ensuring that the tasks of each device can be completed as needed. The entire system shows high stability and reliability in high-concurrency scenarios, and can meet the communication needs of complex application scenarios.

[0053] The parts not involved in the device are the same as those in the prior art or can be implemented by using the prior art. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] Figure 1 It is a schematic diagram of mode 0 of the present invention; Figure 2 It is a schematic diagram of mode 1 of the present invention; Figure 3 It is a schematic diagram of mode 2 of the present invention; Figure 4 It is a schematic diagram of Mode 3 of the present invention; Figure 5 This is a schematic diagram of the arbitration falling edge + low level starting arbitration signal of the present invention; Figure 6 It is the operation flow chart of the present invention; Figure 7 It is a schematic diagram for explaining the data of the present invention. DETAILED DESCRIPTION

[0055] To facilitate understanding of the present invention, the present invention will be described more comprehensively below with reference to the relevant drawings. Several embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

[0056] It should be noted that when an element is referred to as being "fixed on" another element, it may be directly on the other element or there may also be a central element; when an element is considered to be "connected to" another element, it may be directly connected to the other element or there may also be a central element; the terms "vertical", "horizontal", "left", "right" and similar expressions used in this article are for illustrative purposes only.

[0057] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by technicians in the technical field to which the present invention belongs; the terms used in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention; the term "and / or" used herein includes any and all combinations of one or more related listed items. Example

[0058] Reference Figure 1-6 , a multi-master and multi-slave full-duplex communication protocol based on arbitration selection single-line multiplexing mechanism, comprising the following steps: In each communication cycle, the master device is dynamically determined through the arbitration selection line. The master device is responsible for controlling the global timing to ensure the order and effective transmission of the data stream, while the slave device responds according to the instructions of the master device, realizing a highly flexible master-slave role scheduling mechanism.

[0059] First, all devices conduct master-slave negotiation based on a bus. All devices that intend to control the clock send a message carrying the master device identifier. The device carrying the master device identifier participates in the bus competition. After successfully competing through the arbitration selection line, the same clock signal is broadcast to all devices in the line, waking up all slave devices and starting data communication.

[0060] The devices participating in the competition for the master device simultaneously send their own device addresses to the bus. Based on the principle of the smaller address wins, the winner of this round of arbitration selection line is selected and becomes the only master device in this round. The other master devices participating in the election are also converted into slave devices. The winner controls the subsequent clock line and sends command data to control different slave devices on the line. The slave device will give a corresponding response action after receiving the command.

[0061] After the previous round of communication ends, the loser of the previous round of master device competition in the bus starts a new round of master device competition, and the winner of the previous round withdraws from the master device competition and becomes a slave device. Then, the operations of steps 2 and 3 are implemented in a loop until all the devices participating in the first round of slave devices act as master devices and complete the "busy" cycle, that is, complete the task list of controlling the slave devices of their own devices. When all devices on the bus are in an idle state and no device controls the clock line, the communication is completely ended, and the next round of communication begins when a device continues to send a message containing the master device identifier to the bus.

[0062] The mechanism based on the smaller address wins effectively avoids conflicts between devices and ensures the priority of devices through unique addresses. In a multi-master and multi-slave structure, this mechanism can ensure that each device has an equal opportunity to control the bus, greatly improving the flexibility and scalability of the system. At the same time, this round-robin scheduling mechanism avoids a single device occupying the bus for a long time, thereby improving the load balancing capability and resource utilization efficiency of the multi-device system.

[0063] The protocol's cyclic scheduling and task switching design further optimizes communication efficiency, ensuring that each device's tasks can be completed as needed. The entire system exhibits high stability and reliability in high-concurrency scenarios and can meet the communication needs of complex application scenarios.

[0064] In this embodiment, the arbitration selection line is designed based on the timing of line XOR / modulo-2 operation. Multiple master devices send arbitration signals through the selection line. Each master device pulls the selection line low to initiate arbitration. The line XOR allows multiple master devices to send signals at the same time, and finally confirms which master device wins the arbitration.

[0065] The results of modulo-2 addition and modulo-2 subtraction in the modulo-2 operation are the same and consistent with the result of the XOR operation.

[0066] In this embodiment, all master devices compete, and the devices transmit addresses through arbitration selection lines. The arbitration selection lines are used for arbitration, with high bits first and the lower address being the master device. In this scenario, the last two digits of the address of the competing master device are required to be programmable addresses, that is, the maximum number of competing master devices that can be mounted is 4. In other scenarios, it can also be an n-bit programmable address, and the maximum number of competing master devices that can be mounted is 2. n A competitive master device - independently designed according to the application scenario.

[0067] In this embodiment, the unit arbitration interval in the arbitration selection line is determined according to a specific scenario and hardware support, as follows.

[0068] First single-bit arbitration interval: All devices send the first address bit (0) and the arbitration line remains low.

[0069] Second single-bit arbitration interval: All devices send the second address bit (0) and the arbitration line remains low.

[0070] Third single-bit arbitration interval: All devices send the third address bit (0) and the arbitration line remains low.

[0071] Fourth single-bit arbitration interval: All devices send the fourth address bit (1) and the arbitration line goes low.

[0072] Fifth single-bit arbitration interval: All devices send the fifth address bit (1) and the arbitration line remains low.

[0073] The sixth unit arbitration interval: Device A and Device B send the sixth address bit (0), Device C sends the sixth address bit (1), Device C detects that the arbitration line is at a high level, exits arbitration, and identifies through the trigger that it was Device C that triggered or other hardware circuits.

[0074] Seventh single-bit arbitration interval: Device A and Device B send the seventh address bit (1). The address bit sent by Device B is 1 and the arbitration line goes low.

[0075] The eighth unit arbitration interval: The address bit sent by device A is 0, and the address bit sent by device B is 1. Device B detects that the arbitration line is high, exits arbitration, and recognizes through the trigger that it is device B that triggers or other hardware circuits.

[0076] The arbitration link ends when the unit arbitration interval (arbitration selection line high level time > number of master devices * unit arbitration interval) is reached.

[0077] The arbitration line remains low, and device A wins. After another period of time, depending on the specific scenario, it can also be set to a unit arbitration interval to facilitate hardware redundancy design, or it can be shortened. For more efficient communication, device A pulls up the arbitration selection line.

[0078] In this embodiment, after the master device is selected in the arbitration stage, the master device pulls up the arbitration line, and the steps of selecting the slave device are as follows: The M2S line sends the slave device address and waits for the slave device to respond.

[0079] Start condition: Arbitration select line is pulled low.

[0080] Send address: The master device sends an 8-bit address (0Xxx), and the M2S line transmits the address data.

[0081] Read / Write Bit: Send a 1-bit read / write bit, where 1 indicates a read operation and 0 indicates a write operation.

[0082] The operation time of the above two steps is: clock cycle / 2*number of slave devices.

[0083] The slave device sends 1 bit of data through the arbitration selection line / master input slave output, where 1 means response and 0 means no response.

[0084] For the master device: Send data: The master device sends data (0Xxx), and the master output transmits data from the input line.

[0085] Receive data: The slave device sends data (0Xxx), the arbitration selection line / master input slave output transmits data.

[0086] Check bit: Send 1 check bit, where 1 means check and 0 means no check. Depending on the specific check method, the receiver can choose parity check, CRC cyclic redundancy check, Hamming code, etc.

[0087] For slave devices: Send data: Send data (0Xxx) from the device, AS / S2M transmits data.

[0088] Receive data: The master device sends data (0Xxx), and the M2S line transmits data.

[0089] In this embodiment, the main mode is also included: In master mode, the master device provides clock signals and frame synchronization signals, including arbitration start signal, arbitration end signal, communication start signal, communication end signal, etc.

[0090] In this embodiment, a slave mode is also included: In slave mode, the slave device can only respond to triggers passively.

[0091] During the use of this communication protocol, a register is defined which contains the following two bits: DCSH (Datachange-samplingHigh).

[0092] DCSL (Data change-sampling low).

[0093] When DCSH=0, DCSL=0. Mode=0.

[0094] When DCSH=0, DCSL=1. Mode=1.

[0095] When DCSH=1, DCSL=0. Mode=2.

[0096] When DCSH=1, DCSL=1. Mode=3.

[0097] The clock polarity used to determine the communication mode can be changed by programming the master operation register.

[0098] This mode selects data to be broadcast to all devices on the line before selecting a slave device via the arbitration select line / master input to the slave output.

[0099] The high level is mode 0, the low level is mode 1, the rising edge is mode 2, and the falling edge is mode 3. The falling edge and low level are generated and finally pulled back to the high level. Therefore, the rising edge and falling edge are required to be greater than 3 / 8 clock cycle.

[0100] During the use of this communication protocol, a register is defined which contains the following two bits: DWH (Data Width High) DWL (Data Width Low) When DWH=0, DWL=0. DataWidth=8 bits.

[0101] When DWH=0, DWL=1, DataWidth=16 bits.

[0102] When DWH=1, DWL=0, DataWidth=32 bits.

[0103] When DWH=1, DWL=1. DataWidth=64 bits.

[0104] The data width of a frame during communication can be changed by programming the master device operation register.

[0105] The above-described embodiments only express a certain implementation mode of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the patent scope of the present invention. It should be pointed out that, for ordinary technicians in this field, several modifications and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be based on the attached claims.

Claims

1. A multi-master and multi-slave full-duplex communication protocol based on arbitration selection single-line multiplexing mechanism, characterized in that: The steps include: In each communication cycle, the master device is dynamically determined through the arbitration selection line. The master device is responsible for controlling the global timing to ensure the order and effective transmission of the data stream, while the slave device responds according to the instructions of the master device, realizing a highly flexible master-slave role scheduling mechanism; First, all devices conduct master-slave negotiation based on a bus. All devices that intend to control the clock send a message with the master device ID. The device carrying the master device ID participates in the bus competition. After successfully competing through the arbitration selection line, it broadcasts the same clock signal to all devices in the line, wakes up all slave devices, and starts data communication. The devices participating in the competition for the master device simultaneously send their own device addresses to the bus. According to the principle of the smallest address wins, the winner of this round of arbitration selection line is selected and becomes the only master device in this round. The other master devices participating in the election are also converted into slave devices. The winner controls the subsequent clock line and sends command data to control different slave devices on the line. The slave device will give a corresponding response action after receiving the command; After the last round of communication ends, the loser of the master device competition in the last round in the bus starts a new round of master device competition, and the winner of the last round exits the master device competition and becomes a slave device, and then loops to implement the operations of step 2 and step 3 until all the devices participating in the first round of slave devices act as master devices and complete the "busy" cycle, that is, complete the task list of controlling the slave devices of their own devices. When all devices on the bus are in an idle state and no device controls the clock line, the communication is completely ended, and the next round of communication begins when a device continues to send a message containing the master device identifier to the bus; The mechanism based on the smaller address wins effectively avoids conflicts between devices and ensures the priority of devices through unique addresses. In a multi-master and multi-slave structure, this mechanism can ensure that each device has an equal opportunity to control the bus, greatly improving the flexibility and scalability of the system. At the same time, this round-robin scheduling mechanism avoids a single device occupying the bus for a long time, thereby improving the load balancing capability and resource utilization efficiency of the multi-device system.

2. The multi-master and multi-slave full-duplex communication protocol based on arbitration selection single-line multiplexing mechanism according to claim 1 is characterized in that: The arbitration selection line is designed based on the timing of line XOR / modulo 2 operation. Multiple master devices send arbitration signals through the selection line. Each master device pulls the selection line low to initiate arbitration. The line XOR allows multiple master devices to send signals at the same time, and finally confirms which master device wins the arbitration. The results of modulo-2 addition and modulo-2 subtraction in the modulo-2 operation are the same and consistent with the result of the XOR operation.

3. The multi-master and multi-slave full-duplex communication protocol based on arbitration selection single-line multiplexing mechanism according to claim 1 is characterized in that: All master devices compete, and the devices transmit addresses through the arbitration selection line. The arbitration selection line is used for arbitration, with the high bit first and the low address being the master device. In this scenario, the last two bits of the address of the competing master device are required to be programmable addresses, that is, the maximum number of competing master devices that can be mounted is 4. In other scenarios, it can also be an n-bit programmable address, and the maximum number of competing master devices that can be mounted is 2 n A competing master device - independently designed according to the application scenario.

4. The multi-master and multi-slave full-duplex communication protocol based on arbitration selection single-line multiplexing mechanism according to claim 1 is characterized in that: The unit arbitration interval in the arbitration selection line is determined according to the specific scenario and hardware support, as follows; First single-bit arbitration interval: All devices send the first address bit (0), and the arbitration line remains low; Second single-bit arbitration interval: All devices send the second address bit (0), and the arbitration line remains low; The third single-bit arbitration interval: All devices send the third address bit (0), and the arbitration line remains low; Fourth single-bit arbitration interval: All devices send the fourth address bit (1), and the arbitration line goes low; Fifth single-bit arbitration interval: All devices send the fifth address bit (1), and the arbitration line remains low; The sixth unit arbitration interval: Device A and Device B send the sixth address bit (0), Device C sends the sixth address bit (1), Device C detects that the arbitration line is at a high level, exits arbitration, and identifies through the trigger that it is Device C that triggers or other hardware circuits; Seventh single-bit arbitration interval: Device A and Device B send the seventh address bit (1). The address bit sent by Device B is 1, and the arbitration line becomes low. The eighth unit arbitration interval: the address bit sent by device A is 0, and the address bit sent by device B is 1. Device B detects that the arbitration line is at a high level, exits arbitration, and identifies through the trigger that it is device B that triggers or other hardware circuits; The arbitration link ends when the unit arbitration interval (arbitration selection line high level time > number of master devices * unit arbitration interval) is reached. The arbitration line remains at a low level, and device A wins; after a period of time, depending on the specific scenario, it can also be set to a unit arbitration interval to facilitate hardware redundancy design, or it can be shortened. For more efficient communication, device A pulls up the arbitration selection line.

5. The multi-master and multi-slave full-duplex communication protocol based on arbitration selection single-line multiplexing mechanism according to claim 1 is characterized in that: After the master device is selected in the arbitration stage, the master device pulls up the arbitration line, and the steps for selecting the slave device are as follows: The M2S line sends the slave device address and waits for the slave device to respond; Start condition: the arbitration selection line is pulled low; Send address: The master device sends an 8-bit address (0Xxx), and the M2S line transmits the address data; Read / Write bit: Send 1 read / write bit, where 1 indicates a read operation and 0 indicates a write operation; The operation time of the above two steps is: clock cycle / 2*number of slave devices; The slave device sends 1 bit of data through the arbitration selection line / master input slave output, where 1 means response and 0 means no response; For the master device: Send data: The master device sends data (0Xxx), and the master output transmits data from the input line; Receive data: The slave device sends data (0Xxx), the arbitration selection line / master input slave output transmits data; Check bit: Send 1 check bit, where 1 means check, and 0 means no check. Depending on the specific check method, the receiver can choose parity check, CRC cyclic redundancy check, Hamming code, etc. For slave devices: Send data: send data from the device (0Xxx), AS / S2M transmits data; Receive data: The master device sends data (0Xxx), and the M2S line transmits data.

6. The multi-master and multi-slave full-duplex communication protocol based on arbitration selection single-line multiplexing mechanism according to claim 1 is characterized in that: Also includes main mode: In master mode, the master device provides clock signals and frame synchronization signals, including arbitration start signal, arbitration end signal, communication start signal, communication end signal, etc.

7. The multi-master and multi-slave full-duplex communication protocol based on arbitration selection single-line multiplexing mechanism according to claim 1, characterized in that: Also includes slave mode: In slave mode, the slave device can only respond to triggers passively; During the use of this communication protocol, a register is defined which contains the following two bits: DCSH (Datachange-samplingHigh); DCSL (Datachange-samplingLow); When DCSH=0, DCSL=0; Mode=0; When DCSH=0, DCSL=1; Mode=1; When DCSH=1, DCSL=0; Mode=2; When DCSH=1, DCSL=1; Mode=3; The clock polarity can be changed by programming the master device operation register to determine the communication mode; This mode selects data to be broadcast to all devices in the line before selecting the slave device via the arbitration select line / master input slave output; The high level is mode 0, the low level is mode 1, the rising edge is mode 2, and the falling edge is mode 3. The falling edge and low level must be pulled back to the high level. Therefore, the rising edge and falling edge are required to be greater than 3 / 8 clock cycles; During the use of this communication protocol, a register is defined which contains the following two bits: DWH (Data Width High) DWL (Data Width Low) When DWH=0, DWL=0; DataWidth=8 bits; When DWH=0, DWL=1; DataWidth=16 bits; When DWH=1, DWL=0; DataWidth=32 bits; When DWH=1, DWL=1; DataWidth=64 bits; The data width of a frame during communication can be changed by programming the master device operation register.

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