Earphone driving circuit, calibration method and earphone

Abstract

The invention discloses an earphone driving circuit, a calibration method and an earphone, the earphone driving circuit comprises a biasing circuit, an operational amplifier circuit and an output circuit, the biasing circuit generates a bias voltage VPB and a bias voltage VNB through self-biasing; the input end of the operational amplifier circuit comprises a plurality of differential PMOS (P-channel Metal Oxide Semiconductor) tubes, the output end of the operational amplifier circuit comprises a plurality of pairs of load tubes and switch tubes, and the switch tubes are controlled by bias voltage VPB and bias voltage VNB; the input end of the output circuit is connected with the output end of the operational amplifier circuit, the output circuit comprises a power output branch and a calibration output branch, the power output branch and the calibration output branch are mutually independent, the power output branch comprises a plurality of power tubes, the calibration output branch comprises a plurality of calibration MOS tubes, grid electrodes of the power tubes are controlled by a power amplifier enabling PAEN switch, and the calibration MOS tubes are connected with the power amplifier enabling PAEN switch. And the grid electrode of the calibration MOS tube is controlled by the calibration enabling CALIEN switch. According to the invention, the voltage error value offset of the earphone audio system can be calibrated in real time, the harsh feeling caused by pop sound is eliminated, multiple times of non-inductive calibration are realized, and the user experience is improved.

Description

Technical Field

[0001] The present invention relates to the field of earphone driving technology, and in particular to an earphone driving circuit, a calibration method and an earphone. Background Art

[0002] In the headphone audio system, the signal playback path is generally composed of a DAC digital-to-analog converter and a headphone driver circuit, in which the headphone driver circuit usually uses a ClassAB operational amplifier to drive low-load headphones. Due to the high sensitivity of the headphones, a small voltage error value offset in the system will produce a large pop sound and be broadcast, which will give the headphone user a harsh feeling and a poor experience. Therefore, it is necessary to calibrate the output signal to eliminate the voltage error value offset and reduce the pop sound.

[0003] The current processing method is to calibrate in the final test stage, compare the voltage values ​​at both ends of the earphone, and adjust the input data of the DAC digital-to-analog converter to eliminate the voltage error value offset. If the voltage difference between the two ends of the earphone is less than the preset value, such as 500uV, the calibration value of the current DAC digital-to-analog converter is stored; when used subsequently, this calibration value is loaded first to eliminate the pop sound and achieve a better experience. However, in actual use, the voltage error value offset may be larger again as the working state of the circuit changes. If the earphone is calibrated again during use, the voltage value at both ends of the earphone needs to be continuously adjusted, which will cause continuous harsh pop sounds to the user, so it is impossible to calibrate again. Calibration can only be performed once in the final test stage, and multiple calibrations cannot be performed, let alone real-time calibration, so the flexibility and experience are relatively poor. Summary of the invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, the present invention proposes an earphone driving circuit, a calibration method and an earphone, which can calibrate the voltage error value offset of the earphone audio system in real time, eliminate the harsh feeling caused by the pop sound, realize multiple non-sensing calibration, and improve the user experience.

[0005] On the one hand, an embodiment of the present invention provides an earphone driving circuit, including a bias circuit, an operational amplifier circuit and an output circuit, wherein the bias circuit generates a bias voltage VPB and a bias voltage VNB through self-biasing; the input end of the operational amplifier circuit includes multiple differential PMOS tubes, and the output end of the operational amplifier circuit includes multiple pairs of load tubes and switch tubes, the load tubes are used to improve the output gain, and the switch tubes are controlled by the bias voltage VPB and the bias voltage VNB; the input end of the output circuit is connected to the output end of the operational amplifier circuit, the output circuit includes a power output branch and a calibration output branch, the power output branch and the calibration output branch are independent of each other, the power output branch includes multiple power tubes, the calibration output branch includes multiple calibration MOS tubes, the gate of the power tube is controlled by the power amplifier enable PA_EN switch, and the gate of the calibration MOS tube is controlled by the calibration enable CALI_EN switch to perform switch selection on the output branch.

[0006] According to some embodiments of the present invention, the bias circuit includes a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a first PMOS tube, a second PMOS tube, a third PMOS tube and a fourth PMOS tube, the drain of the first NMOS tube is connected to the source of the second NMOS tube, the drain of the third NMOS tube is connected to the source of the fourth NMOS tube, the gate and drain of the second PMOS tube are connected to the source of the first PMOS tube, the drain of the third PMOS tube is connected to the source of the fourth PMOS tube, the gate of the first NMOS tube is controlled by a bias voltage VBN1, the gate of the second NMOS tube is controlled by a bias voltage VBN2, the gate of the third PMOS tube is controlled by a bias voltage VBP1, and the gate of the fourth PMOS tube is controlled by a bias voltage VBP2.

[0007] According to some embodiments of the present invention, the differential PMOS transistor includes a fifth PMOS transistor and a sixth PMOS transistor, the gate of the fifth PMOS transistor is controlled by a differential output signal VIN, and the gate of the sixth PMOS transistor is controlled by a differential output signal VIP.

[0008] According to some embodiments of the present invention, the load tubes include multiple pairs of load NMOS tubes and multiple pairs of load PMOS tubes, the gates of each pair of load NMOS tubes are connected to each other, and the sources are connected to each other, and the gates of each pair of load PMOS tubes are connected to each other, and the sources are connected to each other, to form a folded common-gate and common-source structure.

[0009] According to some embodiments of the present invention, the switching tube includes a fifth NMOS tube, a sixth NMOS tube, a seventh PMOS tube and an eighth PMOS tube, the source of the fifth NMOS tube is connected to the drain of the seventh PMOS tube, the drain of the fifth NMOS tube is connected to the source of the seventh PMOS tube, the source of the sixth NMOS tube is connected to the drain of the eighth PMOS tube, the drain of the sixth NMOS tube is connected to the source of the eighth PMOS tube, the gates of the fifth NMOS tube and the sixth NMOS tube are controlled by the bias voltage VNB, and the gates of the seventh PMOS tube and the eighth PMOS tube are both controlled by the bias voltage VPB.

[0010] According to some embodiments of the present invention, the power output branch also includes a first capacitor and a second capacitor, the power tube includes a power PMOS tube and a power NMOS tube, the first plate of the first capacitor is connected to the gate of the power PMOS tube, the second plate of the first capacitor is connected to the drain of the power PMOS tube, the first plate of the second capacitor is connected to the gate of the power NMOS tube, and the second plate of the second capacitor is connected to the drain of the power NMOS tube.

[0011] According to some embodiments of the present invention, the calibration output branch also includes a third capacitor and a fourth capacitor, the calibration MOS tube includes a calibration PMOS tube and a calibration NMOS tube, the first plate of the third capacitor is connected to the gate of the calibration PMOS tube, the second plate of the third capacitor is connected to the drain of the calibration PMOS tube, the first plate of the fourth capacitor is connected to the gate of the calibration NMOS tube, and the second plate of the fourth capacitor is connected to the drain of the calibration NMOS tube.

[0012] According to some embodiments of the present invention, the number of the calibration MOS tubes is 1 / 20 to 1 / 10 of the number of the power tubes.

[0013] On the other hand, an embodiment of the present invention provides a headphone driving circuit calibration method, comprising: Open the audio playback path of the earphone, send the output signal of the DAC digital-to-analog converter to the earphone drive circuit module, and establish the common mode voltage VCMS; Pull the power amplifier enable PA_EN low to shut down the power output branch, so that the power amplifier output voltage VO_PA is suspended, and the power amplifier output voltage VO_PA is equal to the common mode voltage VCMS, so that the voltages at both ends of the earphone are consistent and in a mute state; Pull the calibration enable CALI_EN high to open the calibration branch, compare the calibration output voltage VO_CALI with the common mode voltage VCMS, and get the calibration comparison result; According to the calibration comparison result, the digital control bit of the DAC digital-to-analog converter is adjusted. If the calibration output voltage VO_CALI is greater than the common-mode voltage VCMS, the digital control bit of the DAC digital-to-analog converter is reduced to reduce the calibration output voltage VO_CALI; if the calibration output voltage VO_CALI is less than the common-mode voltage VCMS and the comparator outputs a low level, the digital control bit of the DAC digital-to-analog converter is increased to increase the calibration output voltage VO_CALI; If after adjusting the digital control bit of the DAC digital-to-analog converter, the output result is stably flipping between high and low levels, and the calibration output voltage VO_CALI is equal to or close to the common-mode voltage VCMS, the calibration is completed; After the calibration is completed, the current digital control bit is saved and switched to the power output branch.

[0014] On the other hand, an embodiment of the present invention provides an earphone, comprising the above-mentioned earphone driving circuit.

[0015] The embodiments of the present invention have at least the following beneficial effects: The headphone driving circuit provided by the present invention includes a bias circuit, an operational amplifier circuit and an output circuit, wherein the operational amplifier circuit includes a load tube and a switch tube, and the output circuit includes a power output branch and a calibration output branch. The bias circuit generates a bias voltage VPB and a bias voltage VNB, and the voltage values ​​of the bias voltage VPB and the bias voltage VNB are adjusted so that the linear resistance value of the switch tube changes, thereby changing the voltage value output to the power tube, thereby controlling the power tube; the load tube is a folded common-gate common-source structure to improve the output gain; the power output branch and the calibration output branch are independent of each other, and the power output branch and the calibration output branch respectively switch the output branch through the power amplifier enable PA_EN and the calibration enable CALI_EN. By setting an independent calibration output branch, the voltage error value offset of the headphone audio system can be calibrated in real time, the harsh feeling caused by the pop sound can be eliminated, multiple senseless calibrations can be achieved, and the user experience can be improved.

[0016] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which: Figure 1 is a schematic structural diagram of an earphone driving circuit according to an embodiment of the present invention; Figure 2 is a schematic structural diagram of a bias circuit of an earphone driving circuit according to an embodiment of the present invention; Figure 3 is a schematic structural diagram of an operational amplifier circuit of an earphone driving circuit according to an embodiment of the present invention; Figure 4 is a schematic structural diagram of an output circuit of an earphone driving circuit according to an embodiment of the present invention; Figure 5 is a schematic diagram of a headphone driver circuit calibration architecture according to an embodiment of the present invention; Figure 6 The figure is a flow chart of a headphone driving circuit calibration method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0018] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0019] In the description of the present invention, it should be understood that descriptions involving orientations, such as up, down, front, back, left, right, etc., and orientations or positional relationships indicated are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0020] In the description of the present invention, "several" means one or more, "multiple" means more than two, greater than, less than, and exceeding are understood as not including the number itself, and "above", "below", and "within" are understood as including the number itself. If there is a description of "first", "second", etc., it is only used for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0021] In the description of the present invention, unless otherwise clearly defined, words such as “set”, “install”, “connect” and “connected” should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above words in the present invention based on the specific content of the technical solution.

[0022] The technical solution of the present invention is described in detail below through the accompanying drawings and specific embodiments.

[0023] Please refer to Figures 1 to 4, this embodiment discloses a headphone driving circuit, including a bias circuit, an operational amplifier circuit and an output circuit. The bias circuit generates a bias voltage VPB and a bias voltage VNB through self-biasing; the input end of the operational amplifier circuit includes a plurality of differential PMOS tubes, the output end of the operational amplifier circuit includes a switch tube and a load tube, the switch tube is controlled by the bias voltage VPB and the bias voltage VNB, and the load tube is a folded common gate common source structure to improve the output gain; the input end of the output circuit is connected to the output end of the operational amplifier circuit, the output circuit includes a power output branch and a calibration output branch, the power output branch and the calibration output branch are independent of each other, the power output branch includes a plurality of power tubes, the calibration output branch includes a plurality of calibration MOS tubes, the gate of the power tube is controlled by the power amplifier enable PA_EN switch, and the gate of the calibration MOS tube is controlled by the calibration enable CALI_EN switch to perform switch selection on the output branch. The bias circuit generates bias voltage VPB and bias voltage VNB. By adjusting the voltage values ​​of bias voltage VPB and bias voltage VNB, the linear resistance value of the switch tube changes, and then the voltage value output to the power tube changes, thereby controlling the power tube; the load tube is a folded common-gate common-source structure to improve the output gain; the power output branch and the calibration output branch are independent of each other, and the power output branch and the calibration output branch respectively switch the output branch through the power amplifier enable PA_EN and the calibration enable CALI_EN. By setting an independent calibration output branch, the voltage error value offset of the headphone audio system can be calibrated in real time, eliminating the harsh feeling caused by the pop sound, achieving multiple senseless calibrations, and improving the user experience.

[0024] Please refer to Figure 2 The bias circuit includes a first NMOS tube NM1, a second NMOS tube NM2, a third NMOS tube NM3, a fourth NMOS tube NM4, a first PMOS tube PM1, a second PMOS tube PM2, a third PMOS tube PM3 and a fourth PMOS tube PM4. The drain of the first NMOS tube NM1 is connected to the source of the second NMOS tube NM2, the drain of the third NMOS tube NM3 is connected to the source of the fourth NMOS tube NM4, the gate and the drain of the second PMOS tube PM2 are connected to the source of the first PMOS tube PM1, the drain of the third PMOS tube PM3 is connected to the source of the fourth PMOS tube PM4, the gate of the first NMOS tube NM1 is controlled by a bias voltage VBN1, the gate of the second NMOS tube NM2 is controlled by a bias voltage VBN2, the gate of the third PMOS tube PM3 is controlled by a bias voltage VBP1, and the gate of the fourth PMOS tube PM4 is controlled by a bias voltage VBP2. The bias voltage signals of bias voltage VBP1, bias voltage VBP2, bias voltage VBN1, and bias voltage VBN2 come from a power module of a previous stage, and the bias current and bias voltage are generated by the power module.

[0025] Please refer to Figure 3 The differential PMOS tube includes a fifth PMOS tube PM5 and a sixth PMOS tube PM6. The gate of the fifth PMOS tube PM5 is controlled by the differential output signal VIN, and the gate of the sixth PMOS tube PM6 is controlled by the differential output signal VIP. The differential output signal VIP and the differential output signal VIN are inputs of the operational amplifier circuit and are connected to the differential output signal of the DAC digital-to-analog converter. The differential PMOS tube circuit amplifies the signal through two mutually coupled MOS tubes, only amplifies the differential signal, and suppresses the common mode signal, and has a strong anti-interference ability.

[0026] Please refer to Figure 3 The load tubes include multiple pairs of load NMOS tubes and multiple pairs of load PMOS tubes. The gates of each pair of load NMOS tubes are connected to each other and the sources are connected to each other. The gates of each pair of load PMOS tubes are connected to each other and the sources are connected to each other to form a folded common-gate common-source structure. The load tubes are of a folded common-gate common-source structure to improve the output gain.

[0027] Please refer to Figure 3 The switch tube includes a fifth NMOS tube NM5, a sixth NMOS tube NM6, a seventh PMOS tube PM7 and an eighth PMOS tube PM8, the source of the fifth NMOS tube NM5 is connected to the drain of the seventh PMOS tube PM7, the drain of the fifth NMOS tube NM5 is connected to the source of the seventh PMOS tube PM7, the source of the sixth NMOS tube NM6 is connected to the drain of the eighth PMOS tube PM8, the drain of the sixth NMOS tube NM6 is connected to the source of the eighth PMOS tube PM8, the gates of the fifth NMOS tube NM5 and the sixth NMOS tube NM6 are controlled by the bias voltage VNB, and the gates of the seventh PMOS tube PM7 and the eighth PMOS tube PM8 are both controlled by the bias voltage VPB.

[0028] Please refer to Figure 4 The power output branch also includes a first capacitor and a second capacitor, the power tube includes a power PMOS tube and a power NMOS tube, the first plate of the first capacitor is connected to the gate of the power PMOS tube, the second plate of the first capacitor is connected to the drain of the power PMOS tube, the first plate of the second capacitor is connected to the gate of the power NMOS tube, and the second plate of the second capacitor is connected to the drain of the power NMOS tube. The first capacitor and the second capacitor are compensation capacitors, and the phase margin of the operational amplifier circuit is compensated by the first capacitor and the second capacitor.

[0029] Please refer to Figure 4The calibration output branch also includes a third capacitor and a fourth capacitor, the calibration MOS tube includes a calibration PMOS tube and a calibration NMOS tube, the first plate of the third capacitor is connected to the gate of the calibration PMOS tube, the second plate of the third capacitor is connected to the drain of the calibration PMOS tube, the first plate of the fourth capacitor is connected to the gate of the calibration NMOS tube, and the second plate of the fourth capacitor is connected to the drain of the calibration NMOS tube. The third capacitor and the fourth capacitor are compensation capacitors, and the phase margin of the operational amplifier circuit is compensated by the third capacitor and the fourth capacitor.

[0030] Please refer to Figure 4 , the number of calibration MOS tubes is 1 / 20 ~ 1 / 10 of the number of power tubes. For example, if the number of power tubes is 200, the number of calibration MOS tubes is 20. The calibration MOS tube is used to achieve a working point that is completely mirrored with the power tube to ensure that the voltage error value offset of the power output branch and the calibration output branch is consistent. There are two output branches, one is a high-power tube that drives low-load headphones; the other is a low-power output stage that outputs calibration signals; when performing calibration work, turn off the last high-power driver tube, but do not turn off the audio signal working path. At this time, the calibration signal is output through the low-power tube, thereby realizing the real-time calibration function.

[0031] This embodiment further provides an earphone, comprising the above earphone driving circuit.

[0032] See also Figure 5The headphone driving circuit calibration architecture of this embodiment includes a ClassAB operational amplifier, an input resistor Rin, a feedback resistor Rf and a low-impedance headphone (for example, 16Ω or 32Ω). The ClassAB operational amplifier is a power amplifier, and its last-stage high-power tube is used to drive the low-impedance headphone; the input resistor Rin and the feedback resistor Rf constitute the amplification gain multiple of the system, where Av=2*Rf / Rin. The headphone driving circuit calibration architecture is provided with two output branches, a working branch and a calibration branch, wherein the working branch output drives the headphone load, and the calibration branch output is connected to the calibration circuit as a calibration reference voltage. In normal use, the high-power tube of the ClassAB operational amplifier outputs the power amplifier output voltage VO_PA signal, and the power amplifier enable PA_EN switch is closed, at which time the headphone is normally driven to play audio. If calibration is required, the high-power tube of the ClassAB operational amplifier is turned off, the calibration branch is turned on, and the calibration output voltage VO_CALI signal is output. At this time, the calibration output voltage CALI_EN switch is closed, and the calibration output voltage VO_CALI and the common mode voltage VCMS are sent to the comparator for error comparison, so that the calibration voltage error value offset value achieves the expected effect. The working branch and the calibration branch of the headset are completely independent. The working branch can be turned off at any time of use, and the calibration branch can be turned on for real-time calibration. After the calibration is completed, switch to the working branch and then play the audio. It has a real-time calibration function to improve flexibility and experience.

[0033] See also Figure 6 This embodiment also provides a headphone driving circuit calibration method, which mainly includes the following steps: S101, open the audio playback path of the headset, send the output signal of the DAC digital-to-analog converter to the headset driving circuit module, and establish the common mode voltage VCMS. First, initialize and power on to establish the normal working point of each module to ensure that the power supply voltage is normal; the headset enters the normal working stage, then open the audio playback path, and send the output signal of the DAC digital-to-analog converter to the headset driving circuit module.

[0034] S102, pull down the power amplifier enable PA_EN, turn off the power output branch, so that the power amplifier output voltage VO_PA is in a suspended state, and the power amplifier output voltage VO_PA is equal to the common mode voltage VCMS, so that the voltages at both ends of the earphone are consistent and in a mute state.

[0035] It should be noted that PA_EN, PA_ENB, CALI_EN and CALI_ENB are register-controlled signals, and their states can be controlled by software. The calibration-related registers are controlled by software to enter the calibration mode. PA_EN and PA_ENB are inverse signals of each other, that is, PA_ENB is the inverted signal of PA_EN. When PA_EN is pulled high, PA_ENB is pulled low. CALI_EN and CALI_ENB are inverse signals of each other, that is, CALI_ENB is the inverted signal of CALI_EN. When CALI_EN is pulled high, CALI_ENB is pulled low.

[0036] S103 , pull the calibration enable CALI_EN high, open the calibration branch, compare the calibration output voltage VO_CALI with the common mode voltage VCMS, and obtain a calibration comparison result.

[0037] S104. According to the calibration comparison result, the digital control bit of the DAC digital-to-analog converter is adjusted. If the calibration output voltage VO_CALI is greater than the common-mode voltage VCMS, the digital control bit of the DAC digital-to-analog converter is reduced to reduce the calibration output voltage VO_CALI. If the calibration output voltage VO_CALI is less than the common-mode voltage VCMS and the comparator outputs a low level, the digital control bit of the DAC digital-to-analog converter is increased to increase the calibration output voltage VO_CALI.

[0038] It should be noted that the digital control bit is generally a control unit of a register. When the calibration output voltage VO_CALI is greater than the common-mode voltage VCMS, the comparator outputs a high level, and at this time the digital control bit of the DAC digital-to-analog converter is reduced, so that the voltage value of the calibration output voltage VO_CALI is reduced; conversely, when the voltage value of the calibration output voltage VO_CALI is less than the common-mode voltage VCMS, the comparator outputs a low level, and at this time the digital control bit of the DAC digital-to-analog converter increases the voltage value of the calibration output voltage VO_CALI.

[0039] S105 , if after adjusting the digital control bit of the DAC digital-to-analog converter, the output result stably flips between high and low levels, the calibration output voltage VO_CALI is equal to or close to the common mode voltage VCMS, and the calibration is completed.

[0040] S106: After the calibration is completed, save the current digital control bit and switch to the power output branch.

[0041] If the pop sound when the earphones are turned on and off becomes louder due to the change in the voltage error value offsett during use, calibration can be repeated to achieve the real-time calibration function and achieve a good listening experience.

[0042] The embodiments of the present invention are described in detail above with reference to the accompanying drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge scope of ordinary technicians in the relevant technical field without departing from the purpose of the present invention.

Claims

1. An earphone driving circuit, characterized in that: include: A bias circuit, wherein the bias circuit generates a bias voltage VPB and a bias voltage VNB by self-biasing; An operational amplifier circuit, wherein the input end of the operational amplifier circuit includes a plurality of differential PMOS tubes, and the output end of the operational amplifier circuit includes a switch tube and a load tube, wherein the switch tube is controlled by the bias voltage VPB and the bias voltage VNB, and the load tube is a folded common-gate common-source structure to improve the output gain; An output circuit, wherein the input end of the output circuit is connected to the output end of the operational amplifier circuit, the output circuit comprises a power output branch and a calibration output branch, the power output branch and the calibration output branch are independent of each other, the power output branch comprises a plurality of power tubes, the calibration output branch comprises a plurality of calibration MOS tubes, the gates of the power tubes are controlled by a power amplifier enable PA_EN switch, and the gates of the calibration MOS tubes are controlled by a calibration enable CALI_EN switch, so as to perform switch selection on the output branch.

2. The earphone driving circuit according to claim 1, characterized in that: The bias circuit includes a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a first PMOS tube, a second PMOS tube, a third PMOS tube and a fourth PMOS tube. The drain of the first NMOS tube is connected to the source of the second NMOS tube, the drain of the third NMOS tube is connected to the source of the fourth NMOS tube, the gate and drain of the second PMOS tube are connected to the source of the first PMOS tube, the drain of the third PMOS tube is connected to the source of the fourth PMOS tube, the gate of the first NMOS tube is controlled by a bias voltage VBN1, the gate of the second NMOS tube is controlled by a bias voltage VBN2, the gate of the third PMOS tube is controlled by a bias voltage VBP1, and the gate of the fourth PMOS tube is controlled by a bias voltage VBP2.

3. The earphone driving circuit according to claim 1, characterized in that: The differential PMOS transistor includes a fifth PMOS transistor and a sixth PMOS transistor, a gate of the fifth PMOS transistor is controlled by a differential output signal VIN, and a gate of the sixth PMOS transistor is controlled by a differential output signal VIP.

4. The earphone driving circuit according to claim 3, characterized in that: The load tubes include multiple pairs of load NMOS tubes and multiple pairs of load PMOS tubes, the gates of each pair of load NMOS tubes are connected to each other, and the sources are connected to each other, and the gates of each pair of load PMOS tubes are connected to each other, and the sources are connected to each other, to form a folded common-gate common-source structure.

5. The earphone driving circuit according to claim 1 or 4, characterized in that: The switch tube includes a fifth NMOS tube, a sixth NMOS tube, a seventh PMOS tube and an eighth PMOS tube, the source of the fifth NMOS tube is connected to the drain of the seventh PMOS tube, the drain of the fifth NMOS tube is connected to the source of the seventh PMOS tube, the source of the sixth NMOS tube is connected to the drain of the eighth PMOS tube, the drain of the sixth NMOS tube is connected to the source of the eighth PMOS tube, the gates of the fifth NMOS tube and the sixth NMOS tube are controlled by the bias voltage VNB, and the gates of the seventh PMOS tube and the eighth PMOS tube are both controlled by the bias voltage VPB.

6. The earphone driving circuit according to claim 1, characterized in that: The power output branch also includes a first capacitor and a second capacitor, the power tube includes a power PMOS tube and a power NMOS tube, the first plate of the first capacitor is connected to the gate of the power PMOS tube, the second plate of the first capacitor is connected to the drain of the power PMOS tube, the first plate of the second capacitor is connected to the gate of the power NMOS tube, and the second plate of the second capacitor is connected to the drain of the power NMOS tube.

7. The earphone driving circuit according to claim 1 or 6, characterized in that: The calibration output branch also includes a third capacitor and a fourth capacitor, the calibration MOS tube includes a calibration PMOS tube and a calibration NMOS tube, the first plate of the third capacitor is connected to the gate of the calibration PMOS tube, the second plate of the third capacitor is connected to the drain of the calibration PMOS tube, the first plate of the fourth capacitor is connected to the gate of the calibration NMOS tube, and the second plate of the fourth capacitor is connected to the drain of the calibration NMOS tube.

8. The earphone driving circuit according to claim 1, characterized in that: The number of the calibration MOS tubes is 1 / 20 to 1 / 10 of the number of the power tubes.

9. A method for calibrating an earphone driving circuit, characterized in that: The earphone driving circuit according to any one of claims 1 to 8 comprises: Open the audio playback path of the earphone, send the output signal of the DAC digital-to-analog converter to the earphone drive circuit module, and establish the common mode voltage VCMS; Pull the power amplifier enable PA_EN low, turn off the power output branch, and make the power amplifier output voltage VO_PA suspended. The power amplifier output voltage VO_PA is equal to the common mode voltage VCMS, so that the voltages at both ends of the earphone are consistent and in a mute state. Pull the calibration enable CALI_EN high to open the calibration branch, compare the calibration output voltage VO_CALI with the common mode voltage VCMS, and get the calibration comparison result; According to the calibration comparison result, the digital control bit of the DAC digital-to-analog converter is adjusted. If the calibration output voltage VO_CALI is greater than the common-mode voltage VCMS, the digital control bit of the DAC digital-to-analog converter is reduced to reduce the calibration output voltage VO_CALI; if the calibration output voltage VO_CALI is less than the common-mode voltage VCMS and the comparator outputs a low level, the digital control bit of the DAC digital-to-analog converter is increased to increase the calibration output voltage VO_CALI; If after adjusting the digital control bit of the DAC digital-to-analog converter, the output result is stably flipping between high and low levels, and the calibration output voltage VO_CALI is equal to or close to the common-mode voltage VCMS, the calibration is completed; After the calibration is completed, the current digital control bit is saved and switched to the power output branch.

10. A headset, characterized in that: The earphone driving circuit comprises the earphone driving circuit according to any one of claims 1 to 8.

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