Semiconductor device

Abstract

A semiconductor device may include a substrate including a first active region defined by a first device isolation layer; a bit line contact disposed on the first active region of the substrate; and a bit line extending in a first direction on the substrate. The bit line includes: a lower conductive layer disposed on the substrate and on a sidewall of the bit line contact; and a metal line stack disposed on the lower conductive layer. The metal line stack includes: a first conductive layer disposed on the lower conductive layer and the bit line contact and including a first metal material; a first intermediate layer disposed on the first conductive layer and including graphene; and a second conductive layer disposed on the first intermediate layer and including a first metal material.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on and claims the priority of Korean Patent Application No. 10-2023-0128483 filed in the Korean Intellectual Property Office on September 25, 2023, and the entire contents of the above application are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a semiconductor device, and more particularly, to a semiconductor device including a bit line. Background Art

[0004] As semiconductor devices are scaled down, the size of each microcircuit pattern used to implement the semiconductor device is further reduced. In addition, as integrated circuit devices become more highly integrated, the line width of the bit line may be reduced, and the interval (or pitch) between the bit lines may be reduced. Therefore, there is a problem that defects may occur in the formation process of the bit line with a reduced line width. Summary of the invention

[0005] The present disclosure relates to a semiconductor device and a method of forming the same, in which defects occurring in a process of forming a bit line having a reduced line width are reduced or prevented.

[0006] According to some aspects of the present invention, a semiconductor device is provided, comprising: a substrate including a first active region defined by a first device isolation layer; a bit line contact arranged on the first active region of the substrate; and a bit line extending along a first direction on the substrate. The bit line comprises: a lower conductive layer arranged on the substrate and on a sidewall of the bit line contact; and a metal line stack arranged on the lower conductive layer. The metal line stack comprises: a first conductive layer arranged on the lower conductive layer and the bit line contact and comprising a first metal material; a first intermediate layer arranged on the first conductive layer and comprising graphene; and a second conductive layer arranged on the first intermediate layer and comprising the first metal material.

[0007] According to some aspects of the present invention, there is provided a semiconductor device, comprising: a substrate, comprising a first active region defined by a first device isolation layer and a second active region defined by a second device isolation layer; a bit line contact, arranged on the first active region of the substrate; a bit line, extending along a first direction on the substrate; and a peripheral circuit gate stack, arranged on the second active region. The bit line comprises: a lower conductive layer, arranged on the substrate and on a sidewall of the bit line contact; and a metal line stack, arranged on the lower conductive layer. The metal line stack comprises: a first conductive layer, arranged on the lower conductive layer and the bit line contact and comprising a first metal material; a first intermediate layer, arranged on the first conductive layer and comprising graphene; and a second conductive layer, arranged on the first intermediate layer and comprising a first metal material.

[0008] According to some aspects of the present invention, a semiconductor device is provided, comprising: a substrate, comprising a first active region defined by a first device isolation layer; a bit line contact, arranged in a bit line contact hole extending to the substrate, the bit line contact connected to the first active region of the substrate; a bit line, extending along a first direction on the substrate, the bit line comprising: a lower conductive layer, arranged on the substrate, on a sidewall of the bit line contact, and extending in the first direction; a metal silicide layer, arranged on the lower conductive layer and extending in the first direction; and a metal line stack, arranged on the metal silicide layer, extending in the first direction, the metal line stack comprising a first conductive layer, a second conductive layer and a first intermediate layer, wherein the first conductive layer comprises a first metal material, the second conductive layer comprises a first metal material, and the first intermediate layer is between the first conductive layer and the second conductive layer and comprises graphene. The semiconductor device further comprises: a bit line spacer, arranged on the sidewall of the bit line and extending in the first direction; and a word line, arranged in a word line trench extending along a second direction intersecting the first direction, the word line trench intersecting the first active region in the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a layout diagram showing a semiconductor device according to some embodiments;

[0011] Figure 2 yes Figure 1 An enlarged layout diagram of Part II;

[0012] Figure 3 It is along Figure 2 A cross-sectional view taken along line AA';

[0013] Figure 4 It is along Figure 2 A cross-sectional view taken along line BB';

[0014] Figure 5 It is along Figure 2 A cross-sectional view taken along line CC';

[0015] Figure 6 yes Figure 3 A magnified view of a portion of CX1;

[0016] Figure 7 and Figure 8 is a cross-sectional view showing a semiconductor device according to some embodiments;

[0017] Fig. 9 and Fig.10 is a cross-sectional view showing a semiconductor device according to some embodiments;

[0018] Fig.11 and Fig.12 is a cross-sectional view showing a semiconductor device according to some embodiments;

[0019] Fig.13A , Fig. 13B , Fig.14A , Fig. 14B , Fig.15A , Fig. 15B , Fig.16A , Fig. 16B , Fig.17A , Fig. 17B , Fig.18A , Fig.18B , Fig.19A , Fig.19B , Fig. 20A , Fig. 20B , Fig.21A , Fig.21B , Fig.22A and Fig. 22B is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to some embodiments;

[0020] Fig.23 is a diagram showing X-ray photoelectron spectroscopy measurement results of a metal wire stack according to some embodiments;

[0021] Fig.24 is a diagram showing a Raman spectrum of a metal wire stack according to some embodiments;

[0022] Fig.25 is a graph showing roughness changes of a metal line according to a comparative example and a metal line stack according to some embodiments before and after annealing; and

[0023] Fig.26 is a graph showing resistivity changes of a metal line according to a comparative example and a metal line stack according to some embodiments before and after annealing. DETAILED DESCRIPTION

[0024] Hereinafter, some examples of embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

[0025] Figure 1 is a layout diagram illustrating a semiconductor device 100 according to some embodiments. Figure 2 yes Figure 1 An enlarged layout diagram of part II. Figure 3 It is along Figure 2 A cross-sectional view taken along line AA'. Figure 4 It is along Figure 2 A cross-sectional view taken along line BB'. Figure 5 It is along Figure 2 A cross-sectional view taken along line CC'. Figure 6 yes Figure 3 An enlarged view of a portion of CX1.

[0026] Reference Figures 1 to 6 , the semiconductor device 100 may include a substrate 110, the substrate 110 includes a cell array area MCA and a peripheral circuit area PCA. The cell array area MCA may include a memory cell area of ​​a dynamic random access memory (DRAM) device, and the peripheral circuit area PCA may include a core area or a peripheral circuit area of ​​the DRAM device. For example, the cell array area MCA may include a cell transistor and a capacitor structure CAP connected thereto, and the peripheral circuit area PCA may include a peripheral circuit transistor PTR, and the peripheral circuit transistor PTR is configured to transmit signals and / or power to the cell transistor included in the cell array area MCA. In some embodiments, the peripheral circuit transistor PTR may constitute various circuits, such as a command decoder, a control logic, an address buffer, a row decoder, a column decoder, a sense amplifier, and / or a data input / output circuit.

[0027] A device isolation trench 112T may be formed in the substrate 110, and a first device isolation layer 112 and a second device isolation layer 112P may be formed in the device isolation trench 112T. A plurality of first active regions AC1 may be defined in the cell array region MCA of the substrate 110 by the first device isolation layer 112, and a plurality of second active regions AC2 may be defined in the peripheral circuit region PCA by the second device isolation layer 112P.

[0028] like Figure 2 As shown, in the cell array area MCA, each of the plurality of first active regions AC1 may be arranged to have a longitudinal axis in a first diagonal direction D1 that is inclined or angled relative to the first horizontal direction X and the second horizontal direction Y. A plurality of word lines WL may extend parallel to each other in the first horizontal direction X across the plurality of first active regions AC1. On the plurality of word lines WL, a plurality of bit lines BL may extend parallel to each other in the second horizontal direction Y. Each of the plurality of bit lines BL may be connected to the plurality of first active regions AC1 through a plurality of bit line contacts DC.

[0029] A plurality of buried contacts BC may each be formed between every two adjacent bit lines BL among the plurality of bit lines BL. A plurality of landing pads LP may be respectively formed on the plurality of buried contacts BC. The plurality of buried contacts BC and the plurality of landing pads LP may connect the lower electrodes 182 of the plurality of capacitor structures CAP formed on the plurality of bit lines BL to the plurality of first active regions AC1. The plurality of landing pads LP may partially overlap the plurality of buried contacts BC and the plurality of bit lines BL, respectively.

[0030] The substrate 110 may include silicon (Si), for example, single crystal Si, polycrystalline Si, or amorphous Si. In some embodiments, the substrate 110 may include at least one selected from germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). In some embodiments, the substrate 110 may include a conductive region, for example, a well doped with an impurity or a structure doped with an impurity.

[0031] The first device isolation layer 112 may include an oxide layer, a nitride layer, or a combination thereof. The first buffer insulating layer 114 and the second buffer insulating layer 116 may be sequentially disposed on the top surface of the substrate 110. Each of the first buffer insulating layer 114 and the second buffer insulating layer 116 may include silicon oxide, silicon oxynitride, or silicon nitride.

[0032] A plurality of word line trenches 120T may extend in the first horizontal direction X and may be arranged in the substrate 110, and a buried gate structure 120 may be arranged in the plurality of word line trenches 120T. The buried gate structure 120 may include a gate dielectric layer 122, a gate electrode 124, and a word line capping layer 126 arranged in each of the plurality of word line trenches 120T. The plurality of gate electrodes 124 may correspond to Figure 2 Multiple word lines WL are shown.

[0033] The plurality of gate dielectric layers 122 may include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, an oxide / nitride / oxide (ONO) layer, or a high-k dielectric layer having a higher dielectric constant than a silicon oxide layer. The plurality of gate electrodes 124 may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), titanium silicon nitride (TiSiN), tungsten silicon nitride (WSiN), or a combination thereof. The plurality of word line capping layers 126 may include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a combination thereof.

[0034] A plurality of bit line contact holes DCH may extend into the substrate 110 through the first buffer insulating layer 114 and the second buffer insulating layer 116, and a plurality of bit line contacts DC may be formed in the plurality of bit line contact holes DCH. The plurality of bit line contacts DC may be connected to the plurality of first active regions AC1, respectively. The plurality of bit line contacts DC may include TiN, TiSiN, W, tungsten silicide, doped polysilicon, or a combination thereof. A plurality of bit line contact spacers DCS may cover the lower sides of the plurality of bit line contacts DC in the plurality of bit line contact holes DCH, respectively.

[0035] The plurality of bit lines BL may extend long on the substrate 110 and the plurality of bit line contacts DC in the second horizontal direction Y. The plurality of bit lines BL may be connected to the plurality of first active regions AC1 through the plurality of bit line contacts DC, respectively.

[0036] Each of the plurality of bit lines BL may include a lower conductive layer 132 , a metal silicide layer 134 , and a metal line stack 136 .

[0037] The lower conductive layer 132 may extend along the second horizontal direction Y on the second buffer insulating layer 116 and may cover both sidewalls of the bit line contact DC. Figure 4 As shown, the top surface of the lower conductive layer 132 may be coplanar with the top surface of the bit line contact DC, and both sidewalls of the bit line contact DC may contact the lower conductive layer 132. The lower conductive layer 132 may include Si, Ge, W, WN, cobalt (Co), nickel (Ni), aluminum (Al), molybdenum (Mo), ruthenium (Ru), Ti, TiN, Ta, TaN or copper (Cu), or a combination of two or more thereof.

[0038] In some embodiments, in the process of forming the bit line contact hole DCH, a portion of the lower conductive layer 132, a portion of the second buffer insulating layer 116, a portion of the first buffer insulating layer 114, and a portion of the substrate 110 may be removed, and a bit line contact DC may be formed in the bit line contact hole DCH. Therefore, the upper side of the bit line contact DC may contact the lower conductive layer 132, and the lower side of the bit line contact DC may contact the substrate 110 (e.g., the first active region AC1).

[0039] The metal silicide layer 134 may be disposed on the top surface of the lower conductive layer 132 and on the top surface of the bit line contact DC to extend in the second horizontal direction Y. In some embodiments, the lower conductive layer 132 may include polysilicon, and the metal silicide layer 134 may include at least one of cobalt silicide, nickel silicide, and tungsten silicide. In some embodiments, optionally, at least one conductive barrier layer of Ti, TiN, and / or TaN may be further disposed on the metal silicide layer 134.

[0040] Metal line stack 136 may include first conductive layer 136A, first intermediate layer 138A, and second conductive layer 136B sequentially disposed on metal silicide layer 134. For example, metal line stack 136 may have a structure in which first intermediate layer 138A is sandwiched between first conductive layer 136A and second conductive layer 136B.

[0041] In some embodiments, the first conductive layer 136A may include a first metal material, and the first metal material may include at least one of Ru, Mo, rhodium (Ro), iridium (Ir), and alloys of one or more thereof. In some embodiments, the first conductive layer 136A may include Ru.

[0042] In some embodiments, the first intermediate layer 138A may include graphene. In an embodiment, the graphene constituting the first intermediate layer 138A may include a plurality of grains having a two-dimensional structure. For example, each grain of the first intermediate layer 138A may have a two-dimensional structure in which 1 to 15 layers of carbon two-dimensional sheets are stacked layer by layer. In some embodiments, the first intermediate layer 138A may have a nanocrystalline structure, and the plurality of grains may have a grain size of about 2 nm to about 200 nm. In some embodiments, the first intermediate layer 138A may have an average grain size of 10 nm or more.

[0043] In some embodiments, the first intermediate layer 138A may include graphene including carbon atoms having a ratio of 50% or more and 99% or less of all carbon atoms in terms of binding energy of carbon atoms included in the graphene. The binding energy of the carbon atoms included in the first intermediate layer 138A may be measured by using an analysis device such as X-ray photoelectron spectroscopy (XPS).

[0044] In some embodiments, when measured by Raman spectroscopy, the first intermediate layer 138A may exhibit a D peak, a 2D peak, a D' peak, and a G peak of carbon atoms, a ratio of the D peak to the G peak of carbon atoms may be 3.0 or less, a ratio of the 2D peak to the G peak may be 0.1 or more, and a ratio of the D' peak to the G peak may be 1.0 or less. Here, the G peak may correspond to about 1580 The Raman shift value of the D peak can correspond to about 1350 The Raman shift value of the 2D peak can correspond to about 2700 The Raman shift value.

[0045] In some embodiments, the second conductive layer 136B may include a first metal material, and the first metal material may include at least one of Ru, Mo, rhodium (Ro), iridium (Ir), and alloys of one or more thereof. In some embodiments, the second conductive layer 136B may include Ru.

[0046] In some embodiments, first intermediate layer 138A may be between first conductive layer 136A and second conductive layer 136B and may function as an anti-agglomeration layer that suppresses agglomeration or merging of grains of the first metal material included in first conductive layer 136A and second conductive layer 136B.

[0047] For example, in the case of the bit line BL including a single layer of metal material (such as Ru) according to the comparative example, when the bit line BL has a reduced line width (for example, a relatively small line width, such as a line width of less than 10 nm), the metal material (such as Ru) included in the bit line BL may cause grain agglomeration or grain merging in a subsequent high temperature process. The bit line BL according to the comparative example is formed as a line pattern extending in the second horizontal direction Y, but after undergoing a subsequent high temperature process, the line width of a portion of the bit line BL may be locally increased due to grain agglomeration, so that the line width of another portion of the bit line BL may be locally reduced or a region where the bit line BL is discontinuously disconnected may be formed.

[0048] However, in some embodiments according to the present disclosure, the first intermediate layer 138A may be between the first conductive layer 136A and the second conductive layer 136B to serve as an anti-agglomeration layer that suppresses agglomeration or merging of grains of the first metal material included in the first conductive layer 136A and the second conductive layer 136B. Therefore, although the bit line BL has a reduced line width (e.g., a relatively small line width), agglomeration of grains of the first metal material included in the first conductive layer 136A and the second conductive layer 136B may be prevented.

[0049] In an embodiment, the metal line stack 136 may have a first thickness t10 in the vertical direction Z. The first conductive layer 136A may have a second thickness t11 in the vertical direction Z, the first intermediate layer 138A may have a third thickness t12 in the vertical direction Z, and the second conductive layer 136B may have a fourth thickness t13 in the vertical direction Z. The second thickness t11 of the first conductive layer 136A may correspond to about 20% to about 80% of the first thickness t10 of the metal line stack 136 in the vertical direction Z. The fourth thickness t13 of the second conductive layer 136B may correspond to about 20% to about 80% of the first thickness t10 of the metal line stack 136 in the vertical direction Z.

[0050] The third thickness t12 of the first intermediate layer 138A may correspond to about 5% to about 50% of the first thickness t10 of the metal wire stack 136 in the vertical direction Z. For example, when the third thickness t12 of the first intermediate layer 138A is less than 5% of the first thickness t10 of the metal wire stack 136, the thickness of the first intermediate layer 138A may be insufficient to perform the grain agglomeration suppression function, and when the third thickness t12 of the first intermediate layer 138A is greater than 50% of the first thickness t10, the resistivity of the entire metal wire stack 136 may increase, so that the electrical performance of the semiconductor device 100 may be degraded. In some embodiments, the third thickness t12 of the first intermediate layer 138A may be 50 angstroms or less. In some embodiments, the third thickness t12 of the first intermediate layer 138A may be 5 angstroms or more. In some embodiments, the third thickness t12 of the first intermediate layer 138A may be in the range of about 5 angstroms to 50 angstroms.

[0051] A plurality of bit line capping layers 140 may be disposed on the plurality of bit lines BL, respectively. Each of the plurality of bit line capping layers 140 may include a first capping layer 142, a second capping layer 144, and a third capping layer 146 sequentially disposed on a top surface of each of the plurality of bit lines BL. The first capping layer 142, the second capping layer 144, and the third capping layer 146 may include at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0052] The bit line spacer 150 may be arranged on both sidewalls of each of the plurality of bit lines BL. The bit line spacer 150 may include a first spacer layer 152, a second spacer layer 154, and a third spacer layer 156. In some embodiments, the first spacer layer 152 and the third spacer layer 156 may include silicon nitride, and the second spacer layer 154 may include silicon oxide. The first spacer layer 152, the second spacer layer 154, and the third spacer layer 156 may be sequentially arranged on the sidewalls of the bit line BL and the sidewalls of the bit line capping layer 140.

[0053] For example, since the bit line spacer 150 is arranged on the sidewall of the bit line BL, the first spacer layer 152 of the bit line spacer 150 may contact the metal line stack 136 of the bit line BL, for example, the first spacer layer 152 may extend along the sidewalls of the first conductive layer 136A, the first intermediate layer 138A, and the second conductive layer 136B of the metal line stack 136 in the vertical direction Z. The bit line spacer 150 may contact the sidewall of the lower conductive layer 132 and the sidewall of the metal line stack 136. The sidewall of the first intermediate layer 138A may contact the bit line spacer 150.

[0054] The plurality of buried contacts BC may each be arranged between every two adjacent bit lines BL among the plurality of bit lines BL. For example, the bottom of each of the plurality of buried contacts BC may be arranged in a buried contact hole BCH extending into the substrate 110 between two adjacent bit lines BL and may contact the first active region AC1. In an embodiment, the plurality of buried contacts BC may include doped polysilicon.

[0055] A plurality of insulating fences (not shown) may be arranged between two adjacent bit lines BL along the second horizontal direction Y. The plurality of insulating fences may be arranged at positions vertically overlapping with the plurality of word line trenches 120T. In a plan view, each of the plurality of buried contacts BC and each of the plurality of insulating fences may be alternately arranged between two bit lines BL extending along the second horizontal direction Y.

[0056] A plurality of landing pads LP may be arranged on a plurality of buried contacts BC, respectively. Each of the plurality of landing pads LP may include a conductive barrier layer (not shown) and a landing pad conductive layer (not shown). The conductive barrier layer may include Ti or TiN or a combination thereof. The landing pad conductive layer may include a metal, a metal nitride or a conductive polysilicon or a combination of two or more thereof. For example, the landing pad conductive layer may include W. The plurality of landing pads LP may have a plurality of island pattern shapes in a plan view.

[0057] The plurality of landing pads LP may be electrically insulated from each other by the insulating pattern 160 surrounding the plurality of landing pads LP. The insulating pattern 160 may include at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0058] The etch stop layer 180 may be disposed on the insulating pattern 160 , and the etch stop layer 180 may include openings 180H, respectively. The openings 180H may be disposed at positions corresponding to the plurality of landing pads LP, and top surfaces of the plurality of landing pads LP may be disposed on bottoms of the openings 180H.

[0059] The capacitor structure CAP may be arranged on each etch stop layer 180. The capacitor structure CAP may include a lower electrode 182, a capacitor dielectric layer 184, and an upper electrode 186. The bottom of the lower electrode 182 may be arranged in the opening 180H of the etch stop layer 180 so that the bottom of the lower electrode 182 is provided on the landing pad LP. The capacitor dielectric layer 184 may be arranged to be relatively thin to cover and conform to the lower electrode 182, and the upper electrode 186 may be arranged on the capacitor dielectric layer 184.

[0060] The peripheral circuit transistor PTR may be disposed on the second active area AC2 in the peripheral circuit area PCA. The peripheral circuit transistor PTR may include a gate dielectric layer 118, a peripheral circuit gate stack PGS, and a gate capping pattern 142P sequentially stacked on the second active area AC2.

[0061] The gate dielectric layer 118 may be arranged on the top surface of the substrate 110. The gate dielectric layer 118 may include at least one selected from a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, an oxide / nitride / oxide (ONO) layer, and a high-k dielectric layer having a higher dielectric constant than the silicon oxide layer. The gate cap pattern 142P may be arranged to cover the top surface of the peripheral circuit gate stack PGS. In an embodiment, the gate cap pattern 142P may include a silicon nitride layer.

[0062] The peripheral circuit gate stack PGS may include a peripheral lower conductive layer 132P, a peripheral metal silicide layer 134P, and a peripheral metal line stack 136P.

[0063] The peripheral lower conductive layer 132P may be disposed on the gate dielectric layer 118 and may include Si, Ge, W, WN, Co, Ni, Al, Mo, Ru, Ti, TiN, Ta, TaN, or Cu or a combination of two or more thereof. The peripheral metal silicide layer 134P may be disposed on the top surface of the peripheral lower conductive layer 132P. In some embodiments, the peripheral metal silicide layer 134P may include at least one of cobalt silicide, nickel silicide, and tungsten silicide. In some embodiments, optionally, at least one conductive barrier layer of Ti, TiN, and / or TaN may be further disposed on the peripheral metal silicide layer 134P.

[0064] The peripheral metal line stack 136P may include a first peripheral conductive layer 136AP, a first peripheral intermediate layer 138AP, and a second peripheral conductive layer 136BP sequentially arranged on the peripheral metal silicide layer 134P. For example, the peripheral metal line stack 136P may have a structure in which the first peripheral intermediate layer 138AP is sandwiched between the first peripheral conductive layer 136AP and the second peripheral conductive layer 136BP.

[0065] In some embodiments, the first peripheral conductive layer 136AP may include a first metal material, and the first metal material may include at least one of Ru, Mo, Ro, Ir, and alloys of one or more thereof. In some embodiments, the first peripheral conductive layer 136AP may include Ru.

[0066] In some embodiments, the first peripheral intermediate layer 138AP may include graphene. In some embodiments, the graphene constituting the first peripheral intermediate layer 138AP may include a plurality of grains having a two-dimensional structure. For example, each grain of the first peripheral intermediate layer 138AP may have a two-dimensional structure in which 1 to 15 layers of carbon two-dimensional sheets are stacked layer by layer. In some embodiments, the first peripheral intermediate layer 138AP may have a nanocrystalline structure, and the plurality of grains may have a grain size of about 2 nm to about 200 nm. In some embodiments, the first peripheral intermediate layer 138AP may have an average grain size of 10 nm or more.

[0067] In some embodiments, the first peripheral intermediate layer 138AP may include graphene including carbon atoms having carbon atoms accounting for 50% or more and 99% or less of all carbon atoms in terms of binding energy of carbon atoms included in the graphene. The binding energy of carbon atoms included in the first peripheral intermediate layer 138AP can be measured by using an analysis device such as XPS.

[0068] In some embodiments, when measured by Raman spectroscopy, the first peripheral intermediate layer 138AP may exhibit a D peak, a 2D peak, a D' peak, and a G peak of carbon atoms, a ratio of the D peak to the G peak of carbon atoms may be 3.0 or less, a ratio of the 2D peak to the G peak may be 0.1 or more, and a ratio of the D' peak to the G peak may be 1.0 or less. Here, the G peak may correspond to about 1580 The Raman shift value of the D peak can correspond to about 1350 The Raman shift value of the 2D peak can correspond to about 2700 The Raman shift value.

[0069] In some embodiments, the second peripheral conductive layer 136BP may include a first metal material, and the first metal material may include at least one of Ru, Mo, Ro, Ir, and alloys of one or more thereof. In some embodiments, the second peripheral conductive layer 136BP may include Ru.

[0070] In some embodiments, peripheral metal line stack 136P may have a first thickness t20 in the vertical direction Z. First peripheral conductive layer 136AP may have a second thickness t21 in the vertical direction Z, first peripheral intermediate layer 138AP may have a third thickness t22 in the vertical direction Z, and second peripheral conductive layer 136BP may have a fourth thickness t23 in the vertical direction Z. Second thickness t21 of first peripheral conductive layer 136AP may correspond to about 20% to about 80% of first thickness t20 of peripheral metal line stack 136P in the vertical direction Z. Fourth thickness t23 of second peripheral conductive layer 136BP may correspond to about 20% to about 80% of first thickness t20 of peripheral metal line stack 136P in the vertical direction Z.

[0071] The third thickness t22 of the first peripheral intermediate layer 138AP may correspond to about 5% to about 50% of the first thickness t20 of the peripheral metal line stack 136P in the vertical direction Z. For example, when the third thickness t22 of the first peripheral intermediate layer 138AP is less than 5% of the first thickness t20, the thickness of the first peripheral intermediate layer 138AP may not be sufficient to perform the grain agglomeration suppression function, and when the third thickness t22 of the first peripheral intermediate layer 138AP is greater than 50% of the first thickness t20, the resistivity of the entire peripheral metal line stack 136P may increase, so that the electrical performance of the semiconductor device 100 may be degraded. In some embodiments, the third thickness t22 of the first peripheral intermediate layer 138AP may be 50 angstroms or less. In some embodiments, the third thickness t22 of the first peripheral intermediate layer 138AP may be 5 angstroms or more. In some embodiments, the third thickness t22 of the first peripheral intermediate layer 138AP may be in the range of about 5 angstroms to 50 angstroms.

[0072] In some embodiments, the constituent materials of the peripheral lower conductive layer 132P, the peripheral metal silicide layer 134P, the first peripheral conductive layer 136AP, the first peripheral intermediate layer 138AP, and the second peripheral conductive layer 136BP may be the same as the constituent materials of the lower conductive layer 132, the metal silicide layer 134, the first conductive layer 136A, the first intermediate layer 138A, and the second conductive layer 136B included in the bit line BL in the cell array area MCA. For example, the peripheral circuit gate stack PGS may be formed simultaneously in the process of forming the bit line BL. However, the present disclosure is not limited thereto.

[0073] The sidewalls of the peripheral circuit gate stack PGS and the gate cap pattern 142P may be covered by an insulating spacer 150P. The insulating spacer 150P may include an oxide layer or a nitride layer or a combination thereof. The peripheral circuit transistor PTR and the insulating spacer 150P may be covered by a protective layer 144P, and a first interlayer insulating layer 148 may be arranged on the protective layer 144P and may fill the space between two adjacent peripheral circuit transistors PTR. A cap insulating layer 146P may be arranged on the first interlayer insulating layer 148 and the protective layer 144P.

[0074] In the peripheral circuit area PCA, a contact plug PCT may be formed in a contact hole PCTH that passes through or extends through the first interlayer insulating layer 148 and the cover insulating layer 146P in a vertical direction. The contact plug PCT may include a conductive barrier layer and a landing pad conductive layer in the same manner as the plurality of landing pads LP formed in the cell array area MCA. A metal silicide layer (not shown) may be between the second active area AC2 and the contact plug PCT. An upper interlayer insulating layer 190 may cover the contact plug PCT and may be disposed on the cover insulating layer 146P.

[0075] In general, as the line width of each of the plurality of bit lines BL decreases, the resistance of the bit line BL increases. Therefore, a technique of using a metal material with low resistivity (such as Ru) as the bit line BL is being attempted. However, when a metal material such as Ru is patterned to have a relatively small line width, grain agglomeration or grain merging may occur in a subsequent high temperature process, resulting in a significant increase in the roughness of the metal material layer and causing a local line width increase region, a line width reduction region, and / or a line disconnection region.

[0076] However, according to some embodiments, metal line stack 136 may include a first intermediate layer 138A including graphene between first conductive layer 136A and second conductive layer 136B, and first intermediate layer 138A may prevent grain agglomeration of metal materials in first conductive layer 136A and second conductive layer 136B. Therefore, bit line BL may have a relatively low resistance while preventing or reducing the occurrence of a local line width increase region, line width decrease region, and / or line disconnection region in bit line BL during a formation process of semiconductor device 100. Therefore, semiconductor device 100 may have relatively high electrical characteristics.

[0077] In the following, reference will be made to Figure 23 to Figure 26 The crystallinity and physical characteristics of the metal line stack 136 included in the bit line BL are described in more detail.

[0078] Fig.23 is a graph showing XPS measurement results of a metal line stack according to some embodiments.

[0079] Reference Fig.23According to some embodiments, a metal wire stack may have a stack structure of a first conductive layer made of a first metal material, a first intermediate layer made of graphene, and a second conductive layer made of the first metal material. In the metal wire stack according to some embodiments, the first intermediate layer may be formed to have a thickness corresponding to about 10% of the total thickness of the metal wire stack. Fig.23 In the embodiment, the first conductive layer can be formed by using Ru as the first metal material, wherein the first intermediate layer can be formed by using graphene to form an intermediate structure on the first conductive layer, and the binding energy of carbon atoms and Ru metal atoms is measured by XPS for the intermediate structure. Fig.23 As shown, it can be noted that the carbon atoms are measured with relatively high intensity in the XPS measurement. peak, and it can be confirmed that the graphene layer is formed on the metal material layer such as Ru in a layered structure.

[0080] although Fig.23 The binding energy of the first intermediate layer including graphene measured using XPS is shown as an example, but in addition to XPS, analysis equipment such as transmission electron microscopy (TEM), energy dispersive X-ray spectroscopy (EDX), and electron energy loss spectroscopy (EELS) may also be able to perform atomic binding energy analysis on a structure in which the first intermediate layer is between the first conductive layer and the second conductive layer.

[0081] Fig.24 is a graph showing a Raman spectrum of a metal wire stack according to some embodiments.

[0082] exist Fig.24 In the embodiment, the first conductive layer can be formed by using Ru as the first metal material, wherein an intermediate structure in which the first intermediate layer is formed by using graphene can be formed on the first conductive layer, and the Raman spectrum of the graphene can be measured for the intermediate structure by Raman spectroscopy.

[0083] Graphene can present D peak, 2D peak, D' peak and G peak of carbon atoms, and the G peak can correspond to about 1580 The Raman shift value of the D peak can correspond to about 1350 The Raman shift value of the 2D peak can correspond to about 2700 The Raman shift value of the carbon atom can be 1.01 (ie, D / G=1.01), the ratio of the 2D peak to the G peak can be 0.10 (ie, 2D / G=0.10), and the ratio of the D' peak to the G peak can be 0.30 (ie, D' / G=0.30). Fig.24 The Raman spectrum shown can confirm that graphene is formed into a layered nanocrystalline structure with relatively high crystallinity.

[0084] Fig.25is a graph showing roughness changes of a metal wire CO11 according to a comparative example and a metal wire stack EX11 according to an embodiment of the inventive concept before and after annealing.

[0085] Reference Fig.25 , the metal wire CO11 according to the comparative example may have a single-layer structure formed of a first metal material, and the metal wire stack EX11 according to the embodiment of the inventive concept may have a stacked structure of a first conductive layer formed of a first metal material, a first intermediate layer formed of graphene, and a second conductive layer formed of a first metal material. In the metal wire stack EX11 according to the embodiment of the inventive concept, the first intermediate layer may be formed to have a thickness corresponding to about 10% of the total thickness of the metal wire stack EX11, and the total thickness of the metal wire CO11 according to the comparative example may be the same as the total thickness of the metal wire stack EX11 according to the embodiment of the inventive concept. In addition, the metal wire CO11 according to the comparative example and the metal wire stack EX11 according to the embodiment of the inventive concept may be annealed at a temperature of about 600° C. for several minutes, and the surface root mean square (RMS) roughness may be measured by an atomic force microscope before and after the annealing process, respectively.

[0086] The metal wire CO11 according to the comparative example had an average roughness of 0.795 nm before the annealing treatment, but had an average roughness of 1.832 nm after the annealing treatment. When compared with the initial value before the annealing treatment, the average roughness of the metal wire CO11 according to the comparative example increased by about 130% after the annealing treatment, which can be assumed to be because the grains of the first metal material were exposed to high temperature during the annealing treatment, causing the grains to aggregate or agglomerate, thereby changing the surface morphology to a roughened surface.

[0087] The metal wire stack EX11 according to an embodiment of the present inventive concept has an average roughness of 0.564 nm before the annealing treatment, but has an average roughness of 0.586 nm after the annealing treatment. When compared with the initial value before the annealing treatment, the average roughness of the metal wire stack EX11 according to an embodiment of the present inventive concept does not increase or slightly increases after the annealing treatment. It can be confirmed that the metal wire stack EX11 according to an embodiment of the present inventive concept shows relatively little surface morphology change even after the annealing treatment. It can be assumed that although the grains of the first metal material are exposed to high temperature during the annealing treatment, due to the presence of the first intermediate layer including graphene sandwiched between the first conductive layer and the second conductive layer, the grains of the first metal material included in the first conductive layer and the second conductive layer do not experience grain aggregation or agglomeration.

[0088] Fig.26 is a graph showing resistivity changes of a metal line CO11 according to a comparative example and a metal line stack EX11 according to an embodiment of the inventive concept before and after annealing.

[0089] Reference Fig.26 The metal wire CO11 according to the comparative example has a resistivity of 14.50 μΩ·cm before annealing, but has a resistivity of 10.62 μΩ·cm after annealing. When compared with the initial value before annealing, the resistivity of the metal wire CO11 according to the comparative example is reduced by about 26.8% of the initial resistivity after annealing.

[0090] The metal wire stack EX11 according to the embodiment of the inventive concept has a resistivity of 16.91 μΩ·cm before the annealing process, but has a resistivity of 12.69 μΩ·cm after the annealing process. When compared with the initial value before the annealing process, the resistivity of the metal wire stack EX11 according to the embodiment of the inventive concept is reduced by about 25.0% of the initial resistivity after the annealing process. Although the metal wire stack EX11 according to the embodiment of the inventive concept has a slightly higher resistivity value than the metal wire CO11 according to the comparative example, it can be confirmed that after the annealing process, the metal wire stack EX11 has a similar value as the metal wire CO11 according to the comparative example in terms of the resistivity reduction rate.

[0091] Refer to Fig.25 and Fig.26 , although the metal line CO11 according to the comparative example has a roughened surface morphology after the annealing process, the metal line stack EX11 according to the embodiment of the inventive concept maintains almost the same initial surface morphology after the annealing process. In addition, after the annealing process, the resistivity of the metal line stack EX11 according to the embodiment of the inventive concept decreases to a similar extent as that of the metal line CO11 according to the comparative example. Therefore, the bit line BL including the metal line stack EX11 according to the embodiment of the inventive concept has a relatively low resistance while preventing or reducing the occurrence of a local line width increase region, a line width decrease region, and / or a line disconnection region in the bit line BL due to a high temperature process.

[0092] Figure 7 and Figure 8 is a cross-sectional view illustrating a semiconductor device 100A according to some embodiments.

[0093] Reference Figure 7 and Figure 8 The metal line stack 136 may include a first conductive layer 136A, a first intermediate layer 138A, and a second conductive layer 136B, and a second thickness t11 of the first conductive layer 136A in the vertical direction Z may be greater than a fourth thickness t13 of the second conductive layer 136B in the vertical direction Z.

[0094] In some embodiments, second thickness t11 of first conductive layer 136A may correspond to about 40% to about 80% of first thickness t10 of metal wire stack 136 in vertical direction Z. Fourth thickness t13 of second conductive layer 136B may correspond to about 10% to about 30% of first thickness t10 of metal wire stack 136 in vertical direction Z. Third thickness t12 of first intermediate layer 138A may correspond to about 5% to about 20% of first thickness t10 of metal wire stack 136 in vertical direction Z.

[0095] Reference Figure 7 and Figure 8 Description of the embodiments and references Figures 1 to 6 The described embodiments are not mutually exclusive, and it will be understood that reference Figure 7 and Figure 8 The thickness of each of the first conductive layer 136A, the first intermediate layer 138A, and the second conductive layer 136B in the described embodiment may be the same as that in the reference Figures 1 to 6 The thickness of each of the first conductive layer 136A, the first intermediate layer 138A, and the second conductive layer 136B in the described embodiment partially overlaps.

[0096] Fig. 9 and Fig.10 is a cross-sectional view illustrating a semiconductor device 100B according to some embodiments.

[0097] Reference Fig. 9 and Fig.10 The metal line stack 136 may include a first conductive layer 136A, a first intermediate layer 138A, and a second conductive layer 136B, and a second thickness t11 of the first conductive layer 136A in the vertical direction Z may be less than a fourth thickness t13 of the second conductive layer 136B in the vertical direction Z.

[0098] In some embodiments, second thickness t11 of first conductive layer 136A may correspond to about 10% to about 30% of first thickness t10 of metal wire stack 136 in vertical direction Z. Fourth thickness t13 of second conductive layer 136B may correspond to about 40% to about 80% of first thickness t10 of metal wire stack 136 in vertical direction Z. Third thickness t12 of first intermediate layer 138A may correspond to about 5% to about 20% of first thickness t10 of metal wire stack 136 in vertical direction Z.

[0099] Reference Fig. 9 and Fig.10 Description of the embodiments and references Figures 1 to 6 The described embodiments are not mutually exclusive, and it will be understood that reference Fig. 9 and Fig.10The thickness of each of the first conductive layer 136A, the first intermediate layer 138A, and the second conductive layer 136B in the described embodiment may be the same as that in the reference Figures 1 to 6 The thickness of each of the first conductive layer 136A, the first intermediate layer 138A, and the second conductive layer 136B in the described embodiment partially overlaps.

[0100] Fig.11 and Fig.12 is a cross-sectional view illustrating a semiconductor device 100C according to some embodiments.

[0101] Reference Fig.11 and Fig.12 The metal wire stack 136 may include a first conductive layer 136A, a first intermediate layer 138A, a second conductive layer 136B, and a second intermediate layer 138B sequentially arranged on the metal silicide layer 134. The second intermediate layer 138B may include graphene. For example, the graphene constituting the second intermediate layer 138B may include a plurality of grains having a two-dimensional structure.

[0102] In some embodiments, the metal line stack 136 may have a first thickness t10 in the vertical direction Z, the first conductive layer 136A may have a second thickness t11 in the vertical direction Z, the first intermediate layer 138A may have a third thickness t12 in the vertical direction Z, the second conductive layer 136B may have a fourth thickness t13 in the vertical direction Z, and the second intermediate layer 138B may have a fifth thickness t14 in the vertical direction Z. The second thickness t11 of the first conductive layer 136A may correspond to about 20% to about 60% of the first thickness t10 of the metal line stack 136 in the vertical direction Z. The fourth thickness t13 of the second conductive layer 136B may correspond to about 20% to about 60% of the first thickness t10 of the metal line stack 136 in the vertical direction Z. The third thickness t12 of the first intermediate layer 138A may correspond to about 5% to about 30% of the first thickness t10 of the metal line stack 136 in the vertical direction Z. A fifth thickness t14 of second intermediate layer 138B may correspond to about 5% to about 30% of the first thickness t10 of metal line stack 136 in vertical direction Z.

[0103] Fig.11 and Fig.12 1 shows a metal wire stack 136 composed of four layers, namely, a first conductive layer 136A, a first intermediate layer 138A, a second conductive layer 136B, and a second intermediate layer 138B. However, in some embodiments, the metal wire stack 136 may further include an additional conductive layer including the first metal material and an additional intermediate layer including graphene.

[0104] Fig.13A , Fig. 13B , Fig.14A , Fig. 14B , Fig.15A , Fig. 15B , Fig.16A , Fig. 16B , Fig.17A , Fig. 17B , Fig.18A , Fig.18B , Fig.19A , Fig.19B , Fig. 20A , Fig. 20B , Fig.21A , Fig.21B , Fig.22A and Fig. 22B is a cross-sectional view illustrating a method of manufacturing a semiconductor device 100 according to some embodiments. Specifically, Fig.13A , Fig.14A , Fig.15A , Fig.16A , Fig.17A , Fig.18A , Fig.19A , Fig. 20A , Fig.21A and Fig.22A is with Figure 2 The cross-sectional view corresponding to the line A-A', Fig. 13B , Fig. 14B , Fig. 15B , Fig. 16B , Fig. 17B , Fig.18B , Fig.19B , Fig. 20B , Fig.21B and Fig. 22B is with Figure 2 The cross-sectional view corresponding to the line BB'.

[0105] Reference Fig.13A and Fig. 13B , a plurality of device isolation trenches 112T may be formed in the substrate 110 .

[0106] Then, a plurality of first device isolation layers 112 filling the plurality of device isolation trenches 112T may be formed. A plurality of first active regions AC1 may be defined in the substrate 110 by forming the plurality of first device isolation layers 112. In a plan view, the plurality of first active regions AC1 may be arranged in a first diagonal direction D1 (refer to FIG. 1 ) inclined at a predetermined angle to the first horizontal direction X and the second horizontal direction Y. Figure 2 ) extends upward.

[0107] In some embodiments, the plurality of first device isolation layers 112 may include silicon oxide, silicon nitride, or silicon oxynitride, or a combination of two or more thereof. In some examples, the first device isolation layer 112 may have a double-layer structure of a silicon oxide layer and a silicon nitride layer. However, the present disclosure is not limited thereto.

[0108] A mask pattern (not shown) may be formed on the substrate 110, and a portion of the substrate 110 may be removed by using the mask pattern as an etching mask to form the word line trench 120T. For example, the mask pattern for forming the word line trench 120T may be formed by using a double patterning technique (DPT) or a quadruple patterning technique (QPT). However, the present disclosure is not limited thereto.

[0109] Then, a gate dielectric layer 122 , a gate electrode 124 , and a word line capping layer 126 may be sequentially formed in the word line trench 120T.

[0110] For example, the gate dielectric layer 122 may be disposed on the inner wall of the word line trench 120T and may conform to the inner wall. The gate electrode 124 may be formed by filling the word line trench 120T with a conductive layer (not shown) and then etching back the upper portion of the conductive layer to expose a portion of the upper side of the word line trench 120T again. A word line capping layer 126 may be formed in the exposed portion of the word line trench 120T.

[0111] Reference Fig.14A and Fig. 14B , a first buffer insulating layer 114 and a second buffer insulating layer 116 may be formed on the first active region AC1 and the first device isolation layer 112. Then, a lower conductive layer 132 may be formed on the first buffer insulating layer 114 and the second buffer insulating layer 116. Portions of the lower conductive layer 132, the first buffer insulating layer 114 and the second buffer insulating layer 116, and the substrate 110 may be removed to form a bit line contact hole DCH. Then, a bit line contact DC may be formed of a conductive material in the bit line contact hole DCH.

[0112] In some embodiments, the lower conductive layer 132 may include Si, Ge, W, WN, Co, Ni, Al, Mo, Ru, Ti, TiN, Ta, TaN, or Cu, or a combination of two or more thereof. In some embodiments, the bit line contact DC may include TiN, TiSiN, W, tungsten silicide, or doped polysilicon, or a combination of two or more thereof.

[0113] Reference Fig.15A and Fig. 15B , a metal silicide layer 134 may be formed on the bit line contact DC and the lower conductive layer 132. The metal silicide layer 134 may include at least one of cobalt silicide, nickel silicide, and tungsten silicide. Alternatively, a conductive barrier layer may be further formed on the metal silicide layer 134 by using at least one of Ti, TiN, and TaN.

[0114] Then, a first conductive layer 136A, a first intermediate layer 138A, and a second conductive layer 136B may be sequentially formed on the metal silicide layer 134 .

[0115] In some embodiments, the first conductive layer 136A may include a first metal material, which may include at least one of Ru, Mo, Ro, Ir, and alloys of one or more thereof. The first conductive layer 136A may be formed by using at least one of a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, and an atomic layer deposition (ALD) process.

[0116] The first intermediate layer 138A may include graphene and may be formed, for example, by using at least one of a CVD process using plasma, a thermal CVD process, and an ALD process. For example, the CVD process using plasma may include at least one of microwave plasma CVD, inductively coupled plasma (ICP) CVD, capacitively coupled plasma (CCP) CVD, and pulsed plasma CVD.

[0117] In some embodiments, the second conductive layer 136B may include a first metal material, which may include at least one of Ru, Mo, Ro, Ir, and alloys of one or more thereof. The second conductive layer 136B may be formed using at least one of a PVD process, a CVD process, and an ALD process.

[0118] Here, the stack structure of the first conductive layer 136A, the first intermediate layer 138A, and the second conductive layer 136B may be referred to as a metal wire stack layer 136L. Then, a bit line capping layer 140 may be formed on the metal wire stack layer 136L. The bit line capping layer 140 may include a first capping layer 142, a second capping layer 144, and a third capping layer 146 that may be sequentially arranged on a top surface of the metal wire stack layer 136L. The first capping layer 142, the second capping layer 144, and the third capping layer 146 may include at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0119] Reference Fig.16A and Fig. 16B , a plurality of bit lines BL may be formed by patterning the metal line stack layer 136L, the metal silicide layer 134, and the lower conductive layer 132 by using the bit line capping layer 140 as an etching mask.

[0120] In the patterning process for forming the plurality of bit lines BL, a portion of the bit line contact DC disposed in the bit line contact hole DCH may also be removed. Fig.16A As shown, the sidewalls of the bit line contact DC may be aligned with the sidewalls of the bit line BL, and the inner walls of the bit line contact hole DCH may be exposed again at both sides of the bit line contact DC.

[0121] Then, a first spacer layer 152 may be formed on the sidewalls of the bit line BL, the bit line capping layer 140, and the bit line contact DC. The first spacer layer 152 may also be disposed on and conform to the inner wall of the bit line contact hole DCH. In some embodiments, the first spacer layer 152 may include silicon nitride.

[0122] Reference Fig.17A and Fig. 17B , a bit line contact spacer DCS may be formed by filling a remaining portion of the bit line contact hole DCH on the first spacer layer 152. For example, the bit line contact spacer DCS may include silicon nitride or silicon oxide.

[0123] Then, a second spacer layer 154 may be formed on sidewalls of the bit line BL and the bit line capping layer 140. In some embodiments, the second spacer layer 154 may include silicon oxide.

[0124] Then, an anisotropic etching process may be performed on the second spacer layer 154 , and the first and second buffer insulating layers 114 and 116 disposed between the bit lines BL may be removed to expose the top surface of the substrate 110 .

[0125] Thereafter, the third spacer layer 156 may be formed on the top surface of the substrate 110 and the second spacer layer 154, and may conform to the top surface of the substrate 110 and the second spacer layer 154. In some embodiments, the third spacer layer 156 may include silicon nitride.

[0126] Reference Fig.18A and Fig.18B , the buried contact hole BCH may be formed by further removing the upper side of the substrate 110 exposed to the space between the plurality of bit lines BL. In some embodiments, the process of forming the buried contact hole BCH may include a wet etching process or a dry etching process or a combination thereof.

[0127] In the etching process for forming the buried contact hole BCH, a portion of the upper side of the bit line capping layer 140 may also be removed so that the top surface level of the bit line capping layer 140 may be lowered.

[0128] Reference Fig.19A and Fig.19B , a buried contact BC filling the buried contact hole BCH may be formed. In some embodiments, the buried contact BC may include doped polysilicon.

[0129] In some embodiments, the buried contact hole BCH is formed to have a linear planar shape arranged between adjacent bit lines BL, and then a preliminary contact layer having a linear planar shape may be formed in the buried contact hole BCH, and the preliminary contact layer may be patterned to form a buried contact BC. Then, an insulating fence may be formed by using an insulating material in a space between the buried contacts BC (e.g., a space from which a portion of the preliminary contact layer is removed).

[0130] In other embodiments, before forming the buried contact hole BCH, a plurality of insulating fences may be formed by using an insulating material at the intersection of two adjacent bit lines BL and the word line trench 120T, the buried contact hole BCH may be formed by removing portions of the substrate 110 arranged between the plurality of bit lines BL and between the plurality of insulating fences, and then a buried contact BC may be formed in the buried contact hole BCH.

[0131] Reference Fig. 20A and Fig. 20B A landing pad conductive layer LPL may be formed on top surfaces of the plurality of buried contacts BC. The landing pad conductive layer LPL may be formed to have a sufficient thickness to contact the plurality of buried contacts BC and cover top surfaces of the plurality of bit line capping layers 140.

[0132] Reference Fig.21A and Fig.21B A mask pattern may be formed on the landing pad conductive layer LPL, and the landing pad conductive layer LPL may be patterned by using the mask pattern as an etching mask to form a landing pad opening LPH. A plurality of landing pads LP arranged on the plurality of buried contacts BC may be formed through the landing pad opening LPH.

[0133] Reference Fig.22A and Fig. 22B , the insulating pattern 160 may be formed in the landing pad opening LPH by using an insulating material. The insulating pattern 160 may be arranged to cover the sidewalls of the plurality of landing pads LP.

[0134] Return to reference Figure 3 and Figure 4 , a plurality of lower electrodes 182 connected to the plurality of landing pads LP may be formed, and a capacitor dielectric layer 184 and an upper electrode 186 may be sequentially formed on sidewalls of the plurality of lower electrodes 182 .

[0135] The semiconductor device 100 may be formed by performing the above-described method, but it is to be understood that the present disclosure is not limited thereto.

[0136] According to some embodiments, the bit line may include a metal line stack, and the metal line stack may have a structure in which a first conductive layer including a first metal material (such as Ru), a first intermediate layer including graphene, and a second conductive layer including the first metal material are stacked in sequence. The first intermediate layer may suppress and prevent grain agglomeration and / or excessive grain growth of the first conductive layer and the second conductive layer in a heat treatment during a manufacturing process, thereby preventing local disconnection of the bit line.

[0137] While the inventive concept has been particularly shown and described with reference to certain examples of embodiments of the inventive concept, it will be understood that various changes in form and details may be made therein without departing from the scope of the appended claims.

Claims

1. A semiconductor device, comprising: a substrate including a first active region defined by a first device isolation layer; a bit line contact disposed on the first active region of the substrate; as well as A bit line extends along a first direction on the substrate, wherein the bit line comprises: a lower conductive layer disposed on the substrate and on sidewalls of the bit line contact; and a metal line stack disposed on the lower conductive layer, and Wherein, the metal wire stack comprises: a first conductive layer disposed on the lower conductive layer and the bit line contact and comprising a first metal material; a first intermediate layer disposed on the first conductive layer and comprising graphene; and The second conductive layer is disposed on the first intermediate layer and includes the first metal material.

2. The semiconductor device according to claim 1, wherein The metal line stack has a first thickness in a vertical direction, wherein the first intermediate layer has a second thickness in the vertical direction, and Wherein, the second thickness is in the range of about 5% to 50% of the first thickness.

3. The semiconductor device according to claim 2, wherein: The second thickness of the first intermediate layer is in a range of about 5 angstroms to 50 angstroms.

4. The semiconductor device according to claim 1, wherein: The first metal material includes at least one of ruthenium (Ru), molybdenum (Mo), rhodium (Ro), iridium (Ir), and alloys of one or more thereof.

5. The semiconductor device according to claim 1, wherein The first metal material includes ruthenium (Ru).

6. The semiconductor device according to claim 1, wherein The first intermediate layer comprises 50% to 99% of a bond's carbon atom.

7. The semiconductor device according to claim 1, wherein As analyzed by Raman spectroscopy, the first intermediate layer has a D peak to G peak ratio of carbon atoms of 3.0 or less, a 2D peak to G peak ratio of 0.1 or more, and a D′ peak to G peak ratio of 1.0 or less.

8. The semiconductor device according to claim 1, further comprising a bit line spacer arranged on a sidewall of the bit line, wherein The bit line spacer contacts a sidewall of the lower conductive layer and a sidewall of the metal line stack.

9. The semiconductor device according to claim 8, wherein: A sidewall of the first intermediate layer contacts the bit line spacer.

10. The semiconductor device according to claim 1, wherein The bit line further includes a metal silicide layer disposed on the lower conductive layer and on the metal line stack.

11. The semiconductor device according to claim 10, wherein: The metal silicide layer is between the lower conductive layer and the first conductive layer and between the bit line contact and the first conductive layer.

12. The semiconductor device according to claim 1, wherein The metal line stack further includes a second intermediate layer disposed on the second conductive layer and including graphene.

13. The semiconductor device according to claim 1, wherein The substrate further includes a second active region defined by a second device isolation layer, wherein the semiconductor device further includes a peripheral circuit gate stack arranged on the second active region, wherein the peripheral circuit gate stack includes: a peripheral lower conductive layer; and a peripheral metal line stack disposed on the peripheral lower conductive layer, and Wherein, the peripheral metal line stack comprises: a first peripheral conductive layer disposed on the peripheral lower conductive layer and comprising the first metal material; a first peripheral intermediate layer disposed on the first peripheral conductive layer and comprising graphene; and A second peripheral conductive layer is disposed on the first peripheral intermediate layer and includes the first metal material.

14. The semiconductor device according to claim 13, wherein: The peripheral metal line stack has a third thickness in a vertical direction, wherein the first peripheral intermediate layer has a fourth thickness in the vertical direction, and Wherein, the fourth thickness is in the range of about 5% to 50% of the third thickness.

15. The semiconductor device according to claim 14, wherein: The fourth thickness of the first peripheral intermediate layer is in a range of about 5 angstroms to 50 angstroms.

16. A semiconductor device comprising: A substrate including a first active region defined by a first device isolation layer and a second active region defined by a second device isolation layer; a bit line contact disposed on the first active region of the substrate; A bit line extending along a first direction on the substrate; as well as A peripheral circuit gate stack is arranged on the second active area, wherein the bit line comprises: a lower conductive layer disposed on the substrate and on sidewalls of the bit line contact; and a metal line stack disposed on the lower conductive layer, and Wherein, the metal wire stack comprises: a first conductive layer disposed on the lower conductive layer and the bit line contact and comprising a first metal material; a first intermediate layer disposed on the first conductive layer and comprising graphene; and The second conductive layer is disposed on the first intermediate layer and includes the first metal material.

17. The semiconductor device according to claim 16, wherein: The peripheral circuit gate stack comprises: a peripheral lower conductive layer; and A peripheral metal line stack is arranged on the peripheral lower conductive layer, Wherein, the peripheral metal line stack comprises: a first peripheral conductive layer disposed on the peripheral lower conductive layer and comprising the first metal material; a first peripheral intermediate layer disposed on the first peripheral conductive layer and comprising graphene; and A second peripheral conductive layer is disposed on the first peripheral intermediate layer and includes the first metal material.

18. The semiconductor device according to claim 17, wherein: The metal line stack has a first thickness in a vertical direction, wherein the first intermediate layer has a second thickness in the vertical direction, wherein the second thickness is about 5% to 50% of the first thickness, wherein the peripheral metal line stack has a third thickness in the vertical direction, wherein the first peripheral intermediate layer has a fourth thickness in the vertical direction, and Wherein, the fourth thickness is about 5% to 50% of the third thickness.

19. A semiconductor device comprising: a substrate including a first active region defined by a first device isolation layer; a bit line contact disposed in a bit line contact hole extending to the substrate, the bit line contact being connected to the first active region of the substrate; A bit line extends along a first direction on the substrate, the bit line comprising: a lower conductive layer disposed on the substrate, on the sidewalls of the bit line contacts, and extending in the first direction; a metal silicide layer disposed on the lower conductive layer and extending in the first direction; and a metal line stack, arranged on the metal silicide layer and extending in the first direction, the metal line stack comprising a first conductive layer, a second conductive layer and a first intermediate layer, wherein the first conductive layer comprises a first metal material, the second conductive layer comprises the first metal material, and the first intermediate layer is between the first conductive layer and the second conductive layer and comprises graphene; A bit line spacer disposed on a sidewall of the bit line and extending in the first direction; and A word line is arranged in a word line trench extending along a second direction intersecting the first direction, wherein the word line trench intersects the first active region in the substrate.

20. The semiconductor device according to claim 19, wherein The first metal material includes ruthenium (Ru), and Wherein, the first intermediate layer comprises 50% to 99% of the bond's carbon atom.

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