Semiconductor device and method for manufacturing the same

Abstract

A semiconductor device and a method for preparing the same. The method for preparing the semiconductor device comprises: providing a substrate, and forming a stacked layer of a plurality of first sacrificial layers and a plurality of second sacrificial layers arranged alternately on the substrate, wherein the second sacrificial layers and the substrate are made of the same material; forming a vertical opening penetrating the stacked layer and extending into the substrate to form a cavity in the substrate; forming a protective layer in the cavity of the substrate; using the protective layer as an etching stop layer, etching part of the second sacrificial layer in the stacked layer laterally along the vertical opening to form a plurality of side cavities spaced apart in the vertical direction; forming a plurality of lower electrodes on the surfaces of the second sacrificial layers exposed in the plurality of side cavities; forming a capacitor dielectric layer on the surfaces of the plurality of lower electrodes, the capacitor dielectric layer also being located in the vertical opening and in contact with the protective layer; forming an upper electrode on the surface of the capacitor dielectric layer, wherein the plurality of lower electrodes, the capacitor dielectric layer and the upper electrode constitute a capacitor structure. The embodiments of the present disclosure can improve device performance.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to semiconductor devices and methods for manufacturing the same. Background Art

[0002] Memory development pursues performance indicators such as high speed, high integration density, and low power consumption. As semiconductor device structures shrink in size, the technical barriers encountered by existing structures are becoming increasingly apparent. Therefore, developing more novel structures based on existing structures is an effective means of breaking through existing technical barriers.

[0003] The emergence of three-dimensional memory meets the above needs. However, in the process of manufacturing three-dimensional memory, when etching the stacked layers to form the active layer of the device or forming capacitors, especially when etching the stacked layers through a lateral wet etching process, the substrate is easily severely damaged, resulting in device failure. Summary of the Invention

[0004] According to a first aspect of an embodiment of the present disclosure, a method for preparing a semiconductor device is provided, comprising: providing a substrate, and forming a stacked layer of alternatingly arranged multiple first sacrificial layers and multiple second sacrificial layers on the substrate, wherein the second sacrificial layers and the substrate are made of the same material; forming a vertical opening penetrating the stacked layer, and the vertical opening extending into the substrate to form a cavity in the substrate; forming a protective layer in the cavity of the substrate; using the protective layer as an etching stop layer, etching part of the second sacrificial layer in the stacked layer laterally along the vertical opening to form multiple side cavities spaced apart in the vertical direction; forming multiple lower electrodes on the surfaces of the second sacrificial layers exposed in the multiple side cavities; forming a capacitor dielectric layer on the surfaces of the multiple lower electrodes, the capacitor dielectric layer also being located in the vertical opening and in contact with the protective layer; and forming an upper electrode on the surface of the capacitor dielectric layer, wherein the multiple lower electrodes, the capacitor dielectric layer and the upper electrode constitute a capacitor structure.

[0005] In some embodiments, the protective layer extends from the substrate toward the stacked layer, and the extension height of the protective layer is less than or equal to the height of the top surface of the second layer among the multiple first sacrificial layers, and greater than or equal to the height of the top surface of the substrate, wherein the first layer among the multiple first sacrificial layers is located on the top surface of the substrate.

[0006] In some embodiments, forming a protective layer in the cavity of the substrate includes: forming a silicon oxide layer on the sidewall of the cavity; forming a silicon germanium layer on the bottom wall of the cavity, wherein the silicon germanium layer fills the cavity and contacts the silicon oxide layer.

[0007] In some embodiments, after forming the plurality of side cavities, the preparation method further includes treating the protective layer, including: oxidizing the surface of the silicon germanium layer to form a silicon germanium oxide layer, the silicon germanium oxide layer being located on the remaining silicon germanium layer; removing germanium atoms in the silicon germanium oxide layer by acidic gas to form a silicon oxide layer having pores; and continuing to remove the remaining silicon germanium layer along the pores by acidic gas to form a cavity, the cavity being located below the oxide layer having pores and exposing the silicon oxide layer located on the sidewalls of the cavity and the substrate on the bottom wall of the cavity.

[0008] In some embodiments, forming a protective layer in the cavity of the substrate includes: forming a silicon oxide layer on the sidewall of the cavity; forming a boron-doped silicon layer on the bottom wall of the cavity, wherein the boron-doped silicon layer fills the cavity and contacts the silicon oxide layer.

[0009] In some embodiments, forming a protective layer in the cavity of the substrate includes: performing a second in-situ water vapor growth process on the surface of the exposed substrate at a pressure of 0-5 Torr and a temperature of 900-1000°C to form a first silicon oxide layer; and / or performing a second in-situ water vapor growth process at a pressure of 10-15 Torr and a temperature of 700-850°C to form a second silicon oxide layer.

[0010] In some embodiments, the preparation method further includes: forming a plurality of active layers arranged at intervals along the vertical direction in the stacked layer, the active layers extending along the first horizontal direction, and the active layers being composed of a second sacrificial layer; forming a plurality of word lines arranged at intervals along the vertical direction in the stacked layer, the word lines being arranged on the active layers and extending along a second horizontal direction intersecting the first horizontal direction; forming at least one bit line extending along the vertical direction in the stacked layer, the active layer contacting the bit line and the lower electrode of the capacitor structure at both ends of the first horizontal direction, respectively.

[0011] According to a second aspect of an embodiment of the present disclosure, a semiconductor device is provided, comprising: a substrate having a cavity; a protective layer located in the cavity of the substrate; a capacitor located on the substrate, the capacitor comprising: a plurality of lower electrodes arranged at intervals along a vertical direction on the substrate; a capacitor dielectric layer located on the surfaces of the plurality of lower electrodes, the capacitor dielectric layer and the protective layer being in contact with each other; and an upper electrode located on the surface of the capacitor dielectric layer.

[0012] In some embodiments, the protective layer includes: a silicon oxide layer located on the sidewalls of the cavity; a silicon oxide layer with pores, located between the silicon oxide layers on the sidewalls of the cavity and contacting the silicon oxide layer on the sidewalls of the cavity, and a cavity, located below the silicon oxide layer with pores, and the cavity exposing the silicon oxide layer on the sidewalls of the cavity and the substrate on the bottom wall of the cavity; wherein the capacitor dielectric layer conformally covers the surface of the silicon oxide layer with pores and the surface of the silicon oxide on the sidewalls of the cavity.

[0013] In some embodiments, the semiconductor device further includes: a plurality of active layers arranged at intervals along the vertical direction, the active layers extending along a first horizontal direction; a plurality of word lines arranged at intervals along the vertical direction, the word lines being disposed on the active layers and extending along a second horizontal direction intersecting the first horizontal direction; and at least one bit line extending along the vertical direction, the active layer contacting the bit line and the lower electrode of the capacitor structure at both ends of the first horizontal direction, respectively.

[0014] In an embodiment of the present disclosure, a method for preparing a semiconductor device is provided, wherein a stack of alternating first sacrificial layers and second sacrificial layers is formed on a substrate, wherein the second sacrificial layers are made of the same material as the substrate. Subsequently, the stack is etched and electrode material is deposited to form a capacitor comprising a plurality of lower electrodes, a capacitor dielectric layer, and an upper electrode. In an embodiment of the present disclosure, a protective layer is provided on the surface of the substrate to protect the substrate before etching the stack, especially when laterally etching and removing the second sacrificial layer made of the same material as the substrate. In addition, the embodiments of the present disclosure can also improve leakage current between the substrate and the device, thereby improving device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figures 1A to 11C A schematic diagram showing the structure of each stage in the semiconductor device manufacturing process of an exemplary embodiment is shown;

[0016] Figures 12 to 14 A schematic structural diagram of each stage in a semiconductor device manufacturing process according to another exemplary embodiment is shown;

[0017] Figures 15 to 21 A schematic structural diagram of each stage in a semiconductor device manufacturing process according to another exemplary embodiment is shown;

[0018] Figure 22 The figure is a schematic structural diagram of an electronic device according to an exemplary embodiment. DETAILED DESCRIPTION

[0019] The technical solutions of the present disclosure will be further described in detail below with reference to the accompanying drawings and examples. Although the accompanying drawings illustrate exemplary implementations of the present disclosure, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0020] The following paragraphs describe the present disclosure in more detail by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become more apparent from the following description and claims. It should be noted that the drawings are highly simplified and not to exact scale, and are intended solely to facilitate and clearly illustrate the embodiments of the present disclosure.

[0021] It will be understood that the meanings of “on,” “over,” and “over” throughout this disclosure should be interpreted in the broadest manner, such that “on” not only means being “on” something with no intervening features or layers (i.e., directly on something), but also includes being “on” something with intervening features or layers.

[0022] In the embodiments of the present disclosure, the terms "first," "second," "third," etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0023] In the embodiments of the present disclosure, the term "layer" refers to a portion of a material including an area having a thickness. A layer may extend over the entirety of a lower or upper structure, or may have an extent that is smaller than the extent of the lower or upper structure. In addition, a layer may be an area of ​​a homogeneous or inhomogeneous continuous structure having a thickness that is smaller than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0024] It should be noted that the technical solutions described in the embodiments of the present disclosure can be arbitrarily combined without conflict.

[0025] The present disclosure also provides a method for preparing a semiconductor device, the method comprising providing a substrate, and forming a stacked layer of alternatingly arranged multiple first sacrificial layers and multiple second sacrificial layers on the substrate, wherein the second sacrificial layers and the substrate are made of the same material; forming a vertical opening penetrating the stacked layer, and the vertical opening extending into the substrate to form a cavity in the substrate; forming a protective layer in the cavity of the substrate; using the protective layer as an etching stop layer, etching part of the second sacrificial layer in the stacked layer laterally along the vertical opening to form multiple side cavities spaced apart in the vertical direction; forming multiple lower electrodes on the surfaces of the second sacrificial layers exposed in the multiple side cavities; forming a capacitor dielectric layer on the surfaces of the multiple lower electrodes, the capacitor dielectric layer also being located in the vertical opening and in contact with the protective layer; and forming an upper electrode on the surface of the capacitor dielectric layer, wherein the multiple lower electrodes, the capacitor dielectric layer and the upper electrode constitute a capacitor structure.

[0026] In an embodiment of the present disclosure, a stack of alternating first sacrificial layers and second sacrificial layers is formed on a substrate, wherein the second sacrificial layers are made of the same material as the substrate. Subsequently, the stack is etched and electrode material is deposited to form a capacitor comprising a plurality of lower electrodes, a capacitor dielectric layer, and an upper electrode. In an embodiment of the present disclosure, a protective layer is provided on the surface of the substrate to protect the substrate before etching the stack, especially when laterally etching and removing the second sacrificial layer made of the same material as the substrate. Furthermore, the embodiments of the present disclosure can also reduce leakage current between the substrate and the device, thereby improving device performance.

[0027] Figures 1A to 11C The following is a schematic diagram showing the structure of each stage in the semiconductor device manufacturing process of an exemplary embodiment. Figure 1A 、 2A , and 11A are planar schematic diagrams of each stage in the preparation of semiconductor devices. Figure 1B 、 2B 、 Figures 3 to 10 ,as well as Figure 11B They are cross-sectional views taken along line AA' at various stages in the preparation of a semiconductor device. Figure 1C and Figure 11C The following are cross-sectional views taken along line BB' at each stage in the preparation of the semiconductor device. Figures 1A to 11C The semiconductor structure and its preparation process provided by the embodiments of the present disclosure are described in detail.

[0028] Please refer to Figures 1A to 1C A substrate 100 is provided, and a stacked layer ST of a plurality of alternating first sacrificial layers 110 and a plurality of second sacrificial layers 120 is formed on the substrate 100. The plurality of first sacrificial layers 110 are spaced apart from each other along a vertical direction Z on the substrate 100, with the first sacrificial layer at the bottom layer (i.e., the first layer) being located on the substrate 100. The plurality of second sacrificial layers 120 are also spaced apart from each other along the vertical direction Z on the substrate 100, with the second sacrificial layer at the bottom layer (i.e., the first layer) being located on the first sacrificial layers 110.

[0029] Please continue to refer to Figures 1A to 1C A plurality of third sacrificial layers 130 are formed in the stacked layer ST. The plurality of third sacrificial layers 130 extend along the first horizontal direction X, separating the plurality of first sacrificial layers 110 from each other in the second horizontal direction Y. The first sacrificial layers 110 extend along the first horizontal direction X, and the plurality of second sacrificial layers 120 from each other in the second horizontal direction Y. The second sacrificial layers 120 extend along the first horizontal direction X. The first horizontal direction X and the second horizontal direction Y intersect with each other. In some embodiments, the first horizontal direction X and the second horizontal direction Y are perpendicular to each other and are both perpendicular to the vertical direction Z.

[0030] The material of the substrate 100 includes a semiconductor material, for example, a single-element semiconductor material (for example, silicon (Si) or germanium (Ge)), a III-V compound semiconductor material (for example, gallium nitride (GaN), gallium arsenide (GaAs) or indium phosphide (InP), etc.), a II-VI compound semiconductor material (for example, zinc sulfide (ZnS), cadmium sulfide (CdS) or cadmium telluride (CdTe), etc.), an organic semiconductor material or other semiconductor materials known in the art.

[0031] The material of the first sacrificial layer 110 is, for example, at least one of silicon oxide, silicon nitride, or silicon oxynitride. The second sacrificial layer 120 is made of the same material as the substrate 100. In some embodiments, the substrate is, for example, a silicon substrate, and the second sacrificial layer 120 is also a silicon layer. The material of the third sacrificial layer 130 is, for example, polysilicon or a carbon layer. The second sacrificial layer 120 in the stacked layer ST comprises a silicon layer of the same material as the substrate 100. Not only can it be directly used as the material of the active layer 200 of the semiconductor device, but it also has a large etching selectivity with the materials of the first sacrificial layer 110 and the third sacrificial layer 130, which is beneficial to the patterning process. In the embodiment of the present disclosure, the semiconductor device of the present disclosure is formed by patterning and pattern filling the first sacrificial layer 110, the second sacrificial layer 120, and the third sacrificial layer 130.

[0032] Please refer to Figure 1B Among the multiple first sacrificial layers 110, the first sacrificial layer 110-1 located in the first layer has a first thickness H1, while the remaining first sacrificial layers 110-2, 110-3, ..., 110-N may have approximately the same second thickness H2. Among the multiple second sacrificial layers 120, each second sacrificial layer 120-1, 120-2, ..., 120-N may have approximately the same third thickness H3. The first thickness H1 may be greater than the second thickness H2, and the second thickness H2 may be greater than the third thickness H3. The first sacrificial layer 110-1 having the first thickness H1 is a layer that directly contacts the substrate 100 and can serve as a dummy layer. Its relatively large thickness can reduce damage to the substrate 100 during subsequent lateral etching of the second and third sacrificial layers 120, 130. The second sacrificial layer 120 having the third thickness H3 is made of the same material as the substrate 100. After patterning, it can serve as a device layer in the semiconductor device. Its relatively small thickness can provide a semiconductor device with a higher stacking density. The first sacrificial layer with the second thickness H2 serves as an isolation layer between device layers. Its thickness is between the first thickness H1 and the third thickness H3, which can provide an ideal isolation effect between device layers and protect the device surface.

[0033] Please refer to Figures 2A to 2B, a plurality of initial active layers 200a are formed in the stacked layer ST. The initial active layer 200a is a portion of the second sacrificial layer 120, and after patterning, the final active layer 200 (eg Figures 11A to 11C As shown). The multiple initial active layers 200a can be spaced apart from each other in the vertical direction Z and the second horizontal direction Y. The multiple initial active layers 200a extend along the first horizontal direction X. The multiple initial active layers 200a are isolated from each other by an isolation structure. The isolation structure may include at least one of silicon oxide, silicon nitride, silicon oxynitride or polysilicon, for example, as shown. Figure 2A and 2B As shown, the multiple initial active layers 200 a arranged at intervals in the vertical direction Z are isolated from each other by the first sacrificial layer 110 . The multiple initial active layers 200 a arranged at intervals in the second horizontal direction Y are isolated from each other by the third sacrificial layer 130 .

[0034] In the embodiment of the present disclosure, the initial active layer 200a can be formed by selectively etching the second sacrificial layer 120, and further forming the active layer 200 of the transistor Tr. The active layer 200 includes a first source / drain region, a channel region, and a second source / drain region arranged in sequence along the first horizontal direction Y. That is, the active layer 200 is composed of the second sacrificial layer 120 in the stacked layer ST, and the material is the same as that of the substrate 100, that is, single crystal silicon. In some embodiments of the present disclosure, before performing lateral wet etching of the silicon layer, the exposed silicon substrate can be protected by a protective layer to prevent the substrate from being severely damaged by wet etching, while improving the leakage current between the device and the substrate.

[0035] Please continue to refer to Figures 2A to 2B A plurality of word lines 300 are formed in the stacked layer ST, spaced apart along the vertical direction Z. The word lines 300 are formed in the first sacrificial layer 110. In some embodiments, the word lines 300 are spaced apart along the vertical direction Z and the first horizontal direction X. The word lines 300 intersect the active layers 200, extend along the second horizontal direction Y, and are disposed on corresponding active layers 200 in the second horizontal direction Y, forming the gate electrodes of the transistors Tr. The gate electrodes cover the channel regions of the active layers 200. A gate dielectric layer is further included between the word lines 300 and the active layers 200. In the present disclosure, the gate electrodes of the transistors can be GAA (Gate all around), CAA (Channel all around), double-gate (DG), or single-gate (SG) gate electrodes. For example, a double-gate (DG) gate electrode is used. In this case, the word line 300 is also a corresponding horizontal double word line. Each word line 300 includes a pair of conductive lines disposed on two opposite surfaces of the active layer 200 in the vertical direction Z.

[0036] The material of the gate dielectric layer can be selected from at least one of silicon oxide, silicon nitride, silicon oxynitride, and a high-k dielectric film having a dielectric constant higher than that of silicon oxide, such as hafnium oxide (HfO2), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), hafnium aluminum oxide (HfAlO3), lanthanum oxide (LaO), aluminum lanthanum oxide (LaAlO), and zirconium oxide (ZrO).

[0037] The material of word line 300 can be selected from at least one of doped polysilicon, metal, metal nitride or metal carbide, such as tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), titanium aluminum carbide (TiAlC), titanium aluminum carbonitride (TiAlCN), titanium silicon carbonitride (TiSiCN), tantalum aluminum carbonitride (TaAlCN) and tantalum silicon carbonitride (TaSiCN).

[0038] Please continue to refer to Figures 2A to 2B At least one bit line 400 extending along the vertical direction Z is formed in the stacked layer ST. In some embodiments, a plurality of bit lines 400 are formed. The plurality of bit lines 400 are arranged spaced apart from each other along the first horizontal direction X and the second horizontal direction Y, and each bit line 300 extends along the vertical direction Z. Figure 2A and Figure 2B As shown, each bit line 300 contacts one end of the plurality of active layers 200 in the vertical direction Z, such as the first source / drain region of the active layer 200. It is worth noting that the bit line 400 is shared between adjacent memory cells in the first horizontal direction X, and the two are mirror-symmetric with each other about the bit line 400.

[0039] The material of the bit line 300 can be selected from at least one of doped polysilicon, metal, metal nitride or metal carbide, such as tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), titanium aluminum carbide (TiAlC), titanium aluminum carbonitride (TiAlCN), titanium silicon carbonitride (TiSiCN), tantalum aluminum carbonitride (TaAlCN) and tantalum silicon carbonitride (TaSiCN).

[0040] Please refer to Figure 3 At least one vertical opening 100A is formed in the stacked layer ST. The vertical opening 100A is between adjacent word lines 300 in the first horizontal direction X, providing a deposition space for the subsequent formation of the capacitor 400. Please continue to refer to Figure 3, forming a vertical opening 100A that penetrates the stacked layer ST and extends into the substrate 100, forming a cavity 100B within the substrate. The substrate cavity 100B includes a bottom wall 101 and two sidewalls 102 located on either side of the bottom wall 101. The two sidewalls 102 oppose each other. The vertical opening 100A extends along the second horizontal direction Y, exposing the first sacrificial layer 110, the second sacrificial layer 120, and the third sacrificial layer 130 in the stacked layer ST, as well as a portion of the surface of the substrate 100. The vertical opening 100A separates the initial active layer 200a in the first horizontal direction X, forming an intermediate active layer 200b.

[0041] Please refer to Figure 4 A conformal first protective material 141 is formed in the vertical opening 100A. The first protective material covers the surfaces of the first sacrificial layer 110, the second sacrificial layer 120, the third sacrificial layer 130, and the surface of the substrate cavity 100B. Figure 4 The first protective material 141 located on the bottom wall 101 of the cavity and the top surface of the stacked layer ST is removed, so that the bottom wall 101 of the substrate 100 extending along the second horizontal direction Y is exposed again. The remaining first protective material 141 is located on the sidewalls of the vertical opening 100A, covering the side surfaces of the first sacrificial layer 110, the second sacrificial layer 120, and the third sacrificial layer 130, as well as the cavity sidewalls 102.

[0042] The first protective material 141 is, for example, a silicon oxide layer formed by an atomic layer deposition (ALD) process, which has not only a relatively ideal density but also a uniform thickness, and can well cover the material surface, provide a barrier, and protect the substrate surface for subsequent process steps.

[0043] Please refer to Figure 5, a second protective material 142 is filled in the cavity 100B of the substrate 100 along the vertical opening 100A. The second protective material 142 covers the bottom wall 101 of the cavity and extends from the substrate 100 toward the stacked layer ST. The extension height of the second protective material 142 is less than or equal to the height of the top surface of the second layer 110-2 in the multiple first sacrificial layers, and is greater than or equal to the height of the top surface of the substrate 100. In some embodiments, the extension height of the second protective material 142 is less than the height of the top surface of the second layer 110-2 in the multiple first sacrificial layers. In some embodiments, the extension height of the second protective material 142 is higher than the height of the top surface of the substrate 100. When the extension height H110 of the protective layer 150 is too low, for example, lower than the top surface of the substrate 100, it will be difficult to protect the shoulder of the substrate 100. During lateral wet etching, the shoulder of the substrate 100 may be easily damaged, resulting in device failure. When the extension height H110 of the protection layer 150 is too high, for example, higher than the first sacrificial layer 110-2 of the second layer, it is easy to affect the devices in the memory cells in the second layer, thereby reducing the integration density of the semiconductor device. Figure 5 As shown, in some embodiments, the second protection material 142 extends to the top surface of the first sacrificial layer 110 - 1 (ie, the first sacrificial layer 110 - 1 located on the top surface of the substrate 100 and having the first thickness H1 ).

[0044] Please continue to refer to Figure 5 In one embodiment of the present disclosure, a single-crystal silicon-germanium (SiGe) layer is selectively and directionally grown along the vertical opening 100A on the substrate surface of the exposed cavity bottom wall 101, using a selective epitaxial growth (SEG) process, for example. The SiGe layer completely fills the cavity 100B within the substrate 100 and extends over a portion of the first sacrificial layer 110-1. The SiGe layer extends along a second horizontal direction Y. The first protective material 141 is located between the SiGe layer and the cavity sidewall 102. In this embodiment, the SiGe layer and the silicon substrate 100 have similar lattices. The SiGe layer, grown directionally on the cavity bottom wall 101, not only simplifies the process and maintains a regular morphology, but also minimizes the impact on other process steps or device performance. During etching, such as wet etching, of the second sacrificial layer 102 in the stack, which is made of the same material as the substrate 100, the SiGe layer is not completely consumed, thereby protecting the surface of the substrate 100.

[0045] Of course, in other embodiments, a single crystal silicon layer (Si) can be selectively and directionally grown on the substrate surface of the exposed cavity bottom wall 101 through a selective epitaxial growth (SEG) process. Specifically, single crystal silicon doped with P-type ions, such as single crystal silicon doped with boron (B) ions, can be epitaxially grown to form multi-hole P-type silicon, thereby suppressing the etching rate of the silicon layer by the etching solution during the wet etching process.

[0046] Please refer to Figure 6 The first protective material 141 exposed by the vertical opening 100A is removed. Specifically, the first protective material 141 not covered by the second protective material 142 is removed, exposing the first sacrificial layer 110, the second sacrificial layer 120, and the third sacrificial layer 130 located on the sidewalls of the vertical opening 100A. The remaining first protective material 141 is located on the cavity sidewalls 102, while the second protective material 142 is located on the cavity bottom wall 101. The top surfaces of the two are flush and in contact with each other, forming an exemplary protective layer 140 of the present disclosure.

[0047] Please refer to Figure 7 Continuing with the protective layer 140 as an etch stop layer, a portion of the second sacrificial layer 120 in the stacked layer ST is laterally etched along the vertical opening 100A, forming a plurality of side cavities 100C spaced apart in the first horizontal direction X, the second horizontal direction Y, and the vertical direction Z. The remaining plurality of second sacrificial layers 120 form the final plurality of active layers 200, that is, the active layer 200 is formed from the intermediate active layer 200b. At this point, according to the embodiment of the present disclosure, the plurality of active layers 200 are spaced apart in the vertical direction Z, the first horizontal direction X, and the second horizontal direction Y, forming a three-dimensional array on the substrate 100, thereby forming a three-dimensional semiconductor device. The active layer 200 is located between the word lines 300, with one end of the active layer 200 in the first horizontal direction X contacting the bit line 400 and the other end being exposed by the side cavity 100C. After a plurality of lower electrodes 510 of the capacitor structure 500 are subsequently formed in the plurality of side cavities 100C, the active layer 200 contacts the lower electrode 510 at the other end in the first horizontal direction X.

[0048] In the disclosed embodiment, the second sacrificial layer 120 is undercut by lateral wet etching. By controlling factors such as the type of etchant and the etching rate during the wet etching process, the second sacrificial layer 120 can be removed relatively completely, and the resulting active layer 200 has a regular morphology, effectively improving the electrical performance of the device. In the disclosed embodiment, the second sacrificial layer 120 and the substrate 100 are made of the same material. Before the lateral wet etching of the second sacrificial layer 120 is performed, a protective layer 140 is formed on the exposed surface of the substrate 100 to protect the substrate 100 surface and effectively reduce damage to the substrate 100.

[0049] Please refer to Figure 8and Figure 9 The plurality of side cavities 100C are connected to the vertical opening 100A to form a comb-shaped opening space. For example, the lower electrode material 510' is deposited along the comb-shaped opening space. The lower electrode material 510' conformally covers the surfaces of the first sacrificial layer 110, the second sacrificial layer 120, the third sacrificial layer 130, and the protective layer 140. Figure 9 Along the vertical opening 100A, the lower electrode material 510' exposed within the vertical opening 100A is removed, forming a plurality of lower electrodes 510 spaced apart from one another in the first horizontal direction X, the second horizontal direction Y, and the vertical direction Z. The plurality of lower electrodes 510 are respectively located within the plurality of side cavities 100C, that is, within the space enclosed by the active layer 200, the first sacrificial layer 110, and the second sacrificial layer 130. The lower electrodes 510 are horizontally oriented U-shaped cylinders with their openings facing the vertical opening 100A.

[0050] Please refer to Figure 10 , a capacitor dielectric layer 520 is formed on the surface of the multiple lower electrodes exposed in the comb-shaped opening space along the vertical opening 100A. The capacitor dielectric layer 520 is located on the inner and outer wall surfaces of the U-shaped cylindrical lower electrode 510. Further, as Figure 10 As shown, the first capacitor dielectric layer 520 is a continuous layer, which is also located on the surface exposed by the vertical opening 100A and contacts the protection layer 140 .

[0051] Please refer to Figures 11A to 11C Continuing along the vertical opening 100A, an upper electrode 530 is formed on the surface of the capacitor dielectric layer 520. The upper electrode 530 fills the remaining space in the comb-shaped opening. The upper electrode 530 can also be referred to as a common electrode. The multiple lower electrodes 510, the capacitor dielectric layer 520, and the upper electrode 530 constitute the capacitor structure 500. It is noteworthy that, as shown in FIG11 , the capacitor structures between adjacent memory cells in the first horizontal direction X are formed simultaneously, and the two are mirror-symmetric with respect to each other about the upper electrode 530.

[0052] The material of the lower electrode 510 can be selected from at least one of a metal, a metal nitride, or a metal oxide, such as tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), platinum (Pt), iridium (Ir), titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), iridium oxide (IrO2), and titanium oxide (TiO). In some embodiments, the lower electrode 510 is, for example, a titanium nitride layer.

[0053] The material of capacitor dielectric layer 520 can be selected from at least one of high-k dielectric films having a higher dielectric constant than silicon oxide, such as hafnium oxide (HfO2), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), hafnium aluminum oxide (HfAlO3), lanthanum oxide (LaO), aluminum lanthanum oxide (LaAlO), and zirconium oxide (ZrO). In some embodiments, capacitor dielectric layer 520 is, for example, a composite layer of hafnium oxide and zirconium oxide.

[0054] The material of the top electrode 530 can be selected from at least one of doped polysilicon, metal, metal nitride, or metal oxide, such as tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), platinum (Pt), iridium (Ir), titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), iridium oxide (IrO2), and titanium oxide (TiO). In some embodiments, the top electrode comprises a composite layer of titanium nitride and polysilicon, with the polysilicon layer and the titanium nitride layer in contact with each other. For example, a titanium nitride layer can be conformally deposited on the surface of the capacitor dielectric layer 520. Subsequently, a polysilicon layer is deposited along the vertical opening 100A in the remaining space of the comb-shaped opening to form the top electrode 530. The top electrode 530 is a unitary layer, and the portion of the first top electrode 530 located within the vertical opening 100A extends along the second horizontal direction Y.

[0055] Figures 12 to 14 Schematic diagrams of the various stages of a semiconductor device fabrication method in another embodiment are shown. In this embodiment, based on the previous embodiment, after forming multiple side cavities, the protective layer is further processed to form a protective layer 150 of another embodiment. In this embodiment, the protective layer 150 includes a cavity, a silicon oxide layer with pores located above the cavity, and a silicon oxide layer located on the sidewalls of the cavity. This embodiment can isolate device layers, such as the contact between the electrode layer and gate electrode in a capacitor and the substrate 100, thereby improving leakage current between the two.

[0056] Please refer to Figure 7 , and please refer to Figure 12Using a protective layer 140 comprising a silicon germanium layer 142 and a silicon oxide layer 141 as an etch stop layer, the second sacrificial layer 120 in the stacked layer ST is laterally etched to form multiple side cavities 100C. The silicon germanium layer 142 is then thermally oxidized to form a silicon germanium oxide layer (SiGeOx) 143. In some embodiments, a high-temperature thermal annealing process, such as at 900°C to 1000°C, is performed in the presence of an oxygen source to thermally oxidize the surface of the silicon germanium layer 142, forming the silicon germanium oxide layer 143. The silicon germanium oxide layer 143 is located on the remaining silicon germanium layer 142. The silicon germanium oxide layer 143 is located on the surface of the silicon germanium layer 142 and is relatively thin, approximately one-fifth to one-third, for example, one-quarter, of the thickness of the initial silicon germanium layer. The oxidized silicon germanium layer provides more stable properties, and Ge atoms are enriched and increased in concentration at the interface between the underlying silicon germanium layer 142 and the overlying silicon germanium oxide layer 143.

[0057] Afterwards, please refer to Figure 13 Afterwards, the underlying silicon-germanium layer 142 is removed to form a cavity 144. In this embodiment, an acidic gas, such as hydrogen chloride (HCl), is used to first remove Ge atoms from the silicon-germanium oxide layer 143, thereby forming a pore. The HCl gas then continues along the pore, removing the remaining silicon-germanium layer 142 beneath the silicon-germanium oxide layer 143, forming a cavity 144. Cavity 144 exposes the silicon oxide layer 141 located on the cavity sidewalls 100 and the substrate 100 located on the cavity bottom wall 101. After the Ge atoms are removed from the upper silicon-germanium oxide layer 143, a silicon oxide layer 145 with pores is formed. The silicon oxide layer 141 located on the cavity sidewalls, the silicon oxide layer 145 with pores, and the cavity 144 form a protective layer 150 according to another exemplary embodiment of the present disclosure. The silicon oxide layer 145 with pores is located between and contacts the silicon oxide layer 141 on the cavity sidewalls. The cavity 144 is located below the silicon oxide layer 145 having pores, and the cavity 145 exposes the silicon oxide layer 141 on the sidewalls of the cavity and the substrate 100 on the bottom wall of the cavity.

[0058] It is worth noting that in this embodiment, the step of forming the cavity 144 is performed after the second sacrificial layer 120 is laterally etched. This can fully avoid the etching solution flowing into the cavity of the substrate 100 due to adverse conditions such as the pores or the silicon germanium oxide layer 143 being too thin, thereby damaging the protective layer 150 and the substrate 100 and affecting the device performance.

[0059] Afterwards, please refer to Figure 14A capacitor structure 500 comprising multiple lower electrodes 510, a capacitor dielectric layer 520, and an upper electrode 530 is formed within the comb-shaped opening space along vertical opening 100A. The capacitor dielectric layer 520 contacts the protective layer 150 and conformally covers the surface of the silicon oxide layer 145 having pores and the surface of the silicon oxide 141 on the sidewalls of the cavity. In this embodiment, leakage current between the device and the substrate 100 can be further reduced.

[0060] Figures 15 to 22 Schematic diagrams of various stages of a semiconductor device fabrication method according to other embodiments are shown. Another embodiment shows a protective layer 180 that does not completely fill the trench within substrate 100. Instead, it is located on the cavity bottom wall 101 and both sidewalls 102 of substrate 100, and further on a portion of the top surface of substrate 100, contacting the first sacrificial layer 110-1 of the first layer. In this embodiment, protective layer 180 does not extend onto the memory cells of the second layer, providing more vertical space for integration and improving integration density.

[0061] Please refer back to Figure 3 and Figure 15 After forming the vertical opening 100A, a fourth sacrificial layer 160 is formed in the vertical opening 100A to conformally cover the fourth sacrificial layer 160, and a fifth sacrificial layer 170 is formed on the surface of the fourth sacrificial layer 160 exposed by the vertical opening 100A. Figure 15 The fifth sacrificial layer 170 located on the cavity bottom wall 101 of the substrate 100 and the top surface of the stacked layer ST is removed along the vertical opening 100A, exposing the fourth sacrificial layer 160 located on the cavity bottom wall 101. The remaining fifth sacrificial layer 170 is located on the sidewalls of the fourth sacrificial layer 160.

[0062] In this embodiment, the fourth sacrificial layer 160 is, for example, a silicon oxide layer or a silicon nitride layer formed by an atomic layer deposition (ALD) process. The fifth sacrificial layer 170 is, for example, a silicon nitride layer, a carbon layer, or a polysilicon layer formed by an ALD process. The thickness of the fourth sacrificial layer 160 can be greater than that of the fifth sacrificial layer 170. The fifth sacrificial layer 170 is located on the surface of the fourth sacrificial layer 160 and forms a barrier when a portion of the fourth sacrificial layer 160 is subsequently removed to form the protective layer 150.

[0063] Please refer to Figure 16The fourth sacrificial layer 160 is etched downward along the vertical opening 100A, for example, by wet etching to remove the fourth sacrificial layer 160 located on the surface of the substrate 100, that is, the bottom wall 101 and the side wall 102. Furthermore, part of the first sacrificial layer 110-1 on the top surface of the substrate 100 is further removed to expose the shoulder of the substrate 100 to form a sacrificial space 100D.

[0064] Please refer to Figure 17 , forming a protective layer 180 in the concave cavity 100B of the substrate. Specifically, in some embodiments, the fifth sacrificial layer 170 is removed, and then, for example, a portion of the substrate is oxidized by an in-situ steam growth (ISSG) process to form a silicon oxide layer. The silicon oxide layer consumes the silicon layer on the surface of the substrate. The thickness of the silicon oxide layer is relatively thick, greater than or equal to 30nm. The silicon oxide layer is located on the bottom wall 101 and sidewall 102 of the substrate, and a portion of the top surface of the substrate 100, contacting the first sacrificial layer 110-1. The fourth sacrificial layer 160 protects the surface of the second sacrificial layer 120 exposed in the vertical opening 100A from oxidation.

[0065] Please continue to refer to Figure 17 , the protective layer 180 can be formed by a single in-situ water vapor growth process. For example, a first in-situ water vapor growth process can be performed on the surface of the exposed substrate at a pressure of 0-5 Torr and a temperature of 900-1000°C to form a first silicon oxide layer 181. At this time, the first silicon oxide layer 181 effectively reduces oxide layer defects through the temperature, improves the interface reliability of Si-SiO2, and forms a high-end morphology through the pressure, thereby better covering the exposed top surface of the substrate 100.

[0066] Please refer to Figure 18 In other embodiments of the present disclosure, the protective layer 180 can also be formed by performing multiple in-situ water vapor growth processes, such as two, three, or four times. For example, a high-quality, highly uniform silicon oxide layer can be formed by performing two in-situ water vapor growth processes. The first ISSG process can form a first silicon oxide layer 181 at a pressure of 0-5 Torr and a temperature of 900-1000°C. Subsequently, a second ISSG process is performed, for example, at a pressure of 10-15 Torr and a temperature of 700-850°C to form a second oxide layer 182. The first ISSG process reduces oxide layer defects at high temperatures, improves Si-SiO2 interface reliability, and forms a high-end morphology at lower pressures. The second ISSG process reduces the reaction rate at low temperatures and complements the oxide layer formed by the first ISSG process at higher pressures, thereby improving the morphology of the first silicon oxide layer 181. The first silicon oxide layer 181 and the second silicon oxide layer 182 form the protective layer 180 of the exemplary embodiment of the present disclosure.

[0067] Afterwards, please refer to Figure 19 A protective layer 180 including a third silicon oxide layer 183 may also be formed. For example, the third silicon oxide layer 183 is formed on the surface of the first silicon oxide layer using an atomic layer deposition (ALD) process. The third silicon oxide layer 183 occupies the location formerly occupied by the fourth sacrificial layer 160. The third silicon oxide layer 183 contacts the first sacrificial layer 110-1 of the first layer. The first silicon oxide layer 181, the second silicon oxide layer 182, and the third silicon oxide layer 183 form the protective layer 180 of the exemplary embodiment of the present disclosure.

[0068] Please refer to Figure 20 The remaining fourth sacrificial layer 160 in the vertical opening 100A is removed, so that the first sacrificial layer 110 , the second sacrificial layer 120 , and the third sacrificial layer 130 on the sidewalls of the vertical opening 100A are exposed again. A protective layer 180 covers the surface of the substrate 100 .

[0069] Please refer back to Figure 7 , and please refer to Figure 21 , continuing to use the protective layer 180 as an etching stop layer, a portion of the second sacrificial layer 120 in the stacked layer ST is laterally wet-etched along the vertical opening 100A to form a plurality of side cavities 100C. The plurality of side cavities 100C are connected to the vertical opening 100A to form a comb-shaped opening space. A capacitor structure 400 including a plurality of lower electrodes 510, a capacitor dielectric layer 520, and an upper electrode 530 is formed in the comb-shaped opening space along the vertical opening 100A. In this embodiment, when the second sacrificial layer 120 is laterally wet-etched, the protective layer 150 of the silicon oxide layer formed by the ISSG process can improve damage to the substrate and improve leakage current between the device and the substrate 100.

[0070] Please refer to Figure 22The present disclosure also provides an electronic device 1 having a storage function. The electronic device includes a processor 2 and a memory device 3 electrically connected to the processor. The memory device 3 includes the semiconductor device 4 described in Figures 1 to 21 above. The electronic device can be a terminal device, such as a personal computer, a mobile phone, a tablet computer, a consumer electronics product such as a smart home appliance, an autonomous driving device, a smart wearable product (such as a smart watch or a smart bracelet), a virtual reality (VR) device, an augmented reality (AR) device, or a server, a data center, etc. The memory device 3 can be, for example, a high-performance, high-bandwidth, high-density non-volatile dual in-line memory module (NVDIMM) or a storage class memory (SCM). The storage function in the electronic device 1 can be implemented through these memory devices 3.

[0071] In some embodiments, the processor 2 and the memory 3 can be two independent chips to form an independent memory. In other embodiments, the memory 3 and the processor 2 can also be integrated into the same chip to form an embedded memory. Figure 21 The described semiconductor device 4 can solve the same technical problem and achieve the same expected effect.

[0072] The above are only specific embodiments of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A method for preparing a semiconductor device, characterized in that: include: Providing a substrate, and forming a stacked layer of a plurality of first sacrificial layers and a plurality of second sacrificial layers arranged alternately on the substrate, wherein the second sacrificial layers and the substrate are made of the same material; forming a vertical opening penetrating the stacked layers, wherein the vertical opening extends into the substrate to form a cavity in the substrate; forming a protective layer in the cavity of the substrate; Using the protective layer as an etching stop layer, a portion of the second sacrificial layer in the stacked layer is laterally etched along the vertical opening to form a plurality of side cavities spaced apart in the vertical direction; forming a plurality of lower electrodes on the surfaces of the second sacrificial layer exposed in the plurality of side cavities respectively; forming a capacitor dielectric layer on the surfaces of the plurality of lower electrodes, wherein the capacitor dielectric layer is also located within the vertical opening and in contact with the protective layer; An upper electrode is formed on the surface of the capacitor dielectric layer, wherein the plurality of lower electrodes, the capacitor dielectric layer and the upper electrode constitute a capacitor structure.

2. The preparation method according to claim 1, characterized in that The protective layer extends from the substrate toward the stacked layer, and the extension height of the protective layer is less than or equal to the height of the top surface of the second layer of the multiple first sacrificial layers, and greater than or equal to the height of the top surface of the substrate, wherein the first layer of the multiple first sacrificial layers is located on the top surface of the substrate.

3. The preparation method according to claim 1 or 2, characterized in that Forming a protective layer in the cavity of the substrate includes: forming a silicon oxide layer on the sidewall of the cavity; A silicon germanium layer is formed on the bottom wall of the cavity. The silicon germanium layer fills the cavity and contacts the silicon oxide layer.

4. The preparation method according to claim 3, characterized in that After forming the plurality of side cavities, the preparation method further includes processing the protective layer, including: Oxidizing the surface of the silicon germanium layer to form a silicon germanium oxide layer, wherein the silicon germanium oxide layer is located on the remaining silicon germanium layer; removing germanium atoms in the silicon germanium oxide layer by acidic gas to form a silicon oxide layer having pores; The remaining silicon germanium layer is continuously removed along the pores by the acid gas to form a cavity. The cavity is located below the silicon oxide layer having the pores and exposes the silicon oxide layer on the sidewalls of the cavity and the substrate on the bottom wall of the cavity.

5. The preparation method according to claim 1 or 2, characterized in that Forming a protective layer in the cavity of the substrate includes: forming a silicon oxide layer on the sidewall of the cavity; A boron-doped silicon layer is formed on the bottom wall of the cavity. The boron-doped silicon layer fills the cavity and is in contact with the silicon oxide layer.

6. The preparation method according to claim 1, characterized in that Forming a protective layer in the cavity of the substrate includes: Performing a first in-situ water vapor growth process on the exposed surface of the substrate at a pressure of 0-5 Torr and a temperature of 900-1000° C. to form a first silicon oxide layer; and / or, A second in-situ water vapor growth process is performed at a pressure of 10-15 Torr and a temperature of 700-850° C. to form a second silicon oxide layer.

7. The preparation method according to claim 1, characterized in that The preparation method further comprises: forming a plurality of active layers spaced apart along the vertical direction in the stacked layers, wherein the active layers extend along a first horizontal direction and are formed by the second sacrificial layer; forming a plurality of word lines spaced apart along the vertical direction in the stacked layer, wherein the word lines are disposed on the active layer and extend along a second horizontal direction intersecting the first horizontal direction; At least one bit line extending along the vertical direction is formed in the stacked layer, and two ends of the active layer in the first horizontal direction respectively contact the bit line and the lower electrode of the capacitor structure.

8. A semiconductor device, characterized in that: include: a substrate having a cavity; a protective layer located in the cavity of the substrate; A capacitor is located on the substrate, and the capacitor includes: A plurality of lower electrodes are arranged on the substrate at intervals along the vertical direction; a capacitor dielectric layer, located on the surfaces of the plurality of lower electrodes, wherein the capacitor dielectric layer and the protective layer are in contact with each other; an upper electrode, located on the surface of the capacitor dielectric layer; The protective layer comprises: a silicon oxide layer located on a sidewall of the cavity; a silicon oxide layer having pores, located between the silicon oxide layers on the sidewalls of the cavity and contacting the silicon oxide layer on the sidewalls of the cavity; and a cavity, located below the silicon oxide layer having pores, wherein the cavity exposes the silicon oxide layer on the sidewalls of the cavity and the substrate on the bottom wall of the cavity; The capacitor dielectric layer conformally covers the surface of the silicon oxide layer having pores and the surface of the silicon oxide on the sidewall of the cavity.

9. The semiconductor device according to claim 8, wherein The semiconductor device further includes: A plurality of active layers are arranged at intervals along the vertical direction, and the active layers extend along a first horizontal direction; a plurality of word lines arranged at intervals along the vertical direction, the word lines being disposed on the active layer and extending along a second horizontal direction intersecting the first horizontal direction; At least one bit line extends along the vertical direction, and two ends of the active layer in the first horizontal direction respectively contact the bit line and the lower electrode of the capacitor structure.

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