Gallium oxide field effect transistor with high breakdown voltage and manufacturing method thereof

Abstract

The invention discloses a high-breakdown-voltage gallium oxide field effect transistor which mainly solves the problems that in the prior art, the electric field concentration effect on the surface of a channel layer cannot be improved in the longitudinal direction, improvement of electric field distribution is relatively limited, and the breakdown voltage of a device is affected. The device comprises a substrate layer, a buffer layer, a channel layer, a source and drain electrode layer, a gate dielectric layer, a gate, a field dielectric layer, a metal field plate and a gate test plate from bottom to top. Five different types of gradient doping concentration channels are transversely distributed on the channel layer, a p-type material layer is arranged between the source electrode layer and the drain electrode layer, and the p-type material layer and the n-type gallium oxide form a PN junction; the field dielectric layers and the metal field plates are arranged in at least three layers, and the field dielectric layers and the metal field plates are alternately distributed up and down to form a multi-layer composite structure, so that a plurality of new electric field peak values are introduced into corners of each layer of stepped gate field plate. The electric field peak value of the side, close to the drain electrode, of the grid electrode is reduced, the electric field concentration effect of the channel surface is improved in the longitudinal direction, and the breakdown voltage is improved. The method can be used for power electronic devices.

Description

Technical Field

[0001] The present invention belongs to the field of microelectronics technology, and in particular relates to a gallium oxide field effect transistor which can be used for power electronic devices. Background Art

[0002] Gallium oxide is a new type of ultra-wide semiconductor material. The advantage of gallium oxide material lies in its extremely wide bandgap width, which is about 4.8-4.9eV at room temperature. It can be used in power devices. Compared with other semiconductor materials such as Si, SiC, GaN, etc., gallium oxide material has a higher bandgap width and a larger breakdown field strength. Its theoretical breakdown field strength can reach 8MV / cm. The Baliga figure of merit of gallium oxide material is as high as 3444, far exceeding that of materials such as Si, SiC, GaN, etc., indicating that gallium oxide material has greater potential in power devices. In addition, large-scale high-quality gallium oxide single crystals can be made by melting method with low production cost. With the rapid development of gallium oxide single crystal growth technology, as well as the realization of high-quality epitaxy and controllable n-type doping technology, gallium oxide has broad application prospects in the field of power electronic devices.

[0003] Although the maximum breakdown electric field of current gallium oxide devices has exceeded the theoretical limits of GaN and SiC, it is still far from the theoretical limits of gallium oxide, and there is still a lot of room for improvement in the withstand voltage characteristics of gallium oxide devices. The main reason for limiting the withstand voltage characteristics of gallium oxide devices is the electric field concentration effect in the channel layer of the device at high voltage. This effect causes the electric field peak to form locally in the area on the surface of the channel layer near the drain side of the gate. When the electric field peak exceeds the limit of the gallium oxide material, the device breaks down. Field plate technology is commonly used to increase the breakdown voltage of power devices, including gate field plates and source field plates. This technology can form a new electric field peak at the edge of the field plate, improve the electric field distribution, and thus increase the breakdown voltage of the device. However, ordinary field plates can only improve the electric field distribution on the side of the gate near the drain in the channel layer in the lateral direction, and their effect on improving the electric field distribution is limited. Therefore, how to better improve the electric field distribution in the channel layer of the device under high voltage, and further increase the breakdown voltage of the device while maintaining a small on-resistance, a large on-current, and a high threshold voltage, has become an important problem to be solved in the research of gallium oxide field-effect transistors, and has also become a major direction for many scientific researchers to study gallium oxide.

[0004] In recent years, researchers have proposed many improved device structures based on this problem, for example. Regarding horizontal device structures, several different structures have been proposed: one is the field plate structure of the gate field plate and the source field plate and the combination of the two field plates, the third is the inclined gate structure, and the fourth is the super junction structure formed by using p-type NiO and other p-type materials and n-type gallium oxide. For vertical devices, three structures have also been proposed, (1) fin gate structure, namely FinFET vertical structure field effect transistor, (2) vertical field effect transistor with current aperture, (3) vertical field effect transistor using n+ contact layer and n- drift layer to form a trench structure, etc.

[0005] Since the horizontal structure has relatively simpler manufacturing steps and less difficult manufacturing process than the vertical structure, the current main research direction is still focused on horizontal devices.

[0006] In his doctoral dissertation "Research on High-Power Metal Oxide Semiconductor Field-Effect Transistors Based on β-Ga2O3" at Xidian University, Feng Zhaoqing proposed a structural solution of adding a gate field plate, a source field plate, and a gate field plate combined with a source field plate to the gallium oxide field effect transistor, such as Figure 1 As shown, Figure 1 (a) is a conventional structure, 1(b) is a gate field plate structure, 1(c) is a source field plate structure, and 1(d) is a structure of a gate field plate combined with a source field plate.

[0007] The device of the gate field plate and source field plate structure introduces a new electric field peak at the edge of the field plate to disperse the electric field concentration effect and improve the electric field concentration effect phenomenon near the gate.

[0008] The device of the gate field plate combined with the source field plate structure introduces two new electric field peaks at the two field plates through the action of two layers of field plates, so that the peak field strength is concentrated at the metal edge of the field plate, which better improves the electric field distribution in the channel and further reduces the field strength at the gate edge.

[0009] However, since these structures can only introduce two new electric field peaks at most, their improvement on the electric field concentration effect is limited.

[0010] In his article Source-Field-Platedβ-Ga2O3 MOSFET With Record Power Figure of Merit of 50.4MW / cm2, Yuanjie Lv proposed adding a source field plate structure to the gallium oxide field effect transistor, such as Figure 2As shown in the figure. The research results of the device with the source field plate structure show that the breakdown voltage of the device with the source field plate increased from 310V to 680V compared with the device without the field plate, and the breakdown electric field was greatly improved. This is due to the introduction of a new electric field peak at the metal edge of the source field plate, which improves the electric field distribution in the channel and alleviates the electric field concentration effect near the gate. However, compared with the electric field distribution of the ordinary structure, this structure only introduces a new electric field peak, which fails to greatly improve the breakdown voltage of the device.

[0011] In summary, although the field plate structure of the existing horizontal device has the advantages of less difficulty in manufacturing process, improved withstand voltage characteristics and better stability compared with other structures, for the electric field concentration effect in the channel layer of the device at high voltage, this field plate structure can only improve the electric field distribution on the side of the gate close to the drain in the channel layer in the horizontal direction, and fails to improve the electric field concentration effect on the surface of the channel layer in the vertical direction, and the improvement effect on the electric field distribution is relatively limited. Summary of the invention

[0012] The purpose of the present invention is to address the deficiencies of the prior art and propose a high breakdown voltage gallium oxide field effect transistor and a method for manufacturing the same, so as to improve the electric field distribution on the surface of the channel layer in both the lateral and longitudinal directions, thereby maximizing the breakdown voltage of the device; at the same time, the device is ensured to have a higher threshold voltage and good gate control capability, a smaller on-resistance and a larger on-current, so that the device has better power characteristics.

[0013] To achieve the above object, the technical solution of the present invention is as follows:

[0014] 1. A high breakdown voltage gallium oxide field effect transistor structure, comprising from bottom to top: a substrate layer 1, a buffer layer 2, a channel layer 3, a source layer 4, a drain layer 5, a gate dielectric layer 7, a gate 8, a field dielectric layer 9, a metal field plate 10, and a gate test plate 11, characterized in that:

[0015] The channel layer 3 includes a laterally distributed channel layer 31 under the source, a channel layer 32 between the source and the gate, a channel layer 33 under the gate, a channel layer 34 between the gate and the drain, and a channel layer 35 under the drain, and the doping concentration is the highest in the channel layer 31 under the source and the channel layer 35 under the drain, the channel layer 32 between the source and the gate and the channel layer 34 between the gate and the drain are the second, and the channel layer 33 under the gate is the lowest, so as to uniformly distribute the electric field and reduce the electric field peak on the side of the upper gate of the channel close to the drain;

[0016] The source and drain layer is provided with a p-type material layer 6 between the source layer 4 and the drain layer 5 to form a PN junction with the n-type gallium oxide to alleviate the electric field concentration effect on the surface of the channel layer;

[0017] The field dielectric layer 9 and the metal field plate 10 are at least three layers each, and are alternately distributed up and down, i.e., the first field dielectric layer 91, the first metal field plate 101, the second field dielectric layer 92, the second metal field plate 102, the third field dielectric layer 93, the third metal field plate 103, ... the nth field dielectric layer, the nth metal field plate, so as to introduce multiple new electric field peaks at the corners of each layer of the stepped gate field plate to reduce the original electric field peak of the gate close to the drain side and improve the breakdown voltage.

[0018] Furthermore, the material of the substrate 1 is a semi-insulating β-Ga2O3 material doped with Mg or Fe; and the material of the buffer layer is an unintentionally doped β-Ga2O3 material.

[0019] Furthermore, the channel layer 3 is an n-type semiconductor, the doping element of which is Si or Sn, and the doping concentration of the channel layer 31 under the source and the channel layer 35 under the drain is 1*10 18 -1*10 20 cm -3 The doping concentration of the channel layer 32 between the source and the gate and the channel layer 34 between the gate and the drain is 1*10 17 -1*10 19 cm -3 The doping concentration of the channel layer 33 under the gate is 1*10 16 -1*10 18 cm -3 , the thickness of each channel layer is 150nm-250nm.

[0020] Furthermore, the material of the source and drain is a superposition of Ti metal and Au metal, and the thickness of the Ti metal is 20nm-60nm, and the thickness of the Au metal is 120nm-180nm; the material of the gate is a superposition of Ni metal and Au metal, and the thickness of the Ni metal is 20nm-60nm, and the thickness of the Au metal is 120nm-180nm.

[0021] Furthermore, the p-type material layer 6 is made of p-type NiO or p-type CuO material, with a thickness of 20nm-100nm and a doping concentration of 1*10 17 -1*10 19 cm -3 The gate dielectric layer 7 is made of Al2O3, HfO2 or SiO2 high-k material with a thickness of 10nm-30nm.

[0022] Furthermore, the material of each layer of field dielectric is SiN or SiO2, with a thickness of 100nm-300nm; the material and thickness of each layer of metal field plate are consistent with those of the gate.

[0023] Furthermore, the lateral distances between the metal field plates from the first layer to the Nth layer and the gate gradually increase, and the lateral distances between the metal field plates and the drain gradually decrease, and each layer is located between the gate and the drain in the lateral direction.

[0024] 2. A method for preparing a high breakdown voltage gallium oxide field effect transistor, comprising the following steps:

[0025] S1) selecting a semi-insulating substrate material having an unintentionally doped buffer layer of β-Ga2O3, and cleaning and surface treating the substrate material;

[0026] S2) performing homoepitaxial growth on the buffer layer by molecular beam epitaxy (MBE) on the cleaned substrate to generate an n-type β-Ga2O3 channel layer with a thickness of 150nm-250nm;

[0027] S3) cleaning and surface treatment are performed on the surface of the channel layer;

[0028] S4) photolithography is performed on the sample after the above steps through a mesa isolation region photomask, and then the mesa of the sample is etched by RIE equipment using BCl3 and Ar until the substrate layer is formed to form small isolation blocks with equal intervals, wherein the etching depth of the substrate layer is greater than 100nm;

[0029] S5) After the sample with the isolated small block is photolithographically formed by the photomask in the area between the source and the gate and the area between the gate and the drain, the n-type ion is implanted in the area by an ion implanter to form the doping of the channel layer between the source and the gate and the channel layer between the gate and the drain, with the doping concentration of 1*10 17 cm -3 -1*10 19 cm -3 ; The sample with the isolated small block is photolithographically formed through the source region and the drain region photomask, and then the n-type ion is implanted into the region by the ion implanter to form the doping of the channel layer under the source and the channel layer under the drain, with a doping concentration of 1*10 18 cm -3 -1*10 20 cm -3 ;

[0030] S6) using an electron beam evaporation station to evaporate 20nm-60nm of Ti metal and then 120nm-180nm of Au metal from the sample processed in step S5), and then using an RTP device to perform a rapid thermal annealing process on the sample to form a source and a drain;

[0031] S7) The sample with the source and drain formed thereon is photolithographically processed through a photolithography plate in the p-type material layer region, and a magnetron sputtering device is used to generate a 20nm-100nm thick and 1*10 17 cm -3 -1*10 19 cm -3 A p-type material layer;

[0032] S8) depositing a gate dielectric layer with a thickness of 10 nm to 30 nm on the sample processed by the above steps S1) to S7) by ICPCVD equipment;

[0033] S9) performing photolithography on the gate dielectric layer corresponding to the gate region by using a gate region photomask, and then evaporating 20nm-60nm of Ni metal in the region by using an electron beam evaporation station, and then evaporating 120nm-180nm of Au metal to form a gate;

[0034] S10) depositing a first field dielectric layer with a thickness of 100 nm to 300 nm on the sample formed with the gate by a PECVD device;

[0035] S11) performing photolithography on the first field dielectric layer through a photomask in the first metal field plate region, and then using an electron beam evaporation station to first evaporate 20nm-60nm of Ni metal in the region, and then evaporate 120nm-180nm of Au metal to form a first metal field plate;

[0036] S12) fabricating a second field dielectric layer on the first metal field plate in the same manner as step S10), and then fabricating a second metal field plate on the second field dielectric layer in the same manner as step S11), and so on, until n layers of field dielectric layers and n layers of metal field plates are alternately completed, where n is greater than or equal to 3;

[0037] S13) The sample after step S12) is photolithographically processed by using a source region and a drain region photomask, and then the field dielectric and the gate dielectric deposited in the source region and the drain region are dry-etched by using an RIE device to expose the ohmic contact metal in the source and drain regions, thereby forming a gate test plate for subsequent test characterization and completing device fabrication.

[0038] Compared with the prior art, the present invention has the following advantages:

[0039] Firstly, the present invention adopts a lateral variable doping structure in the channel layer region, and divides the channel layer region into five regions in the horizontal direction, namely, the channel layer under the source, the channel layer between the source and the gate, the channel layer under the gate, the channel layer between the gate and the drain, and the channel layer under the drain. The channel layer under the source and the channel layer under the drain adopt high doping concentrations, which can reduce the ohmic contact resistance of the source and the drain; the channel layer between the source and the gate and the channel layer between the gate and the drain adopt sub-high doping concentrations, which can reduce the on-resistance of the device and increase the on-current of the device; the channel layer under the gate adopts a low doping concentration, which can improve the voltage control ability of the gate on the region, thereby improving the threshold voltage of the device. When the doping concentration of the region is less than the critical doping concentration corresponding to the threshold voltage of the device being greater than zero volts, an enhanced device is formed; at the same time, the low doping concentration in the region can alleviate the electric field concentration effect in the region where the gate is close to the drain in the channel layer, thereby improving the breakdown voltage of the device.

[0040] Secondly, since a layer of p-type material is deposited above the channel layer region between the gate and the drain, the p-type material and the n-type gallium oxide can form a PN junction. The PN junction can be used to deplete electrons on the surface of the channel layer at high voltage, thereby improving the electric field distribution on the surface of the channel layer without reducing the channel carrier concentration, that is, without increasing the on-resistance at low voltage, thereby alleviating the electric field concentration effect on the surface of the channel layer and increasing the breakdown voltage of the device.

[0041] Thirdly, since the present invention arranges at least three layers of alternately distributed field dielectric layers and metal field plates on the gate, that is, adopts a multi-layer stepped gate field plate structure on the side close to the drain, multiple new electric field peaks can be generated at the corners of each stepped gate field plate, and the electric field distribution is uniformly introduced into the passivation layer, thereby effectively alleviating the electric field concentration effect in the channel layer region at high voltage and improving the breakdown voltage of the device.

[0042] Fourthly, the present invention adopts an unintentionally doped buffer layer structure between the substrate layer and the channel layer, which can improve the morphology and crystal quality of the channel layer grown on the upper side of the buffer layer and enhance the overall performance of the device.

[0043] Fifth, the preparation process of the present invention is relatively simple, the material cost is low, and the preparation process is environmentally friendly and safe. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 It is a structural diagram of the present invention, wherein:

[0045] Figure 1 (a) is a schematic diagram of the three-dimensional structure of the present invention;

[0046] Figure 1 (b) is a schematic diagram of a three-dimensional structure of the present invention with additional directions and orientations;

[0047] Figure 2 It is three views of the present invention in different directions, wherein:

[0048] Figure 2 (a) is a side view of the present invention at the AA' position perpendicular to the YOZ plane and looking toward the positive direction of the X axis;

[0049] Figure 2 (b) is a side view of the present invention at the BB' position perpendicular to the YOZ plane and looking toward the positive direction of the X axis;

[0050] Figure 2 (c) is a side view of the present invention at the CC' position perpendicular to the YOZ plane and looking toward the positive direction of the X axis;

[0051] Figure 2 (d) is a front view of the present invention at the position D-D', perpendicular to the XOZ plane and looking toward the negative direction of the Y axis;

[0052] Figure 2 (e) is a top view of the present invention at the position D-D', perpendicular to the XOY plane and looking toward the negative direction of the Z axis;

[0053] Figure 3 It is a schematic diagram of the connection between the gate metal and the field plate metal of the present invention;

[0054] Figure 4 Schematic diagram of the manufacturing process of the device of the present invention. DETAILED DESCRIPTION

[0055] The present invention combines two improvement methods, namely, improving the electric field distribution on the side of the gate close to the drain in the channel layer in the lateral direction and improving the electric field distribution on the surface of the channel layer in the longitudinal direction, to maximize the breakdown voltage of the device. At the same time, it ensures a higher threshold voltage and good gate control capability of the device, ensures a smaller on-resistance and a larger on-current of the device, and enables the device to have better power characteristics.

[0056] The device structure and manufacturing method of the present invention are described in detail below with reference to the accompanying drawings.

[0057] Reference Figure 1 and Figure 2 The high breakdown voltage gallium oxide field effect transistor structure of the present invention comprises a substrate layer 1, a buffer layer 2, a channel layer 3, a source electrode 4, a drain electrode 5, a p-type material layer 6, a gate dielectric layer 7, a gate electrode 8, a dielectric layer 9, a metal field plate 10 and a gate test plate 11. Among them:

[0058] The substrate layer 1 is a semi-insulating β-Ga2O3 material doped with Mg or Fe.

[0059] The buffer layer 2 is an unintentionally doped β-Ga2O3 material and is located on the upper part of the substrate 1.

[0060] The channel layer 3 is an n-type semiconductor, doped with Si or Sn, with a thickness of 150nm-250nm. It is located on the upper part of the buffer layer 2 and is divided into five regions in the lateral direction, namely, a channel 31 under the source, a channel 32 between the source and the gate, a channel 33 under the gate, a channel 34 between the gate and the drain, and a channel 35 under the drain. The channels at different positions have different doping concentrations, among which the doping concentrations of the channel 31 under the source and the channel 35 under the drain are both 1*10 18 -1*10 20 cm -3 The doping concentration of the channel 32 between the source and the gate and the channel 34 between the gate and the drain are both 1*10 17 -1*10 19 cm -3 The doping concentration of the gate bottom channel 33 is 1*10 16 -1*10 18 cm -3 That is, the doping concentration of the channel 31 under the source and the channel 35 under the drain is the highest, the doping concentration of the channel 32 between the source and the gate and the channel 34 between the gate and the drain is the second highest, and the doping concentration of the channel 33 under the gate is the lowest.

[0061] The source electrode 4 is a Ti / Au metal, wherein the thickness of the Ti metal is 20nm-60nm, and the thickness of the Au metal is 120nm-180nm, and is located on the left side of the upper side of the overall channel layer.

[0062] The drain electrode 5 is a Ti / Au metal, wherein the thickness of the Ti metal is 20nm-60nm, and the thickness of the Au metal is 120nm-180nm, and is located on the right side of the upper side of the overall channel layer.

[0063] The p-type material layer 6 is a p-type NiO or p-type CuO material with a thickness of 20nm-100nm and a doping concentration of 1*10 17 -1*10 19 cm -3 , which is located on the upper side of the overall channel layer.

[0064] The gate dielectric layer 7 is any one high-k material of Al 2 O 3 , HfO 2 , and SiO 2 , and has a thickness of 10 nm to 30 nm. The gate dielectric layer 7 is located on the upper side of the overall channel layer and the p-type material layer 6 .

[0065] The gate 8 is made of Ni / Au metal, wherein the thickness of the Ni metal is 20nm-60nm, and the thickness of the Au metal is 120nm-180nm, and is located on the upper side of the gate dielectric layer 7 .

[0066] The dielectric layer 9 is configured to have at least three layers, namely a first field dielectric layer 91, a second field dielectric layer 92, a third field dielectric layer 93, ... an nth field dielectric layer 9n, made of the same material. The thickness of each field dielectric layer is 100nm-300nm, and the material is SiN or SiO2.

[0067] The metal field plate 10 is configured to have at least three layers, namely a first metal field plate 101, a second metal field plate 102, a third metal field plate 103, ... an nth metal field plate 10n, each layer being a superposition of Ni metal and Au metal, wherein the thickness of the Ni metal is 20nm-60nm, and the thickness of the Au metal is 120nm-180nm.

[0068] Each layer of field dielectric layer and metal field plate are staggered, that is, the first layer of field dielectric layer 91 is located on the upper side of gate dielectric layer 7 and gate electrode 8; the first layer of field plate metal 101 is located on the upper side of the first layer of field dielectric layer 91, and on the upper side of gate electrode 8 close to the drain; the second layer of field dielectric layer 92 is located on the upper side of the first layer of field dielectric layer 91 and the first layer of metal field plate 101; the second layer of field plate metal 102 is located on the upper side of the second layer of field dielectric layer 92; the third layer of field dielectric layer 93 is located on the upper side of the second layer of field dielectric layer 92 and the second layer of metal field plate 102; the third layer of field plate metal 103 is located on the upper side of the third layer of field dielectric layer 93, and on the upper side of the second metal field plate 102 close to the drain, and so on.

[0069] The gate test plate 11 is located on the side of the overall channel layer, and is connected to the gate 8, the first metal field plate 101, the second metal field plate 102 and the third metal field plate 103 respectively. Figure 3 shown.

[0070] Reference Figure 4 The present invention provides the following three embodiments for manufacturing a high breakdown voltage gallium oxide field effect transistor:

[0071] Example 1: Fabrication of substrate layer 1 is a Mg-doped semi-insulator β-Ga2O3 material, buffer layer 2 is an unintentionally doped β-Ga2O3 material; channel layer 3 is an n-type semiconductor, doped with Si, with a thickness of 250 nm and a doping concentration of 1*10 18 cm -3 , 1*10 17 cm -3 , 1*10 16 cm -3 The p-type material layer 6 is a p-type NiO material with a thickness of 100 nm and a doping concentration of 1*10 17 cm -3The gate dielectric layer 7 is made of Al2O3 material with a thickness of 30nm; the field dielectric layer is made of SiN material, the thickness of each of the three field dielectric layers is 150nm, and the Ni / Au material thickness of each metal field plate in the three metal field plates is 20 / 120nm for the gallium oxide field effect transistor.

[0072] Step 1: Select a Mg-doped β-Ga2O3 semi-insulating substrate material 1 on which an unintentionally doped buffer layer has been grown.

[0073] Step 2: Clean and surface treat the substrate 1, such as Figure 4 (a).

[0074] 2.1) Ultrasonic cleaning was performed using acetone, ethanol, and deionized water for 5 minutes each;

[0075] 2.2) Rinse with deionized water for 10 minutes;

[0076] 2.3) Blow dry with high purity N2.

[0077] Step 3: epitaxially grow an n-type β-Ga2O3 channel layer 3 on the cleaned substrate buffer layer, such as Figure 4 (b).

[0078] Through the molecular beam epitaxy MBE method, 7N Ga and high-purity 4N SiO2 are used to provide Ga and Si elements, and the pressure corresponding to the Ga source is set to 2.1*10 -4 Pa, substrate temperature of 550 ° C, gas used is a mixture of ozone and oxygen, of which ozone accounts for 5%, oxygen accounts for 95%, and the flow rate of the mixed gas is 5 sccm. Homoepitaxial growth is performed on the buffer layer 2, and Si elements are doped to generate a 250nm thick layer with a doping concentration of 1*10 16 cm -3 n-type β-Ga2O3 channel layer 3.

[0079] Step 4: Cleaning and surface treatment of the epitaxial channel layer 3.

[0080] 4.1) Use acetone, ethanol, and deionized water to ultrasonically clean for 5 minutes each, then rinse with deionized water for 10 to 15 minutes, and then soak in piranha solution for 5 to 10 minutes;

[0081] 4.2) Use deionized water for ultrasonic cleaning for 5 minutes, then rinse with deionized water for 10 minutes, and finally blow dry with high-purity N2.

[0082] Step 5: Photolithography and etching are performed on the surface of the channel layer 3 to form small isolated blocks with equal spacing, such as Figure 4 (c).

[0083] 5.1) Photolithography of the sample using a mesa isolation area photomask;

[0084] 5.2) The photolithographic sample was etched to a depth of 120 nm using RIE equipment using BCl3 and Ar, that is, etching to the substrate layer to form isolated small blocks with equal spacing.

[0085] Step 6: The channel layer is laterally doped and ion implanted to form five channels, such as Figure 4 (d).

[0086] 6.1) Photolithography the sample through the photomask of the region between the source and the gate and the region between the gate and the drain;

[0087] 6.2) Place the sample in an ion implanter and select Si ions. Set the angle to 6° and the dose to 1*10 15 cm -3 The implantation process condition with energy of 6Kev is used to implant the implantation area, and then annealing is carried out under N2 conditions at 900℃ to form a doping concentration of 1*10 in the area between the source and the gate and between the gate and the drain. 17 cm -3 The sample is formed into a channel 32 and a channel 34;

[0088] 6.3) Photolithography the sample using source and drain region photomasks;

[0089] 6.4) Place the sample in an ion implanter and select Si ions. Set the angle to 6° and the dose to 5*10 15 cm -3 The implantation process condition with energy of 8Kev is used to implant the implantation area, and then annealing is carried out under N2 conditions at 900℃ to form a doping concentration of 1*10 in the source and drain regions. 18 cm -3 The sample is formed into channel 31 and channel 35.

[0090] Finally, the channels 32 and 34 formed in 6.2), the channels 31 and 35 formed in 6.4), and the channel 33 in the gate region where ion implantation is not performed are obtained, for a total of 5 channels.

[0091] Step 7: Evaporate Ti / Au metal on the channel layer to form source 4 and drain 5, as shown in FIG. Figure 4 (e).

[0092] 7.1) Photolithography the sample using source and drain region photomasks;

[0093] 7.2) First evaporate 20nm of Ti metal and then evaporate 120nm of Au metal on the sample using an electron beam evaporation station;

[0094] 7.3) Perform a rapid thermal annealing process on the sample using an RTP device to form a source and a drain.

[0095] Step 8: Sputter p-type NiO on the channel layer to form a p-type material layer 6, such as Figure 4 (f).

[0096] 8.1) performing a photolithography process on the sample using a photomask in the p-type material layer region;

[0097] 8.2) Using magnetron sputtering equipment, the general conditions were set as RF power of 100 W, growth environment of 0.6 Pa, target material of 99.99% NiO, and Ar / O2 flow rate ratio of 2:1. 1*10 17 cm -3 NiO thin film layer.

[0098] Step 9: Deposit a layer of Al2O3 on the sample by ICPCVD equipment to form a gate dielectric layer 7, such as Figure 4 (g).

[0099] Step 10: Evaporate Ni / Au metal on the gate dielectric layer to form a gate 8, such as Figure 4 (h).

[0100] 10.1) Photolithography the sample using a gate region photomask;

[0101] 10.2) Use an electron beam evaporation station to first evaporate 20nm of Ni metal and then evaporate 120nm of Au metal to form a gate.

[0102] Step 11: Prepare a composite field plate structure consisting of three field dielectric layers and three metal field plates arranged alternately.

[0103] 11.1) A layer of SiN with a thickness of 150 nm is deposited on the sample by PECVD equipment to form the first field dielectric layer, such as Figure 4 (i);

[0104] 11.2) The sample is photolithographically processed using the photomask in the first metal field plate region, and then 20 nm of Ni metal is evaporated on the first field dielectric layer using an electron beam evaporation station, followed by 120 nm of Au metal, to form the first metal field plate. Figure 4 (j);

[0105] 11.3) A layer of SiN with a thickness of 150 nm is deposited on the sample by PECVD equipment to form the second field dielectric layer, such as Figure 4 (k);

[0106] 11.4) The sample is photolithographically processed using the second metal field plate region photolithography plate, and then 20 nm of Ni metal is evaporated on the second field dielectric layer using an electron beam evaporation station, followed by 120 nm of Au metal, to form the second field plate. Figure 4 (k);

[0107] 11.5) A layer of SiN with a thickness of 150 nm is deposited on the sample by PECVD equipment to form the third field dielectric layer, such as Figure 4 (k);

[0108] 11.6) The sample is photolithographically processed using the third metal field plate region photolithography plate; then, 20 nm of Ni metal is evaporated on the third field dielectric layer using an electron beam evaporation station, followed by 120 nm of Au metal, to form the third field plate. Figure 4 (k).

[0109] Step 12: Etch the field dielectric and gate dielectric deposited in the source and drain regions to expose the ohmic contact metal in the source and drain regions, such as Figure 4 (l).

[0110] 12.1) After the sample is photolithographically processed through the source and drain region photomasks,

[0111] 12.2) Dry-etch the field dielectric and gate dielectric deposited in the source and drain regions using RIE equipment to expose the ohmic contact metal in the source and drain regions for subsequent testing and characterization, thus completing device fabrication.

[0112] Example 2: Fabrication of substrate layer 1 is a semi-insulating β-Ga2O3 material doped with Fe, buffer layer 2 is an unintentionally doped β-Ga2O3 material; channel layer 3 is an n-type semiconductor, doped with Sn, with a thickness of 150 nm and a doping concentration of 1*10 20 cm -3 , 1*10 19 cm -3 , 1*10 18 cm -3 ; The p-type material layer 6 is a p-type CuO material with a thickness of 20nm and a doping concentration of 1*10 19 cm -3 The gate dielectric layer 7 is made of HfO2 material with a thickness of 10 nm; the field dielectric layer is made of SiO2 material, the thickness of each of the three field dielectric layers is 300 nm, and the Ni / Au material thickness of each of the three metal field plates is 60 / 180 nm for a gallium oxide field effect transistor.

[0113] Step 1: Select a Fe-doped β-Ga2O3 semi-insulating substrate material 1 on which an unintentionally doped buffer layer has been grown.

[0114] Step 2: Clean and surface treat the substrate 1, such as Figure 4 (a).

[0115] First, ultrasonic cleaning was performed using acetone, ethanol, and deionized water for 10 minutes each;

[0116] Secondly, rinse with deionized water for 15 minutes;

[0117] Finally, blow dry with high-purity N2.

[0118] Step 3: epitaxially grow an n-type β-Ga2O3 channel layer 3 on the cleaned substrate buffer layer, such as Figure 4 (b).

[0119] Through the molecular beam epitaxy MBE method, 7N Ga and high-purity 4N SnO2 are used to provide Ga and Sn elements. The corresponding pressure of the Ga source is 2.1*10 -4 Pa, substrate temperature of 650 ° C, gas using a mixture of ozone and oxygen, in which ozone accounts for 5%, oxygen accounts for 95%, and the flow rate of the mixed gas is 5sccm, homoepitaxial growth is performed on the buffer layer 2, and Sn elements are doped to generate a 150nm thick and doping concentration of 1*10 18 cm -3 n-type β-Ga2O3 channel layer 3.

[0120] Step 4: Cleaning and surface treatment of the epitaxial channel layer 3.

[0121] First, ultrasonic cleaning was performed in acetone, ethanol, and deionized water for 10 minutes each, followed by rinsing with deionized water for 15 minutes, and then soaking in piranha solution for 10 minutes;

[0122] Next, use deionized water for ultrasonic cleaning for 10 minutes, rinse with deionized water for 15 minutes, and finally blow dry with high-purity N2.

[0123] Step 5: Photolithography and etching are performed on the surface of the channel layer 3 to form small isolated blocks with equal spacing, such as Figure 4 (c).

[0124] First, the sample is photolithographically processed through a mesa-isolated area photomask;

[0125] Next, the photolithographic sample was etched to a depth of 200 nm using BCl3 and Ar using RIE equipment, that is, etching to the substrate layer to form isolated small blocks with equal intervals.

[0126] Step 6: The channel layer is laterally doped and ion implanted to form five channels, such as Figure 4 (d).

[0127] First, the sample is photolithographically processed through a photomask for the region between the source and the gate and the region between the gate and the drain;

[0128] Next, the sample was placed in an ion implanter and Si ions were selected at an angle of 9° and a dose of 5*10 15 cm -3 Under the process condition of energy of 10Kev, the implantation is performed in the implantation area, and then annealed under 1100℃ N2 condition to form the doping concentration of 1*10 in the area between the source and the gate and between the gate and the drain. 19 cm -3 The sample is formed into a channel 32 and a channel 34;

[0129] Next, the sample is photolithographically processed through the source region and drain region photomasks;

[0130] Then, the sample was placed in an ion implanter and Si ions were selected at an angle of 9° and a dose of 1*10 16 cm -3 , the implantation is performed in the implantation area under the process condition of energy of 12Kev, and then annealed under 1100℃ N2 condition to form the source and drain regions with doping concentration of 1*10 20 cm -3 The sample is formed into channel 31 and channel 35.

[0131] At this point, channel 32, channel 34, channel 31, and channel 35 are formed, and together with channel 33 in the gate region where ion implantation is not performed, there are five channels in total.

[0132] Step 7: Evaporate Ti / Au metal on the channel layer to form source 4 and drain 5, as shown in FIG. Figure 4 (e).

[0133] First, the sample was photolithographically processed using the source and drain region photolithography plates. Then, 60nm of Ti metal was evaporated from the sample using an electron beam evaporation station, followed by 180nm of Au metal.

[0134] Then, the sample is subjected to a rapid thermal annealing process using an RTP device to form a source and a drain.

[0135] Step 8: Sputter p-type NiO on the channel layer to form a p-type material layer 6, such as Figure 4 (f).

[0136] First, the sample is subjected to a photolithography process through a photomask in the p-type material layer region;

[0137] Then, using magnetron sputtering equipment, under the process conditions of RF power of 150W, growth environment of 0.6Pa, target material of 99.99% NiO, Ar / O2 flow rate ratio of 2:1, 1*10 19 cm -3 Thick p-type NiO thin film layer.

[0138] Step 9: Deposit a layer of Al2O3 on the sample by ICPCVD equipment to form a gate dielectric layer 7, such as Figure 4 (g).

[0139] Step 10: Evaporate Ni / Au metal on the gate dielectric layer to form a gate 8, such as Figure 4 (h).

[0140] First, the sample is photolithographically processed through a gate region photomask;

[0141] Next, an electron beam evaporation station is used to sequentially evaporate 60 nm of Ni metal and 80 nm of Au metal on the gate dielectric layer to form a gate.

[0142] Step 11: Prepare a composite field plate structure consisting of three field dielectric layers and three metal field plates arranged alternately.

[0143] First, a layer of SiN with a thickness of 300 nm was deposited on the sample by PECVD equipment to form the first field dielectric layer. Figure 4 (i);

[0144] Secondly, the sample is photolithographically processed through the photolithography plate in the first metal field plate region; then, 60nm of Ni metal is evaporated on the first field dielectric layer through an electron beam evaporation station, followed by 180nm of Au metal, to form the first metal field plate. Figure 4 (j).

[0145] Next, a layer of SiN with a thickness of 300 nm was deposited on the first metal field plate sample by PECVD equipment to form the second field dielectric layer. Figure 4 (k);

[0146] Next, the sample is photolithographically processed through the second metal field plate region photolithography, and then 60nm of Ni metal is evaporated on the second field dielectric layer through an electron beam evaporation station, followed by 180nm of Au metal, to form the second field plate. Figure 4 (k);

[0147] Next, a layer of SiN with a thickness of 300 nm is deposited on the sample by PECVD equipment to form the third field dielectric layer. Figure 4 (k);

[0148] Then, the sample is photolithographically processed through the third metal field plate region photolithography. Then, 60nm of Ni metal and 180nm of Au metal are sequentially evaporated on the third field dielectric layer using an electron beam evaporation station to form the third field plate. Figure 4 (k).

[0149] Step 12: After the sample is subjected to the photolithography process through the source region and the drain region photomask, the field dielectric and gate dielectric deposited in the source region and the drain region are dry-etched using RIE equipment to expose the ohmic contact metal in the source and drain regions for subsequent testing and characterization to complete the device manufacturing, such as Figure 4 (l).

[0150] Example 3: Fabrication: The substrate layer 1 is made of Fe-doped semi-insulator β-Ga2O3 material, the buffer layer 2 is unintentionally doped β-Ga2O3 material; the channel layer 3 is an n-type semiconductor, the doping element is Si, the thickness is 200nm, and the doping concentration is 1*10 19 cm -3 , 1*10 18 cm -3 , 1*10 17 cm -3 The p-type material layer 6 is a p-type NiO material with a thickness of 60 nm and a doping concentration of 1*10 18 cm -3 The gate dielectric layer 7 is made of SiO2 material with a thickness of 20nm; the field dielectric layer is made of SiO2 material, and the thickness of each of the four field dielectric layers is 200nm. The Ni / Au material thickness of each of the four metal field plates is 40 / 150nm for the gallium oxide field effect transistor.

[0151] Step A: Select a Fe-doped β-Ga2O3 semi-insulating substrate material 1 on which an unintentionally doped buffer layer has been grown.

[0152] Step B: Cleaning and surface treatment of substrate 1, such as Figure 4 (a).

[0153] B1) ultrasonic cleaning with acetone, ethanol and deionized water for 8 minutes each;

[0154] B2) Rinse with deionized water for 12 minutes and then blow dry with high-purity N2.

[0155] Step C: epitaxially grow an n-type β-Ga2O3 channel layer 3 on the cleaned substrate buffer layer, such as Figure 4 (b).

[0156] By using the molecular beam epitaxy (MBE) method, 7N Ga and high-purity 4N SiO2 are used to provide Ga and Si elements, and homoepitaxial growth is performed on the buffer layer 2 to dope Si elements to generate a 200nm thick and 1*10 17 cm -3 The n-type β-Ga2O3 channel layer 3, wherein the process conditions of molecular beam epitaxy MBE are as follows:

[0157] The corresponding pressure of Ga source is 2.1*10 -4 Pa,

[0158] The substrate temperature is 600°C.

[0159] The gas used is a mixture of ozone and oxygen, of which ozone accounts for 5% and oxygen accounts for 95%.

[0160] The flow rate of the mixed gas is 5 sccm.

[0161] Step D: cleaning and surface treatment of the epitaxial channel layer 3.

[0162] D1) ultrasonically clean with acetone, ethanol, and deionized water for 8 minutes each, then rinse with deionized water for 12 minutes, and then soak in piranha solution for 8 minutes;

[0163] D2) Use deionized water for ultrasonic cleaning for 5 minutes, then rinse with deionized water for 10 minutes, and finally blow dry with high-purity N2.

[0164] Step E: Photolithography and etching are performed on the surface of the channel layer 3 to form isolated small blocks with equal spacing, such as Figure 4 (c).

[0165] E1) photolithography of the sample through a mesa isolation area photomask;

[0166] E2) The photolithographic sample is etched to a depth of 150 nm using BCl3 and Ar through RIE equipment, that is, etching to the substrate layer to form isolated small blocks with equal spacing.

[0167] Step F: The channel layer is laterally doped and ion implanted to form five channels, such as Figure 4 (d).

[0168] F1) photolithography the sample through a photomask in the region between the source and the gate and in the region between the gate and the drain;

[0169] F2) Place the sample in an ion implanter and select Si ions to implant in the implantation area, then anneal at 1000℃ N2 to form a doping concentration of 1*10 in the area between the source and the gate and between the gate and the drain. 18 cm-3 The process conditions of the ion implantation are: the implantation angle is 8°, the dose is 3*10 15 cm -3 , energy is 8Kev;

[0170] F3) photolithography the sample through the source region and the drain region photomask;

[0171] F4) Place the sample in an ion implanter and select Si ions to implant in the implantation area, then anneal at 1000℃ N2 to form a doping concentration of 1*10 in the source and drain regions. 19 cm -3 The process conditions of the ion implantation are: the implantation angle is 8°, the dose is 8*10 15 cm -3 , energy is 10Kev;

[0172] Thus, five channels are obtained, including the gate region channel 33 where ion implantation has not been performed, and the above-formed channels 32 , 34 , 31 , and 35 .

[0173] Step G: Evaporating Ti / Au metal on the channel layer to form source 4 and drain 5, as shown in FIG. Figure 4 (e).

[0174] G1) photolithography the sample through the source region and the drain region photomask;

[0175] G2) 40nm of Ti metal and 150nm of Au metal are sequentially evaporated on the channel layer through an electron beam evaporation station; then a rapid thermal annealing process is performed on the sample through an RTP device to form a source and a drain.

[0176] Step H: Sputter p-type NiO on the channel layer to form a p-type material layer 6, such as Figure 4 (f).

[0177] H1) performing a photolithography process on the sample through a photomask in the p-type material layer region;

[0178] H2) Sputter 1*10 on the channel layer using magnetron sputtering equipment 18 cm -3 A thick NiO film layer is formed, wherein the process conditions of the sputtering setting are as follows:

[0179] RF power is 120W,

[0180] The growth environment is 0.6pa,

[0181] The target material is 99.99% NiO.

[0182] The Ar / O2 flow rate ratio was 2:1.

[0183] Step I: Deposit a layer of SiO2 on the sample by ICPCVD equipment to form a gate dielectric layer 7, such as Figure 4 (g).

[0184] Step J: Evaporating Ni / Au metal on the gate dielectric layer to form a gate 8, such as Figure 4 (h).

[0185] J1) photolithography the sample through the gate area photomask;

[0186] J2) Using an electron beam evaporation station, 40 nm thick Ni metal is evaporated on the gate dielectric layer, and then 150 nm thick Au metal is evaporated to form a gate.

[0187] Step K: preparing a composite field plate structure composed of four field dielectric layers and four metal field plates arranged alternately.

[0188] K1) A layer of SiN with a thickness of 200 nm is deposited on the sample by PECVD equipment to form the first field dielectric layer, such as Figure 4 (i);

[0189] K2) The sample is photolithographically processed through the photolithography plate in the first metal field plate region, and 40nm of Ni metal is evaporated on the first field dielectric layer through an electron beam evaporation station, followed by 150nm of Au metal, to form the first field plate. Figure 4 (j);

[0190] K3) A layer of SiN with a thickness of 200 nm is deposited on the sample by PECVD equipment to form the second field dielectric layer, such as Figure 4 (m);

[0191] K4) The sample is photolithographically processed through the second metal field plate region photolithography plate, and 40nm of Ni metal is first evaporated on the second field dielectric layer using an electron beam evaporation station, followed by 150nm of Au metal, to form the second field plate. Figure 4 (m);

[0192] K5) A layer of SiN with a thickness of 200 nm is deposited on the sample by PECVD equipment to form the third field dielectric layer, such as Figure 4 (m);

[0193] K6) The sample is photolithographically processed through the third metal field plate region photolithography, and 40nm of Ni metal is first evaporated on the third field dielectric layer using an electron beam evaporation station, followed by 150nm of Au metal, to form the third field plate. Figure 4 (m).

[0194] K7): A layer of SiN with a thickness of 200 nm is deposited on the sample by PECVD equipment to form the fourth field dielectric layer, such as Figure 4 (m);

[0195] K8) The sample is photolithographically processed through the fourth field plate metal region photolithography. 40nm of Ni metal and 150nm of Au metal are sequentially evaporated on the fourth field dielectric layer through an electron beam evaporation station to form the fourth field plate. Figure 4 (m).

[0196] Step L: Etching the field dielectric and gate dielectric deposited in the source and drain regions to expose the ohmic contact metal in the source and drain regions, that is, after the sample is subjected to a photolithography process through the source and drain region photomasks, the field dielectric and gate dielectric deposited in the source and drain regions are dry-etched through RIE equipment to expose the ohmic contact metal in the source and drain regions for subsequent testing, such as Figure 4 (n), device fabrication is completed.

[0197] The above descriptions are only three specific examples of the present invention and do not constitute any limitation to the present invention. Obviously, for professionals in this field, after understanding the content and principles of the present invention, it is possible to make various modifications and changes in form and details without deviating from the principles and structures of the present invention. For example, the dielectric layer and the metal field plate composite structure may have more layers in addition to the three layers and four layers given in this example; the preparation method of the source, drain and gate is not limited to electron beam evaporation, and any one of the methods such as magnetron sputtering or thermal evaporation can also be used; the preparation method of the channel layer is not limited to molecular beam epitaxy, and metal organic chemical vapor deposition and other methods can also be used; the p-type material is not limited to NiO and CuO, and NiO x / CuO x / SnO x / MnO x / FeO x / Cr2O3, etc. However, these modifications and changes based on the concept of the present invention are still within the protection scope of the claims of the present invention.

Claims

1. A high breakdown voltage gallium oxide field effect transistor structure, comprising from bottom to top: A substrate layer (1), a buffer layer (2), a channel layer (3), a source and drain layer (4, 5), a gate dielectric layer (7), a gate (8), a field dielectric layer (9), a metal field plate (10), and a gate test plate (11), characterized in that: The channel layer (3) comprises a laterally distributed channel layer (31) below the source electrode, a channel layer (32) between the source electrode and the gate electrode, a channel layer (33) below the gate electrode, a channel layer (34) between the gate electrode and the drain electrode, and a channel layer (35) below the drain electrode, and the doping concentration of the channel layer (31, 35) below the source electrode and the drain electrode is the highest, the channel layer (32) between the source electrode and the gate electrode and the channel layer (34) between the gate electrode and the drain electrode is the second highest, and the channel layer (33) below the gate electrode is the lowest, so as to uniformly distribute the electric field and reduce the electric field peak value on the side of the upper gate electrode of the channel electrode close to the drain electrode; The source-drain electrode layer is provided with a p-type material layer (6) between the source electrode layer (4) and the drain electrode layer (5) so as to form a PN junction with the n-type gallium oxide and alleviate the electric field concentration effect on the surface of the channel layer; The field dielectric layer (9) and the metal field plate (10) each have at least three layers, and are alternately arranged up and down, namely, a first field dielectric layer (91), a first metal field plate (101), a second field dielectric layer (92), a second metal field plate (102), a third field dielectric layer (93), a third metal field plate (103), ... an nth field dielectric layer, an nth metal field plate, so as to introduce multiple new electric field peaks at the corners of each layer of the stepped gate field plate, reduce the original electric field peak on the side of the gate close to the drain, and improve the breakdown voltage.

2. The structure according to claim 1, characterized in that: The material of the substrate (1) is a semi-insulating β-Ga2O3 material doped with Mg or Fe; The material of the buffer layer is unintentionally doped β-Ga2O3 material.

3. The structure according to claim 1, characterized in that: The channel layer (3) is an n-type semiconductor, the doping element of which is Si or Sn, and the doping concentration of the channel layer (31) under the source and the channel layer (35) under the drain is 1*10 18 -1*10 20 cm -3 1*10 of the channel layer (32) between the source and the gate and the channel layer (34) between the gate and the drain 17 -1*10 19 cm -3 The doping concentration of the channel layer (33) under the gate is 1*10 16 -1*10 18 cm -3 , the thickness of each channel layer is 150nm-250nm.

4. The structure according to claim 1, characterized in that ； The source and drain electrodes are made of a superposition of Ti metal and Au metal, with the thickness of the Ti metal being 20nm-60nm and the thickness of the Au metal being 120nm-180nm; The material of the gate is a superposition of Ni metal and Au metal, the thickness of the Ni metal is 20nm-60nm, and the thickness of the Au metal is 120nm-180nm.

5. The structure according to claim 1, characterized in that: The p-type material layer (6) is made of p-type NiO or p-type CuO material, with a thickness of 20nm-100nm and a doping concentration of 1*10 17 -1*10 19 cm -3 ; The gate dielectric layer (7) is made of Al2O3, HfO2 or SiO2 high-k material and has a thickness of 10nm-30nm.

6. The structure according to claim 1, characterized in that: The material of each layer of field medium is SiN or SiO2, and the thickness is 100nm-300nm; The material and thickness of each layer of metal field plate are consistent with those of the gate.

7. The structure according to claim 1, characterized in that The lateral distances between the metal field plates from the first layer to the Nth layer and the gate electrode gradually increase, and the lateral distances between the metal field plates and the drain electrode gradually decrease, and each layer is located between the gate electrode and the drain electrode in the lateral direction.

8. A method for preparing a high breakdown voltage gallium oxide field effect transistor, characterized in that: The steps include: S1) selecting a semi-insulating substrate material having an unintentionally doped buffer layer of β-Ga2O3, and cleaning and surface treating the substrate material; S2) performing homoepitaxial growth on the buffer layer by molecular beam epitaxy (MBE) on the cleaned substrate to generate an n-type β-Ga2O3 channel layer with a thickness of 150nm-250nm; S3) cleaning and surface treatment are performed on the surface of the channel layer; S4) photolithography is performed on the sample after the above steps through a mesa isolation region photomask, and then the mesa of the sample is etched by RIE equipment using BCl3 and Ar until the substrate layer is formed to form small isolation blocks with equal intervals, wherein the etching depth of the substrate layer is greater than 100nm; S5) After the sample with the isolated small block is photolithographically formed by the photomask in the area between the source and the gate and the area between the gate and the drain, the n-type ion is implanted in the area by an ion implanter to form the doping of the channel layer between the source and the gate and the channel layer between the gate and the drain, with the doping concentration of 1*10 17 cm -3 -1*10 19 cm -3 The sample with isolated small blocks is photolithographically processed through the photomasks in the source and drain regions, and then the n-type ions are implanted in the region using an ion implanter to form the doping of the channel layer under the source and the channel layer under the drain, with a doping concentration of 1*10 18 cm -3 -1*10 20 cm -3 ; S6) using an electron beam evaporation station to evaporate 20nm-60nm of Ti metal and then 120nm-180nm of Au metal from the sample processed in step S5), and then using an RTP device to perform a rapid thermal annealing process on the sample to form a source and a drain; S7) The sample with the source and drain formed thereon is photolithographically processed through a photolithography plate in the p-type material layer region, and a magnetron sputtering device is used to generate a 20nm-100nm thick and 1*10 17 cm -3 -1*10 19 cm -3 A p-type material layer; S8) depositing a gate dielectric layer with a thickness of 10 nm to 30 nm on the sample processed by the above steps S1) to S7) by ICPCVD equipment; S9) performing photolithography on the gate dielectric layer corresponding to the gate region by using a gate region photomask, and then evaporating 20nm-60nm of Ni metal in the region by using an electron beam evaporation station, and then evaporating 120nm-180nm of Au metal to form a gate; S10) depositing a first field dielectric layer with a thickness of 100 nm to 300 nm on the sample formed with the gate by using a PECVD device; S11) performing photolithography on the first field dielectric layer through a photomask in the first metal field plate region, and then using an electron beam evaporation station to first evaporate 20nm-60nm of Ni metal in the region, and then evaporate 120nm-180nm of Au metal to form a first metal field plate; S12) fabricating a second field dielectric layer on the first metal field plate in the same manner as step S10), and then fabricating a second metal field plate on the second field dielectric layer in the same manner as step S11), and so on, until n layers of field dielectric layers and n layers of metal field plates are alternately completed, where n is greater than or equal to 3; S13) The sample after step S12) is photolithographically processed by using a source region and a drain region photomask, and then the field dielectric and the gate dielectric deposited in the source region and the drain region are dry-etched by using an RIE device to expose the ohmic contact metal in the source and drain regions, thereby forming a gate test plate for subsequent test characterization and completing device fabrication.

9. The method according to claim 8, characterized in that In step S1), the substrate is cleaned and surface treated, which is achieved as follows: First, ultrasonically clean the sample with acetone, ethanol, and ionized water for 5-10 minutes each; Rinse with deionized water for 10-15 minutes; Finally, blow dry with high-purity N2.

10. The method according to claim 8, characterized in that In step S3), the epitaxial material is cleaned and surface treated as follows: First, ultrasonically clean the surface with acetone, ethanol, and deionized water for 5 to 10 minutes each, then rinse with deionized water for 10 to 15 minutes, and then soak in piranha solution for 5 to 10 minutes. Afterwards, ultrasonic cleaning was performed with deionized water for 5 minutes to 10 minutes, and rinsing was performed with deionized water for 10 minutes to 15 minutes; Finally, blow dry with high-purity N2.

11. The method according to claim 8, characterized in that Step S2) homoepitaxial growth is performed on the buffer layer using a molecular beam epitaxy (MBE) method, and the process conditions are as follows: 7N Ga and high-purity 4N SnO2 or SiO2 powder are used to provide Ga element and Sn element or Si element; The corresponding pressure of Ga source is 2.1*10 -4 Pa; The substrate temperature is 550-650°C; The gas used is a mixed gas of ozone and oxygen, wherein ozone accounts for 5% and oxygen accounts for 95%, and the flow rate of the mixed gas is 5 sccm.

12. The method according to claim 8, characterized in that: In step S5), an ion implanter is used to implant n-type ions into the region between the source and the gate and the region between the gate and the drain. The sample is first placed in the ion implanter and Si ions are selected. The angle is set to 6°-9° and the dose is 1*10 15 cm -3 -5*10 15 cm -3 , the energy is 6-10Kev, and the implantation is performed in the implantation area; then annealed under N2 conditions at 900℃-1100℃ to form a doping concentration of 1*10 17 cm -3 -1*10 19 cm -3 An n-type channel layer; In step S5), the source region and the drain region are implanted with n-type ions using an ion implanter. The sample is first placed in the ion implanter and Si ions are selected. The angle is set to 6°-9° and the dose is 5*10 15 cm -3 -1*10 16 cm -3 , the energy is 8-12Kev, and the implantation is performed in the implantation area; then annealed under N2 conditions at 900℃-1100℃ to form a doping concentration of 1*10 18 cm -3 -1*10 20 cm -3 n-type channel layer.

13. The method according to claim 8, characterized in that Step S7) grows a p-type material layer by magnetron sputtering equipment. The process conditions are as follows: The RF power is set to 100W-150W, the growth environment is 0.6Pa, and the target material is 99.99% NiO or CuO. Under the condition of Ar / O2 flow rate ratio of 2:1, sputtering 1*10 17 cm -3 -1*10 19 cm -3 NiO or CuO thin film layer.

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