Chamfered replacement gate structure

Abstract

The invention relates to a chamfered replacement gate structure. The present disclosure relates to semiconductor structures, and more particularly, to chamfered replacement gate structures and methods of manufacture. The structure includes: a recessed gate dielectric material in a trench structure; a plurality of recessed work function materials within the trench structure on the recessed gate dielectric material; a plurality of additional work function materials within the trench structure and over the recessed gate dielectric material and the plurality of recessed work function materials; a gate metal within the trench structure and over the plurality of additional work function materials, the gate metal and the plurality of additional work function materials having a planar surface below a top surface of the trench structure; and a cap material over the gate metal and the plurality of additional work function materials.

Description

[0001] This application is a divisional application of an application with a filing date of April 8, 2019, application number 201910274505.X, and invention name “Chamfered replacement gate structure”. Technical Field

[0002] The present disclosure relates to semiconductor structures, and more particularly, to chamfered replacement gate structures and methods of fabricating them. Background Art

[0003] An integrated circuit (IC) chip includes several levels of stacked or sequentially formed material layers to define active devices (e.g., FETs) and passive devices (wiring, etc.). For example, a fin FET will include a gate dielectric material and a metal gate material formed on a semiconductor material. The metal gate material will be protected by a cap material with sidewall spacers disposed on the sides of the gate dielectric material and the metal gate material. The source and drain regions are formed on the sides of the gate material in or on the semiconductor material.

[0004] As the size of FinFETs continues to shrink (e.g., 22nm and beyond), the work function metal chamfering process is necessary to achieve the desired threshold voltage (Vth). However, the nominal gate conductor (PC) critical dimension (CD) is challenging for the chamfering process and subsequent metal fill process at these smaller technology nodes. Also, as the gate size shrinks, the gate resistance increases, and more low resistance metals such as tungsten (W) are required relative to higher resistance work function metals (WFM) such as TiN. In addition, at such technology nodes, the source and gate contact formation process can result in shorts to the gate material and / or gate dielectric material. Summary of the invention

[0005] In one aspect of the present disclosure, a structure includes: a recessed gate dielectric material located in a trench structure; a plurality of recessed work function materials located in the trench structure and on the recessed gate dielectric material; a plurality of additional work function materials located in the trench structure and above the recessed gate dielectric material and the plurality of recessed work function materials; a gate metal located in the trench structure and above the plurality of additional work function materials, the gate metal and the plurality of additional work function materials having a flat surface located below a top surface of the trench structure; and a cap material located above the gate metal and the plurality of additional work function materials.

[0006] In one aspect of the present disclosure, a structure includes: a trench structure; a sidewall material lining the sidewalls of the trench structure; a dielectric material located on a surface of the sidewall material, the dielectric material having a height lower than a top surface of the trench structure; a plurality of recessed work function gate materials disposed above the dielectric material and having a height lower than a top surface of the trench structure; a work function gate material located above the plurality of recessed work function gate materials, wherein a bottom of the work function gate material contacts the sidewall material above the dielectric material; and a gate metal formed within a remaining portion of the trench structure and on top of the work function gate material.

[0007] In one aspect of the present disclosure, a method includes: forming a trench structure; forming a sidewall material lining the sidewalls of the trench structure; forming a dielectric material on a surface of the sidewall material; recessing the dielectric material to a height below a top surface of the trench structure; forming a plurality of work function gate materials above the dielectric material; recessing the plurality of work function gate materials to a height below the top surface of the trench structure; forming a work function gate material above the plurality of recessed work function gate materials, wherein a bottom of the work function gate material contacts the sidewall material above the dielectric material; and forming a gate metal within a remaining portion of the trench structure and on top of the work function gate material. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The present disclosure is described in the following detailed description by way of non-limiting examples of exemplary embodiments of the present disclosure and with reference to the several accompanying drawings.

[0009] Figure 1 A gate dielectric material and a work function metal in a trench formed in a dielectric material and a corresponding fabrication process are shown, among other features, according to aspects of the present disclosure.

[0010] Figure 2 A chamfered (recessed) work function metal and a corresponding fabrication process are shown, among other features, in accordance with aspects of the present disclosure.

[0011] Figure 3 Materials over the chamfered work function metal and corresponding fabrication processes are shown, among other features, in accordance with aspects of the present disclosure.

[0012] Figure 4 A chamfered (recessed) gate dielectric material and a corresponding fabrication process are shown, among other features, in accordance with aspects of the present disclosure.

[0013] Figure 5 A gate material overlying a recessed gate dielectric material and a corresponding fabrication process are shown, among other features, in accordance with aspects of the present disclosure.

[0014] Figure 6Recessed gate materials and corresponding fabrication processes are shown, among other features, in accordance with aspects of the present disclosure.

[0015] Figure 7 A cap material on a recessed gate material and a corresponding fabrication process are shown, among other features, in accordance with aspects of the present disclosure. DETAILED DESCRIPTION

[0016] The present disclosure relates to semiconductor structures, and more specifically, to chamfered gate structures and methods of manufacturing. More specifically, the present disclosure provides spacer chamfers for alternative metal gate technologies. Advantageously, the methods described herein provide improved device and process control. For example, the methods described herein result in structures with improved metal gate fill load control in self-aligned contact (SAC) gate modules. In addition, the methods described herein significantly reduce or eliminate gate to source / drain contact shorts in smaller technology nodes, such as 22nm and larger.

[0017] In an embodiment, the gate structure includes a trench structure formed in a dielectric layer over a substrate. A recessed high-K gate dielectric material is located at the bottom of the trench. A work function metal is located over the high-K gate dielectric material. A first metal layer (TiN) is located over the work function metal, and a second metal (W) is located over the TiN layer. A cap is located over the second metal. A top surface of the high-K gate dielectric is located below a bottom surface of the second metal.

[0018] The chamfered gate structure of the present invention can be manufactured in a variety of ways using a variety of different tools. In general, methods and tools are used to form structures with micrometer and nanometer sizes. The method, i.e., technology, for manufacturing the chamfered gate structure of the present invention has been adopted from integrated circuit (IC) technology. For example, the structure can be built on a wafer and implemented with a material film patterned by a photolithography process. In particular, the manufacture of the chamfered gate structure uses three basic building blocks: (i) thin film material is deposited on a substrate, (ii) a patterned mask is applied on top of the film by photolithography imaging, and (iii) the film is selectively etched to the mask.

[0019] Figure 1 A starting structure having a gate dielectric material and a work function metal in a trench and a corresponding manufacturing process according to aspects of the present disclosure, among other features, is shown. More specifically, the structure 10 includes a fin structure 12 composed of a semiconductor material. In an embodiment, the semiconductor material can be composed of any suitable material, including but not limited to Si, SiGe, SiGeC, SiC, GaAs, InAs, InP and other III / V or II / VI compound semiconductors. In another embodiment, the fin structure 12 can be composed of a silicon-on-insulator (SOI) wafer.

[0020] In an embodiment, the fin structure 12 may be fabricated using a conventional sidewall imaging technique (SIT). In an example of the SIT technique, a conventional chemical vapor deposition (CVD) process is used to deposit, for example, SiO 2 The mandrel material is deposited on the semiconductor material. The resist formed on the mandrel material is exposed to light to form a pattern (opening). Reactive ion etching (RIE) is performed through the opening to form the mandrel. Spacers are formed on the sidewalls of the mandrel, which are preferably a different material from the mandrel and are formed using conventional deposition processes known to those skilled in the art. For example, the spacers can have a width that matches the size of the fin structure 12. The mandrel is removed or stripped using a conventional etching process that is selective to the mandrel material. Etching is then performed within the spacing of the spacers to form sub-lithographic features. The sidewall spacers can then be stripped.

[0021] Still reference Figure 1 After a conventional dummy gate formation process, a dielectric material 14 is deposited on the fin structure 12. The dielectric material 14 may be any interlayer dielectric material, such as oxide, deposited using a conventional deposition method such as CVD and then subjected to a polishing process such as chemical mechanical polishing (CMP).

[0022] More specifically, in an embodiment, a dummy gate is formed on the fin structure 12 by depositing a polysilicon (poly) material and then performing a patterning process such as a conventional CMOS lithography and etching process. A spacer material is then deposited on the sidewalls of the patterned polysilicon material, and a conventional anisotropic etching process may then be performed to remove the spacer material on the substrate (e.g., the fin structure 12). A trench 16 is formed in the dielectric material 14 by removing the dummy gate material such as the polysilicon material. In an embodiment, the sidewall spacers 18 deposited on the sidewalls of the patterned polysilicon material will now be the sidewalls of the trench 16. In an embodiment, the sidewall spacers 18 may be a SiN material deposited by any conventional deposition process such as a CVD process, as an example.

[0023] Figure 1 Also shown is a gate dielectric material 20 deposited in the trench 16, over the sidewall spacers 18 and the upper surface of the dielectric material 14. In an embodiment, the gate dielectric material 20 may be a high-k dielectric material. For example, the gate dielectric material 20 may be HfO 2 Al 2 O 3 、 2 O 3 、TiO 2 ,La 2 O 3 、SrTiO 3、LaAlO 3 、ZrO 2 , Y 2 O 3 , Gd 2 O 3 As an example, the gate dielectric material 20 can be deposited by an atomic layer deposition (ALD) process to a thickness of about 1.5 nm; although other dimensions are contemplated herein.

[0024] Depending on the desired device performance, multiple materials 22, 24, 26, such as work function materials, are deposited on the gate dielectric material 20 to different thicknesses. In an embodiment, the multiple materials 22, 24, 26 can be metal layers, such as a bottom cluster 22 of TiN material, a P-type work function metal 24, and a TiN material 26; although other metals or amorphous materials (a-Si) are contemplated herein. Depending on the initial width of the trench 16, the different materials 22, 24, 26 can be deposited to a certain thickness by an ALD blanket deposition process. For example, the combination of materials 22, 24, and 26 can have a thickness of about 10 nm.

[0025] exist Figure 2 In the embodiment, materials 22, 24, 26 are recessed within trench 16 using a selective etching chemistry that does not attack gate dielectric material 20. In this manner, only materials 22, 24, 26 are recessed, leaving gate dielectric material 20 on the sidewalls of trench 16. In an embodiment, materials 22, 24, 26 may be recessed to approximately 10 nm above the surface of fin structure 12; although other dimensions are contemplated herein depending on device performance requirements.

[0026] like Figure 3 As shown, a bottom metal cluster 28 is deposited on the recessed materials 22, 24, 26 and the gate dielectric material 20. Depositing the bottom metal cluster 28 on the recessed materials 22, 24, 26 will result in a single step configuration (as shown by the circle marked "S"). In an embodiment, the metal 28 can be, for example, TiN. The metal 28 can be deposited by a conventional blanket deposition process such as CVD.

[0027] exist Figure 4In the embodiment, the metal 28 and the gate dielectric material 20 are recessed (chamfered) from the sidewalls of the trench 16. As shown, the recessed metal 28 and the gate dielectric material 20 are at the same height above the recessed materials 22, 24, 26. The recess will ensure that there is enough space in the trench 16 for subsequent filling of metal materials such as work function materials and tungsten metal for self-aligned contact replacement gate structures. In an embodiment, the metal 28 and the gate dielectric material 20 can be removed using conventional photolithography and etching processes. For example, a mask / resist deposited over the structure will be patterned to expose the metal 28 and the gate dielectric material 20 while protecting the sidewall spacers 18 and the dielectric material 14. The exposed metal 28 and the gate dielectric material 20 are then subjected to an etching process with selective chemistry to partially remove these materials to a predetermined depth within the trench 16. The mask / resist is then removed using a conventional stripping process.

[0028] exist Figure 5 In the embodiment, a gate material 30 such as a work function metal is deposited on the work function metal 28 and the sidewall spacers 18. In addition, the gate material 30 will cover the gate dielectric material 20. In this way, the gate dielectric material 20 is now completely covered, such as protected, during subsequent processing steps. In an embodiment, the gate material 30 such as a work function metal is an N-type work function metal such as TiAlC.

[0029] A top metal material cluster 32 is deposited on the work function metal 30, and a barrier metal 34 is deposited on the top cluster metal material 32. In an embodiment, the top metal material cluster 32 may be one or more layers of TiN, as an example. The barrier metal 34 may also be, for example, TiN; although other barrier metals are contemplated herein. The deposition of the materials 32, 34, 26 on the recessed materials 22, 24, 26, 28 will result in a double step configuration (as shown by the circle labeled "2S").

[0030] Due to the recessing of the material in the trench, sufficient space may be left for depositing the gate metal material 36. For example, the remaining portion of the trench 16 may have a width of about 4 nm, filled with the gate metal material 36. In this way, it is now possible to have improved fill load control in a self-aligned contact (SAC) gate module for smaller technology nodes, such as 22 nm and larger. In an embodiment, the gate metal material 36 is tungsten (W).

[0031] refer to Figure 6, the work function metal 30, the top metal material cluster 32, the barrier metal 34 and the gate metal material 36 are planarized using a conventional CMP process. After the planarization process, the materials 30, 32, 34 and 36 are recessed, as shown by the reference numeral 38. In this way, the work function metal 30, the top metal material cluster 32, the barrier metal 34 and the gate metal material 36 will form a single flat surface that is recessed. In an embodiment, the materials 30, 32, 34 and 36 can be recessed using a maskless process with an etching chemistry that is highly selective to the materials 30, 32, 34 and 36. In this way, the metal materials 30, 32, 34 and 36 are recessed below the surface of the sidewall spacer 18 (forming a recess 38). In an embodiment, the materials 30, 32, 34 and 36 can be recessed to a depth of about 15nm to about 25nm. The recessing process will reduce the height of the metal materials 30, 32, 34 and 36, ensuring that the source / drain contact metal itself will not short-circuit with the gate material.

[0032] Figure 7 A cap material 40 is shown deposited within the recess 38. In an embodiment, the cap material 40 is a SiN material deposited using a conventional CVD process. The SiN material may be planarized by a CMP process. In an embodiment, the cap material 40 will protect the underlying materials 30, 32, 34, and 36 (where 30, 32, 34, and 36 also protect the gate dielectric material 20) during source / drain contact formation.

[0033] After the CMP process, source / drain contacts 42 are formed in the dielectric material 14 on the sides of the sidewall spacers 18. The source / drain contacts 42 may be formed by conventional contact formation processes, such as photolithography, etching, and deposition of a metal material in a trench formed by an etching process. Advantageously, recessed gate materials, such as metal materials and gate dielectric materials, are not exposed during the formation of the source / drain contacts 42, thereby eliminating any shorts between the source / drain contacts 42 and the gate material, particularly any shorts formed to the gate dielectric material 20 (which is now recessed below the surface of the dielectric material 14).

[0034] The method as described above is used in the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in the form of raw wafers as bare chips (i.e., as a single wafer with multiple unpackaged chips) or in a packaged form. In the latter case, the chip is mounted in a single-chip package (such as a plastic carrier, whose leads are fixed to a motherboard or other higher-level carrier) or a multi-chip package (such as a ceramic carrier, which has one or both of surface interconnects and / or buried interconnects). In any case, the chip is then integrated with other chips, discrete circuit elements and / or other signal processing devices as part of (a) an intermediate product (such as a motherboard) or (b) a final product. The final product can be any product that includes an integrated circuit chip, from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices and central processing units.

[0035] The description of various embodiments of the present disclosure has been given for the purpose of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein are selected to best explain the principles of the embodiments, practical applications, or technical improvements to technologies found in the marketplace, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A semiconductor structure comprising: a sidewall spacer located on a sidewall of the trench structure, the sidewall spacer extending from and contacting a surface of the fin structure including a semiconductor material and an interlayer dielectric material; a first source or drain contact located between and in contact with the sidewall spacer and the interlayer dielectric material on a first side, the first source or drain contact also extending to and in contact with the surface of the fin structure; a second source or drain contact separated from the sidewall spacer by the interlayer dielectric material on a second side, the second source or drain contact also extending to and in direct contact with the surface of the fin structure; a gate dielectric material directly contacting the surface of the fin structure and partially extending upwardly and directly contacting the sidewall spacers within the trench structure; a plurality of recessed work function materials within the trench structure, located on the recessed gate dielectric material, the plurality of recessed work function materials being stacked on top of each other and including a flat surface located below a topmost portion of the gate dielectric material, wherein the plurality of recessed work function materials include a first work function material, a second work function material, and a third work function material; a plurality of additional work function materials located within the trench structure and above the recessed gate dielectric material and the plurality of recessed work function materials, the plurality of additional work function materials comprising a bottommost work function material and a topmost work function material; a barrier metal directly contacting a top surface of the topmost work function material; a gate metal located in the trench structure and above the plurality of additional work function materials and defined on the sides and bottom by the barrier metal material; and a capping material directly contacting the gate metal and each of the plurality of additional work function materials, the capping material also contacting the bottommost work function material and the topmost of the upwardly extending portions of the topmost work function material, wherein: The topmost portion of the gate dielectric material is below a bottom surface of the gate metal, The bottommost work function material of the plurality of additional work function materials is aligned with the gate dielectric material along the sidewall spacers of the trench structure; The bottom-most work function material of the plurality of additional work function materials separates a bottom surface of the cap material from the top-most portion of the gate dielectric material; The first work function material directly contacts a top surface of the gate dielectric material; The first work function material further includes an upwardly extending portion that directly contacts the gate dielectric material that contacts the sidewall spacer in the trench structure; The second work function material directly contacts the top surface of the first work function material; The second work function material includes an upwardly extending portion that directly contacts the upwardly extending portion of the first work function metal; The third work function material directly contacts the top surfaces of the first work function material and the second work function material, The third work function material includes an upwardly extending portion that is planar with the upwardly extending portions of the first work function material and the second work function material; A top surface of the third work function material is recessed relative to the upwardly extending portions of the first work function material and the second work function material; The bottommost work function material of the plurality of additional work function materials includes an upwardly extending portion directly contacting the sidewall spacer; The bottommost work function material contacts the top surface of the third work function material; The topmost work function material includes a cluster of metal material that contacts the entire top surface of the bottommost work function material and is separated from the sidewall spacers by the bottommost work function material; The topmost work function material includes an upwardly extending portion that is planar with the upwardly extending portion of the bottommost work function material; The topmost work function material includes a recessed surface that is recessed below a top surface of the upwardly extending portion of the bottommost work function material; A top surface of the barrier metal material, a top surface of the gate metal, and the upwardly extending portions of the bottommost work function material and the topmost work function material are planar; The barrier metal material is located between the plurality of additional work function materials and the plurality of recessed work function materials; and The cap material is separated from the topmost portion of the gate dielectric material by the bottommost work function material, which is directly above the topmost portion of the recessed gate dielectric material and extends partially over the sidewall spacers.

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