Electrostatic discharge / electrical overload protection circuit

Abstract

The application discloses an electrostatic discharge / electric overload protection circuit, and belongs to the field of integrated circuits. The protection circuit is arranged between a voltage source and an electronic device. The electrostatic discharge / electric overload protection circuit adopts a metal oxide semiconductor field effect transistor to set a clamping voltage. When the electrostatic discharge / electric overload attacks, the voltage size can be clamped at the breakdown voltage of the source-drain of the metal oxide semiconductor field effect transistor. The protection circuit adopts a parasitic diode as a clamping circuit, and can quickly discharge current. The application solves the problems of the prior art, i.e. the protection circuit adopts more diodes in series and parallel connection, occupies a larger area, and has poor discharge current capacity.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit technology, in particular to a static discharge / electrical overload protection circuit. BACKGROUND

[0002] In the era of various electronic components entering millions of households, static discharge / electrical overload (ESD / EOS) as a major killer of electronic components can cause semiconductor devices (diodes, transistors, etc.) in electronic circuits to burn out or break down, affecting the normal function of the circuit. There are many scenarios that can produce ESD / EOS, from natural lightning to simple circuit switching, and even people's movements can carry tens of thousands of volts of high voltage on their bodies, so the direct or indirect economic losses caused by it every year are very large. Therefore, it has high practical value to take protective measures against ESD / EOS and build an ESD / EOS protection circuit between electronic components and voltage sources.

[0003] The existing ESD / EOS protection circuit usually works in a diode breakdown mode, that is, a plurality of Zener diodes are connected in series to limit the clamping voltage, so that the voltage received by the protected circuit is not greater than the breakdown voltage. And use metal oxide semiconductor (MOS) tube as a switch, when the external ESD / EOS voltage is greater than the clamping voltage, open the discharge circuit, play the role of ESD / EOS protection.

[0004] The protection mode of this ESD / EOS protection circuit has defects. Since a plurality of Zener diodes are connected in series and in parallel, the layout area is large, which is not conducive to the miniaturization of the chip in a high-voltage ESD / EOS protection circuit. And after the circuit plays the role of clamping, the resistance of the Zener diode is certain after being broken down, and the circuit cannot well clamp the voltage if the ESD / EOS fluctuates after clamping, and the clamping capacity is unstable. SUMMARY

[0005] The present application provides a static discharge / electrical overload protection circuit, which uses a metal oxide semiconductor field effect transistor (MOSFET) to set the clamping voltage of the ESD / EOS protection circuit. When ESD / EOS attacks, the voltage can be clamped at the breakdown voltage of the MOSFET source and drain, and the parasitic diode of the MOSFET can be used as a clamping circuit, and the current can be quickly discharged, overcoming the problem of large area occupied by the use of more diodes in series and in parallel in the prior art and poor discharge current capacity.

[0006] The embodiment of the present application provides a static discharge / electrical overload protection circuit connected between a voltage source and an electronic device, comprising: a reference circuit for opening a feedback control circuit when the voltage of an external voltage source is higher than a clamping voltage, and clamping the voltage at a set voltage; and a feedback control circuit for quickly discharging current when a static discharge / electrical overload voltage attacks.

[0007] Optionally, in one embodiment of the present application, the reference circuit is composed of a P-type lateral double diffused metal oxide semiconductor field effect transistor PM0 and a first resistor R0.

[0008] The feedback control circuit is composed of a Zener diode D0, a second resistor R1 and an N-type lateral double diffused metal oxide semiconductor field effect transistor NM0.

[0009] Optionally, in one embodiment of the present application, the gate of the P-type lateral double diffused metal oxide semiconductor field effect transistor PM0 in the reference circuit is connected to one end of the first resistor R0, the other end of the first resistor R0 and the source of the P-type lateral double diffused metal oxide semiconductor field effect transistor PM0 are both connected to the positive pole of a voltage source, the drain of the P-type lateral double diffused metal oxide semiconductor field effect transistor PM0 is connected to the cathode of the Zener diode D0, one end of the second resistor R1 and the gate of the N-type lateral double diffused metal oxide semiconductor field effect transistor NM0; the second resistor R1 is connected in parallel with the Zener diode D0, the anode of the Zener diode D0, the other end of the second resistor R1 and the source of the N-type lateral double diffused metal oxide semiconductor field effect transistor NM0 are all connected to the negative pole of the voltage source, and the drain of the N-type lateral double diffused metal oxide semiconductor field effect transistor NM0 is connected to the positive pole of the voltage source.

[0010] Optionally, in one embodiment of the present application, the P-type lateral double diffused metal oxide semiconductor field effect transistor PM0 is a breakdown tube, the second resistor R1 generates the opening voltage of the N-type lateral double diffused metal oxide semiconductor field effect transistor NM0, and the N-type lateral double diffused metal oxide semiconductor field effect transistor NM0 is a discharge tube to release electrostatic discharge / electrical overload current.

[0011] Optionally, in one embodiment of the present application, the ground end of the protected electronic device is connected to the drain of the N-type lateral double diffused metal oxide semiconductor field effect transistor NM0.

[0012] The electrostatic discharge / electrical overload protection circuit of the embodiment of the present application is arranged between a voltage source and an electronic device, adopts a metal oxide semiconductor field effect transistor to set the clamping voltage of the electrostatic discharge / electrical overload protection circuit, and can clamp the voltage size at the breakdown voltage of the source and drain of the metal oxide semiconductor field effect transistor when the electrostatic discharge / electrical overload attacks, uses the parasitic diode to set the clamping circuit, and can quickly discharge current. Thus, the protection circuit of the present application can discharge a large amount of current in a relatively short time, makes the protected circuit more difficult to be broken down by high voltage, can provide more stable ESD / EOS protection, and the clamping voltage is more stable.

[0013] Additional aspects and advantages of the application will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following and the attached drawings. BRIEF DESCRIPTION OF DRAWINGS

[0014] The above and / or additional aspects and advantages of the present application will become apparent and be more readily understood through consideration of the following description, taken in conjunction with the accompanying drawings, in which:

[0015] Figure 1 A schematic diagram of an electrostatic discharge / electrical overload protection circuit according to an embodiment of the present application;

[0016] Figure 2 A circuit diagram of an electrostatic discharge / electrical overload protection circuit according to an embodiment of the present application;

[0017] Figure 3 A clamping effect diagram of Example 1 of an ESD / EOS protection circuit according to an embodiment of the present application. DETAILED DESCRIPTION

[0018] Embodiments of the present application are described in detail below with reference to the attached drawings, which show by way of example, embodiments in which like reference numerals refer to like elements or elements having similar functions. The embodiments described below are illustrative, and are not intended to be limiting, of the present application.

[0019] The embodiments of the present application disclose a novel ESD / EOS protection circuit, which can clamp the voltage at a protected circuit to a normal working voltage when the protected circuit is subjected to a high ESD / EOS voltage impact, so as to ensure that the protected circuit is not affected by external ESD / EOS and maintains normal working. It should be noted that the protected circuit in the embodiments of the present application generally includes but is not limited to MOS, capacitor, inductor, resistor and the like. It should be pointed out that the high voltage and the low voltage in the embodiments of the present application are relative concepts. For example, the protected circuit can be a circuit that can normally work under a voltage below 50 V, and then a voltage with a peak value exceeding 50 V is a high ESD / EOS voltage, which needs the ESD / EOS protection circuit to play a clamping role to clamp the voltage to 50 V. It should be pointed out that the above only indicates the standard for distinguishing the high voltage and the low voltage, and according to the actual situation, the protected circuit can also be a circuit that works under other voltages, and the clamping voltage can also be changed accordingly.

[0020] Based on the types and application scenarios of the protected circuits described above, the electrostatic discharge / electrical overload protection circuit according to the embodiments of the present application is introduced.

[0021] As Figure 1 and Figure 2As shown, the ESD / EOS protection circuit of the embodiment of the present application is composed of a reference circuit and a feedback control circuit. The ESD / EOS protection circuit of the embodiment of the present application should be placed between a voltage source and an electronic device. When the ESD / EOS protection circuit of the embodiment of the present application is applied, it should be connected in parallel to the two ends of the electronic device that needs to be protected. The components of the ESD / EOS protection circuit include: a reference circuit, which is used to open the feedback control circuit when the voltage of the external voltage source is higher than the clamping voltage, and clamp the voltage at a set voltage; a feedback control circuit, which is used to quickly discharge current when the ESD / EOS voltage attacks.

[0022] The reference circuit is composed of a P-type lateral double diffusion metal oxide semiconductor field effect transistor (PLDMOS) PM0 and a first resistor R0. The clamping voltage is determined by the parameters and type of the PLDMOS. The feedback control circuit is composed of a Zener diode D0, a second resistor R1 and an N-type lateral double diffusion metal oxide semiconductor field effect transistor (NLDMOS) NM0.

[0023] In the reference circuit, the gate of the P-type lateral double diffusion metal oxide semiconductor field effect transistor PM0 is connected to one end of the first resistor R0. The other end of the first resistor R0 and the source of the P-type lateral double diffusion metal oxide semiconductor field effect transistor PM0 are both connected to the positive pole of the voltage source. The drain of the P-type lateral double diffusion metal oxide semiconductor field effect transistor PM0 is connected to the cathode of the Zener diode D0, one end of the second resistor R1 and the gate of the N-type lateral double diffusion metal oxide semiconductor field effect transistor NM0. The second resistor R1 is connected in parallel to the Zener diode D0. The anode of the Zener diode D0 and the other end of the second resistor R1 are both connected to the negative pole of the voltage source. The source of the N-type lateral double diffusion metal oxide semiconductor field effect transistor NM0 is connected to the negative pole of the voltage source. The drain of the N-type lateral double diffusion metal oxide semiconductor field effect transistor NM0 is connected to the positive pole of the voltage source.

[0024] As an embodiment, the reference circuit is composed of a P-type lateral double diffusion metal oxide semiconductor field effect transistor (referred to as PM0) and a Zener diode D0. The gate and the source of the P-type lateral double diffusion metal oxide semiconductor field effect transistor PM0 are connected to the positive pole of the voltage source. The drain of the P-type lateral double diffusion metal oxide semiconductor field effect transistor PM0 is connected to the cathode of the Zener diode D0.

[0025] As an embodiment, the P-type lateral double diffusion metal oxide semiconductor field effect transistor PM0 is a breakdown tube. The second resistor R1 generates the turn-on voltage of the N-type lateral double diffusion metal oxide semiconductor field effect transistor NM0. The N-type lateral double diffusion metal oxide semiconductor field effect transistor NM0 is a discharge tube, which releases the ESD / EOS current.

[0026] As an embodiment, the ground end of the working circuit to be protected is connected to the place. The high-voltage end is connected to the drain of the N-type lateral double diffusion metal oxide semiconductor field effect transistor NM0.

[0027] The working principle of the embodiment of the present application is as follows: when the voltage of the external voltage source is greater than the specified clamping voltage, the source-drain of the P-type lateral double diffused metal oxide semiconductor field effect transistor PM0 is broken down to generate a reference voltage, and the voltage remains unchanged. The drain of the P-type lateral double diffused metal oxide semiconductor field effect transistor PM0 generates a driving current, the driving current flows through the second resistor R1 to increase the voltage across the second resistor R1, so that the gate of the high-voltage discharge tube NM0 is greater than its threshold voltage, the N-type lateral double diffused metal oxide semiconductor field effect transistor NM0 is turned on, a large amount of current is discharged, and the entire circuit is clamped at a certain voltage. And unlike the clamping of the diode, the clamping and driving of the P-type lateral double diffused metal oxide semiconductor field effect transistor PM0 can adjust the gate voltage to a certain extent to provide higher driving current due to the presence of the gate resistor R0. It should be noted that the value of the first resistor R0 needs to be carefully designed to prevent the P-type lateral double diffused metal oxide semiconductor field effect transistor PM0 from being turned on and the clamping capability of the circuit from being lost.

[0028] It should be pointed out that the clamping voltage value in the embodiment of the present application should be the same as the source-drain breakdown voltage value of the PLDMOS tube PM0, so the type of PLDMOS tube can be selected according to the required clamping voltage value.

[0029] The embodiment of the present application does not limit the value of the second resistor R1, and the types of NLDMOS and PLDMOS are not limited, which can be determined according to the actual application requirements; optionally, for the specific circuit connection relationship of the device requiring ESD / EOS protection, it can also be flexibly set according to the actual application requirements; optionally, for the value of the PM0 gate resistor R0, it is recommended to select the interval of 50Ω to 500Ω to ensure high driving current and stable clamping capability.

[0030] It should be noted that in order to reduce the chip area, the PLDMOS is used as a breakdown tube in the embodiment of the present application, and the source-drain breakdown voltage of the PLDMOS is used to specify the clamping voltage value. The following will be illustrated by a specific example.

[0031] Example 1:

[0032] It should be pointed out that the ESD / EOS protection circuit shown in Example 1 is an embodiment of the present application with a certain specified clamping voltage, which is completely the same as the above-mentioned embodiment of the present application except for the source-drain breakdown voltage value of PM0.

[0033] The clamping voltage capability of Example 1 when a high-voltage ESD / EOS is applied is as shown in Figure 3 , which can clamp the voltage at a certain value and rapidly discharge the current in a short time. It shows the good ESD / EOS protection capability of the circuit.

[0034] It is emphasized that the circuit of the embodiments of the present application is not limited to the clamping voltage of this example 1. For the embodiments of the present application, the clamping voltage can be defined by replacing the LDMOS with different breakdown voltage. It is emphasized that in other applications of the present application, the NLDMOS / PLDMOS can be replaced by other types of MOS transistors or switching devices according to the specific form of implementation, which is still considered as a derivative of the present application.

[0035] According to the ESD / EOS protection circuit of the embodiments of the present application, the clamping voltage can be changed by changing the MOS model of the reference circuit, and the adjustment capability is flexible. Compared with the increase of circuit area caused by the series connection of multiple Zener diodes, the present application only uses one LDMOS, which greatly reduces the chip area. The present application can discharge a large amount of current in a relatively short time, so that the protected circuit is more difficult to be broken down by high voltage. The embodiments of the present application can provide more stable ESD / EOS protection, and the clamping voltage is more stable.

[0036] In the description of the present specification, the description referring to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" and the like means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any appropriate manner in one or N embodiments or examples. In addition, the person skilled in the art can combine and combine the different embodiments or examples described in the present specification and the features of the different embodiments or examples without contradiction.

[0037] In addition, the terms "first", "second" are only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of "N" is at least two, for example, two, three, etc., unless otherwise specifically limited.

Claims

1. An electrostatic discharge / electrical overload protection circuit, connected between a voltage source and electronic equipment, characterized in that, include: The reference circuit is used to activate the feedback control circuit when the external voltage source voltage is higher than the clamping voltage, so as to clamp the voltage at the set voltage. Feedback control circuit is used to quickly discharge current when electrostatic discharge / electrical overload voltage occurs; The reference circuit consists of a P-type lateral double-diffused metal-oxide-semiconductor field-effect transistor PMO and a first resistor R0. The feedback control circuit consists of a Zener diode D0, a second resistor R1, and an N-type lateral double-diffused metal-oxide-semiconductor field-effect transistor NM0. In the reference circuit, the gate of the P-type lateral double-diffused metal-oxide-semiconductor field-effect transistor PMO is connected to one end of the first resistor R0. The other end of the first resistor R0 and the source of the P-type lateral double-diffused metal-oxide-semiconductor field-effect transistor PMO are both connected to the positive terminal of the voltage source. The drain of the P-type lateral double-diffused metal-oxide-semiconductor field-effect transistor PMO is connected to the cathode of the Zener diode D0, one end of the second resistor R1, and the gate of the N-type lateral double-diffused metal-oxide-semiconductor field-effect transistor NM0. The second resistor R1 is connected in parallel with the Zener diode D0. The anode of the Zener diode D0, the other end of the second resistor R1, and the source of the N-type lateral double-diffused metal-oxide-semiconductor field-effect transistor NM0 are all connected to the negative terminal of the voltage source. The drain of the N-type lateral double-diffused metal-oxide-semiconductor field-effect transistor NM0 is connected to the positive terminal of the voltage source.

2. The circuit according to claim 1, characterized in that, The P-type lateral double-diffused metal-oxide-semiconductor field-effect transistor PM0 acts as a breakdown transistor, generating the turn-on voltage of the N-type lateral double-diffused metal-oxide-semiconductor field-effect transistor NM0 across the second resistor R1. The N-type lateral double-diffused metal-oxide-semiconductor field-effect transistor NM0 acts as a discharge transistor, releasing electrostatic discharge / electrical overload current.

3. The circuit according to claim 1, characterized in that, The ground terminal of the protected electronic device is grounded, and the high-voltage terminal is connected to the drain of the N-type lateral double-diffused metal-oxide-semiconductor field-effect transistor NM0.

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