Semiconductor Structure, Method of Manufacturing the Semiconductor Structure, and Image Sensor

Abstract

An embodiment of the present application provides a semiconductor structure, a manufacturing method of the semiconductor structure, and an image sensor, relating to the technical field of semiconductor manufacturing. The semiconductor structure includes: a substrate and a photoelectric functional layer formed on the surface of the substrate; the photoelectric functional layer includes a photoelectric induction layer and an isolation structure for separating the photoelectric induction layer into a plurality of photoelectric induction regions; the photoelectric induction region includes a plurality of stacked photoelectric induction material layers and a cross-layer doping structure extending along the normal direction of the photoelectric induction layer; the cross-layer doping structure has the same doping type as the photoelectric induction layer; wherein, the cross-layer doping structure is formed by an ion implantation process; taking the normal direction of the photoelectric induction layer as the depth direction of ion implantation and the thickness direction of the photoelectric induction material layer, along the normal direction of the photoelectric induction layer, the ion implantation depth for forming the cross-layer doping structure is at least greater than the thickness of the photoelectric induction material layer farthest from the substrate. Through the embodiment of the present application, the imaging quality of the image sensor is improved.

Description

Technical Field

[0001] The embodiments in the present application relate to the field of semiconductor manufacturing technology, and specifically relate to a semiconductor structure, a manufacturing method of the semiconductor structure, and an image sensor. Background Art

[0002] Complementary Metal Oxide Semiconductor (CMOS) image sensors are widely used in the fields of consumer electronics, security monitoring, assisted driving, medical devices, etc. due to their advantages such as low cost, anti-blur, and flexible access. Among them, the Back-Side Illumination (BSI) CMOS image sensor changes the light incident direction, enabling light to directly irradiate the photodiode, improving the device sensitivity and light utilization rate, and is often used in fields with high requirements for the pixel performance of image sensors.

[0003] However, in the existing manufacturing process of back-side illumination CMOS image sensors, a high-energy ion implantation process is usually used to form the photodiode (PD). As the process size shrinks, high-energy ion implantation may cause damage to the back-side illumination CMOS image sensor and lead to crosstalk between pixels, reducing the imaging quality of the device. Summary of the Invention

[0004] In view of this, multiple embodiments of the present application provide a semiconductor structure, a manufacturing method of the semiconductor structure, and an image sensor to improve the imaging quality of back-side illumination CMOS image sensors.

[0005] In one aspect, an embodiment of the present application provides a semiconductor structure, including: a substrate and a photoelectric functional layer formed on the surface of the substrate; the photoelectric functional layer is used to realize photoelectric signal conversion based on the photoelectric effect; the photoelectric functional layer includes a photoinductive layer and an isolation structure for separating the photoinductive layer into multiple photoinductive regions; the photoinductive region includes multiple stacked photoinductive material layers and a cross-layer doping structure extending along the normal direction of the photoinductive layer; the doping type of the cross-layer doping structure is the same as the doping type of the photoinductive layer; wherein, the cross-layer doping structure is formed by an ion implantation process; taking the normal direction of the photoinductive layer as the depth direction of ion implantation and the thickness direction of the photoinductive material layer, along the normal direction of the photoinductive layer, the ion implantation depth of forming the cross-layer doping structure is at least greater than the thickness of the photoinductive material layer farthest from the substrate.

[0006] Optionally, the doping elements of the photoinductive material layer include: phosphorus element, arsenic element, and antimony element.

[0007] Optionally, among the multiple optoelectronic sensing material layers, the doping elements of adjacent optoelectronic sensing material layers are different.

[0008] Optionally, an optoelectronic sensing material layer with a doping element of phosphorus is formed between the optoelectronic sensing material layer with a doping element of arsenic and the optoelectronic sensing material layer with a doping element of antimony.

[0009] Optionally, the doping element of the interlayer doping structure is phosphorus.

[0010] Optionally, the semiconductor structure further includes: a target grid structure formed on the side of the isolation structure away from the substrate; the target grid structure includes a first grid layer, a second grid layer, and a third grid layer arranged in a stacked manner, wherein the material of the first grid layer is hafnium dioxide, the material of the second grid layer is titanium nitride, and the material of the third grid layer is tungsten.

[0011] In another aspect, an embodiment of the present application provides a method for manufacturing a semiconductor structure, the method including: providing a substrate; forming an optoelectronic functional layer on the substrate; the optoelectronic functional layer is used to realize optoelectronic signal conversion based on the photoelectric effect; the optoelectronic functional layer includes an optoelectronic sensing layer and an isolation structure for separating the optoelectronic sensing layer into multiple optoelectronic sensing regions; the optoelectronic sensing region includes multiple optoelectronic sensing material layers arranged in a stacked manner and an interlayer doping structure extending along the normal direction of the optoelectronic sensing layer; the doping type of the interlayer doping structure is the same as the doping type of the optoelectronic sensing layer; wherein, the interlayer doping structure is formed by an ion implantation process; taking the normal direction of the optoelectronic sensing layer as the depth direction of ion implantation and the thickness direction of the optoelectronic sensing material layer, along the normal direction of the optoelectronic sensing layer, the ion implantation depth of forming the interlayer doping structure is at least greater than the thickness of the optoelectronic sensing material layer farthest from the substrate.

[0012] Optionally, the semiconductor structure further includes a target grid structure formed on the side of the isolation structure away from the substrate; the step of preparing the optoelectronic functional layer on the substrate includes: forming multiple optoelectronic sensing regions and the isolation structure on the substrate; forming a transition grid structure on the side of the optoelectronic sensing region away from the substrate, and forming a target grid structure on the side of the isolation structure away from the substrate; wherein, the transition grid structure and the target grid structure are alternately and spaced apart; using the transition grid structure and the target grid structure as masks, forming the interlayer doping structure in the optoelectronic sensing region by an ion implantation process; removing the transition grid structure.

[0013] Optionally, the distance between the adjacent transition grating structure and the target grating structure falls within the range of 500 nm to 1000 nm.

[0014] In yet another aspect, an embodiment of the present application provides an image sensor, which includes the semiconductor structure as described in the above embodiment, or a semiconductor structure manufactured by the manufacturing method of the semiconductor structure as described in the above embodiment.

[0015] In multiple embodiments provided by the present application, by forming a photoelectric functional layer including a photoinductive layer and an isolation structure on the surface of a substrate, the photoinductive layer is separated into multiple photoinductive regions by the isolation structure. Each photoinductive region includes multiple stacked photoinductive material layers and an interlayer doping structure. Among them, the interlayer doping structure extends along the normal direction of the photoinductive layer, and the doping type of the interlayer doping structure is the same as that of the photoinductive layer. The interlayer doping structure is formed by an ion implantation process. Along the normal direction of the photoinductive layer, the ion implantation depth for forming the interlayer doping structure is at least greater than the thickness of the photoinductive material layer farthest from the substrate. The unexpected effects achieved include: Since the doping type of the interlayer doping structure is the same as that of the photoinductive layer, and the interlayer doping structure spans at least two photoinductive material layers along the normal direction of the photoinductive layer, the number of photo-generated carriers in the photoelectric conversion process is increased, and the imaging quality of the image sensor is improved. Description of the Drawings

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for describing the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0017] Figure 1 It is a schematic flow chart of the manufacturing method of the semiconductor structure provided by an embodiment of the present application.

[0018] Figure 2 It is a schematic diagram of the front-end wafer prepared by the front-end process (Front End Of Line, FEOL) provided by an embodiment of the present application.

[0019] Figure 3 It is a schematic flow chart of the step of providing a substrate provided by an embodiment of the present application.

[0020] Figure 4 It is a schematic diagram of forming an isolation layer in a semiconductor substrate provided by an embodiment of the present application.

[0021] Figure 5Schematic diagram of a substrate provided for an embodiment of the present application.

[0022] Figure 6 Schematic flow diagram for preparing an optoelectronic functional layer on the surface of a substrate provided for an embodiment of the present application.

[0023] Figure 7 Schematic diagram of forming an optoelectronic sensing layer on the surface of a substrate provided for an embodiment of the present application.

[0024] Figure 8 Schematic diagram of using an isolation structure to divide an optoelectronic sensing layer into multiple optoelectronic sensing regions provided for an embodiment of the present application.

[0025] Figure 9 Schematic diagram of forming a grid material layer on the surface of an optoelectronic sensing layer provided for an embodiment of the present application.

[0026] Figure 10 Schematic diagram of forming a target grid structure and a transition grid structure provided for an embodiment of the present application.

[0027] Figure 11 Schematic diagram of forming a cross-layer doping structure by ion implantation provided for an embodiment of the present application.

[0028] Figure 12 Schematic diagram of a semiconductor structure provided for an embodiment of the present application.

[0029] Figure 13 Schematic diagram of an image sensor provided for an embodiment of the present application.

[0030] Explanation of structure labels

[0031] 100, Front - end wafer; 1001, Front - end wafer substrate; 1011, First surface; 1012, Second surface; 1002, Semiconductor substrate; 101, Substrate; 102, Protective layer; 1021, Gate dielectric layer; 1022, Etch stop layer; 103, Dielectric layer; 104, Shallow trench isolation structure; 105, Gate structure; 106, Contact structure; 1061, Contact extension; 1062, Contact connection; 200, Substrate; 210, Isolation layer; 220, Photoelectric induction layer; 220a, Photoelectric induction region; 221, First photoelectric induction material layer; 222, Second photoelectric induction material layer; 223, Third photoelectric induction material layer; 224, Fourth photoelectric induction material layer; 230, Isolation structure; 240, Insulating layer; 250, Grating material layer; 251, First sub - grating material layer; 252, Second sub - grating material layer; 253, Third sub - grating material layer; 260, Target grating structure; 261, First grating layer; 262, Second grating layer; 263, Third grating layer; 270, Transition grating structure; 280, Inter - layer doping structure; 400, Image sensor; 410, Filter structure. Detailed implementation manners

[0032] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments.

[0033] The accompanying drawings provided in the embodiments of the present application only illustrate the basic concept of the present application in a schematic manner. The components shown in the drawings only relate to those in the present application, rather than being drawn according to the number, shape, and size of the components in actual implementation. The form, quantity, and proportion of each component in actual implementation may change, and the layout form of its components may also be more complex.

[0034] In the description of the embodiments of the present application, it should be understood that the terms "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", "center", etc., the orientation or positional relationship indicated by them is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present application, rather than indicating or implying that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it cannot be understood as a limitation to the present application. The terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of the described features.

[0035] In related technologies, during the process of manufacturing a back-illuminated incident CMOS image sensor, a high-energy ion implantation process is usually adopted in the front-end process to fabricate a photodiode. During the ion implantation process, a large number of high-speed ions collide with the semiconductor lattice, resulting in a large number of point defects, dislocations and other lattice damages in the region near the surface of the semiconductor substrate. These lattice damages may affect the transport of photo-generated carriers, reduce the mobility and quantum efficiency of the carriers in the photodiode, increase the dark current, cause enhanced crosstalk between pixels, and lead to blurred imaging of the image sensor.

[0036] In addition, the lattice damage effect is related to ion implantation parameters such as the dose and energy of ion implantation. The degree of lattice damage will increase with the increase of the dose and ion energy. Even when the ion implantation energy is too high, the lattice structure near the semiconductor substrate surface within the ion range will be completely destroyed and become amorphous, resulting in a decline or even failure of the photodiode performance and a reduction in the reliability of the image sensor.

[0037] Therefore, it is necessary to provide a semiconductor structure, a manufacturing method of the semiconductor structure and an image sensor. By forming a photoelectric functional layer including a photoinductive layer and an isolation structure on the substrate surface, the photoinductive layer is separated into multiple photoinductive regions by the isolation structure. Each photoinductive region includes multiple stacked photoinductive material layers and an interlayer doping structure. Among them, the interlayer doping structure extends along the normal direction of the photoinductive layer, and the doping type of the interlayer doping structure is the same as that of the photoinductive layer. The interlayer doping structure is formed by an ion implantation process. Along the normal direction of the photoinductive layer, the ion implantation depth for forming the interlayer doping structure is at least greater than the thickness of the photoinductive material layer farthest from the substrate. Since the doping type of the interlayer doping structure is the same as that of the photoinductive layer, and the interlayer doping structure spans at least two photoinductive material layers along the normal direction of the photoinductive layer, on the one hand, the damage to the device caused by ion implantation can be reduced, and the reliability of the image sensor can be improved. On the other hand, the crosstalk and dark current between adjacent pixels can be reduced, the number of photo-generated carriers in the photoelectric conversion process can be increased, the photoelectric conversion efficiency of the photodiode can be improved, and the imaging quality of the image sensor can be improved.

[0038] Please refer to Figure 1 An embodiment of the present application provides a manufacturing method of a semiconductor structure. The manufacturing method of the semiconductor structure may include the following steps.

[0039] S110: Provide a substrate.

[0040] In this embodiment, the substrate can be prepared based on a semiconductor substrate. Specifically, the front-end wafer completed in the previous process can be bonded to a carrier wafer, and then the bonded wafer can be flipped and the material on the back surface of the front-end wafer can be thinned to obtain a semiconductor substrate. The thinning degree of the material on the back surface of the front-end wafer can be determined according to process requirements, and the embodiments of the present application do not make specific limitations. Among them, the front-end wafer can be manufactured through the following process steps.

[0041] Please refer to Figure 2 . The front-end wafer 100 may include a front-end wafer substrate 1001, a protective layer 102, a dielectric layer 103, and a plurality of shallow trench isolation structures 104. Among them, a plurality of gate structures 105 are arranged at intervals within the protective layer 102, and a plurality of contact structures 106 are arranged at intervals within the dielectric layer 103. The specific structures of each part of the front-end wafer 100 are as follows:

[0042] The front-end wafer substrate 1001 may be composed of a semiconductor material, an insulating material, a conductive material, or any combination thereof. For example, the front-end wafer substrate 1001 may be made of materials such as silicon (Si), silicon germanium (SiGe), silicon germanium carbide (SiGeC), silicon carbide (SiC), etc. The front-end wafer substrate 1001 may be a single-layer structure or a multi-layer structure. In this embodiment, a silicon wafer is used as the front-end wafer substrate 1001. Specifically, the thickness of the front-end wafer substrate 1001 may be 2.5um to 3.5um, for example, 2.5um, 2.8um, 3um, 3.5um, etc. The front-end wafer substrate 1001 has opposite first surface 1011 and second surface 1012.

[0043] A plurality of shallow trench isolation structures 104 are formed in the front-end wafer substrate 1001. The shallow trench isolation structures 104 may extend from the second surface 1012 towards the first surface 1011. The distance between the shallow trench isolation structures 104 and the first surface 1011 is less than the thickness of the front-end wafer substrate 1001. The material filled in the shallow trench isolation structures 104 may be an oxide to isolate electrical crosstalk between different active regions and improve the imaging quality of the image sensor. The shallow trench isolation structures 104 may be formed in any manner in related technologies, and will not be elaborated here.

[0044] After the plurality of shallow trench isolation structures 104 are formed, a protective layer 102, a plurality of gate structures 105, a dielectric layer 103, and a plurality of contact structures 106 can be sequentially formed on the second surface 1012. Among them, the protective layer 102 may include a gate dielectric layer 1021 and an etch stop layer 1022. The specific formation process is as follows:

[0045] After multiple shallow trench isolation structures 104 are formed, a gate dielectric layer 1021 for isolation and threshold voltage adjustment can be formed on the second surface 1012 first. Specifically, methods such as thermal oxidation or chemical vapor deposition (CVD) can be used to form a gate dielectric layer 1021 made of silicon dioxide or a low dielectric constant material on the second surface 1012.

[0046] After the gate dielectric layer 1021 is formed, polysilicon can be deposited on the surface of the gate dielectric layer 1021 away from the front - end wafer substrate 1001 by methods such as chemical vapor deposition to form a plurality of gate structures 105 distributed at intervals.

[0047] After the plurality of gate structures 105 are formed, an etch stop layer 1022 can be formed between the surface of the gate dielectric layer 1021 away from the front - end wafer substrate 1001 and the plurality of gate structures 105. Specifically, the etch stop layer 1022 can be multiple layers, for example, two layers. To reduce the risk of the etch stop layer 1022 cracking and causing the contact structure 106 to fail, the material of the etch stop layer 1022 can include silicon oxide, silicon carbonitride, or silicon nitride, etc. The etch stop layer 1022 can be formed by methods such as chemical vapor deposition or physical vapor deposition (PVD).

[0048] After the etch stop layer 1022 is formed, a dielectric layer 103 can be formed on the surface of the etch stop layer 1022 away from the front - end wafer substrate 1001. Specifically, to improve the reliability of the contact structure 106, a dielectric layer 103 made of silicon dioxide or other low dielectric constant materials can be formed by methods such as chemical vapor deposition or physical vapor deposition.

[0049] Subsequently, the dielectric layer 103 is etched to form a plurality of openings, and a conductive material is deposited in the openings. For example, titanium, titanium nitride, and tungsten are deposited to form a plurality of contact extensions 1061 that are in contact with the gate structures 105. Then, a contact connection portion 1062 for connecting to other conductive layers is formed on the surface of the dielectric layer 103 away from the front - end wafer substrate 1001, obtaining the front - end wafer 100. The contact connection portion 1062 and the contact extension 1061 form the contact structure 106.

[0050] In the embodiments of the present application, the thicknesses of the gate dielectric layer 1021, the etch stop layer 1022, and the dielectric layer 103, as well as the sizes of the gate structure 105 and the contact structure 106 are not specifically limited. During the manufacturing process, the above - mentioned structural parameters can be determined according to process requirements.

[0051] Please refer to Figures 3 to 5。In this embodiment, the substrate 200 may include a substrate 101, an isolation layer 210, a protective layer 102, a dielectric layer 103, a plurality of shallow trench isolation structures 104, a plurality of gate structures 105, and a plurality of contact structures 106. Specifically, the steps of providing the substrate may include sub-steps S111 and S112.

[0052] S111: Form an isolation layer in the substrate of the semiconductor substrate.

[0053] In this embodiment, the isolation layer 210 can be used to achieve electrical isolation between the front-end wafer 100 and the structure formed on the back side of the front-end wafer 100. Specifically, the isolation layer 210 can be formed on the side of the shallow trench isolation structure 104 away from the protective layer 102. To improve the isolation effect, an ion implantation (IMP) process can be used to implant gallium silicide (SiGa) into the semiconductor substrate 1002 to form the isolation layer 210.

[0054] In some embodiments, the isolation layer 210 can be formed by implanting ions of other elements in Group III of the periodic table into the semiconductor substrate 1002. For example, boron ions can be implanted.

[0055] S112: After the isolation layer is formed, remove the substrate of the semiconductor substrate on the side of the isolation layer away from the shallow trench isolation structure to expose the surface of the isolation layer away from the shallow trench isolation structure.

[0056] In this embodiment, a planarization process such as chemical mechanical polishing (CMP) can be used to remove the semiconductor substrate 1002 that does not include the shallow trench isolation structure 104 to obtain the substrate 200.

[0057] S120: Prepare an optoelectronic functional layer on the substrate.

[0058] To reduce the damage to the device caused by ion implantation, the optoelectronic functional layer can be directly formed on the surface of the substrate away from the front-end wafer. At the same time, to reduce crosstalk between pixels, the optoelectronic sensing layer in the optoelectronic functional layer can be set as a multi-layer structure composed of different materials to cover a wider spectral range, reduce the propagation distance of light when passing through the component, and thus reduce light leakage between adjacent pixels.

[0059] In this embodiment, the optoelectronic functional layer can be used to achieve optoelectronic signal conversion based on the photoelectric effect. Specifically, the optoelectronic functional layer can include an optoelectronic sensing layer and an isolation structure. Among them, the optoelectronic sensing layer can be used to generate photo-generated carriers. The isolation structure can be used to divide the optoelectronic sensing layer into multiple optoelectronic sensing regions.

[0060] Please refer to Figure 6The steps of preparing the optoelectronic functional layer on the substrate may include sub-steps S121, S122, S123, and S124.

[0061] S121: Form a plurality of optoelectronic induction regions and isolation structures on the substrate.

[0062] To reduce the lateral movement of carriers between adjacent pixels, the optoelectronic induction layer can be separated into a plurality of optoelectronic induction regions by using the isolation structure, so as to reduce the adverse effect of crosstalk between pixels on the imaging quality of the image sensor.

[0063] Please refer to Figure 7 In this embodiment, an optoelectronic induction layer 220 with an N-type doping can be formed on the surface exposed by the isolation layer 210 first. To reduce crosstalk between pixels and dark current, the optoelectronic induction layer 220 may include a plurality of stacked optoelectronic induction material layers. Specifically, the optoelectronic induction layer 220 may include a first optoelectronic induction material layer 221, a second optoelectronic induction material layer 222, a third optoelectronic induction material layer 223, and a fourth optoelectronic induction material layer 224.

[0064] In this embodiment, the doping elements of the optoelectronic induction material layer may include: phosphorus (P) element, arsenic (As) element, and antimony (Sb) element. To improve the optoelectronic conversion efficiency of the photodiode, among the plurality of optoelectronic induction material layers, the doping elements of adjacent optoelectronic induction material layers are different. An optoelectronic induction material layer with a doping element of phosphorus element is formed between the optoelectronic induction material layer with a doping element of arsenic element and the optoelectronic induction material layer with a doping element of antimony element. Specifically, the doping element of the first optoelectronic induction material layer 221 may be a phosphorus element, that is, the material of the first optoelectronic induction material layer 221 may be phosphosilicon (SiP). The doping element of the second optoelectronic induction material layer 222 may be an arsenic element, that is, the material of the second optoelectronic induction material layer 222 may be arsenosilicon (SiAs). The doping element of the third optoelectronic induction material layer 223 may be a phosphorus element, that is, the material of the third optoelectronic induction material layer 223 may be phosphosilicon (SiP). The doping element of the fourth optoelectronic induction material layer 224 may be an antimony element, that is, the material of the fourth optoelectronic induction material layer 224 may be antimonosilicon (SiSb).

[0065] In some embodiments, the doping type of the optoelectronic induction layer 220 may be P-type. Correspondingly, the doping elements of the optoelectronic induction material layer may include: boron (B) element, gallium (Ga) element, and indium (In) element. The process of forming the optoelectronic induction layer 220 with a P-type doping is similar to the process of forming the optoelectronic induction layer 220 with an N-type doping described above, and will not be elaborated here.

[0066] Please refer to Figure 8After the photoinductive layer 220 is formed, based on the mask corresponding to the isolation structure 230, the photoinductive layer 220 and the isolation layer 210 can be etched to obtain a plurality of etching openings. Then, a glass material is filled into the etching openings by a spin-on process, and planarization is performed to obtain the isolation structure 230. In this embodiment, the isolation structure 230 can be a backside deep trench isolation (BDTI) structure. The shape of the isolation structure 230 is not specifically limited in the embodiments of the present application. The isolation structure 230 can divide the photoinductive layer 220 into a plurality of photoinductive regions 220a.

[0067] S122: Form a transition grid structure on the side of the photoinductive region away from the substrate, and form a target grid structure on the side of the isolation structure away from the substrate.

[0068] To simplify the subsequent process of manufacturing the interlayer doping structure by ion implantation and reduce the number of masks and process steps added during the manufacturing of the interlayer doping structure, the transition grid structure and the target grid structure can be formed first, so that in the subsequent ion implantation process, ions are implanted into the photoinductive region using the two grid structures as masks.

[0069] Please refer to Figure 9 To reduce current leakage and short circuit, in this embodiment, an insulating layer 240 can be formed on the exposed surfaces of the photoinductive layer 220 and the isolation structure 230 first. The material of the insulating layer 240 can be silicon dioxide (SiO2). Subsequently, a grid material layer 250 can be formed on the side of the insulating layer 240 away from the photoinductive layer 220. Specifically, the grid material layer 250 can include a first sub-grid material layer 251, a second sub-grid material layer 252, and a third sub-grid material layer 253 arranged in a stacked manner. Among them, the material of the first sub-grid material layer 251 can be hafnium dioxide (HfO2), the material of the second sub-grid material layer 252 can be titanium nitride (TiN), and the material of the third sub-grid material layer 253 can be tungsten (W). Among them, titanium nitride can be used as a stable layer to reduce crosstalk between pixels.

[0070] Please refer to Figure 10。In this embodiment, after the grating material layer 250 is formed, the grating material layer 250 can be etched based on the masks corresponding to the target grating structure 260 and the transition grating structure 270 to obtain the transition grating structure 270 and the target grating structure 260 that are alternately and spaced apart on the surface of the insulating layer 240 away from the photoelectric induction layer 220. Among them, the target grating structure 260 can be a grating structure corresponding to the isolation structure 230 in the normal direction of the photoelectric induction layer 220. The transition grating structure 270 can be a grating structure corresponding to the photoelectric induction region 220a in the normal direction of the photoelectric induction layer 220. Any two transition grating structures 270 or any two target grating structures 260 are not adjacent. The specific structures of the two grating structures are the same. Taking the target grating structure 260 as an example, the specific structures of the two grating structures will be briefly described.

[0071] The target grating structure 260 may include a first grating layer 261, a second grating layer 262, and a third grating layer 263. Among them, the first grating layer 261 corresponds to the first sub-grating material layer 251, so the material of the first grating layer 261 is hafnium dioxide. The second grating layer 262 corresponds to the second sub-grating material layer 252, so the material of the second grating layer 262 is titanium nitride. The third grating layer 263 corresponds to the third sub-grating material layer 253, so the material of the third grating layer 263 is tungsten. Taking the direction perpendicular to the normal direction of the photoelectric induction layer 220 as the width direction, the widths of the first grating layer 261, the second grating layer 262, and the third grating layer 263 in the width direction can be equal.

[0072] To limit the size of the subsequent formed interlayer doping structure, in this embodiment, the distance between adjacent transition grating structures 270 and target grating structures 260 can fall within the range of 500 nm to 1000 nm. For example, the distance between adjacent transition grating structures 270 and target grating structures 260 can be 500 nm, 600 nm, 750 nm, 900 nm, 1000 nm.

[0073] S123: Using the transition grating structure and the target grating structure as masks, an interlayer doping structure is formed in the photoelectric induction region by an ion implantation process.

[0074] Please refer to Figure 11。In order to increase the number of photo-generated carriers generated when the photo-electric induction layer 220 receives light, improve the photo-electric conversion efficiency of the photo-diode, and further improve the imaging quality of the photo-diode, in this embodiment, the doping type of the ions implanted into the photo-electric induction region 220a can be the same as the doping type of the photo-electric induction layer 220. At the same time, in order to make the cross-layer doping structure 280 extend along the normal direction of the photo-electric induction layer 220 and span at least two photo-electric induction material layers, the normal direction of the photo-electric induction layer 220 can be used as the depth direction of ion implantation and the thickness direction of the photo-electric induction material layer. Along the normal direction of the photo-electric induction layer 220, the ion implantation depth of the cross-layer doping structure 280 is at least greater than the thickness of the photo-electric induction material layer farthest from the substrate. Specifically, the doping type of the photo-electric induction layer 220 and the doping type of the cross-layer doping structure 280 can both be N-type, or both be P-type. For example, when the doping type of the photo-electric induction layer 220 and the doping type of the cross-layer doping structure 280 are both N-type, the doping element of the cross-layer doping structure 280 can be phosphorus. When the cross-layer doping structure 280 spans two photo-electric induction material layers, the cross-layer doping structure 280 can span the fourth photo-electric induction material layer 224 and the third photo-electric induction material layer 223; when the cross-layer doping structure 280 spans three photo-electric induction material layers, the cross-layer doping structure 280 can span the fourth photo-electric induction material layer 224, the third photo-electric induction material layer 223 and the second photo-electric induction material layer 222; when the cross-layer doping structure 280 spans four photo-electric induction material layers, the cross-layer doping structure 280 can span the fourth photo-electric induction material layer 224, the third photo-electric induction material layer 223, the second photo-electric induction material layer 222 and the first photo-electric induction material layer 221.

[0075] S124: Remove the transition grid structure.

[0076] Please refer to Figure 12 。In this embodiment, after the cross-layer doping structure 280 is formed, the transition grid structure 270 can be removed by an etching process to obtain the semiconductor structure 300.

[0077] In some embodiments, in order to activate the doped ions, reduce the generation of dark current, improve the photo-electric performance of the photo-diode, and improve the yield and imaging quality of the image sensor, the semiconductor structure 300 can also be subjected to a single annealing treatment. Specifically, in order to shorten the annealing time and reduce the region of lateral diffusion, so that the boundary of the photosensitive region is clear, laser annealing can be used for the annealing treatment. For example, the laser annealing can be carried out in an oxygen-containing environment, and the specific process parameters are as follows: the pulse energy can be 25mj to 35mj, for example, 25mj, 27mj, 30mj, 32mj, 35mj. The time of laser annealing can be 2s to 4s, for example, 2s, 3s, 4s.

[0078] In some embodiments, the interlayer doping structure 280 may be formed first, and then the target grid structure 260 may be formed. Specifically, after forming a plurality of photoinductive regions 220a and isolation structures 230 on the substrate, based on a mask corresponding to the interlayer doping structure 280, ions may be first implanted into the photoinductive regions 220a to form the interlayer doping structure 280, and then the target grid structure 260 may be formed on the side of the isolation structure 230 away from the substrate.

[0079] Please continue to refer to Figure 12 . Another embodiment of the present application provides a semiconductor structure 300, which may include a substrate and a photo - electric functional layer formed on the surface of the substrate.

[0080] In this embodiment, the photo - electric functional layer may be used to realize photo - electric signal conversion based on the photo - electric effect. Specifically, the photo - electric functional layer may include a photoinductive layer 220 and an isolation structure 230 for separating the photoinductive layer 220 into a plurality of photoinductive regions 220a. Among them, the photoinductive region 220a may include a plurality of stacked photoinductive material layers and an interlayer doping structure 280 extending along the normal direction of the photoinductive layer 220. The doping type of the interlayer doping structure 280 is the same as that of the photoinductive layer 220.

[0081] In this embodiment, the interlayer doping structure 280 may be formed by an ion implantation process. Taking the normal direction of the photoinductive layer 220 as the depth direction of ion implantation and the thickness direction of the photoinductive material layer, along the normal direction of the photoinductive layer 220, the ion implantation depth for forming the interlayer doping structure 280 is at least greater than the thickness of the photoinductive material layer farthest from the substrate.

[0082] In this embodiment, the doping elements of the photoinductive material layer may include: phosphorus element, arsenic element, and antimony element.

[0083] In this embodiment, among the plurality of photoinductive material layers, the doping elements of adjacent photoinductive material layers are different. Among them, a photoinductive material layer with a doping element of phosphorus element may be formed between a photoinductive material layer with a doping element of arsenic element and a photoinductive material layer with a doping element of antimony element.

[0084] In this embodiment, the doping element of the interlayer doping structure 280 may be phosphorus element.

[0085] In this embodiment, the semiconductor structure 300 may further include a target grid structure 260 formed on a side of the isolation structure 230 away from the substrate. Specifically, the target grid structure 260 may include a first grid layer 261, a second grid layer 262, and a third grid layer 263 arranged in a stacked manner. Among them, the material of the first grid layer 261 may be hafnium dioxide, the material of the second grid layer 262 may be titanium nitride, and the material of the third grid layer 263 may be tungsten.

[0086] Regarding the technical effects of the semiconductor structure 300 described in the above embodiments, reference may be made to other embodiments of the present application for comparison and explanation, which will not be elaborated here.

[0087] Please refer to Figure 13 . Another embodiment of the present application provides an image sensor 400, which may include: the semiconductor structure 300 described in the above embodiments, or a semiconductor structure 300 manufactured by the manufacturing method of the semiconductor structure described in the above embodiments, and a color filter structure 410.

[0088] In this embodiment, a color filter structure 410 may be formed between adjacent target grid structures 260. Specifically, the color filter structure 410 may be formed on a surface of the insulating layer 240 away from the photoelectric induction layer 220. The color filter structure 410 may include a plurality of color filters, and the plurality of color filters form a color filter array.

[0089] In this embodiment, the color filter structure 410 may include color filters of three primary colors, that is, blue color filters, green color filters, and red color filters. Specifically, the color filters may be polymeric materials, such as negative photoresists based on acrylic polymers, and may contain color dyes. When light passes through the color filters, the color can be changed, maintaining a high transmittance in a specific wavelength band, thereby enhancing the effect of photoelectric conversion. The color filters may be arranged in any suitable combination.

[0090] In some embodiments, a transparent filter may also be provided on the basis of the color filters. The blue color filters, green color filters, red color filters, and transparent filters may be arranged in an interleaved manner.

[0091] In this embodiment, the top of the color filter structure 410 may be in an arc shape protruding outward, so as to focus the incident light on the photoelectric induction layer 220. According to the light collection requirements, the curvature of the surface of the color filter structure 410 can be changed to improve the photosensitive efficiency.

[0092] In some embodiments, after forming the filter structure 410, a microlens structure may be continuously formed on the filter structure 410. The microlens structure can be formed by any method for forming a microlens structure, and the embodiments of the present application do not make specific limitations. The number of filter structures 410 can be set according to actual requirements and is only used as an example in the drawings of this embodiment.

[0093] Regarding the technical effects of the image sensor 400 described in the above embodiments, reference can be made to other embodiments of the present application for comparative explanation and will not be elaborated here.

[0094] In multiple embodiments of the present application, by forming a photoelectric functional layer including a photoelectric induction layer and an isolation structure on the substrate surface, the photoelectric induction layer is separated into multiple photoelectric induction regions by the isolation structure. Each photoelectric induction region includes multiple stacked photoelectric induction material layers and an interlayer doping structure. Among them, the interlayer doping structure extends along the normal direction of the photoelectric induction layer, and the doping type of the interlayer doping structure is the same as that of the photoelectric induction layer. The interlayer doping structure is formed by an ion implantation process. Along the normal direction of the photoelectric induction layer, the ion implantation depth for forming the interlayer doping structure is at least greater than the thickness of the photoelectric induction material layer farthest from the substrate. The unexpected effects achieved include: Since the doping type of the interlayer doping structure is the same as that of the photoelectric induction layer, and the interlayer doping structure spans at least two photoelectric induction material layers along the normal direction of the photoelectric induction layer, on the one hand, the damage to the device caused by ion implantation can be reduced, and the production yield and reliability of the image sensor can be improved. On the other hand, the crosstalk and dark current between adjacent pixels can be reduced, the number of photo-generated carriers in the photoelectric conversion process can be increased, the photoelectric conversion efficiency of the photodiode can be improved, and the imaging quality of the image sensor can be improved.

[0095] It can be understood that the specific examples in the present application are only to help those skilled in the art better understand the embodiments of the present application, rather than limiting the scope of the present application.

[0096] It can be understood that in various embodiments of the present application, the magnitudes of the sequence numbers of the processes do not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.

[0097] It can be understood that the various embodiments described in the present application can be implemented alone or in combination, and the embodiments of the present application do not limit this.

[0098] Unless otherwise specified, all technical and scientific terms used in the embodiments of this application have the same meanings as those commonly understood by those skilled in the technical field of this application. The terms used in this application are only for the purpose of describing specific embodiments and are not intended to limit the scope of this application. The term "and / or" used in this application includes any and all combinations of one or more of the related listed items. The singular forms "a", "above-mentioned" and "the" used in the embodiments of this application are also intended to include the plural forms unless the context clearly indicates otherwise.

[0099] In several embodiments provided by this application, it should be understood that the disclosed semiconductor structure or image sensor can be implemented in other ways. For example, the embodiments of the semiconductor structure or image sensor described above are merely illustrative.

[0100] As described above, these are only specific embodiments of this application, but the protection scope of this application is not limited thereto. Any person skilled in the technical field of this application can easily think of changes or substitutions within the technical scope disclosed in this application, and all of them should be covered by the protection scope of this application. Therefore, the protection scope of this application shall be subject to the protection scope of the claims.

Claims

1. A manufacturing method of a semiconductor structure, characterized in that, The method includes: providing a substrate; forming a photoelectric functional layer on the surface of the substrate; the photoelectric functional layer is used to realize photoelectric signal conversion based on the photoelectric effect; the photoelectric functional layer includes a photoinductive layer and an isolation structure for separating the photoinductive layer into a plurality of photoinductive regions; the photoinductive region includes four stacked photoinductive material layers and a cross-layer doping structure extending along the normal direction of the photoinductive layer; the doping type of the cross-layer doping structure is the same as that of the photoinductive layer; wherein, the semiconductor structure further includes a target grid structure formed on the side of the isolation structure away from the substrate; the step of preparing the photoelectric functional layer on the substrate includes: forming a plurality of the photoinductive regions and the isolation structure on the substrate; forming a transition grid structure on the side of the photoinductive region away from the substrate, and forming a target grid structure on the side of the isolation structure away from the substrate; wherein, the transition grid structure and the target grid structure are alternately and spaced apart; using the transition grid structure and the target grid structure as masks, forming the cross-layer doping structure in the photoinductive region by an ion implantation process; removing the transition grid structure; wherein, taking the normal direction of the photoinductive layer as the depth direction of ion implantation and the thickness direction of the photoinductive material layer, along the normal direction of the photoinductive layer, the ion implantation depth of forming the cross-layer doping structure is greater than the thickness of the remaining photoinductive material layers except the photoinductive material layer closest to the substrate among the four photoinductive material layers.

2. The method according to claim 1, characterized in that, The distance between adjacent ones of the transition grid structure and the target grid structure falls within the range of 500 nm to 1000 nm.

3. A semiconductor structure, characterized in that, The semiconductor structure is manufactured according to the manufacturing method of the semiconductor structure as claimed in claim 1 or 2; the semiconductor structure includes: a substrate; a photoelectric functional layer formed on the surface of the substrate; the photoelectric functional layer is used to realize photoelectric signal conversion based on the photoelectric effect; the photoelectric functional layer includes a photoinductive layer and an isolation structure for separating the photoinductive layer into a plurality of photoinductive regions; the photoinductive region includes four stacked photoinductive material layers and a cross-layer doping structure extending along the normal direction of the photoinductive layer; the doping type of the cross-layer doping structure is the same as that of the photoinductive layer; a target grid structure formed on the side of the isolation structure away from the substrate; wherein, the cross-layer doping structure is formed by an ion implantation process with the transition grid structure and the target grid structure as masks; taking the normal direction of the photoinductive layer as the depth direction of ion implantation and the thickness direction of the photoinductive material layer, along the normal direction of the photoinductive layer, the ion implantation depth of forming the cross-layer doping structure is greater than the thickness of the remaining photoinductive material layers except the photoinductive material layer closest to the substrate among the four photoinductive material layers.

4. The semiconductor structure according to claim 3, wherein, The doping elements of the photoinductive material layer include: phosphorus element, arsenic element and antimony element.

5. The semiconductor structure according to claim 4, wherein, Among the multiple optoelectronic induction material layers, the doping elements of adjacent optoelectronic induction material layers are different.

6. The semiconductor structure according to claim 4, wherein An optoelectronic induction material layer with a doping element of phosphorus is formed between the optoelectronic induction material layer with a doping element of arsenic and the optoelectronic induction material layer with a doping element of antimony.

7. The semiconductor structure according to claim 3, wherein, The doping element of the cross-layer doping structure is phosphorus.

8. The semiconductor structure according to claim 3, wherein The target grid structure includes a first grid layer, a second grid layer, and a third grid layer arranged in a stacked manner, wherein the material of the first grid layer is hafnium dioxide, the material of the second grid layer is titanium nitride, and the material of the third grid layer is tungsten.

9. An image sensor, characterized in that, Comprising: A semiconductor structure manufactured by the manufacturing method of the semiconductor structure according to any one of claims 1 to 2 or a semiconductor structure according to any one of claims 3 to 8.

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