Preparation method of solar cell and solar cell

Abstract

A method for preparing a solar cell and a solar cell, belonging to the field of photovoltaics. The method for preparing a solar cell includes: forming an alkali-resistant film layer on the front surface of a silicon substrate; forming a first tunneling layer and a first doping layer on the back surface of the silicon substrate; removing the first doping layer, the first tunneling layer and a part of the silicon substrate in the region outside the first region; forming a second tunneling layer and a second doping layer on the back surface, and the doping type of the second doping layer is opposite to that of the first doping layer; removing the second doping layer, the second tunneling layer and a part of the silicon substrate in the region outside the second region; removing the mask layer; forming a first electrode in contact with the first doping layer in the first region, and forming a second electrode in contact with the second doping layer in the second region. By means of the mask layer, the present invention protects the front surface during subsequent polishing and other processes, so that a thinner original silicon wafer can be selected, and two doping layers can be accurately divided and isolated on the back surface, achieving the goals of reducing costs, improving the process yield and enhancing the battery performance.

Description

Technical Field

[0001] The present invention relates to the field of photovoltaics, and particularly to a method for manufacturing a solar cell and a solar cell. Background Art

[0002] As the core product of the photovoltaic industry, crystalline silicon solar cells have continuously made progress in improving the photoelectric conversion efficiency, reducing the manufacturing cost, and enhancing the reliability in recent years. With the evolution of technology, from traditional PERC (Passivated Emitter and Rear Cell) cells, TOPCon (Tunnel Oxide Passivated Contact) cells to various back contact (BC) cell solutions with optimized structures, they have all become the key research and industrialization directions in the industry.

[0003] Among them, for a BC cell, spaced P-type semiconductor structures and N-type semiconductor structures are prepared on the back of the cell, and a first electrode and a second electrode are respectively formed thereon. The positive and negative electrodes of the BC cell are both on the back of the cell, and there is no metal electrode shading on the front, avoiding the shading loss of the metal electrode, greatly improving the optical absorption of the cell, and achieving a good short-circuit current density; and the BC cell eliminates the front surface emitter, reducing the front surface recombination loss.

[0004] For a TOPCon cell, a tunneling layer with a thickness of 1 nm to 2 nm is deposited on the back of the silicon substrate, and then a doped polysilicon layer is deposited. The two together form a passivated contact structure, providing good interface passivation for the back of the silicon substrate. The ultra-thin oxide layer allows electrons to tunnel into the polysilicon layer while blocking the transport of holes, reducing the recombination current. The lateral transport characteristics of the doped layer reduce the series resistance. The above two characteristics together improve the open-circuit voltage, fill factor of the solar cell, and the conversion efficiency of the solar cell.

[0005] The combination of a TOPCon cell and a back BC cell forms a TBC (TOPCon - Back Contact) cell, fully integrating the advantages of both, and is expected to achieve the goal of further improving the photoelectric conversion efficiency and the overall performance of the cell. In practical applications, the high-efficiency and low-cost TBC cell helps to reduce the component cost and increase the power generation revenue in distributed power generation systems and large-scale photovoltaic power stations.

[0006] The inventors' research found that: Although the TBC cell integrates the advantages of TOPCon and BC technologies, the existing technologies still face several problems. If patterned P regions and N regions are directly formed on the back of the silicon substrate, a high process precision is required, otherwise there is a tendency for the P region and the N region to be connected at a certain point, resulting in leakage. If the traditional TOPCon technology is used to fabricate the back structure, multiple double-sided alkaline etching and cleaning operations are required to control the cell quality and reduce the defect density, and the process will inevitably have a high requirement for the silicon wafer thickness. Too thick silicon wafers not only increase the material cost but also indirectly limit the mass production scale and market competitiveness of the cells. At the same time, how to maintain a high consistency and yield rate in complex steps such as multi-layer film deposition, diffusion, doping, cleaning, and texturing is also a challenge that technicians need to face. The TBC cell manufacturing process under the existing technology has not reached an ideal level in key indicators such as silicon wafer thinning, reducing the fragmentation rate, and improving the efficiency, and it is urgent to solve these problems by optimizing the cell structure and improving the process steps.

[0007] In view of this, it is necessary to provide an improved method for manufacturing a solar cell and a solar cell to solve the above technical problems. Summary of the Invention

[0008] The present invention aims to at least solve one of the technical problems existing in the prior art. The present invention provides a method for manufacturing a solar cell and a solar cell. By depositing an alkali-resistant mask layer on the front side of the silicon substrate, the front side is protected from etching during subsequent polishing and cleaning processes, so that a thinner original silicon wafer can be selected without increasing the fragmentation rate, and etching can be performed multiple times on the back side to accurately divide and isolate the two doped layers to prevent leakage, and finally achieve the goals of reducing the raw material cost, improving the process yield rate, and enhancing the cell performance.

[0009] A method for manufacturing a solar cell includes the following steps: forming a mask layer on the front side of the silicon substrate, the mask layer being an alkali-resistant film layer; forming a first tunneling layer and a first doped layer on the back side of the silicon substrate; the back side of the silicon substrate has a first region and a second region arranged at intervals, removing the first doped layer, the first tunneling layer, and part of the silicon substrate in the region outside the first region; forming a second tunneling layer and a second doped layer on the back side of the silicon substrate, the doping type of the second doped layer being opposite to that of the first doped layer; removing the second doped layer, the second tunneling layer, and part of the silicon substrate in the region outside the second region; removing the mask layer; forming a first electrode in contact with the first doped layer in the first region, and forming a second electrode in contact with the second doped layer in the second region.

[0010] In some embodiments, the mask layer is doped with a gettering element, and the doping content of the gettering element is 1 wt% - 4 wt%.

[0011] In some embodiments, the gettering element is a Group III element and / or a Group V element; or the gettering element is phosphorus and / or boron.

[0012] In some embodiments, the mask layer is a single-layer film; or the mask layer includes a first mask layer formed on the front surface of the silicon substrate and a second mask layer formed on the surface of the first mask layer away from the silicon substrate, and the first mask layer is doped with the gettering element.

[0013] In some embodiments, the mask layer includes a first mask layer formed on the front surface of the silicon substrate and a second mask layer formed on the surface of the first mask layer away from the silicon substrate; the first mask layer is a film layer of one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride doped with a gettering element; and / or the second mask layer is a film layer of one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride; and / or the thickness of the first mask layer is less than the thickness of the second mask layer; and / or the thickness of the first mask layer is 10%-40% of the thickness of the entire mask layer.

[0014] In some embodiments, "removing the mask layer" includes: removing the mask layer by pickling or removing the mask layer by RCA cleaning.

[0015] In some embodiments, after removing the mask layer, a textured structure is formed on the front surface of the silicon substrate.

[0016] A solar cell includes: a silicon substrate, the back surface of the silicon substrate having a first region, a second region, and a spacer region located between the first region and the second region, the width of the spacer region being 30 μm - 100 μm, and the thickness of the silicon substrate in the first region being greater than the thickness of the silicon substrate in the second region; a first tunneling layer in the first region, a first doping layer on the side of the first tunneling layer away from the silicon substrate, the first doping layer having a doping type opposite to that of the silicon substrate; a second tunneling layer in the second region, a second doping layer on the side of the second tunneling layer away from the silicon substrate, the second doping layer having the same doping type as the silicon substrate; a first electrode in contact with the first doping layer; and a second electrode in contact with the second doping layer.

[0017] In some embodiments, the thickness of the silicon substrate in the first region is 3 μm - 8 μm greater than the thickness of the silicon substrate in the second region.

[0018] In some embodiments, the ratio of the area of the first region to the area of the second region is 0.5:1 - 1.5:1; or, the ratio of the width of the first region to the width of the second region is 0.5:1 - 1.5:1; or, the width of the first region is 200 μm - 800 μm and the width of the second region is 200 μm - 800 μm.

[0019] In some embodiments, the solar cell further includes a passivation layer on the side where the back surface of the silicon substrate is located, and the passivation layer contacts the surface of the silicon substrate exposed outward at the spacer region; or, the solar cell further includes a passivation layer on the side where the back surface of the silicon substrate is located, the passivation layer contacts the surface of the silicon substrate exposed outward at the spacer region at the spacer region, the passivation layer contacts the surface of the first doped layer away from the silicon substrate and / or the side surface facing the spacer region in the first region, and the passivation layer contacts the surface of the second doped layer away from the silicon substrate and / or the side surface facing the spacer region in the second region.

[0020] In some embodiments, the solar cell further includes an antireflection layer on the side where the back surface of the silicon substrate is located, and the antireflection layer contacts the surface of the passivation layer away from the silicon substrate; or, the antireflection layer contacts the surface of the first doped layer away from the silicon substrate in the first region, contacts the surface of the second doped layer away from the silicon substrate in the second region, and contacts the surface of the passivation layer exposed outward in the spacer region in the spacer region.

[0021] In some embodiments, in the direction away from the silicon substrate, the passivation layer in direct contact with the back surface of the silicon substrate exposed in the spacer region is an aluminum oxide layer with a thickness of 2 nm - 7 nm.

[0022] In some embodiments, the silicon substrate is an N-type silicon substrate, the first doped layer is a P-type doped layer, and the second doped layer is an N-type doped layer; or, the silicon substrate is an N-type silicon substrate, the first doped layer is a boron-doped polysilicon layer, and the second doped layer is a phosphorus-doped polysilicon layer.

[0023] Compared with the prior art, the beneficial effects of the present invention are as follows: By depositing an alkali-resistant mask layer on the front side of the silicon substrate, the front side is protected during subsequent polishing and alkali etching processes, reducing the etching amount on the side where the front side is located; on the one hand, a thinner original silicon wafer can be selected without increasing the fragmentation rate, ultimately achieving the goals of reducing raw material costs, improving process yield, and enhancing battery performance; on the other hand, on the premise of protecting the front side of the silicon substrate, alkali etching can be performed multiple times on the back side, so that the thickness of the silicon substrate in the first region of the solar cell is greater than the thickness of the silicon substrate in the second region, and the width of the spacer is appropriately reduced, accurately dividing and isolating the first doping structure and the second doping structure in the extension direction and thickness direction of the silicon substrate, expanding the light absorption area and reducing leakage, which is beneficial to improving battery efficiency.

[0024] Furthermore, by utilizing the organic cooperation of the mask layer with the impurity-absorbing function on the front side and the first doping layer and the second doping layer on the back side, double-sided impurity absorption is achieved, reducing the adverse effects of metal impurities on device performance and improving the open-circuit voltage and conversion efficiency; by using the mask layer to protect the front side during the steps of double-sided polishing and alkali etching to remove the doping layer in the local area, the excessive thinning of the front-side silicon wafer is effectively avoided, enabling the present invention to use a thinner silicon wafer and reducing costs; at the same time, the process flow of this method has high consistency and scalability, facilitating large-scale production. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a flowchart of a method for manufacturing a solar cell according to an embodiment of the present invention.

[0026] Figure 2 It is a schematic diagram after preparing a mask layer on the front side of the silicon substrate.

[0027] Figure 3 For Figure 2 It is a schematic diagram after preparing a first tunneling layer, a first polycrystalline silicon doped layer, and a BSG layer on the back side of the silicon substrate on the basis of

[0028] Figure 4 For Figure 3 It is a schematic diagram after removing the first doping layer and the first tunneling layer in the area outside the first region on the basis of

[0029] Figure 5 For Figure 4 It is a schematic diagram after preparing a second tunneling layer, a second doping layer, and a PSG layer on the back side of the silicon substrate on the basis of

[0030] Figure 6 For Figure 5 It is a schematic diagram after removing the second doping layer and the second tunneling layer in the area outside the second region on the basis of

[0031] Figure 7 ForFigure 6 Schematic diagram after removing the mask layer on the front side based on [reference].

[0032] Figure 8 For [reference], Figure 7 Schematic diagram after texturing the front side of the silicon substrate based on [reference].

[0033] Figure 9 For [reference], Figure 8 Schematic diagram after removing the BSG layer in the first region and the PSG layer in the second region based on [reference].

[0034] Figure 10 For [reference], Figure 9 Schematic diagram after fabricating the first electrode and the second electrode based on [reference].

[0035] Figure 11 For [reference], Figure 9 Schematic diagram after sequentially fabricating the passivation layer and the antireflection layer on both sides, and then fabricating the first electrode and the second electrode on the back side based on [reference].

[0036] Figure 12 Is Figure 11 Partial enlarged view of.

[0037] Figure 13 Schematic diagram of the structure of the solar cell in another embodiment of the present invention.

[0038] Figure 14 For Figure 13 Partial enlarged view of.

[0039] Figure 15 Back side schematic diagram of the solar cell in one embodiment of the present invention.

[0040] Figure 16 For Figure 15 Partial enlarged view of.

[0041] 1 - silicon substrate, 11 - first region, 12 - second region, 13 - spacer region, 14 - third region, 15 - fourth region, 2 - mask layer, 31 - first tunneling layer, 32 - first doping layer, 33 - first oxide layer; 41 - second tunneling layer, 42 - second doping layer, 43 - second oxide layer, 5 - passivation layer, 6 - antireflection layer, 7 - first electrode, 8 - second electrode. Detailed implementation manners

[0042] The present invention will be described in detail below with reference to the specific implementation manners shown in the drawings. However, these implementation manners do not limit the present invention; any structural, methodical, or functional transformation made by those of ordinary skill in the art based on these implementation manners is included within the protection scope of the present invention.

[0043] In the various drawings of the present invention; for the convenience of illustration; the dimensions of certain structures or parts are exaggerated relative to other structures or parts; therefore, it is only used to illustrate the basic structure of the subject matter of the present invention.

[0044] Please refer to Figures 1 to 12 As shown, the present invention provides a method for preparing a solar cell, and a solar cell is prepared based on a silicon substrate 1.

[0045] For the convenience of description, with reference to the silicon substrate 1, the light-receiving surface (or main light-receiving surface) of the silicon substrate 1 is defined as the front surface, and the backlight surface (or secondary light-receiving surface) disposed opposite to the light-receiving surface is defined as the back surface. The film layers located on the front surface of the silicon substrate 1 are collectively referred to as the front film layers. The surface of the front film layer away from or facing away from the silicon substrate 1 is the front surface of the corresponding front film layer, and the surface of the front film layer facing the silicon substrate 1 is the back surface of the corresponding front film layer. The film layers located on the back surface of the silicon substrate 1 are collectively referred to as the back film layers. The surface of the back film layer facing the silicon substrate 1 is the front surface of the corresponding back film layer, and the surface of the back film layer away from or facing away from the silicon substrate 1 is the back surface of the corresponding back film layer.

[0046] The back surface of the silicon substrate 1 has a first region 11, a second region 12 arranged at intervals, and a spacer region 13 located between the first region 11 and the second region 12. The first region 11 is used to form a P-type doping structure, simply referred to as the P region, the second region 12 is used to form an N-type doping structure, simply referred to as the N region, and the spacer region 13 is used to separate the P region and the N region to prevent leakage.

[0047] The first region 11, the second region 12, and the spacer region 13 are defined regions. In some embodiments, a plurality of the first regions 11 and a plurality of the second regions 12 are alternately arranged, and any adjacent first region 11 and second region 12 are separated by the spacer region 13.

[0048] The inventors have found through research that the area ratio of the first region 11 and the second region 12 will affect the open-circuit voltage (Voc) and short-circuit current density (Jsc) of the solar cell, thereby affecting the efficiency of the cell. Specifically, when the area of the first region 11 increases, the area of the second region 12 correspondingly decreases, which will reduce the passivation performance of the entire back surface and reduce the open-circuit voltage of the cell; conversely, reducing the area of the first region 11 will reduce the short-circuit current density of the cell.

[0049] In one embodiment, the ratio of the area of the first region 11 to the area of the second region 12 is 0.5:1 - 1.5:1, so that the P region and the N region have a good ratio, and the short-circuit current density and open-circuit voltage of the solar cell reach a balance, and the efficiency of the cell is relatively good.

[0050] In one embodiment, the first region 11 and the second region 12 are arranged alternately. In the arrangement direction of the first region 11 and the second region 12, the ratio of the width W1 of the first region 11 to the width W2 of the second region 12 is 0.5:1 - 1.5:1. In the direction perpendicular to the arrangement direction of the first region 11 and the second region 12, the sizes of the first region 11 and the second region 12 are substantially the same.

[0051] In one example, the width W1 of the first region 11 is 200 μm - 800 μm, and the width W2 of the second region 12 is 200 μm - 800 μm.

[0052] In one embodiment, as Figure 15 and Figure 16 shown, in the implemented embodiment, the first region 11 and the second region 12 preferably have a finger-like distribution, and the spacer region 13 separates the two to prevent leakage between the P region and the N region and reduce the battery efficiency. Specifically, the first region 11 and the second region 12 are alternately distributed along a first direction, and the first region 11 and the second region 12 are arranged with a preset distance offset in a second direction perpendicular to the first direction. Further, a third region 14 extending along the second direction connects a plurality of the first regions 11, and the third region 14 is used to form a first bus electrode connected in series with the first electrode 7; a fourth region 15 extending along the second direction connects a plurality of second regions 12, and the fourth region 15 is used to form a second bus electrode connected in series with the second electrode 8.

[0053] In one embodiment, the width W3 of the spacer region 13 is 30 μm - 100 μm, preferably 70 μm ± 10 μm, to ensure the isolation between the P region and the N region and avoid leakage. In some embodiments, the silicon substrate 1 is an N-type single-crystalline silicon wafer with a resistivity of 0.5 ohm·m - 1.5 ohm·m and a thickness of 140 μm ± 20 μm. Hereinafter, the thickness of the silicon substrate 1 is taken as 140 μm for illustration.

[0054] Please refer to Figures 1 to 12As shown in the figure, the method for preparing the solar cell includes the following steps: forming a mask layer 2 on the front surface of the silicon substrate 1, and the mask layer 2 is an alkali-resistant film layer; forming a first tunneling layer 31 and a first doping layer 32 on the back surface of the silicon substrate 1, and the first doping layer 32 is located on the side of the first tunneling layer 31 away from the silicon substrate 1; removing the first doping layer 32 in the area outside the first region 11; forming a second tunneling layer 41 and a second doping layer 42 on the back surface of the silicon substrate 1, the second doping layer 42 is located on the side of the second tunneling layer 41 away from the silicon substrate 1, and the doping type of the second doping layer 42 is opposite to that of the first doping layer 32; removing the second doping layer 42 in the area outside the second region 12; removing the mask layer 2; forming a first electrode 7 in contact with the first doping layer 32 in the first region 11; forming a second electrode 8 in contact with the second doping layer 42 in the second region 12.

[0055] Please refer to Figure 2 As shown in the figure, in the present invention, by forming the mask layer 2 with alkali-resistant characteristics on the front surface of the silicon substrate 1, the front surface is protected during subsequent polishing, cleaning, and etching processes, reducing or avoiding etching and thinning of the silicon substrate 1 from the front surface. Thus, a thinner original silicon wafer can be selected without increasing the fragmentation rate, ultimately achieving the goals of reducing raw material costs, improving process yield, and enhancing battery performance.

[0056] The thicker the mask layer 2, the better the protection effect on the front surface of the silicon substrate 1, and the corresponding cost will increase. In one embodiment, the thickness of the mask layer 2 is 10 nm - 100 nm. If the thickness of the mask layer 2 is below this range, the protection effect on the front surface will be weakened. If the thickness of the mask layer 2 is too thick, the deposition and removal costs will increase.

[0057] The inventors have found through research that in the existing battery preparation process, it is often only possible to effectively perform gettering on the back surface of the silicon substrate 1, and it is impossible to effectively perform gettering on the front surface of the silicon substrate 1 without increasing process complexity and fragmentation rate. The lack of double-sided gettering will cause metal impurities in the silicon substrate 1 to be difficult to fully remove, thus affecting the open-circuit voltage and conversion efficiency of the solar cell.

[0058] In view of this, in some embodiments of the present invention, the mask layer 2 is doped with gettering elements. The gettering elements refer to: elements that can diffuse into the silicon substrate 1, and by utilizing the characteristics of these elements, impurities in the silicon substrate 1 can be removed or reduced when diffusing in the silicon substrate 1. Effective gettering can be performed on the front surface of the silicon substrate 1 during subsequent high-temperature steps (such as boron diffusion or phosphorus diffusion), that is, impurities in the silicon substrate 1 are adsorbed from the front surface of the silicon substrate 1, thereby further reducing the recombination loss caused by metal impurities and enhancing the open-circuit voltage and conversion efficiency of the solar cell.

[0059] In the present invention, the gettering element is a Group III element and / or a Group V element. In one embodiment, the gettering element is phosphorus and / or boron, which has good gettering effect and low cost. Hereinafter, doping with phosphorus or boron will be taken as an example for description.

[0060] The mask layer 2 doped with the gettering element not only has alkali resistance, can protect the front surface of the silicon substrate 1 from etching during double-sided polishing and alkali etching to remove the doped layer in a local area, but also the gettering element inside it interacts with the impurities on the surface of the silicon substrate 1 during the high-temperature step, which helps to achieve double-sided gettering, so that while thinning the thickness of the original silicon wafer, a high product yield can be maintained. Incorporating an appropriate amount of phosphorus element into the alkali-resistant mask layer 2 to form a phosphorus-containing mask layer 2, or incorporating an appropriate amount of boron to form a boron-containing mask layer 2, can both achieve the dual effects of alkali solution etching resistance and gettering.

[0061] In one embodiment, by adding 1 wt%-4 wt% of the gettering element to the mask layer 2, the finally formed solar cell can obtain a higher open-circuit voltage and conversion efficiency, while effectively reducing the material and production costs, which is beneficial to the large-scale industrialization of high-efficiency solar cells.

[0062] In the present invention, the gettering element can be doped in the entire mask layer 2, or can be doped in a part of the mask layer 2, and both can achieve the dual effects of alkali resistance and gettering.

[0063] In one embodiment of the present invention, the gettering element is doped in a part of the mask layer 2 close to or in contact with the silicon substrate 1, and the gettering element is not doped in a part of the mask layer 2 far from or not in contact with the silicon substrate 1.

[0064] In one embodiment, the mask layer 2 includes a first mask layer formed on the front surface of the silicon substrate 1 and a second mask layer formed on the surface of the first mask layer far from the silicon substrate 1, and only the first mask layer is doped with the gettering element, and the second mask layer is not doped with the gettering element.

[0065] Through this layered design, the film layer in direct contact with the front surface of the silicon substrate 1 contains the gettering element, which can not only provide a phosphorus source or a boron source for subsequent diffusion, etc., and effectively getter the front surface of the silicon substrate 1, but also maintain excellent corrosion resistance during double-sided polishing and alkali etching to remove the doped layer in a local area; the outer film layer is not doped with the gettering element, which helps to reduce the usage amount of materials such as phosphorus source and boron source and maintain the overall film quality uniformity and etching resistance of the mask layer 2.

[0066] In a specific implementation of the present invention, by using this double-layer mask structure, the thickness of the original silicon wafer can be more effectively reduced without increasing the fragmentation rate, and good front surface quality can be ensured, thus realizing the organic unity of double-sided gettering and thinning cost. Experimental results show that this double-layer mask scheme can reduce the manufacturing cost and enhance the operability and scalability of the process while maintaining or improving the open-circuit voltage and conversion efficiency of solar cells, providing a better technical path for the large-scale mass production of solar cells.

[0067] In a specific embodiment of the present invention, the first mask layer is a film layer composed of one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride doped with the gettering element, and the content of the gettering element is controlled within the range of 1 wt% - 4 wt%; and / or the second mask layer is a film layer composed of one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride.

[0068] When implementing the present invention, by designing the first mask layer as a film layer doped with the gettering element, sufficient phosphorus source, boron source, etc. can be provided under high-temperature conditions to achieve gettering on the front side of the silicon substrate 1, and the structural stability of the film layer during the heat treatment process can be ensured. And by designing the second mask layer as a film layer not doped with the gettering element, the overall alkali resistance stability and mechanical strength of the mask layer 2 can be further improved, ensuring that the front side of the silicon wafer is protected from etching during the double-sided polishing and alkali etching processes to remove the doped layer in the local area. In a preferred embodiment of the present invention, the number of layers and material combination of the mask layer 2 can be adjusted according to actual production requirements, so as to achieve a balance between performance and cost.

[0069] In addition, by making the thickness of the first mask layer less than that of the second mask layer, the usage amount of the gettering element such as phosphorus source and / or boron source, the film layer stress, and the density of the film layer can be more effectively controlled, ensuring the stability and consistency of the mask layer 2 in the subsequent manufacturing process, thereby further reducing the thickness of the original silicon wafer and reducing the fragmentation rate. This combined laminated design and thickness matching scheme can simplify the process steps and reduce the material cost while improving the open-circuit voltage and conversion efficiency of the battery, providing a more robust technical path for the large-scale production of TBC batteries.

[0070] In one embodiment, the thickness of the first mask layer is 10% - 40% of the thickness of the entire mask layer 2. This ratio range can not only achieve good gettering effects but also reduce the cost of the mask layer 2. If the first mask layer is too thin, it will lead to insufficient gettering elements such as phosphorus source or boron source, reducing the gettering effect; if the first mask layer is too thick, it will increase the cost and is likely to form a dead layer on the front side of the silicon substrate 1.

[0071] When implementing the present invention, a first mask layer containing the gettering element may be first deposited on the front surface of the silicon substrate 1. The first mask layer may be formed by one or a combination of silicon oxide, silicon nitride, and silicon oxynitride doped with the gettering element. The content of the gettering element is controlled within the range of 1 wt% - 4 wt%, so as to achieve effective front-side gettering in subsequent high-temperature steps. Subsequently, the second mask layer is formed on the first mask layer. The second mask layer is one or a combination of silicon oxide, silicon nitride, or silicon oxynitride that does not contain the gettering element doped, thereby imparting higher alkali resistance and structural stability to the overall mask layer 2.

[0072] In an embodiment of the present invention, the mask layer 2 is a single-layer film. When implementing the present invention, if a single-layer structure mask layer 2 is selected, 1 wt% - 4 wt% of the gettering element is uniformly incorporated throughout the mask layer 2 to achieve gettering on the front surface of the silicon substrate 1 in high-temperature steps. At the same time, this single-layer film has alkali resistance characteristics and can effectively protect the front surface of the silicon substrate 1 during double-sided polishing and alkali etching to remove the doped layer in a local area, reducing the increase in the fragmentation rate caused by over-etching.

[0073] In a single-layer structure, there is no need for hierarchical stacking, and the deposition of the gettering element and the formation of the mask layer 2 can be completed in one film-forming step, simplifying the process steps, reducing the requirements for materials and equipment, and being beneficial to reducing defects or stress problems introduced at the film layer interface, thereby ensuring the uniformity and stability of the film layer. While maintaining the effective gettering and protection effects on the front surface of the silicon substrate 1, this single-layer mask solution can achieve the goals of cost reduction and efficiency improvement by reducing the initial silicon wafer thickness. Using this method in actual production can significantly shorten the preparation process, improve the flexibility and stability of the production line, and thus be beneficial to the large-scale and low-cost manufacturing of TBC batteries.

[0074] The process for forming the mask layer 2 includes but is not limited to the following two types.

[0075] The first type: A silicon paste layer is prepared on the front surface of the silicon substrate 1 by spraying, coating, printing, or transfer printing processes. The silicon paste layer is dried, and the drying temperature is 100°C - 200°C; the silicon paste layer is cured, and the curing temperature is 300°C - 600°C.

[0076] When depositing the mask layer 2 that does not contain the gettering element doped, the silicon paste includes silicon powder and an organic carrier. When depositing the mask layer 2 doped with the gettering element, the silicon paste includes silicon powder, a gettering element source such as a phosphorus source and / or a boron source, and an organic carrier.

[0077] Taking the formation of the phosphorus-doped mask layer 2 as an example, silicon powder, an organic carrier, and a phosphorus source are mixed to form a silicon slurry with an appropriate viscosity, which is uniformly deposited on the front surface of the silicon substrate 1 by means of spraying or printing. Then, the solvent and low-boiling organic components are removed by drying at 100°C - 200°C, so that the silicon slurry is preliminarily fixed on the surface of the silicon substrate 1. Subsequently, a curing treatment is carried out at 300°C - 600°C to decompose the organic carrier and form a dense, stable, phosphorus-doped film layer. This film layer plays a gettering role in subsequent high-temperature processes and has alkali resistance, effectively protecting the front surface from excessive etching during double-sided polishing and alkali etching to remove the doped layer in a local area. By this method, the manufacturing process of the mask layer 2 is simplified and flexible, adaptable to different production line conditions. At the same time, the phosphorus doping concentration and the film layer thickness can be effectively controlled, achieving the technical goals of double-sided gettering and thinning the silicon wafer thickness, thereby improving the battery efficiency and reducing the cost without increasing the fragmentation rate, which is beneficial to the large-scale production of TBC batteries. When forming the mask layer 2 without phosphorus doping, only silicon powder and an organic carrier need to be mixed to form a silicon slurry with an appropriate viscosity, which will not be elaborated here.

[0078] Among them, the silicon powder is a combination of one or more of silicon oxide powder, silicon nitride powder, and silicon oxynitride powder; the phosphorus source is composed of one or more of phosphoric acid, ammonium dihydrogen phosphate, diammonium hydrogen phosphate, and polyphosphoric acid. The organic carrier includes one or more of acrylic resin, ethyl cellulose, diethylene glycol monobutyl ether acetate, ethylene glycol, tributyl citrate, and polyamide wax.

[0079] By reasonably selecting the phosphorus source and the components of the organic carrier, a phosphorus-containing silicon slurry film layer can be rapidly and uniformly prepared on the front surface of the silicon substrate 1. In the subsequent drying and curing processes, the components of the organic carrier will decompose, volatilize, or cure to form a stable film layer structure, enabling the phosphorus element to be uniformly distributed in the film layer. This film layer provides phosphorus elements to play a gettering role in high-temperature steps and effectively protects the front surface of the silicon substrate 1 with its alkali resistance during double-sided polishing and alkali etching to remove the doped layer in a local area.

[0080] In addition, the selection and combination of the organic carrier can ensure good rheology and adhesion of the slurry, so as to form a uniform and dense film layer on the surface of the silicon substrate 1. In this way, by controlling the combination ratio of the silicon powder, the phosphorus source, and the organic carrier and the processing parameters, the function customization of the mask layer 2 can be flexibly achieved, that is, ensuring good phosphorus diffusion gettering efficiency, film layer stability, and acid-base tolerance, thereby reducing the fragmentation rate, increasing the open-circuit voltage and conversion efficiency, and providing better process conditions for reducing the original silicon wafer thickness and large-scale production.

[0081] When forming the boron-doped mask layer 2, only the phosphorus source needs to be replaced with a boron source. When forming the mask layer 2 doped with both boron and phosphorus, only the phosphorus source needs to be replaced with a mixture of a boron source and a phosphorus source.

[0082] Among them, the boron source is composed of one or more of boric acid, boron, methylboronic acid, ethylboronic acid, and phenylboronic acid.

[0083] Second: The mask layer 2 is formed by PECVD (Plasma Enhanced Chemical Vapor Deposition) process.

[0084] When depositing the phosphorus-doped mask layer 2, appropriate reaction gases such as a silicon source (such as silane or silicomethane), a nitrogen source, and an oxygen source can be introduced into the PECVD equipment, and phosphine or other phosphorus-containing precursor gases can be added under process conditions to achieve uniform, controllable, and phosphorus-doped film deposition on the front side of the silicon wafer. When depositing the mask layer 2 without phosphorus doping, no phosphorus-containing gas is introduced into the reaction gas.

[0085] In one embodiment, silicon nitride doped with phosphorus atoms in-situ is formed as the mask layer 2 by PECVD process. The temperature of the PECVD process is 400°C - 600°C, the silane flow rate is 1000 sccm - 3000 sccm, the ammonia flow rate is 5000 sccm - 20000 sccm, the phosphine flow rate is 300 sccm - 2000 sccm, the pressure is 1000 mTorr - 3000 mTorr, and the single-layer mask layer 2 is deposited with a thickness of 10 nm - 100 nm.

[0086] In another embodiment, a double-layer mask layer 2 is formed by PECVD. That is, the bottom layer close to the silicon substrate 1 is silicon nitride doped with phosphorus atoms in-situ, and the outer layer is a silicon nitride layer. The PECVD process temperature is 400°C - 600°C, the silane flow rate is 1000 sccm - 3000 sccm, the ammonia flow rate is 5000 sccm - 20000 sccm, the phosphine flow rate is 300 sccm - 2000 sccm, the pressure is 1000 mTorr - 3000 mTorr, and silicon nitride doped with phosphorus atoms is deposited with a thickness of 10 nm - 30 nm. Then, the flow rate of phosphine is adjusted to 0, and other conditions remain unchanged, and a silicon nitride layer with a thickness of 10 nm - 70 nm is continuously deposited.

[0087] Compared with the single-layer film, the double-layer film reduces the consumption of phosphine, saves costs, and during subsequent boron diffusion and phosphorus diffusion, the phosphorus atoms in the silicon nitride diffuse to the silicon substrate 1, and the activation of phosphorus atoms is completed at high temperature to achieve gettering on the front side of the silicon substrate 1.

[0088] In the above two embodiments, only ammonia is replaced by oxygen, and other gases and flow rates remain unchanged, and phosphorus-doped silicon oxide can be obtained as the mask layer 2.

[0089] When depositing the boron-doped mask layer 2, appropriate reaction gases such as a silicon source (e.g., silane or silicomethane), a nitrogen source, and an oxygen source can be introduced into the PECVD equipment, and diborane or other boron-containing precursor gases can be added under process conditions to deposit a uniform, controllable, and boron-doped film layer on the front side of the silicon substrate 1. When depositing the mask layer 2 without boron doping, boron-containing gases are not introduced into the reaction gases.

[0090] In one embodiment, silicon nitride doped with boron atoms in situ is formed as the mask layer 2 through the PECVD process. The temperature of the PECVD process is 400°C - 600°C, the flow rate of silane is 1000 sccm - 3000 sccm, the flow rate of ammonia is 5000 sccm - 20000 sccm, the flow rate of diborane is 300 sccm - 2000 sccm, the pressure is 1000 mTorr - 3000 mTorr, and silicon nitride doped with boron is deposited with a thickness of 10 nm - 100 nm.

[0091] In another embodiment, a double-layer mask layer 2 is formed through PECVD, that is, the bottom layer close to the silicon substrate 1 is a silicon nitride layer doped with boron atoms in situ, and the outer layer is a silicon nitride layer. The temperature of the PECVD process is 400°C - 600°C, the flow rate of silane is 1000 sccm - 3000 sccm, the flow rate of ammonia is 5000 sccm - 20000 sccm, the flow rate of diborane is 300 sccm - 2000 sccm, the pressure is 1000 mTorr - 3000 mTorr, and silicon nitride doped with boron is deposited with a thickness of 10 nm - 30 nm. Then, the flow rate of diborane is adjusted to 0, and other conditions remain unchanged, and a silicon nitride layer with a thickness of 10 nm - 70 nm is continuously deposited.

[0092] Compared with the single-layer film, the double-layer film reduces the consumption of diborane and saves costs. During boron diffusion and phosphorus diffusion, boron atoms in the silicon nitride diffuse to the silicon substrate 1, and boron atoms are activated at high temperature to complete front-side gettering.

[0093] In the above two embodiments, if ammonia is replaced with oxygen and other gases and their flow rates remain unchanged, boron-doped silicon oxide can be obtained as the mask layer 2.

[0094] When depositing the mask layer 2 containing boron and phosphorus, only phosphine and diborane need to be added together. In one embodiment, their flow rates are the same as those in the above embodiments. In one embodiment, the sum of the flow rates of phosphine and diborane is 300 sccm - 2000 sccm, and their ratio is not limited. Preferably, the flow rate of phosphine is greater than that of diborane. Since the activation temperature of phosphorus is lower than that of boron, costs can be reduced while ensuring the gettering effect.

[0095] When depositing the mask layer 2 containing other gettering elements, only need to replace phosphine or diborane with a gas containing other gettering elements.

[0096] The mask layer 2 obtained by using the PECVD process has high density and excellent adhesion, ensuring effective protection for the front side of the silicon substrate 1 in subsequent double-sided polishing and alkali etching steps, and avoiding thinning the silicon substrate 1 from the front side. At the same time, the mask layer 2 doped with gettering elements such as phosphorus and boron can effectively achieve front-side gettering in high-temperature steps, reduce carrier recombination caused by metal impurities in the silicon substrate 1, and thus improve the open-circuit voltage and conversion efficiency of the battery. The PECVD process has the characteristics of high process repeatability and large-scale mass production, which is conducive to strictly controlling the film thickness, gettering element content and film uniformity, and meeting the requirements of the TBC battery for the mask layer 2. In the embodiments of the present invention, the mask layer 2 deposited by PECVD can also achieve the goal of thinning the original silicon wafer thickness and maintaining a good yield, providing a stable and efficient mask film-forming technical path for the industrial production of TBC batteries.

[0097] After forming the mask layer 2 by the above method, polish the silicon substrate 1 to form a planar structure on the back side, which is beneficial to forming a high-quality back-side film layer. Of course, when the back side of the silicon substrate 1 is a planar structure, polishing may not be required.

[0098] The present invention adopts a double-sided polishing process, for example, polishing with a polishing alkali solution. The process is mature and does not require a single-sided mask, and the process cost is low.

[0099] In one embodiment, first remove the damaged layer on the surface of the silicon substrate 1 in a mixed solution of potassium hydroxide (KOH) and hydrogen peroxide (H2O2), and then polish in a sodium hydroxide (NaOH) solution or a potassium hydroxide solution to form a planar structure on the back side of the silicon substrate 1. The base size is 15 μm or more, and the reflectivity is about 40%, for example, 35%-40%.

[0100] The planar structure formed by alkali solution polishing is not an absolute plane. From a microscopic perspective, the surface has several "base structures of pyramids". The height of the base is very low, basically at the nanometer level. Therefore, the sizes of the top and bottom of the base structure are not much different, and usually the size of the top is measured. The base size refers to the distance between the two farthest points on the edge of the base structure of the pyramid, or after the edge of the base structure of the pyramid is smoothed into a curve, the distance between the two farthest points on the curve. Generally, the projection of the base structure of the pyramid on the silicon substrate 1 is a quadrilateral, and the base size refers to the distance of the top diagonal.

[0101] In this process, the etching depth of the alkaline solution is 3 μm - 8 μm, for example, about 5 μm, which can remove the damaged layer during the original silicon wafer cutting process more thoroughly. After alkaline polishing, only the back surface of the silicon substrate 1 is thinned, and the front surface is not thinned under the protection of the mask layer 2, ensuring the overall thickness of the silicon substrate 1.

[0102] In the present invention, the "etching depth of the alkaline solution" refers to the etching depth of the silicon substrate 1.

[0103] The first doped layer 32 is a P-type doped layer, for example, a boron-doped polysilicon layer. The first tunneling layer 31 and the first doped layer 32 form a first doping structure.

[0104] In an embodiment of the present invention, as Figure 3 shown, "forming the first tunneling layer 31 and the first doped layer 32" includes the following steps: forming the first tunneling layer 31; forming a first amorphous silicon layer, using BCl3 or BBr3 as a boron diffusion source, at a temperature of 850 °C - 1100 °C, performing boron diffusion on the first amorphous silicon layer to form the first doped layer 32, and forming a first oxide layer 33 on the surface.

[0105] When implementing the present invention, after the deposition and double-sided polishing of the mask layer 2 are completed, a first tunneling layer 31 with a thickness of about 1 nm - 2 nm can be formed on the back surface of the silicon wafer by LPCVD (Low Pressure Chemical Vapor Deposition) or thermal oxidation process. The first tunneling layer 31 is a silicon oxide layer or a silicon carbide layer, and the first tunneling layer 31 lays the foundation for subsequent polycrystalline silicon passivation contact.

[0106] Subsequently, a first amorphous silicon layer with a thickness of 50 nm - 500 nm is deposited to cover the side of the first tunneling layer 31 away from the silicon substrate 1, and BCl3 or BBr3 is introduced as a boron diffusion source in a tube diffusion device, and boron diffusion is performed at a high temperature of about 850 °C - 1100 °C to achieve the conversion of amorphous silicon to boron-doped polysilicon, and at the same time, a first oxide layer 33 is formed on its surface. The first oxide layer 33 is a borosilicate glass layer (BSG layer) with a thickness of about 30 nm - 150 nm. By controlling the diffusion conditions and time, the surface doping concentration of the first doped layer 32 can reach 2E19atoms / cm 3 - 2E20atoms / cm 3 , thereby obtaining a high-quality p-type doped layer.

[0107] In this process, through the gettering effect of the mask layer 2 and precise doping on the back surface, the impurity content inside the silicon substrate 1 can be effectively reduced and carrier recombination can be inhibited, enabling the solar cell to obtain a higher open-circuit voltage. In addition, the stability and uniformity of the first doping layer 32 contribute to ensuring the subsequent distinction between the P region and the N region and the precise layout of the back contact structure, thereby providing a high-quality basic structure for the final TBC cell. Generally speaking, this step clarifies the specific conditions and parameters for forming the first tunneling layer 31 and the first doping layer 32, enabling the TBC cell of the present invention to further improve the efficiency without increasing the fragmentation rate and achieving the goals of low cost and high performance.

[0108] In an embodiment of the present invention, as Figure 4 shown, "removing the first doping layer 32 in the area outside the first area 11" includes: removing the first oxide layer 33 in the area outside the first area 11 on the back surface; removing the first oxide layer 33 diffused around the front surface and the side surfaces; and removing the first doping layer 32 in the area outside the first area 11 on the back surface and the first doping layer 32 on the front surface by alkali etching. This step retains the first oxide layer 33 in the first area 11 to protect the internal first doping layer 32 in the subsequent texturing step.

[0109] It should be noted that the thickness of the first tunneling layer 31 is less than 3 nm and can fall off when the first doping layer 32 is removed, so there is no need to set a separate removal step.

[0110] To achieve precise functional partitioning of different regions on the back surface, it is necessary to selectively remove the formed P-type doping layer and related film layers in the specified second region 12 and the spacer region 13. This step can be achieved by combining laser film opening with subsequent acid cleaning (chain acid pickling) and alkali etching processes in a chain machine. First, the laser film opening process is used to completely remove the first oxide layer 33 in the second region 12 and the spacer region 13 to ensure the complete removal of the polysilicon layer in this region subsequently. At the same time, due to the diffusion phenomenon caused by high-temperature diffusion, the first oxide layer 33 also has a certain distribution on the front and side surfaces. Therefore, chain acid pickling is used to remove the first oxide layer 33 diffused on the front and side surfaces to ensure the final surface quality and the uniformity of current transmission. After the first oxide layer 33 is removed, alkali etching is used to selectively etch and remove the region outside the first region 11 on the back surface (the second region 12 and the spacer region 13) and the first doping layer 32 deposited on the front surface. This step removes the P-type doping layer that originally continuously covered the back surface in the second region 12 and the spacer region 13, thus creating conditions for realizing N-type doping and the back contact structure separated from the P region in this region. Through this selective removal, the P region and the N region can be precisely divided on the back surface, laying a foundation for realizing double-sided impurity absorption and efficient charge separation of the TBC battery. At the same time, under the protection of the existing mask layer 2 on the front surface, the thickness and quality of the silicon wafer are maintained, thereby achieving the goal of reducing costs and increasing efficiency.

[0111] When "removing the first doping layer 32 in the region outside the first region 11", the boron atoms diffused into the silicon substrate 1 will be completely etched away, that is, a part of the silicon substrate 1 will be etched away, resulting in a height difference between the first region 11 and the region outside the first region 11 in the direction away from the silicon substrate 1. That is, the back surface S1 of the silicon substrate 1 in the first region 11 remains unchanged, and a part of the back surface of the region outside the first region 11 is etched away. The back surfaces S2 of the silicon substrate 1 in the second region 12 and S3 of the silicon substrate 1 in the spacer region 13 are flush, and the thickness of the silicon substrate 1 in the second region 12 and the spacer region 13 is thinner than the thickness of the silicon substrate 1 in the first region 11, and the thickness difference is about 3 μm - 8 μm, as Figure 4 shown.

[0112] The second doping layer 42 is an N-type doping layer, such as a phosphorus-doped polysilicon layer. The second tunneling layer 41 and the second doping layer 42 form a second doping structure.

[0113] In an embodiment of the present invention, please refer to Figure 5As shown, "forming the second tunneling layer 41 and the second doping layer 42 on the back surface" includes: forming the second tunneling layer 41; forming a second amorphous silicon layer, using phosphorus oxychloride as a diffusion source, at a temperature of 850°C - 950°C, performing phosphorus diffusion on the second amorphous silicon layer to form the second doping layer 42, and forming a second oxide layer 43 on the surface. The second oxide layer 43 is a phosphorosilicate glass layer (PSG layer) formed on the surface of the second doping layer 42.

[0114] Among them, the second tunneling layer 41 is a silicon oxide layer or a silicon carbide layer, with a thickness of 1nm - 2nm; and / or the surface doping concentration of the second doping layer 42 is 9E19 atoms / cm 3 -9E20 atoms / cm 3 , with a thickness of 50nm - 500nm; and / or the thickness of the second oxide layer 43 is 10nm - 50nm.

[0115] When the first doping layer 32 and related film layers in the second region 12 and the spacer region 13 are removed, a second tunneling layer 41 with a thickness of about 1nm - 2nm is deposited on the entire back surface. Specifically, the same or similar processes and materials as the first tunneling layer 31 can be selected, such as a silicon oxide or silicon carbide layer.

[0116] Then, a second amorphous silicon layer is formed on the second tunneling layer 41; phosphorus oxychloride (POCl3) is introduced into a tube diffusion furnace as a phosphorus diffusion source, and the diffusion temperature is controlled at 850°C - 950°C to convert the amorphous silicon layer into an N-type doped layer (here, a phosphorus-doped polysilicon layer), and a PSG layer is simultaneously formed on the surface, with a thickness between 10nm - 50nm. By adjusting the diffusion conditions and time, the surface doping concentration of the second doping layer 42 can reach 9E19 atoms / cm 3 -9E20 atoms / cm 3 , and the thickness of the polysilicon layer is in the range of 50nm - 500nm, preferably less than 400nm, preferably 80nm - 120nm, to ensure excellent conductivity and passivation performance.

[0117] In some embodiments of the present invention, such as Figure 6As shown, "removing the second doping layer 42 in the area outside the second area 12" includes: removing the second oxide layer 43 in the area outside the second area 12 on the back surface; removing the second oxide layer 43 that extends around the front surface and the sides; removing the area outside the second area 12 on the back surface (the first area 11 and the spacer 13) and the second doping layer 42 on the front surface. In this step, the second oxide layer 43 of the second area 12 is retained to protect the internal second doping layer 42 in the subsequent texturing step. It should be noted that the thickness of the second tunneling layer 41 is less than 3 nm and can fall off when the second doping layer 42 is removed, so there is no need to set a separate removal step. In the actual process, the second tunneling layer 41 has no impact on the subsequent steps and does not need to be specifically removed.

[0118] After the second doping layer 42 and the second oxide layer 43 have been formed on the back surface, in order to achieve precise control of the alternating distribution of the P region / N region in the final cell structure, it is necessary to selectively remove the N-type doping layer and the second oxide layer 43 above it in the first area 11.

[0119] Specifically, the second doping layer 42 and the second oxide layer 43 are removed through laser film opening, chain pickling, and alkali etching processes. Through laser film opening, the second oxide layer 43 in the first area 11 and the spacer 13 is first removed completely. Then, the PSG layer generated by chain pickling is removed from the front surface and the sides. Subsequently, through the alkali etching process, the second doping layer 42 in the first area 11, the spacer 13, and the front surface is selectively removed to remove these N-type doping layers. At this time, the first area 11 is protected by the first oxide layer 33 to protect the internal P-type doping layer.

[0120] Through the precise removal operation of the second oxide layer 43 and the N-type doping layer, a back contact structure with regular alternation of the P region and the N region is finally presented on the back surface, improving the charge separation and collection efficiency. Thus, under the double-sided gettering and protection of the front mask, a TBC cell with a higher open-circuit voltage and higher conversion efficiency can be obtained with a thinner silicon substrate 1 and a lower fragmentation rate, which is beneficial to the stable and controllable process and large-scale industrial production.

[0121] Based on the above steps, the first doping layer 32 (p-type) and the second doping layer 42 (n-type) are alternately distributed on the back surface, thus realizing the back contact cell design. This N-type doping layer is spaced apart from the previously formed P-type doping layer, greatly improving the charge separation and collection efficiency.

[0122] Meanwhile, due to the presence of the mask layer 2 on the front side, double-sided gettering is achieved during boron diffusion and phosphorus diffusion. When removing part of the doped layer, the front side of the silicon substrate 1 is protected from being etched, ensuring that the minority carrier lifetime on the front side remains at a relatively high level and enabling the use of a thinner original silicon wafer, which is beneficial for cost reduction and efficiency improvement. In actual preparation, by strictly controlling the diffusion parameters and film quality, a back-contact TBC cell with excellent electrical properties and repeatability can be obtained, laying a solid foundation for high efficiency, low cost, and large-scale mass production.

[0123] After forming the P region and the N region based on the above steps, the mask layer 2 on the front side can be removed. In an embodiment of the present invention, as Figure 7 shown, "removing the mask layer 2" includes removing the mask layer 2 by pickling or removing the mask layer 2 by RCA cleaning (Radio Corporation of America Clean). Preferably, a single-sided cleaning is performed using a chain machine, and the first oxide layer 33 located in the first region 11 and the second oxide layer 43 located in the second region 12 are retained.

[0124] Specifically, after double-sided polishing to form the first tunneling layer 31 and the first doped layer 32, and removing the first doped layer 32 in the region outside the first region 11; forming the second tunneling layer 41 and the second doped layer 42, and removing the second doped layer 42 in the region outside the second region 12, finally, the mask layer 2 on the front side needs to be completely removed to ensure that the front surface of the finished cell is flat, clean, and suitable for subsequent texturing, passivation, and electrode formation. By using pickling or RCA cleaning, the residual mask layer 2 can be effectively removed, thereby exposing the smooth surface of the silicon substrate 1, creating ideal conditions for the deposition of subsequent texturing, passivation film (such as alumina film), and antireflection layer 6 (such as silicon nitride film).

[0125] During this process, the pickling process (such as HF solution treatment) can quickly dissolve and remove the silicon oxide, silicon nitride, or silicon oxynitride components in the mask layer 2, while RCA cleaning can remove organic residues and metal ion contamination through a standardized cleaning process. Due to the presence of the mask layer 2 on the front side before, the silicon substrate 1 is effectively protected during the polishing and alkali etching steps, thereby achieving appropriate thinning of the initial silicon wafer thickness and reducing the fragmentation rate, and effectively reducing the influence of metal impurities during the double-sided gettering process. Through the removal in this step, the front side finally presents a clean state, providing excellent interface conditions for the subsequent preparation of high-efficiency TBC cells.

[0126] As Figure 8 shown, the method for preparing a solar cell according to the present invention further includes: after removing the mask layer 2, forming a textured structure on the front side of the silicon substrate 1, and also forming a pyramid textured structure in the spacer region 13 on the back side.

[0127] The base size of the pyramid texture refers to the width size of the base of the pyramid. The base of the pyramid is square, and in the industry, the diagonal of the square is called the base width or the base size. In some embodiments, the base size of the texture is not greater than 5 μm, or not greater than 4 μm, or not greater than 3 μm, preferably 1 μm - 3 μm.

[0128] The pyramid texture can reduce the reflectivity of the front surface, reducing it to 10% or less, such as 7% - 10%.

[0129] The texturing process is to etch from the surface of the silicon substrate 1 into the interior of the silicon substrate 1. In some embodiments, as Figure 11 and 12 shown, the back surface S3 of the silicon substrate 1 in the spacer region 13 is flush with the back surface S2 of the silicon substrate 1 in the second region 12. Alternatively, the etching may also cause a slight reduction in the thickness of the silicon substrate 1 in the spacer region 13, so there is a certain height difference between the back surface S3 of the silicon substrate 1 in the spacer region 13 and the back surface S2 of the silicon substrate 1 in the second region 12, and the side surface S5 of the silicon substrate 1 in the second region 12 facing the spacer region 13 is exposed outward. The finally formed solar cell is as Figure 12 and Figure 13 shown.

[0130] Please refer to Figure 9 and Figure 10 shown. After texturing, pickling or RCA cleaning is used to remove the first oxide layer 33 in the first region 11 and the second oxide layer 43 in the second region 12, and subsequent steps can be carried out, such as preparing the first electrode 7 and the second electrode 8.

[0131] Please refer to Figures 11 to 14 shown. In an embodiment of the present invention, before forming the first electrode 7 and the second electrode 8, the method for preparing a solar cell further includes forming a passivation layer 5 on both sides of the solar cell, and the thickness of the passivation layer 5 is 2 nm - 7 nm.

[0132] ALD (Atomic Layer Deposition) process can be used to form an alumina layer on both sides as the passivation layer 5. This alumina layer can provide excellent charge compensation and surface passivation effects at the interface, helping to reduce surface recombination and increase the open - circuit voltage.

[0133] In an embodiment of the present invention, before forming the first electrode 7 and the second electrode 8, the method for preparing a solar cell further includes forming an antireflection layer 6 on both sides of the solar cell, which can construct an optical interface with low reflectivity on the cell surface to maximize the coupling and absorption of incident light.

[0134] In one embodiment, the antireflection layer 6 is one or more of silicon nitride, silicon oxynitride, and silicon oxide, and / or the thickness of the antireflection layer 6 is 60 nm - 130 nm. The antireflection layer 6 can be deposited by PECVD process.

[0135] In one embodiment of the present invention, the passivation layer 5 is first deposited on both sides by the above process, and then the antireflection layer 6 is deposited on both sides by the above process. Through the dual functions of the passivation layer 5 and the antireflection layer 6, the present invention further reduces surface recombination and improves optical efficiency, enhancing both the open-circuit voltage and the fill factor of the solar cell. Coupled with the advantages of front surface gettering and wafer thinning in cell manufacturing, the final product TBC cell can achieve higher conversion efficiency and stable performance under low-cost conditions, providing a reliable technical guarantee for large-scale production.

[0136] The preparation of the first electrode 7 and the second electrode 8 can adopt, but is not limited to, the processes commonly used in the art. In the present invention, the first electrode 7 and the second electrode 8 are formed by screen printing and sintering processes.

[0137] The solar cell obtained by the above method has a high open-circuit voltage, fill factor, and conversion efficiency. The following will detail the preparation method of the solar cell of the present invention and the solar cell prepared thereby with a specific embodiment.

[0138] The present invention also provides a solar cell, which can be prepared by the above preparation method or by other methods.

[0139] Please refer to Figures 10 to 14 As shown, the solar cell includes a silicon substrate 1, a first doping structure on the back surface of the silicon substrate 1, a second doping structure on the back surface of the silicon substrate 1 and spaced from the first doping structure, a first electrode 7 in contact with the first doping structure, and a second electrode 8 in contact with the second doping structure.

[0140] One of the first doping structure and the second doping structure has the same doping type as the silicon substrate 1, and the other has a doping type opposite to that of the silicon substrate 1. One of the first doping structure and the second doping structure is a P-type doping structure; the other doping structure is an N-type doping structure.

[0141] The back surface of the silicon substrate 1 has a first region 11, a second region 12, and a spacer region 13 located between the first region 11 and the second region 12. The first doping structure is located in the first region 11, and the second doping structure is located in the second region 12. Therefore, parameters such as the area, width, and thickness of the silicon substrate 1 located in the first region 11, the second region 12, and the spacer region 13 all have a great impact on the performance of the battery. Changing any one of these parameters can optimize the battery efficiency.

[0142] In one embodiment, the ratio of the area of the first region 11 to the area of the second region 12 is 0.5:1 - 1.5:1, such that the P region and the N region have a good ratio, and the short-circuit current density and open-circuit voltage of the battery reach a balance, and the efficiency of the battery is optimal. If this ratio is too small, the area of the first region 11 is too large and the area of the second region 12 is too small, which will reduce the passivation performance of the entire back surface and reduce the open-circuit voltage of the battery. If this ratio is too large, the area of the first region 11 is too small and the area of the second region 12 is too large, which will reduce the area of the PN junction, be unfavorable for the generation and separation of carriers, and reduce the short-circuit current density of the battery.

[0143] In one embodiment, the first region 11 and the second region 12 are alternately arranged. In the arrangement direction of the first region 11 and the second region 12, the ratio of the width W1 of the first region 11 to the width W2 of the second region 12 is 0.5:1 - 1.5:1. In the direction perpendicular to the arrangement direction of the first region 11 and the second region 12, the sizes of the first region 11 and the second region 12 are substantially the same.

[0144] In one embodiment, the width W1 of the first region 11 is 200 μm - 800 μm, and the width W2 of the second region 12 is 200 μm - 800 μm.

[0145] In one embodiment, the width W1 of the first region 11 is less than the width W2 of the second region 12. The width W1 of the first region 11 is 300 μm ± 100 nm, and the width W2 of the second region 12 is 420 μm ± 100 nm.

[0146] The width W3 of the spacer region 13 is 30 μm - 100 μm, preferably 70 μm ± 10 μm, which forms an insulating isolation between the first doping structure and the second doping structure in the transverse direction. If the spacer region 13 is too wide, it will reduce the width of the first region 11 and / or the second region 12 and reduce the efficiency of the battery. If the spacer region 13 is too narrow, electrical isolation cannot be achieved.

[0147] In addition, the thickness d1 of the silicon substrate 1 in the first region 11 is greater than the thickness d2 of the silicon substrate 1 in the second region 12. In the thickness direction of the silicon substrate 1, the first doping structure and the second doping structure are insulated from each other.

[0148] In one embodiment, the thickness d1 of the silicon substrate 1 in the first region 11 is 3 μm - 8 μm greater than the thickness d2 of the silicon substrate 1 in the second region 12, preferably about 5 μm; such that the P region and the N region are staggered in the thickness direction of the silicon substrate 1, avoiding leakage between the two regions.

[0149] In the present invention, through the width of the spacer region 13 and the thickness difference of the silicon substrate 1 in the first region 11 and the second region 12, the insulation between the first doping structure and the second doping structure is comprehensively improved, avoiding the occurrence of leakage points and improving the battery efficiency.

[0150] The first doping structure includes a first tunneling layer 31 in the first region 11 and a first doping layer 32 on the side of the first tunneling layer 31 away from the silicon substrate 1. The doping type of the first doping layer 32 is opposite to that of the silicon substrate 1, and the first electrode 7 is in contact with the first doping layer 32.

[0151] The second doping structure includes a second tunneling layer 41 in the second region 12 and a second doping layer 42 on the side of the second tunneling layer 41 away from the silicon substrate 1. The doping type of the second doping layer 42 is the same as that of the silicon substrate 1, and the second electrode 8 is in contact with the second doping layer 42.

[0152] In one embodiment, the silicon substrate 1 is an N-type silicon substrate, the first doping layer 32 is a P-type doping layer, and the second doping layer 42 is an N-type doping layer. In the direction away from the silicon substrate 1, the P-type doping layer is higher than the N-type doping layer, and its back surface and side surfaces can all receive sunlight, increasing the light absorption area and improving the battery efficiency.

[0153] In one specific embodiment, the first doping layer 32 is a boron-doped polysilicon layer, and its surface doping concentration reaches 2E19 atoms / cm 3 -2E20 atoms / cm 3 , with a thickness of 50 nm - 500 nm, preferably less than 400 nm, and preferably 80 nm - 120 nm.

[0154] The second doping layer 42 is a phosphorus-doped polysilicon layer, and its surface doping concentration reaches 9E19 atoms / cm 3 -9E20 atoms / cm 3, with a thickness in the range of 50 nm - 500 nm, preferably 400 nm or less, and preferably 80 nm - 120 nm.

[0155] In one embodiment, the solar cell further includes a passivation layer 5 on the side where the back surface of the silicon substrate 1 is located, which passivates the back surface structure and improves the open circuit voltage. The passivation layer 5 is an alumina layer with a thickness of 2 nm - 7 nm.

[0156] In one example, as Figures 10 to 12 shown, the passivation layer 5 contacts the surface of the silicon substrate 1 exposed outward at the spacer region 13. The surface includes the back surface S3 of the silicon substrate 1 in the spacer region 13 and the side surface S4 of the silicon substrate 1 in the first region 11 facing the spacer region 13.

[0157] In another example, as Figure 13 and Figure 14 shown, the thickness of the silicon substrate 1 in the spacer region 13 is less than the thickness of the silicon substrate 1 in the second region 12. The surface includes the back surface S3 of the silicon substrate 1 in the spacer region 13, the side surface S4 of the silicon substrate 1 in the first region 11 facing the spacer region 13, and the side surface S5 of the silicon substrate 1 in the second region 12 facing the spacer region 13.

[0158] In addition, as Figures 10 to 13 shown, the side surface of the first doping structure facing the spacer region 13 and the side surface S4 of the silicon substrate 1 in the first region 11 facing the spacer region 13 are generally in the same plane, and are also exposed outward at the spacer region 13 and covered by the passivation layer 5. As Figure 13 and Figure 14 shown, the side surface of the second doping structure facing the spacer region 13 and the side surface S5 of the silicon substrate 1 in the second region 12 facing the spacer region 13 are generally in the same plane, and are also exposed outward at the spacer region 13 and covered by the passivation layer 5. Specifically, the passivation layer 5 contacts the surface of the silicon substrate 1 exposed outward at the spacer region 13 at the spacer region 13. The passivation layer 5 contacts the surface of the first doping layer 32 away from the silicon substrate 1 and / or the side surface facing the spacer region 13 in the first region 11. The passivation layer 5 contacts the surface of the second doping layer 42 away from the silicon substrate 1 and / or the side surface facing the spacer region 13 in the second region 12.

[0159] In another embodiment, the passivation layer 5 contacts the surface of the spacer region 13 and the surface exposed outward at the spacer region 13. The passivation layer 5 contacts the surface of the first doped layer 32 away from the silicon substrate 1 in the first region 11, and the passivation layer 5 contacts the surface of the second doped layer 42 away from the silicon substrate 1 in the second region 12.

[0160] In a specific embodiment, in the direction away from the silicon substrate 1, the passivation layer 5 in direct contact with the back surface S3 of the silicon substrate 1 exposed in the spacer region 13 is an alumina layer with a thickness of 2 nm - 7 nm, which ensures the passivation effect of the spacer region 13 and improves the open-circuit voltage.

[0161] In one embodiment, the solar cell further includes an antireflection layer 6 on the side where the back surface of the silicon substrate 1 is located, which reduces the light reflection on the back side. The antireflection layer 6 is one or more of silicon nitride, silicon oxynitride, and silicon oxide films, and / or the thickness of the antireflection layer 6 is 60 nm - 130 nm.

[0162] In one embodiment, the passivation layer 5 only covers the surface of the spacer region 13 or covers the entire back surface region, and the antireflection layer 6 contacts the surface of the passivation layer 5 away from the silicon substrate 1.

[0163] In another embodiment, the passivation layer 5 only covers the entire surface of the spacer region 13. The antireflection layer 6 contacts the surface of the first doped layer 32 away from the silicon substrate 1 in the first region 11, contacts the surface of the second doped layer 42 away from the silicon substrate 1 in the second region 12, and contacts the surface of the passivation layer 5 exposed outward in the spacer region 13. The surface of the passivation layer 5 exposed outward is the surface of the passivation layer 5 away from the silicon substrate 1, away from the first doping structure, and away from the second doping structure.

[0164] In addition, the characteristic parameters of the above-mentioned solar cell in the present invention are applicable to the corresponding structures in the preparation method of the solar cell; the characteristic parameters in the preparation method of the above-mentioned solar cell are applicable to the corresponding characteristics in the solar cell. The solar cell can be prepared by the preparation method of the above-mentioned solar cell, or can be prepared by other preparation methods.

[0165] Hereinafter, specific embodiments will be provided to illustrate in detail the preparation method of the solar cell of the present invention.

[0166] Embodiment

[0167] An N-type monocrystalline silicon wafer is selected as the silicon substrate 1, with a resistivity of 1 Ω·cm and an initial thickness of about 140 μm.

[0168] First, a double-layer mask layer 2 is formed on the front side of the silicon substrate 1 by spraying or printing processes. The bottom layer is a phosphorus-doped silicon oxide film with a phosphorus content of 3 wt%; the outer layer is silicon oxide without phosphorus doping. The mask layer 2 is dried at 150 °C and then cured at 400 °C to obtain a dense, alkali-resistant film layer that can achieve gettering during subsequent high-temperature steps. The mask layer 2 provides stable protection for the front side of the silicon substrate 1 during double-sided polishing, etching, and cleaning processes, preventing the front side from being affected by alkali etching. Thus, thinner original silicon wafers can be used without increasing the fragment rate, reducing costs.

[0169] After forming the mask layer 2, the silicon wafer is polished on both sides to remove the damaged layer and obtain a flat and smooth back side. First, the damaged layer on the surface of the silicon wafer is removed in a mixed solution of KOH and H2O2, and then alkali polishing is performed in a sodium hydroxide solution or a potassium hydroxide solution. The base size of the back side of the silicon wafer is 15 μm, the reflectivity is 40%, and the alkali etching depth is about 5 μm, which can more thoroughly remove the damage caused during the cutting of the original silicon wafer. After double-sided alkali polishing, the thickness of the silicon substrate 1 is 135 μm.

[0170] Subsequently, about 1.5 nm of SiOx and 300 nm of intrinsic amorphous silicon layer are deposited on the back side of the silicon wafer by LPCVD process. Boron diffusion is performed on the amorphous silicon layer using BCl3 or BBr3 as the diffusion source under the condition of 850 °C - 1050 °C to convert it into a p-type doped layer (boron-doped polysilicon layer), and a 60-nm-thick first oxide layer 33 (BSG layer) is formed on the surface, with a doping concentration of 8E19 atoms / cm 3 At this time, gettering of the front side of the silicon wafer is simultaneously achieved based on the mask layer 2 during high-temperature treatment, which helps to reduce metal impurities and improve the open-circuit voltage.

[0171] The first oxide layer 33 in the area outside the first region 11 is removed by laser opening the film. The laser is a green picosecond laser with a power of 50 W. The first oxide layer 33 that spreads around the front side and the side is removed by chain pickling. The pickling solution is HF with a concentration of 9%. Then, the removal of the p-type doped layer in the second region 12, the spacer region 13, and the front side is completed using a tank-type alkali etching device, that is, an alkali solution is added to the tank-type machine. The alkali solution is a sodium hydroxide solution or a potassium hydroxide solution, and the alkali etching depth is about 5 μm. The boron atoms in the silicon substrate 1 are completely etched away to avoid leakage due to PN contact. After this step, the thickness of the silicon substrate 1 is thinned to about 130 μm; the base size of the second region 12 is 30 μm. Through this step, preliminary isolation preparation of the P region and the N region is completed on the back side.

[0172] Deposit a 1.5 nm silicon oxide and a 20 nm amorphous silicon layer on the entire back surface; use a tube diffusion equipment, with POCl3 as the diffusion source, perform phosphorus diffusion at 850°C - 950°C to form an N-type doped layer (phosphorus-doped polysilicon layer, surface doping concentration is 8E20 atoms / cm 3 ), and a 50 nm thick second oxide layer 43 (PSG layer).

[0173] Use a laser to remove the second oxide layer 43 in the area outside the second region 12. The laser is a violet picosecond laser with a power of 10 W. Use a chain machine to pickle and remove the second oxide layer 43 on the front and side surfaces around the diffusion. Then use a tank machine for an alkali etching step to remove the N-type doped layer outside the second region 12 and on the front surface, so that the back surface finally presents a back contact structure with an alternating distribution of p-type and n-type doped layers.

[0174] After completing the above P-region and N-region structure division, use a chain machine to pickle the mask layer 2 on the front surface to completely remove the mask layer 2. At this time, the front surface of the silicon substrate 1 remains clean and flat, and the impurity concentration has been effectively reduced during the double-sided diffusion and gettering process.

[0175] Then use a texturing alkali solution to form a pyramid-shaped textured surface structure on the front surface of the silicon substrate 1. The base size of the pyramid is 2 μm and the reflectivity is 8%.

[0176] After texturing, remove the remaining first oxide layer 33 in the first region 11 and the remaining second oxide layer 43 in the second region 12.

[0177] Subsequently, use the ALD process to deposit about 4 nm of aluminum oxide on both the front and back surfaces as the passivation layer 5.

[0178] Use the PECVD process to deposit an 80 nm silicon nitride layer on both the front and back surfaces as the antireflection layer 6, significantly improving the surface passivation effect and the incident light absorption rate.

[0179] Screen print and sinter finger-shaped electrodes in the electrode regions of the first region 11 and the second region 12 to complete the preparation of the solar cell.

[0180] Comparative example

[0181] The difference from this embodiment is only that: the initial thickness of the silicon wafer is 150 μm, both the front and back sides are thinned by 5 μm during double-sided polishing, and the thickness of the silicon substrate 1 after polishing is about 140 μm; when removing the regions outside the first region 11 on the back side and the P-type doping layer on the front side, the silicon substrate 1 is thinned on both sides, and the thickness of the silicon substrate 1 in the second region 12 and the spacer region 13 becomes about 130 μm; when removing the regions outside the second region 12 on the back side and the N-type doping layer on the front side, a texturing alkali solution is directly used to form the same textured surface structure on the front side of the silicon substrate 1 and the spacer region 13 as in the embodiment, and the thickness of the finally remaining silicon substrate 1 is basically the same as that in the embodiment.

[0182] The solar cells obtained in the embodiment and the comparative example were tested, and the results are shown in Table 1.

[0183] Table 1

[0184]

[0185] Note: Voc represents the open-circuit voltage, Jsc represents the short-circuit current density, FF represents the fill factor, and EFF represents the conversion efficiency.

[0186] From the experimental results, in the embodiment, a 140-μm original silicon wafer is used. Since the front side is protected by the mask layer 2 during alkali polishing and cleaning, only the back side of the silicon substrate 1 is etched, and the finally remaining thickness of the silicon substrate 1 is about 130 μm. In the comparative example, a 150-μm original silicon wafer is used, and double-sided etching occurs during alkali polishing and cleaning, and the finally remaining thickness of the silicon substrate 1 is about 130 μm. It can be seen that compared with the comparative example, the thickness of the original silicon wafer in the embodiment is reduced by 10 μm, saving the cost of the silicon wafer.

[0187] The mask layer 2 doped with the gettering element in the embodiment has the effect of double-sided gettering, significantly reducing the metal impurities in the silicon wafer, having a better passivation effect, and effectively reducing the recombination caused by metal impurities; the comparative example is single-sided gettering on the back side, and the open-circuit voltage, fill factor, etc. are significantly lower.

[0188] In summary, compared with the comparative example, the embodiment of the present invention can still obtain a higher open-circuit voltage and fill factor while reducing the thickness of the original silicon wafer by 10 μm, with the efficiency increased by 0.17%, and at the same time maintaining a good fragmentation rate and yield. It can be seen that the preparation method of the present invention can reduce the thickness of the original silicon wafer by about 10 μm under the same final thickness and structure conditions and improve the conversion efficiency, showing significant cost reduction and efficiency improvement advantages, and being more conducive to the large-scale and stable mass production of solar cells.

[0189] It should be understood that although this specification is described in terms of embodiments, not every embodiment contains only one independent technical solution. This narrative style of the specification is only for clarity. Those skilled in the art should regard the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

[0190] The series of detailed descriptions listed above are only specific descriptions of the feasible embodiments of the present invention; they are not intended to limit the protection scope of the present invention. Any equivalent embodiments or modifications made without departing from the spirit of the art of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for preparing a solar cell, characterized in that: It includes the following steps: A mask layer (2) is formed on the front surface of the silicon substrate (1), and the mask layer (2) is an alkali-resistant film layer; the mask layer (2) includes a first mask layer formed on the front surface of the silicon substrate (1) and a second mask layer formed on the surface of the first mask layer away from the silicon substrate (1). The first mask layer is a film layer composed of one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride doped with gettering elements, and the content of the gettering elements is 1 wt% - 4 wt%. The thickness of the first mask layer is 10% - 40% of the thickness of the entire mask layer (2); the second mask layer is not doped with the gettering elements; A first tunneling layer (31) and a first doping layer (32) are formed on the back surface of the silicon substrate (1); The back surface of the silicon substrate (1) has a first region (11) and a second region (12) arranged at intervals. The first doping layer (32), the first tunneling layer (31), and a part of the silicon substrate (1) in the region outside the first region (11) are removed; A second tunneling layer (41) and a second doping layer (42) are formed on the back surface of the silicon substrate (1), and the doping type of the second doping layer (42) is opposite to that of the first doping layer (32); The second doping layer (42), the second tunneling layer (41), and a part of the silicon substrate (1) in the region outside the second region (12) are removed; The mask layer (2) is removed; A first electrode (7) in contact with the first doping layer (32) is formed in the first region (11), and a second electrode (8) in contact with the second doping layer (42) is formed in the second region (12).

2. The method for preparing a solar cell according to claim 1, wherein: The first mask layer is a phosphorus-doped silicon oxide film, and the phosphorus content is 3 wt%.

3. The manufacturing method of the solar cell according to claim 1, wherein: The gettering elements are elements of the third main group and / or elements of the fifth main group.

4. The manufacturing method of the solar cell according to claim 1, characterized in that: The gettering elements doped in the first mask layer are phosphorus and / or boron.

5. The manufacturing method of a solar cell according to claim 1, wherein: The second mask layer is a film layer composed of one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride; And / or, the thickness of the first mask layer is less than the thickness of the second mask layer.

6. The manufacturing method of a solar cell according to claim 1, wherein: Removing the mask layer (2) includes: removing the mask layer (2) by pickling or removing the mask layer (2) by RCA cleaning.

7. The manufacturing method of the solar cell according to claim 1, wherein: After removing the mask layer (2), a textured structure is formed on the front surface of the silicon substrate (1).

8. A solar cell, characterized in that: Prepared by the method for preparing a solar cell according to any one of claims 1 to 7, the solar cell includes: A silicon substrate (1), the back surface of the silicon substrate (1) has a first region (11), a second region (12), and a spacer region (13) located between the first region (11) and the second region (12). The width of the spacer region (13) is 30 μm - 100 μm, and the thickness of the silicon substrate (1) in the first region (11) is greater than the thickness of the silicon substrate (1) in the second region (12); A first tunneling layer (31) located in the first region (11), and a first doping layer (32) located on a side of the first tunneling layer (31) away from the silicon substrate (1), wherein the doping type of the first doping layer (32) is opposite to that of the silicon substrate (1); A second tunneling layer (41) located in the second region (12), and a second doping layer (42) located on a side of the second tunneling layer (41) away from the silicon substrate (1), wherein the doping type of the second doping layer (42) is the same as that of the silicon substrate (1); A first electrode (7) in contact with the first doping layer (32); A second electrode (8) in contact with the second doping layer (42).

9. The solar cell according to claim 8, wherein: The thickness of the silicon substrate (1) in the first region (11) is 3 μm - 8 μm greater than the thickness of the silicon substrate (1) in the second region (12).

10. The solar cell according to claim 8, characterized in that: The ratio of the area of the first region (11) to the area of the second region (12) is 0.5:1 - 1.5:1; Or, the ratio of the width of the first region (11) to the width of the second region (12) is 0.5:1 - 1.5:1; Or, the width of the first region (11) is 200 μm - 800 μm, and the width of the second region (12) is 200 μm - 800 μm.

11. The solar cell according to any one of claims 8-10, characterized in that: Further comprising a passivation layer (5) on a side where the back surface of the silicon substrate (1) is located, and the passivation layer (5) is in contact with the surface of the silicon substrate (1) exposed outward at the spacer region (13); Or, the solar cell further comprises a passivation layer (5) on a side where the back surface of the silicon substrate (1) is located, the passivation layer (5) is in contact with the surface of the silicon substrate (1) exposed outward at the spacer region (13) at the spacer region (13), the passivation layer (5) is in contact with the surface of the first doping layer (32) away from the silicon substrate (1) and / or the side surface facing the spacer region (13) in the first region (11), and the passivation layer (5) is in contact with the surface of the second doping layer (42) away from the silicon substrate (1) and / or the side surface facing the spacer region (13) in the second region (12).

12. The solar cell according to claim 11, wherein: Further comprising an antireflection layer (6) on a side where the back surface of the silicon substrate (1) is located, The antireflection layer (6) is in contact with the surface of the passivation layer (5) away from the silicon substrate (1); Or, the antireflection layer (6) is in contact with the surface of the first doping layer (32) away from the silicon substrate (1) in the first region (11), is in contact with the surface of the second doping layer (42) away from the silicon substrate (1) in the second region (12), and is in contact with the surface of the passivation layer (5) exposed outward at the spacer region (13) at the spacer region (13).

13. The solar cell according to claim 11, characterized in that: In a direction away from the silicon substrate (1), the passivation layer (5) in direct contact with the back surface of the silicon substrate (1) exposed in the spacer region (13) is an aluminum oxide layer with a thickness of 2 nm - 7 nm.

14. The solar cell according to claim 11, wherein: The silicon substrate (1) is an N-type silicon substrate, the first doped layer (32) is a P-type doped layer, and the second doped layer (42) is an N-type doped layer; or, the silicon substrate (1) is an N-type silicon substrate, the first doped layer (32) is a boron-doped polysilicon layer, and the second doped layer (42) is a phosphorus-doped polysilicon layer; And / or, the width of the first region is 300 μm ± 100 nm, and the width of the second region is 420 μm ± 100 nm.

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