Semiconductor device structure based on OLED display, forming method and display device

Abstract

The application relates to a semiconductor device structure based on an OLED display, a forming method and a display device, the semiconductor device structure comprising a substrate, the substrate comprising a first well region and a second well region, a first conduction structure on the first well region and a second conduction structure on the second well region, the first conduction structure and the second conduction structure being connected, a first active region in the first well region, the first active region comprising a source region and a drain region, a second active region in the second well region, the second active region forming a gate electrode. In the embodiment of the application, the second conduction structure and the conduction process of the second conduction structure are added through the above device structure, so that it is more difficult to open the conductive channel between the source region and the drain region, thereby improving the subthreshold swing, further increasing the change range of the gate voltage, making the compensation space larger, and achieving the goal of improving the display effect of the final product.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor device structure, formation method and display device based on OLED display. Background Technology

[0002] Microdisplay technology is an important technology in the rapidly developing display field. It integrates all the pixel units and driving units required for a display screen onto a single chip, giving it advantages such as small size, high resolution, and low power consumption.

[0003] Organic light-emitting diodes (OLEDs), as light-emitting devices, are current-driven, meaning their brightness is directly proportional to the current flowing through them. In some common driving circuits, the current range required to control the OLED's emission from its dimmest to its brightest is 10 pA to 10 nA. Because the current range required to control the OLED's emission from its dimmest to its brightest is relatively small, most devices struggle to meet such a low current requirement. However, metal-oxide-semiconductor field-effect transistors (MOSFETs) have a subthreshold current that perfectly matches the current range required for OLED emission. Therefore, MOSFETs are typically used in driving circuits to control OLED emission.

[0004] Figure 1 This is a MOS transistor transfer characteristic curve provided in an embodiment of this application, such as... Figure 1 As shown, this curve represents the relationship between the control voltage and current of some MOSFETs. From Figure 1 As can be seen, for some MOSFETs, when the current is in the range of 10pA-10nA, the control voltage is between 0.5-0.8V, that is, the range of control voltage variation is about 0.3V. This indicates that the input voltage of the drive circuit needs to be controlled within 0.3V.

[0005] However, the threshold voltage drift of MOSFETs is significant both in their manufacturing and application. Therefore, to ensure that OLEDs within different pixels emit the same light intensity under the same input voltage, it is crucial to mitigate the adverse effects of threshold voltage drift on OLED light emission as much as possible. Summary of the Invention

[0006] To address the aforementioned technical problems, this application provides a semiconductor device structure, a method for forming the structure, and a display device based on OLED displays.

[0007] In a first aspect, the embodiments of the present application disclose a semiconductor device structure based on OLED display, comprising:

[0008] a substrate; the substrate comprises a first well region and a second well region; the first well region is implanted with first doping ions, and the second well region is implanted with second doping ions; the first doping ions and the second doping ions are of different conductive types;

[0009] a first conductive structure located on the first well region and a second conductive structure located on the second well region; the first conductive structure and the second conductive structure are connected;

[0010] a first active region located in the first well region; the first active region comprises a source region and a drain region; the source region and the drain region are implanted with third doping ions; the source region and the drain region are located on two sides of the first conductive structure respectively;

[0011] a second active region located in the second well region; the second active region comprises a first doped region, and the first doped region is implanted with fourth doping ions; the first doped region forms a gate electrode;

[0012] the second doping ions, the third doping ions and the fourth doping ions are of the same conductive type.

[0013] In some possible embodiments, the second active region further comprises a second doped region; the second doped region is implanted with the fourth doping ions;

[0014] the first doped region and the second doped region are located on two sides of the second conductive structure respectively; the first doped region and the second doped region form the gate electrode.

[0015] In some possible embodiments, the first conductive structure and the second conductive structure are of the same size in a first direction;

[0016] the first active region and the second active region are of the same size in a second direction;

[0017] an area of a first overlapping region corresponding to the first active region and the first conductive structure is equal to an area of a second overlapping region corresponding to the second active region and the second conductive structure.

[0018] In some possible embodiments, the first conductive structure is larger than the second conductive structure in the first direction;

[0019] the first active region and the second active region are of the same size in the second direction;

[0020] an area of a first overlapping region corresponding to the first active region and the first conductive structure is greater than an area of a second overlapping region corresponding to the second active region and the second conductive structure.

[0021] In some possible embodiments, the first conductive structure and the second conductive structure have the same size in the first direction;

[0022] The first active region has a size in the second direction smaller than a size of the second active region in the second direction;

[0023] The first active region and the first conductive structure correspond to a first overlapping area having an area smaller than a second overlapping area corresponding to the second active region and the second conductive structure.

[0024] In some possible embodiments, the second active region further comprises a second doped region; the second doped region is implanted with second doped ions; the first doped region and the second doped region are respectively located on two sides of the second conductive structure; and the first doped region forms a gate electrode;

[0025] The first conductive structure has a size in the first direction larger than a size of the second conductive structure in the first direction;

[0026] The first active region and the second active region have the same size in the second direction;

[0027] The first active region and the first conductive structure correspond to a first overlapping area having an area larger than a second overlapping area corresponding to the second active region and the second conductive structure.

[0028] In some possible embodiments,

[0029] The first doped ions implanted in the first well region have a first concentration;

[0030] The third doped ions implanted in the source region and the drain region have a second concentration;

[0031] The second concentration is greater than the first concentration;

[0032] The second doped ions implanted in the second well region have a third concentration;

[0033] The fourth doped ions implanted in the first doped region have a fourth concentration;

[0034] The fourth concentration is greater than the third concentration.

[0035] In some possible embodiments, the second doped ions implanted in the second well region have a fifth concentration;

[0036] The fifth concentration is greater than the third concentration, and the fifth concentration is smaller than the fourth concentration.

[0037] In some possible embodiments, the first conductive structure and the second conductive structure are polycrystalline silicon.

[0038] In some possible embodiments, the first conductive structure and the second conductive structure are an integral structure.

[0039] In a second aspect, the embodiments of the present application disclose a forming method of a semiconductor device structure based on OLED display, which comprises the following steps:

[0040] providing a substrate;

[0041] forming a first well region and a second well region in the substrate; the first well region is implanted with first doping ions, and the second well region is implanted with second doping ions; the first doping ions and the second doping ions are of different conductive types;

[0042] forming a first conduction structure and a second conduction structure on the first well region and the second well region; the first conduction structure and the second conduction structure are connected;

[0043] forming a first active region in the first well region; the first active region comprises a source region and a drain region; the source region and the drain region are implanted with third doping ions; the source region and the drain region are respectively located on two sides of the first conduction structure;

[0044] forming a second active region in the second well region; the second active region comprises a first doped region; the first doped region is implanted with fourth doping ions; the first doped region forms a gate electrode;

[0045] the second doping ions, the third doping ions and the fourth doping ions are of the same conductive type.

[0046] In some possible embodiments, the second active region further comprises a second doped region; the second doped region is implanted with the fourth doping ions;

[0047] the first doped region and the second doped region are respectively located on two sides of the second conduction structure; the first doped region and the second doped region form the gate electrode.

[0048] In a third aspect, the embodiments of the present application disclose a display device, which comprises the semiconductor device structure based on OLED display as described above.

[0049] In a fourth aspect, the embodiments of the present application disclose an electronic device, which comprises the semiconductor device structure based on OLED display as described above.

[0050] The technical scheme provided by the embodiments of the present application has the following technical effects:

[0051] The semiconductor device structure of the embodiment of the present application comprises a substrate, the substrate comprises a first well region and a second well region, the first well region is implanted with first doping ions, the second well region is implanted with second doping ions, the first doping ions and the second doping ions are of different conductive types, a first conduction structure located on the first well region and a second conduction structure located on the second well region, the first conduction structure and the second conduction structure are connected, a first active region located in the first well region, the first active region comprises a source region and a drain region, the source region and the drain region are implanted with third doping ions, the source region and the drain region are located on two sides of the first conduction structure respectively, a second active region located in the second well region, the second active region comprises a first doped region, the first doped region is implanted with fourth doping ions, the first doped region forms a gate, the second doping ions, the third doping ions and the fourth doping ions are of the same conductive type. In the embodiment of the present application, the gate voltage corresponding to the second conduction structure is controlled, so that the second conduction structure can drive the first conduction structure to form an inversion layer, and then the source region and the drain region are turned on, that is, the second conduction structure and the conduction process of the second conduction structure are equivalent to be increased, so that it is more difficult to open the conductive channel between the source region and the drain region, thereby improving the sub-threshold swing, and then increasing the change range of the gate voltage, so that the compensation space becomes larger, thereby achieving the goal of improving the display effect of the final product. BRIEF DESCRIPTION OF DRAWINGS

[0052] In order to more clearly illustrate the technical solutions and advantages of the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and those skilled in the art can also obtain other drawings according to these drawings without creative labor.

[0053] Figure 1 It is a MOS tube transfer characteristic curve provided by the embodiment of the present application;

[0054] Figure 2 It is a schematic diagram of a driving circuit of an OLED provided by the embodiment of the present application;

[0055] Figure 3 It is a channel conduction structure schematic diagram of a MOS tube provided by the embodiment of the present application;

[0056] Figure 4 It is a three-dimensional schematic diagram of a semiconductor device structure provided by the embodiment of the present application Figure 1 ;

[0057] Figure 5 It is an application schematic diagram of a semiconductor device structure provided by the embodiment of the present application Figure 1 ;

[0058] Figure 6is a top view schematic of a semiconductor device structure provided by an embodiment of the present application Figure 1 ;

[0059] Figure 7 is a top view schematic of a semiconductor device structure provided by an embodiment of the present application Figure 2 ;

[0060] Figure 8 is a perspective schematic of a semiconductor device structure provided by an embodiment of the present application Figure 2 ;

[0061] Figure 9 is an application schematic of a semiconductor device structure provided by an embodiment of the present application Figure 2 ;

[0062] Figure 10 is a top view schematic of a semiconductor device structure provided by an embodiment of the present application Figure 3 ;

[0063] Figure 11 is a top view schematic of a semiconductor device structure provided by an embodiment of the present application Figure 4 ;

[0064] Figure 12 is a top view schematic of a semiconductor device structure provided by an embodiment of the present application Figure 5 ;

[0065] Figure 13 is a top view schematic of a semiconductor device structure provided by an embodiment of the present application Figure 6 ;

[0066] Figure 14 is a schematic diagram of a forming method of a semiconductor device structure based on OLED display provided by an embodiment of the present application. DETAILED DESCRIPTION

[0067] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0068] It should be noted that the description of the embodiments of the present application refers to "one embodiment" or "an embodiment" of the present application, which means that a specific feature, structure, or characteristic described in connection with the embodiment can be included in at least one implementation of the present application. It is to be understood that the terms "upper", "lower", "top", "bottom", and the like as used herein refer to the orientation or position of the drawings as shown in the drawings, and are used for convenience only to provide reference directions in order to facilitate the description of the present application and to simplify the description, and do not indicate or imply that a device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore should not be construed as limiting the present application. The terms "first", "second", "third", etc. are used only for descriptive purposes and should not be construed as indicating or implying relative importance or a specific number of the technical features indicated. Therefore, the features defined as "first", "second" can include one or more of the features. Moreover, the terms "first", "second", etc. are used to distinguish similar objects, and do not necessarily indicate a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein. In addition, in the description of the embodiments, "a plurality of" means two or more, unless otherwise specified. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system or product including a series of steps or units does not necessarily limit to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to the process, method, product or device.

[0069] It should be understood that when an element or layer is referred to as being "on", "adjacent", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer, or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on", "directly adjacent", "directly connected to", or "directly coupled to" another element or layer, then there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application. When a second element, component, region, layer or section is discussed, it should not be understood that a first element, component, region, layer or section is necessarily present.

[0070] To make the objectives, technical solutions, and advantages disclosed in the embodiments of this application clearer, the embodiments of this application will be further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of the embodiments of this application and are not intended to limit the embodiments of this application.

[0071] In this embodiment of the application, the threshold voltage V t This refers to the gate voltage when a conductive channel is formed between the source and drain of a MOSFET. Subthreshold current refers to the gate voltage V0 of the MOSFET. G Below the threshold voltage V t This refers to the minute leakage current between the source and drain when the device is in a subthreshold state.

[0072] In this embodiment, under the ideal current-voltage characteristics of a MOSFET, when the gate voltage V G Less than the threshold voltage V t The leakage current is 0. However, in practice, when the gate voltage V... G Less than the threshold voltage V t When the value is greater than 0, the MOSFET is in a weak inversion state (different from the strong inversion state when it is turned on), and this region is called the subthreshold region. When the MOSFET is operating in the subthreshold region, although there are charge carriers in the conductive channel, the concentration is low, so the leakage current is very small, but it is not actually zero. This leakage current is called the subthreshold current.

[0073] Figure 2 This is a schematic diagram of an OLED driving circuit provided in an embodiment of this application, as shown below. Figure 2 As shown, the driving circuit on the left is a simplified illustration. In actual applications, the driving circuit can be a 2T1C circuit, a 6T1C circuit, or other similar circuits.

[0074] Optionally, one end of the OLED is grounded, and the other end is connected to the source of a MOSFET. The drain of the MOSFET is connected to a power supply. The different brightness levels of the OLED are achieved by controlling the gate voltage V of the MOSFET. G The control voltage in Figure 2 generates different leakage currents, and the range of leakage current is 10pA-10nA.

[0075] Figure 3 This is a schematic diagram of the channel conduction structure of a MOS transistor provided in an embodiment of this application, as shown below. Figure 3 As shown, this includes the non-conducting stage of the source and drain above the arrow corresponding to the NMOS transistor and the conducting stage of the source and drain below the arrow. The NMOS transistor includes a P-type substrate 301, an oxide layer 302, polysilicon 303, a source region 304, and a drain region 305.

[0076] like Figure 3As shown, the NMOS tube takes P-type semiconductor as substrate, on a low-doped P-type substrate 301, two high-doped N-type semiconductors, i.e. source region 304 and drain region 305, are made by diffusion process, and are respectively connected to source and drain, an oxide layer 302 is added on the P-type substrate, and a gate is made by polycrystalline silicon 303. The P-type semiconductor can provide a large number of holes, and the N-type semiconductor can provide a large number of electrons.

[0077] Optionally, there are two back-to-back PN junctions between the source region 304 and the drain region 305, when the gate voltage is 0, one of the PN junctions is always in reverse bias state, and there is no conductive channel between the source region 304 and the drain region 305, at this time, even if a voltage is applied to the drain, there is no leakage current.

[0078] When the gate voltage is greater than the threshold voltage, as shown in FIG. 3B, a conductive channel 306 is formed between the source region 304 and the drain region 305. Figure 3 Because the conductive channel is an N-type conductive channel, which is opposite to the conductive type of the P-type substrate 301, it is called an inversion layer. Similarly, the channel conduction structure of the PMOS tube can be obtained.

[0079] In some optional embodiments, the driving circuit usually uses MOS tubes (NMOS tubes or PMOS tubes) to control the OLED to emit light. However, because the threshold voltage drift of the MOS tube will adversely affect the realization of the same luminous intensity of the OLED in different pixels under the same input voltage, in some optional embodiments, some additional circuits can be added on the basis of the original MOS tube to compensate for the influence of the threshold voltage drift and improve the display effect of the final product.

[0080] In some possible embodiments, the compensation effect of the threshold voltage drift is related to the change range of the gate voltage (corresponding to the current 10 pA-10 nA in the application), the greater the change range of the gate voltage, the greater the compensable space, and the better the display effect of the final product.

[0081] In some possible embodiments, the change range of the gate voltage can be expanded by increasing the subthreshold swing (STS) of the device.

[0082] Figure 4 FIG. 1 is a schematic diagram of a semiconductor device structure provided by an embodiment of the application; Figure 1 As shown in FIG. 1, the semiconductor device structure includes: Figure 4 As shown in FIG. 1, the semiconductor device structure includes:

[0083] The substrate (not shown in the figure) can be a P-type substrate or an N-type substrate. Figure 4The substrate (not shown) includes a first well region 401 and a second well region 402, the first well region 401 is implanted with first doping ions, and the second well region 402 is implanted with second doping ions, wherein the first doping ions and the second doping ions are of different conductive types.

[0084] A first conductive structure 403 is located on the first well region 401, and a second conductive structure 404 is located on the second well region 402, wherein the first conductive structure 403 and the second conductive structure 404 are connected. In an alternative embodiment, the first conductive structure 403 and the second conductive structure 404 can be two parts (as shown), but the two parts are connected together through a contact. In another alternative embodiment, the first conductive structure 403 and the second conductive structure 404 can be an integral structure. Figure 4

[0085] A first active region 405 is located in the first well region 401, the first active region 405 includes a source region 4051 and a drain region 4052, both of which are implanted with third doping ions, and the source region 4051 and the drain region 4052 are respectively located on two sides of the first conductive structure. Optionally, the source region 4051 can form a source, and the drain region 4052 can form a drain.

[0086] A second active region 406 is located in the second well region 402, the second active region 406 includes a first doped region, the first doped region is implanted with fourth doping ions, and the first doped region forms a gate. Wherein the second doping ions, the third doping ions and the fourth doping ions are of the same conductive type.

[0087] Optionally, the second active region including the first doped region can be embodied as the second active region being the first doped region.

[0088] Optionally, the first conductive structure and the second conductive structure are metal or polysilicon. When the first conductive structure and the second conductive structure are an integral structure, the first conductive structure and the second conductive structure can be an entire metal structure or an entire polysilicon structure.

[0089] As described above, the embodiments of the present application add some additional circuits to compensate for the influence of threshold voltage drift on the basis of the original MOS tube, and improve the display effect of the final product. Therefore, Figure 4 The semiconductor device structure shown can be regarded as two parts, the left part (including the first well region 401, the first active region 405 located in the first well region 401, and the first conductive structure 403 located on the first well region 401) can be regarded as an NMOS tube or a PMOS tube. The following will introduce the semiconductor device structure when the left part is an NMOS tube or a PMOS tube.

[0090] ​In one alternative embodiment, Figure 4 The left side is an NMOS transistor, which includes a first well region 401 on the substrate and a first active region 405 in the first well region 401. The first active region 405 includes a source region 4051 and a drain region 4052, and a first conductive structure 403 located on the first well region 401. The first dopant ion implanted in the first well region 401 is a P-type impurity, and the third dopant ion implanted in the source region 4051 and the drain region 4052 is an N-type impurity. The concentration of the first dopant ion implanted in the first well region 401 is a first concentration, and the concentration of the third dopant ion implanted in the source region 4051 and the drain region 4052 is a second concentration, which is higher than the first concentration.

[0091] Optional, such as Figure 4 As shown, an oxide layer may exist between the first well region 401 and the first conductive structure 403.

[0092] Figure 4 The right-hand portion includes a second well region 402 on the substrate, a second active region 406 on the second well region 402, and a second conductive structure 404 located on the second well region 402. The first conductive structure 403 and the second conductive structure 404 can be connected by a contact.

[0093] Optionally, the second dopant ion implanted in the second well region 402 is an N-type impurity, and the fourth dopant ion implanted in the first doped region included in the second active region 406 is an N-type impurity. The concentration of the second dopant ion implanted in the second well region 402 is the third concentration, and the concentration of the fourth dopant ion implanted in the first doped region is the fourth concentration, which is higher than the third concentration.

[0094] Optionally, the concentration of the first doped ion implanted in the first well region 401 and the concentration of the second doped ion implanted in the second well region 402 can be the same or different, that is, the first concentration can be equal to the third concentration or the first concentration can be different from the third concentration.

[0095] Optionally, the concentration of the fourth doped ion implanted in the first doped region can be the same as or different from the concentration of the third doped ion implanted in the source region 4051 and the drain region 4052. That is, the second concentration can be equal to the fourth concentration, or the second concentration can be different from the fourth concentration.

[0096] Optionally, the concentrations of the second and fourth doped ions can also be the same.

[0097] Optionally, the third and fourth doped ions can be the same doped ion (with identical concentration, dosage, or element). Alternatively, the third and fourth doped ions can be doped ions with the same conductivity type but different concentrations, dosages, or elements.

[0098] Optionally, as shown in FIG. 4B, there can be an oxide layer between the second well region 402 and the second conductive structure 404. Figure 4

[0099] In an optional embodiment, the left part of FIG. 4A is a PMOS transistor, which includes a first well region 401 on a substrate, a first active region 405 in the first well region 401, the first active region 405 including a source region 4051 and a drain region 4052, and a first conductive structure 403 on the first well region 401. The first doping ions implanted in the first well region 401 are N-type impurities, and the third doping ions implanted in the source region 4051 and the drain region 4052 are P-type impurities. The concentration of the first doping ions implanted in the first well region 401 is a first concentration, and the concentration of the third doping ions implanted in the source region 4051 and the drain region 4052 is a second concentration, which is higher than the first concentration. Figure 4 Optionally, as shown in FIG. 4B, there can be an oxide layer between the first well region 401 and the first conductive structure 403.

[0100] Figure 4

[0101] Figure 4 The right part of FIG. 4A is a PMOS transistor, which includes a second well region 402 on a substrate, a second active region 406 in the second well region 402, and a second conductive structure 404 on the second well region 402. The first conductive structure 403 and the second conductive structure 404 can be connected through a contact.

[0102] Optionally, the second doping ions implanted in the second well region 402 are P-type impurities, and the fourth doping ions implanted in the first doping region of the second active region 406 are P-type impurities. The concentration of the second doping ions implanted in the second well region 402 is a third concentration, and the concentration of the fourth doping ions implanted in the first doping region is a fourth concentration, which is higher than the third concentration.

[0103] Optionally, the concentration of the first doping ions implanted in the first well region 401 and the concentration of the second doping ions implanted in the second well region 402 can be the same or different, i.e., the first concentration can be equal to the third concentration, or the first concentration can not be equal to the third concentration.

[0104] Optionally, the concentration of the fourth doping ions implanted in the first doping region and the concentration of the third doping ions implanted in the source region 4051 and the drain region 4052 can be the same or different, i.e., the second concentration can be equal to the fourth concentration, or the second concentration can not be equal to the fourth concentration.

[0105] ​​​Optionally, the third doping ions and the fourth doping ions can be the same doping ions (completely same in concentration, dose or element).

[0106] Optionally, as shown in FIG. 4B, there can be an oxide layer between the second well region 402 and the second conduction structure 404. Figure 4

[0107] Since the structures of the NMOS and the PMOS, the semiconductor device structures obtained by expanding the structures and the circuit principles are corresponding, the embodiments in the present application will be described by taking the semiconductor device structure corresponding to the NMOS as an example, and the semiconductor device structure corresponding to the PMOS can be inferred by referring to the semiconductor device structure corresponding to the NMOS, and the full text will not be described in detail.

[0108] Figure 5 is an application example of a semiconductor device structure provided by the present application Figure 1 , the semiconductor device structure corresponding to Figure 4 is shown in FIG. 4A. Figure 5 The left part of the cross-sectional view in the source-drain non-conduction stage and the source-drain conduction stage is shown in FIG. 4B, and the right part of the cross-sectional view in the source-drain non-conduction stage and the source-drain conduction stage is shown in FIG. 4C. Figure 4 The left part of the cross-sectional view in the source-drain non-conduction stage and the source-drain conduction stage is shown in FIG. 4B, and the right part of the cross-sectional view in the source-drain non-conduction stage and the source-drain conduction stage is shown in FIG. 4C. Figure 4 The left part of the cross-sectional view in the source-drain non-conduction stage and the source-drain conduction stage is shown in FIG. 4B, and the right part of the cross-sectional view in the source-drain non-conduction stage and the source-drain conduction stage is shown in FIG. 4C.

[0109] In the embodiments of the present application, the first doping region of the second active region 406 forms a gate, the fourth doping ions injected in the first doping region and the second doping ions injected in the second well region 402 are N-type impurities, and a large number of electrons exist, and the first doping ions injected in the first well region 401 are P-type impurities, and a large number of holes exist.

[0110] ​When the gate voltage is 0, the second well region 402 remains unchanged. When the gate voltage is greater than 0, since the fourth dopant ions implanted in the first doped region and the second dopant ions implanted in the second well region 402 are N-type impurities, a large number of electrons accumulate in the region near the oxide layer of the second well region 402. This causes a large number of holes to accumulate on the side of the second conductive structure 404 (e.g., polycrystalline silicon) near the oxide layer. Since the first conductive structure 403 and the second conductive structure 404 are either in contact or integral, a large number of holes also accumulate on the side of the first conductive structure 403 near the oxide layer. At this time, the large number of holes accumulated on the side of the first conductive structure 403 near the oxide layer repels the holes in the first well region 401 near the oxide layer and attracts electrons, forming a conductive channel that conducts the source and drain. When the drain is connected to a voltage source, a subthreshold leakage current is generated, thereby lighting up the OLED through the source.

[0111] Figure 3 The semiconductor structure shown directly controls the gate voltage, forming a conductive channel between the source and drain regions through polysilicon inversion, thus connecting the source and drain. However, Figure 5 The semiconductor device structure shown requires first controlling the gate voltage of the right-hand portion, causing the polysilicon corresponding to the right-hand portion to invert and conduct to the polysilicon corresponding to the left-hand portion, thereby forming a conductive channel between the source region 4051 and the drain region 4052. Figure 3 The semiconductor structure shown (a typical MOS transistor) makes it more difficult to form a conductive channel, meaning it is more difficult to turn on the conductive channel. Therefore, its subthreshold swing is increased, which in turn increases the range of gate voltage variation, making the compensation space larger, thereby achieving the goal of improving the display effect of the final product.

[0112] Figure 6 This is a top view schematic diagram of a semiconductor device structure provided in an embodiment of this application. Figure 1 , Figure 6 for Figure 4 Top view, including Figure 4 The substrate not shown in the figure has a first doped region in the second active region 406 forming the gate (CT in the figure). In this article, CTs are schematic conductors connected to the electrode.

[0113] In one alternative embodiment, such as Figure 6 As shown, the first conductive structure 403 and the second conductive structure 404 have the same dimensions in the first direction. Specifically, when the first conductive structure 403 and the second conductive structure 404 are a single integral structure, its top view can be shown as follows. Figure 10 The image shows a rectangle.

[0114] In this embodiment, the first active region 405 includes not only the source region 4051 and the drain region 4052, but also a region covered by the first conductive structure, which is ultimately used to form a conductive channel. The second active region includes not only the first doped region, but also a region covered by the second conductive structure.

[0115] Optionally, the first active region 405 and the second active region 406 have the same dimensions in the second direction, that is, the first active region 405 and the second active region 406 have the same span in the second direction.

[0116] Thus, the area of ​​the first overlapping region corresponding to the first active region 405 and the first conductive structure 403 is ultimately reduced ( Figure 6 (Illustrated by the dashed circle on the left) The area of ​​the second overlapping region corresponding to the second active region 406 and the second conductive structure 404 ( Figure 6 (Illustrated by the dashed circle on the right) Equal, meaning that when the two active regions and the polysilicon above overlap, the two overlapping areas are equal.

[0117] Figure 7 This is a top view schematic diagram of a semiconductor device structure provided in an embodiment of this application. Figure 2 , Figure 7 To Figure 6 The top view of the semiconductor device structure shown has been slightly modified, including... Figure 4 Substrate not shown in the image.

[0118] In one alternative embodiment, such as Figure 7 As shown, the dimension of the first conductive structure 403 on the first well region 401 in the first direction is larger than the dimension of the second conductive structure 404 on the second well region 402 in the first direction.

[0119] In this embodiment, the first active region 405 includes not only the source region 4051 and the drain region 4052, but also a region covered by the first conductive structure, which is ultimately used to form a conductive channel. The second active region includes not only the first doped region, but also a region covered by the second conductive structure.

[0120] Optionally, the first active region 405 and the second active region 406 have the same size in the second direction, but different sizes in the first direction. For example, the size of the first active region 405 in the first direction is larger than the size of the second active region 406 in the first direction.

[0121] Thus, the area of ​​the first overlapping region corresponding to the first active region 405 and the first conductive structure 403 is ultimately reduced ( Figure 7 (The area circled by the dashed line on the left) is greater than the area of ​​the second overlapping region corresponding to the second active region 406 and the second conductive structure 404. Figure 7(Illustrated by the dashed circle on the right) This means that the two active regions overlap with the polysilicon above, and the first overlapping area corresponding to the first overlapping region is greater than the second overlapping area corresponding to the second overlapping region.

[0122] From the above Figure 6-7 The relationship between the two overlapping regions can be summarized from the two diagrams as follows: Figure 6 In the middle, the areas of the first overlapping region and the second overlapping region are equal. Figure 7 In the first overlapping region, the area is larger than the area of ​​the second overlapping region.

[0123] Based on the above analysis, the semiconductor device structure in the embodiments of this application is relatively... Figure 3 The semiconductor structure shown (a typical MOSFET) makes it more difficult to form a conductive channel, meaning it's more difficult to turn on the conductive channel. The voltage applied to the gate corresponding to the second active region causes an inversion layer to form on the polysilicon in the second overlapping region. The smaller the area of ​​the second overlapping region, the weaker the ability to conduct to the first overlapping region, thus making it more difficult to turn on the conductive channel. In other words, the subthreshold swing is significantly increased.

[0124] Therefore, the larger the ratio of the first overlapping region to the second overlapping region, the more difficult it is to open the conductive channel, meaning the greater the increase in the subthreshold swing of the semiconductor device. Thus, with the ratio of the first overlapping region to the second overlapping region determined, the dimensions of the first conductive structure 403 and the second conductive structure 404 can be flexibly adjusted in the first or second direction, as can the dimensions of the first active region 405 and the second active region 406 in the first and second directions. Furthermore, in some possible embodiments that meet the conditions, the use of polysilicon material can be saved, or the area of ​​the first and second active regions can be controlled to save material, enabling miniaturization of the semiconductor device structure, saving the area of ​​the driving transistor, thereby reducing the pixel area and improving the resolution of the final product.

[0125] Figure 8 This is a three-dimensional schematic diagram of a semiconductor device structure provided in an embodiment of this application. Figure 2 ,like Figure 8 As shown, the semiconductor device structure includes:

[0126] substrate ( Figure 8 (Not shown in the image) The substrate includes a first well region 401 and a second well region 402. The first well region 401 is implanted with a first doped ion, and the second well region 402 is implanted with a second doped ion. The first doped ion and the second doped ion have different conductivity types.

[0127] A first conductive structure 403 is located on the first well region 401, and a second conductive structure 404 is located on the second well region 402, wherein the first conductive structure 403 and the second conductive structure 404 are connected by a contact. In an alternative embodiment, the first conductive structure 403 and the second conductive structure 404 can be two parts (as shown in Figure 4 ), but the two parts are connected together. In another alternative embodiment, the first conductive structure 403 and the second conductive structure 404 can be an integral structure as shown in Figure 8 .

[0128] A first active region 405 is located in the first well region 401, the first active region 405 includes a source region 4051 and a drain region 4052, both of which are implanted with third doping ions, and the source region 4051 and the drain region 4052 are located on two sides of the first conductive structure respectively. Optionally, the source region 4051 can form a source, and the drain region 4052 can form a drain.

[0129] A second active region 406 is located in the second well region 402, the second active region 406 includes a first doped region 4061 and a second doped region 4062, both of which are implanted with fourth doping ions, and the first doped region 4061 and the second doped region 4062 are located on two sides of the second conductive structure respectively. The first doped region 4061 and the second doped region 4062 form a gate. The second doping ions, the third doping ions and the fourth doping ions are of the same conductivity type.

[0130] Optionally, the first conductive structure and the second conductive structure are metal or polysilicon. When the first conductive structure and the second conductive structure are an integral structure, the first conductive structure and the second conductive structure can be an integral metal structure or an integral polysilicon structure.

[0131] In an alternative embodiment, when the left part of Figure 8 is an NMOS transistor, the NMOS transistor includes a first well region 401 on a substrate, a first active region 405 in the first well region 401, the first active region 405 includes a source region 4051 and a drain region 4052, and a first conductive structure 403 located on the first well region 401. The first doping ions implanted in the first well region 401 are P-type impurities, and the third doping ions implanted in the source region 4051 and the drain region 4052 are N-type impurities, wherein the concentration of the first doping ions implanted in the first well region 401 is a first concentration, and the concentration of the third doping ions implanted in the source region 4051 and the drain region 4052 is a second concentration, the second concentration is higher than the first concentration.

[0132] Figure 4The right part of the semiconductor device structure includes a second well region 402 on a substrate, and a second active region 406 in the second well region 402 and a second conductive structure 404 on the second well region 402, the second active region 406 includes a first doped region 4061 and a second doped region 4062. The first conductive structure 403 and the second conductive structure 404 are an integral structure.

[0133] Optionally, the second doped ions implanted in the second well region 402 are N-type impurities, the first doped region 4061 and the second doped region 4062 included in the second active region 406 are implanted with fourth doped ions which are N-type impurities, wherein the third concentration of the second doped ions implanted in the second well region 402 and the concentration of the fourth doped ions implanted in the first doped region 4061 and the second doped region 4062 are the fourth concentration, and the fourth concentration is higher than the third concentration.

[0134] Optionally, the concentration of the first doped ions implanted in the first well region 401 and the concentration of the second doped ions implanted in the second well region 402 can be the same or different, that is, the first concentration can be equal to the third concentration, or the first concentration can be different from the third concentration.

[0135] Optionally, the concentration of the fourth doped ions implanted in the first doped region 4061 and the second doped region 4062 and the concentration of the third doped ions implanted in the source region 4051 and the drain region 4052 can be the same or different, that is, the second concentration can be equal to the fourth concentration, or the second concentration can be different from the fourth concentration.

[0136] Optionally, the concentration of the second doped ions and the fourth doped ions can also be the same.

[0137] Optionally, the third doped ions and the fourth doped ions can be the same kind of doped ions (the same concentration, dose or element). The third doped ions and the fourth doped ions can also be doped ions of the same conductivity type, but different concentrations, doses or elements.

[0138] Optionally, as shown in Figure 8 , there can be an oxide layer under the entire conductive structure (including the first conductive structure 403 and the second conductive structure 404).

[0139] Figure 9 is an application of a semiconductor device structure provided by the embodiment of the present application Figure 2 , corresponding to Figure 8 the semiconductor device structure. Figure 9 includes the source-drain non-conduction stage above the arrow and the source-drain conduction stage below the arrow. In the source-drain non-conduction stage and the source-drain conduction stage, the left side of the figure represents Figure 8The cross-sectional view on the left shows the source-drain non-conducting stage and the source-drain conducting stage, while the view on the right shows... Figure 8 Cross-sectional view of the right side.

[0140] In this embodiment, the first doped region 4061 and the second doped region 4062 form a gate. The fourth doped ion implanted in the first doped region 4061 and the second doped region 4062, and the second doped ion implanted in the second well region 402 are N-type impurities, which contain a large number of electrons. The first doped ion implanted in the first well region 401 is a P-type impurity, which contains a large number of holes.

[0141] When the gate voltage is 0, the second well region 402 remains unchanged. When the gate voltage is greater than 0, a large number of electrons accumulate in the region of the second well region 402 near the oxide layer, causing a large number of holes to accumulate on the side of the second conductive structure 404 (e.g., polycrystalline silicon) near the oxide layer. Since the first conductive structure 403 and the second conductive structure 404 are either in contact or integral, a large number of holes also accumulate on the side of the first conductive structure 403 near the oxide layer. At this time, the large number of holes accumulated on the side of the first conductive structure 403 near the oxide layer repel the holes in the first well region 401 near the oxide layer and attract electrons, forming a conductive channel that connects the source and drain. When the drain is connected to a voltage source, a subthreshold leakage current is generated, thereby lighting up the OLED through the source.

[0142] Figure 3 The semiconductor structure shown directly controls the gate voltage, forming a conductive channel between the source and drain regions through polysilicon inversion, thus connecting the source and drain. However, Figure 9 The semiconductor device structure shown requires controlling the gate voltage of the right-hand portion first, causing the polysilicon corresponding to the right-hand portion to invert and transfer to the polysilicon corresponding to the left-hand portion, thereby forming a conductive channel between the source region 4051 and the drain region 4052. Figure 3 The semiconductor structure shown (a typical MOS transistor) makes it more difficult to form a conductive channel, meaning it is more difficult to turn on the conductive channel. Therefore, its subthreshold swing is increased, which in turn increases the range of gate voltage variation, making the compensation space larger, thereby achieving the goal of improving the display effect of the final product.

[0143] Figure 10 This is a top view schematic diagram of a semiconductor device structure provided in an embodiment of this application. Figure 3 , Figure 10 for Figure 8 Top view, including Figure 8 The substrate is not shown in the figure. The first doped region 4061 and the second doped region 4062 (the two CTs in the figure) of the second active region 406 are connected to the gate.

[0144] In one alternative embodiment, such as Figure 10 As shown, the first conductive structure 403 and the second conductive structure 404 have the same dimensions in the first direction. Specifically, when the first conductive structure 403 and the second conductive structure 404 are a single integral structure, its top view can be shown as follows. Figure 10 The image shows a rectangle.

[0145] In this embodiment, the first active region 405 includes not only the source region 4051 and the drain region 4052, but also a region covered by the first conductive structure that ultimately forms a conductive channel. The second active region includes not only the first doped region 4061 and the second doped region 4062, but also a region covered by the second conductive structure.

[0146] Optionally, the first active region 405 and the second active region 406 have the same size in the second direction, that is, the first active region 405 and the second active region 406 can be regions of the same size, or the first active region 405 and the second active region 406 have the same span in the second direction.

[0147] Thus, the area of ​​the first overlapping region corresponding to the first active region 405 and the first conductive structure 403 is ultimately reduced ( Figure 10 (Illustrated by the dashed circle on the left) The area of ​​the second overlapping region corresponding to the second active region 406 and the second conductive structure 404 ( Figure 11 (Illustrated by the dashed circle on the right) Equal, meaning that when the two active regions and the polysilicon above overlap, the two overlapping areas are equal.

[0148] Figure 4 This is a top view schematic diagram of a semiconductor device structure provided in an embodiment of this application. Figure 12 , Figure 5 To Figure 12 The top view of the semiconductor device structure shown has been slightly modified, including... Figure 8 Substrate not shown in the image.

[0149] In one alternative embodiment, such as Figure 8 As shown, the dimension of the first conductive structure 403 on the first well region 401 in the first direction is larger than the dimension of the second conductive structure 404 on the second well region 402 in the first direction.

[0150] In this embodiment, the first active region 405 includes not only the source region 4051 and the drain region 4052, but also a region covered by the first conductive structure that ultimately forms a conductive channel. The second active region includes not only the first doped region 4061 and the second doped region 4062, but also a region covered by the second conductive structure.

[0151] Optionally, the first active region 405 and the second active region 406 have the same size in the second direction, i.e., the first active region 405 and the second active region 406 can be regions of the same size, or the first active region 405 and the second active region 406 have the same span in the second direction.

[0152] Alternatively, the first active region 405 and the second active region 406 have the same size in the second direction, but have different sizes in the first direction, e.g., the first active region 405 has a larger size in the first direction than the second active region 406.

[0153] As such, ultimately, the first active region 405 and the first conductive structure 403 correspond to a first overlapping area (encircled by the dashed circle on the left in FIG. 4B) having a larger area than a second overlapping area (encircled by the dashed circle on the right in FIG. 4B) corresponding to the second active region 406 and the second conductive structure 404, i.e., the two active regions and the polysilicon above them overlap, and of the two overlapping areas obtained, the first overlapping area corresponding to the first overlapping area is larger than the second overlapping area corresponding to the second overlapping area. Figure 12 Figure 12

[0154] Figure 10-12 is a top view of a semiconductor device structure provided by an embodiment of the present application Figure 10 , Figure 11 is a top view of a semiconductor device structure provided by an embodiment of the present application Figure 12 after a slight adjustment. Figure 3 does not show the substrate.

[0155] In an optional embodiment, as shown in FIG. 4A, the first conductive structure 403 and the second conductive structure 404 have the same size in the first direction. Specifically, when the first conductive structure 403 and the second conductive structure 404 form an integral structure, a top view of the integral structure can be a rectangle as shown in FIG. 4A. Figure 4 Figure 8

[0156] In an embodiment of the present application, the first active region 405 not only includes the source region 4051 and the drain region 4052, but also includes a region covered by the first conductive structure and ultimately forming a conductive channel. The second active region not only includes the first doped region 4061 and the second doped region 4062, but also includes a region covered by the second conductive structure.

[0157] Optionally, the first active region 405 has a smaller size in the second direction than the second active region 406, i.e., the first active region 405 has a smaller span than the second active region 406.

[0158] ​​​​Thus, the area of the first overlapping region corresponding to the first active region 405 and the first conductive structure 403 is smaller than the area of the second overlapping region corresponding to the second active region 406 and the second conductive structure 404. Figure 4 The dotted circle on the left side of FIG. 4A circumscribes the first active region 405 and the first conductive structure 403, and the dotted circle on the right side of FIG. 4A circumscribes the second active region 406 and the second conductive structure 404. That is, the two active regions and the polysilicon above them overlap, and the first overlapping region corresponding to the first active region 405 and the first conductive structure 403 is smaller than the second overlapping region corresponding to the second active region 406 and the second conductive structure 404. Figure 8

[0159] From the above Figure 13 The relationship between the two overlapping regions can be summarized as follows: Figure 6 In the case of FIG. 4A, the area of the first overlapping region is equal to the area of the second overlapping region. Figure 13 In the case of FIG. 4B, the area of the first overlapping region is greater than the area of the second overlapping region. Figure 10 In the case of FIG. 4C, the area of the first overlapping region is smaller than the area of the second overlapping region.

[0160] In combination with the above analysis, the semiconductor device structure in the embodiments of the present application is more difficult to form a conductive channel relative to Figure 8 the semiconductor structure shown in FIG. 1 (a common MOS tube). That is, it is more difficult to open a conductive channel. The voltage applied to the gate corresponding to the second active region causes the polysilicon in the second overlapping region to form an inversion layer. The smaller the area of the second overlapping region, the weaker the ability to conduct to the first overlapping region. The larger the area of the second overlapping region, the stronger the ability to conduct to the first overlapping region. It is more difficult to conduct from a small overlapping region to a large overlapping region, so it is more difficult to open a conductive channel. That is, the subthreshold swing is improved more. It is easier to conduct from a large overlapping region to a small overlapping region, so it is easier to open a conductive channel, and the subthreshold swing is improved less.

[0161] Therefore, the greater the ratio of the first overlapping region to the second overlapping region, the more difficult it is to open a conductive channel, that is, the more the subthreshold swing of the semiconductor device is improved. Thus, when the ratio of the first overlapping region to the second overlapping region is determined, the size of the first conductive structure 403 and the second conductive structure 404 in the first direction or the second direction can be flexibly adjusted, and the size of the first active region 405 and the second active region 406 in the first direction and the second direction can also be flexibly adjusted. Furthermore, in some embodiments that meet the conditions, the polysilicon material can be saved, or the area of the first active region and the second active region can be controlled and the material can be saved, so that the semiconductor device structure is miniaturized.

[0162] In the embodiments of the present application, Figure 4 the semiconductor device structure shown in FIG. 4A and Figure 13 ​One important difference in the semiconductor device structure shown is that... Figure 13 In the second active region 406, the first doped region forms the gate, while... Figure 13 In this design, the first doped region 4061 and the second doped region 4062 form the gate. However, since the fourth doped ion implanted in the second active region 406 and the second doped ion implanted in the second well region 402 are examples of the same conductivity type (N-type impurities), this does not hinder the realization of the function. However, compared to forming the gate with the first doped region of the second active region 406, when the gate is formed with the first doped region 4061 and the second doped region 4062, the electrons accumulated in the region of the second well region 402 near the oxide layer are more uniform, which makes the large number of holes accumulated on the side of the second conductive structure 404 (such as polysilicon) near the oxide layer more uniformly distributed. On the other hand, forming the gate with the first doped region of the second active region 406 is more material-efficient than forming the gate with the first doped region 4061 and the second doped region 4062.

[0163] Figure 13 This is a top view schematic diagram of a semiconductor device structure provided in an embodiment of this application. Figure 3 , Figure 9 To Figure 14 The top view of the semiconductor device structure shown has been slightly modified, including... Figure 14 The substrate is not shown in the image. The substrate includes a first well region 401 and a second well region 402. The first well region 401 is implanted with a first dopant ion, and the second well region 402 is implanted with a second dopant ion. The first dopant ion and the second dopant ion have different conductivity types.

[0164] A first conductive structure 403 is located on the first well region 401, and a second conductive structure 404 is located on the second well 402, wherein the first conductive structure 403 and the second conductive structure 404 are connected. In an optional embodiment, the first conductive structure 403 and the second conductive structure 404 can be two parts (e.g., Figure 4 (as shown), but these two parts are connected together by contact. In another alternative embodiment, the first conductive structure 403 and the second conductive structure 404 can be as shown... ​ As shown, it is an integral structure.

[0165] A first active region 405 is located within the first well region 401. The first active region 405 includes a source region 4051 and a drain region 4052. Both source region 4051 and drain region 4052 are implanted with third doped ions, and the source region 4051 and drain region 4052 are located on opposite sides of the first conductive structure. Optionally, source region 4051 can be connected as a source, and drain region 4052 can be connected as a drain.

[0166] The second active region 406 is located in the second well region 402, and includes a first doped region 4061 and a second doped region 4062, which are located on two sides of the second conductive structure respectively. Both the first doped region 4061 and the second doped region 4062 are implanted with fourth doped ions, and the first doped region 4061 forms a gate or the second doped region 4062 forms a gate.

[0167] In an optional embodiment, as shown in FIG. 4B, the size of the first conductive structure 403 on the first well region 401 in the first direction is greater than the size of the second conductive structure 404 on the second well region 402 in the first direction. ​

[0168] In the embodiments of the present application, the first active region 405 includes not only the source region 4051 and the drain region 4052, but also a region covered by the first conductive structure and finally forming a conductive channel. The second active region 406 includes not only the first doped region 4061 and the second doped region 4062, but also a region covered by the second conductive structure.

[0169] Optionally, the size of the first active region 405 and the second active region 406 in the second direction is the same, i.e., the span of the first active region 405 and the second active region 406 in the second direction is the same.

[0170] Alternatively, the size of the first active region 405 and the second active region 406 in the second direction is the same, but the size in the first direction is different, for example, the size of the first active region 405 in the first direction is greater than the size of the second active region 406 in the first direction.

[0171] Therefore, the area of the first overlapping region corresponding to the first active region 405 and the first conductive structure 403 (as shown by the dashed circle on the left side of FIG. 4A) is greater than the area of the second overlapping region corresponding to the second active region 406 and the second conductive structure 404 (as shown by the dashed circle on the right side of FIG. 4A), i.e., the two active regions and the polysilicon above them overlap, and the first overlapping area corresponding to the first overlapping region is greater than the second overlapping area corresponding to the second overlapping region. ​ ​ In some possible embodiments, the concentration of the first doped ions implanted in the first well region is a first concentration, the concentration of the third doped ions implanted in the source region and the drain region is a second concentration, the second concentration is greater than the first concentration. The concentration of the second doped ions implanted in the second well region is a third concentration, the concentration of the fourth doped ions implanted in the first doped region is a fourth concentration, and the fourth concentration is greater than the third concentration.

[0172] In some possible embodiments, the concentration of the first doped ions implanted in the first well region is a first concentration, the concentration of the third doped ions implanted in the source region and the drain region is a second concentration, the second concentration is greater than the first concentration. The concentration of the second doped ions implanted in the second well region is a third concentration, the concentration of the fourth doped ions implanted in the first doped region is a fourth concentration, and the fourth concentration is greater than the third concentration.

[0173] ​​In this embodiment, based on improving the subthreshold swing through semiconductor device structure adjustment, the subthreshold swing can be further improved or decreased by adjusting the concentration of dopant ions. However, the final subthreshold swing is greater than that of the original MOS transistor ( ​ The subthreshold swing (as shown).

[0174] For example, in ​ In the semiconductor device structure shown, the subthreshold swing can be further adjusted by regulating the concentration of the second doped ion in the second well region 402. Optionally, the concentration of the second doped ion in the second well region 402 can be increased from a third concentration to a fifth concentration. A higher concentration means an increase in the number of electrons in the second well region 402. The fifth concentration is greater than the third concentration and less than the fourth concentration.

[0175] When the gate voltage is greater than 0, more electrons accumulate in the region of the second well region 402 near the oxide layer, resulting in more holes accumulating on the side of the second conductive structure 404 (e.g., polycrystalline silicon) near the oxide layer. Since the first conductive structure 403 and the second conductive structure 404 are connected or are a single unit, more holes also accumulate on the side of the first conductive structure 403 near the oxide layer. At this time, the large number of holes accumulated on the side of the first conductive structure 403 near the oxide layer repels the holes in the first well region 401 near the oxide layer and attracts electrons, making it easier to form a conductive channel and connect the source and drain. When the drain is connected to a voltage source, a subthreshold leakage current is generated, thereby lighting up the OLED through the source. Because it is easier to open the conductive channel, the subthreshold swing is reduced.

[0176] Similarly, when the concentration of the second doped ions in the second well region 402 is reduced from the first concentration to the sixth concentration, when the gate voltage is greater than 0, fewer electrons will accumulate in the region of the second well region 402 near the oxide layer. This results in fewer holes accumulating on the side of the second conductive structure 404 (e.g., polysilicon) near the oxide layer. Since the first conductive structure 403 and the second conductive structure 404 are connected or are a single unit, even fewer holes will accumulate on the side of the first conductive structure 403 near the oxide layer. At this time, the large number of holes accumulated on the side of the first conductive structure 403 near the oxide layer repels the holes in the first well region 401 near the oxide layer and attracts electrons, making it more difficult to form a conductive channel and conduct the source and drain. When the drain is connected to a voltage source, a subthreshold leakage current will be generated, thereby lighting up the OLED through the source. Since it is more difficult to open the conductive channel, the subthreshold swing will increase.

[0177] Optionally, the sixth concentration is lower than the second concentration.

[0178] Therefore, on the basis of improving the sub-threshold swing through the semiconductor device structure, if the concentration of the second doping ions of the second well region 402 is further improved, the sub-threshold swing will be reduced, and vice versa.

[0179] ​ FIG. 1 is a schematic diagram of a forming method of a semiconductor device structure based on an OLED display according to an exemplary embodiment. It should be noted that the present specification provides method operation steps as described in the embodiments or flowcharts, but more or fewer operation steps can be included based on conventional or non-inventive labor. The order of steps listed in the embodiments is only one of the many step execution orders, and does not represent the only execution order. In actual system or product execution, the method order shown in the embodiments or the accompanying drawings can be executed in sequence or in parallel (for example, in a parallel processor or multi-thread processing environment). Specifically, as shown in ​ The flowchart includes at least the following steps S1401-S1403:

[0180] In step S1401, a substrate is provided.

[0181] In step S1403, a first well region and a second well region are formed in the substrate; the first well region is implanted with first doping ions, and the second well region is implanted with second doping ions; the first doping ions and the second doping ions are of different conductive types.

[0182] In an optional embodiment, the first doping ions in the first well region are of a first concentration, and the second doping ions in the second well region are of a third concentration; the first concentration can be equal to the third concentration, or the first concentration can not be equal to the third concentration.

[0183] In step S1405, a first conduction structure and a second conduction structure are formed on the first well region and the second well region; the first conduction structure and the second conduction structure are connected.

[0184] In an optional embodiment, the first conduction structure and the second conduction structure can be two parts, but the two parts are connected together. In another optional embodiment, the first conduction structure 403 and the second conduction structure 404 can be an integral structure, that is, when formed, they are formed together as an integral structure.

[0185] Optionally, the first conduction structure and the second conduction structure are metal or polysilicon. When the first conduction structure and the second conduction structure are an integral structure, the first conduction structure and the second conduction structure can be an entire metal structure or an entire polysilicon structure.

[0186] In step S1407, a first active region is formed in the first well region; the first active region comprises a source region and a drain region; the source region and the drain region are implanted with third doping ions; the source region and the drain region are respectively located at two sides of the first conduction structure.

[0187] In an alternative embodiment, the source region can be connected as a source, and the drain region can be connected as a drain.

[0188] Optionally, the third doping ions implanted in the source region and the drain region have a second concentration, and the second concentration is greater than the first concentration.

[0189] In step S1409, a second active region is formed in the second well region; the second active region comprises a first doped region, the first doped region is implanted with fourth doping ions, and the first doped region forms a gate; wherein the second doping ions, the third doping ions and the fourth doping ions have the same conductivity type.

[0190] In an alternative embodiment, the second active region comprises a first doped region and a second doped region, the first doped region and the second doped region are both implanted with fourth doping ions, and are respectively located at two sides of the second conduction structure. Optionally, the first doped region and the second doped region can form a gate.

[0191] In an alternative embodiment, the ion concentration of the second well region implanted with the second doping ions is a fifth concentration, and the fifth concentration is greater than the third concentration.

[0192] In the embodiments of the present application, the process (including materials, temperature, thickness, etc.) of forming the semiconductor device structure based on OLED display can refer to the process of forming CMOS tubes in the prior art, which will not be described here.

[0193] In another alternative embodiment, ​ The left part of the semiconductor device structure shown is existing, and therefore, the left part of the semiconductor device structure can be provided, and on this basis, the right part of the structure is formed.

[0194] It should be noted that the method and structure embodiments provided in the above embodiments belong to the same concept, and the specific implementation process is described in the structure embodiments, which will not be described here.

[0195] Correspondingly, the embodiments of the present application also provide a display device, which comprises the semiconductor device structure described above, and further comprises a light emitting device connected with the semiconductor device structure.

[0196] Correspondingly, the embodiments of the present application also provide an electronic device, which comprises the semiconductor device structure described above.

[0197] The electronic device described in the embodiments of the present application can be any electronic product or device such as a smart phone, a desktop computer, a tablet computer, a notebook computer, a digital assistant, an augmented reality (AR) / virtual reality (VR) device, a smart voice interaction device, a smart home appliance, a smart wearable device, a vehicle-mounted terminal device, or the like, and can also be any intermediate product including the above-mentioned memory device.

[0198] It should be noted that the above-mentioned sequence of the embodiments of the present application is only for description, and does not represent the advantages and disadvantages of the embodiments. The above-mentioned embodiments of the present application are described. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims can be performed in an order different from that in the embodiments and still achieve the desired result. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or sequential order shown to achieve the desired result. In some embodiments, multi-task processing and parallel processing are possible or advantageous.

[0199] Each of the embodiments in the present specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other. Each embodiment focuses on the difference from other embodiments. In particular, for the device embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the part of the method embodiments.

[0200] A person of ordinary skill in the art can understand that all or part of the steps of the above-mentioned embodiments can be completed by hardware, or by program instructing relevant hardware, and the program can be stored in a computer readable storage medium, which can be a read-only memory, a magnetic disk or an optical disk, etc.

[0201] The above-mentioned is only the preferred embodiment of the present application, and does not limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A semiconductor device structure based on OLED display, characterized in that, Comprising: a substrate; the substrate comprising a first well region and a second well region; the first well region being implanted with first doping ions, the second well region being implanted with second doping ions; the first doping ions and the second doping ions being of different conductivity types; a first conduction structure on the first well region and a second conduction structure on the second well region; the first conduction structure and the second conduction structure being connected; a first active region in the first well region; the first active region comprising a source region and a drain region; the source region and the drain region being implanted with third doping ions; the source region and the drain region being located on two sides of the first conduction structure respectively; a second active region in the second well region; the second active region comprising a first doped region, the first doped region being implanted with fourth doping ions, the first doped region forming a gate; the second doping ions, the third doping ions and the fourth doping ions being of the same conductivity type.

2. The OLED display based semiconductor device structure of claim 1, wherein, the second active region further comprising a second doped region; the second doped region being implanted with the fourth doping ions; the first doped region and the second doped region being located on two sides of the second conduction structure respectively; the first doped region and the second doped region forming a gate.

3. The OLED display-based semiconductor device structure according to claim 2, wherein: the first conduction structure and the second conduction structure have the same size in a first direction; the first active region and the second active region have the same size in a second direction; an area of a first overlapping region corresponding to the first active region and the first conduction structure is equal to an area of a second overlapping region corresponding to the second active region and the second conduction structure.

4. The OLED display-based semiconductor device structure according to claim 2, wherein: the first conduction structure has a size in a first direction that is greater than a size of the second conduction structure in the first direction; the first active region and the second active region have the same size in a second direction; an area of a first overlapping region corresponding to the first active region and the first conduction structure is greater than an area of a second overlapping region corresponding to the second active region and the second conduction structure.

5. The OLED display-based semiconductor device structure according to claim 2, wherein: the first conduction structure and the second conduction structure have the same size in a first direction; the first active region has a size in a second direction that is less than a size of the second active region in the second direction; an area of a first overlapping region corresponding to the first active region and the first conduction structure is less than an area of a second overlapping region corresponding to the second active region and the second conduction structure.

6. The OLED display based semiconductor device structure of claim 1, wherein, the second active region further comprising a second doped region; the second doped region being implanted with the fourth doping ions; the first doped region and the second doped region being located on two sides of the second conduction structure respectively; the first doped region forming a gate; the first conduction structure has a size in a first direction that is greater than a size of the second conduction structure in the first direction; The first active region and the second active region have the same size in a second direction; An area of a first overlapping region corresponding to the first active region and the first conductive structure is greater than an area of a second overlapping region corresponding to the second active region and the second conductive structure.

7. The OLED display based semiconductor device structure of claim 1, wherein: The first dopant ions implanted in the first well region have a first concentration; The third dopant ions implanted in the source region and the drain region have a second concentration; The second concentration is greater than the first concentration; The second dopant ions implanted in the second well region have a third concentration; The fourth dopant ions implanted in the first dopant region have a fourth concentration; The fourth concentration is greater than the third concentration.

8. The OLED display based semiconductor device structure of claim 7, wherein: The second dopant ions implanted in the second well region have a fifth concentration; The fifth concentration is greater than the third concentration, and the fifth concentration is less than the fourth concentration.

9. The OLED display based semiconductor device structure according to any of claims 1-8, wherein, The first conductive structure and the second conductive structure are polysilicon.

10. The OLED display based semiconductor device structure of claim 9, wherein, The first conductive structure and the second conductive structure are an integral structure.

11. A method for forming a semiconductor device structure based on an OLED display, characterized by, The method comprises: providing a substrate; forming a first well region and a second well region in the substrate; the first well region is implanted with first dopant ions, and the second well region is implanted with second dopant ions; the first dopant ions and the second dopant ions have different conductive types; forming a first conductive structure and a second conductive structure on the first well region and the second well region; the first conductive structure and the second conductive structure are connected; forming a first active region in the first well region; the first active region comprises a source region and a drain region; the source region and the drain region are implanted with third dopant ions; the source region and the drain region are respectively located on two sides of the first conductive structure; forming a second active region in the second well region; the second active region comprises a first dopant region, and the first dopant region is implanted with fourth dopant ions; the first dopant region forms a gate electrode; The second dopant ions, the third dopant ions, and the fourth dopant ions have the same conductive type.

12. The method of forming a semiconductor device structure of claim 11, wherein, The second active region further comprises a second dopant region; the second dopant region is implanted with the fourth dopant ions; The first dopant region and the second dopant region are respectively located on two sides of the second conductive structure; the first dopant region and the second dopant region form a gate electrode.

13. A display device, characterized by The display device comprises the OLED display based semiconductor device structure according to any one of claims 1 to 10.

14. An electronic device, comprising: The electronic device comprises the OLED display based semiconductor device structure according to any one of claims 1 to 10.

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