Work cycle correction method and work cycle correction device
Through the working cycle correction method and device, the DC voltage of the data signal is detected and the working cycle of the clock signal is adjusted, which solves the problem of distortion of the clock signal working cycle and improves the data reading efficiency.
Patent Information
- Application Number
- CN202311319945.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-09-27
- Filing Date
- 2023-10-12
- Publication Date
- 2025-03-28
AI Technical Summary
In high-speed applications, distortion of the operating cycle of the clock signal will cause the effective window of the output data to become smaller, which will affect the efficiency of data reading.
Through a working cycle correction method and device, the DC voltage of the data signal generated by multiple data pads is detected by using a working cycle adjuster, detection circuit, comparator and control logic, and the working cycle of the clock signal is adjusted according to the comparison results to correct the skew of the clock signal.
Effectively correct the skew of the clock signal, improve the efficiency of data reading, and ensure that the effective window of output data remains in an ideal state.
Smart Images
Figure CN119718004A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a calibration method and a device, and in particular to a duty cycle calibration method and a duty cycle calibration device. Background Art
[0002] During the transmission process, the clock signal is often affected by external instruments, external packaging and internal clock paths, which causes the duty cycle to be distorted, which will affect the size of the effective window of the output data. In high-speed applications, it is necessary to minimize the duty cycle distortion to avoid poor efficiency in reading data.
[0003] Figure 1 This is a diagram showing the relationship between the read enable (RE) clock signal and the data signal when reading data in the traditional way. Figure 1 , the duty cycle of the read enable signal RE1 is an ideal 50%, that is, the length of the logic high and the length of the logic low are the same, so the data signal IDQ×1 read by the read enable signal RE1 has an effective window of 50%. The duty cycle of the read enable signal RE2 becomes 60% to 40%, that is, the length of the logic high is greater than the length of the logic low, so the data signal IDQ×2 read by the read enable signal RE2 has an effective window of only 40%, which will make the data reading efficiency worse. Similarly, the duty cycle of the read enable signal RE3 becomes 40% to 60%, that is, the length of the logic high is less than the length of the logic low, so the data signal IDQ×3 read by the read enable signal RE3 has an effective window of only 40%, which will also make the data reading efficiency worse. Summary of the invention
[0004] In view of the above content, the present invention provides a duty cycle correction method and a duty cycle correction device, which can correct the skew of the clock signal and improve the data reading efficiency.
[0005] The present invention provides a duty cycle correction device, which includes a duty cycle adjuster, a detection circuit, a comparator and a control logic. The duty cycle adjuster is used to adjust the duty cycle of a clock signal generated by a clock signal generator, and input the adjusted clock signal to multiple data pads of a storage device to generate multiple data signals, wherein the multiple data pads are divided into at least two groups and defined with mutually inverted data patterns. The detection circuit includes multiple detectors respectively coupled to the multiple data pads, used to detect the DC voltage of the data signal generated by the first group of data pads to generate a first average DC voltage, and to detect the DC voltage of the data signal generated by the second group of data pads to generate a second average DC voltage. The comparator is coupled to the detection circuit, used to compare the first average DC voltage and the second average DC voltage, and output a comparison result. The control logic is coupled to the comparator, used to control the duty cycle adjuster to adjust the duty cycle of the clock signal according to the comparison result.
[0006] In one embodiment of the present invention, the duty cycle correction device further includes a switching circuit. The switching circuit includes a plurality of switches respectively coupled to the plurality of detectors, and is used to switch the plurality of switches to connect the output end of the detector coupled to the first group of data pads to the first end of the comparator, and to connect the output end of the detector coupled to the second group of data pads to the second end of the comparator.
[0007] In one embodiment of the present invention, the comparator includes outputting a logic low comparison result when judging that the first average DC voltage is higher than the second average DC voltage, and outputting a logic high comparison result when judging that the first average DC voltage is lower than the second average DC voltage.
[0008] In one embodiment of the present invention, the control logic includes determining whether the comparison result is a logic low, if the comparison result is a logic low, controlling the duty cycle adjuster to reduce the duty cycle of the clock signal, and determining whether the comparison result is converted to a logic high, and when it is determined that the comparison result is not converted to a logic high, repeatedly controlling the duty cycle adjuster to reduce the duty cycle of the clock signal and the comparison until the comparison result is converted to a logic high, and if the comparison result is a logic high, controlling the duty cycle adjuster to extend the duty cycle of the clock signal, and determining whether the comparison result is converted to a logic low, and when it is determined that the comparison result is not converted to a logic low, repeatedly controlling the duty cycle adjuster to extend the duty cycle of the clock signal and the comparison until the comparison result is converted to a logic low.
[0009] The present invention provides a duty cycle correction method, which is suitable for controlling a duty cycle adjuster to correct the duty cycle of a clock signal. The method includes the following steps: using a duty cycle adjuster to adjust the duty cycle of a clock signal generated by a clock signal generator, and inputting the adjusted clock signal to a plurality of data pads of a storage device to generate a plurality of data signals, wherein the plurality of data pads are divided into at least two groups and are defined with mutually inverted data patterns; using a detection circuit including a plurality of detectors respectively coupled to the plurality of data pads, detecting the DC voltage of the data signal generated by the first group of data pads to generate a first average DC voltage, and detecting the DC voltage of the data signal generated by the second group of data pads to generate a second average DC voltage; using a comparator coupled to the detection circuit, comparing the first average DC voltage and the second average DC voltage, and outputting a comparison result; and using a control logic coupled to the comparator, according to the comparison result, controlling the duty cycle adjuster to adjust the duty cycle of the clock signal.
[0010] In one embodiment of the present invention, the duty cycle correction method also includes using a switching circuit of multiple switches respectively coupled to multiple detectors to switch the multiple switches to connect the output end of the detector coupled to the first group of data pads to the first end of the comparator, and to connect the output end of the detector coupled to the second group of the data pads to the second end of the comparator.
[0011] In one embodiment of the present invention, the steps of using a comparator of a coupled detection circuit to compare a first average DC voltage and a second average DC voltage and outputting a comparison result include outputting a logic low comparison result when it is determined that the first average DC voltage is higher than the second average DC voltage; and outputting a logic high comparison result when it is determined that the first average DC voltage is lower than the second average DC voltage.
[0012] In one embodiment of the present invention, the step of controlling the duty cycle adjuster to adjust the duty cycle of the clock signal according to the comparison result by using the control logic coupled to the comparator includes determining whether the comparison result is a logic low, if the comparison result is a logic low, controlling the duty cycle adjuster to reduce the duty cycle of the clock signal, and determining whether the comparison result is converted to a logic high, and when it is determined that the comparison result has not been converted to a logic high, repeatedly controlling the duty cycle adjuster to reduce the duty cycle of the clock signal and comparing until the comparison result is converted to a logic high, and if the comparison result is a logic high, controlling the duty cycle adjuster to extend the duty cycle of the clock signal, and determining whether the comparison result is converted to a logic low, and when it is determined that the comparison result has not been converted to a logic low, repeatedly controlling the duty cycle adjuster to extend the duty cycle of the clock signal and comparing until the comparison result is converted to a logic low.
[0013] In one embodiment of the present invention, the detector includes detecting the lengths of high points and low points of the data signal waveform to calculate the DC voltage.
[0014] In one embodiment of the present invention, the detector comprises a low pass filter or a DC converter.
[0015] In one embodiment of the present invention, the control logic includes a chip external controller or an internal circuit.
[0016] In one embodiment of the present invention, the comparator includes an operational amplifier.
[0017] In one embodiment of the present invention, the number of bits representing the value 0 and the number of bits representing the value 1 in the data pattern are the same.
[0018] In an embodiment of the present invention, the number of the first set of data pads is the same as the number of the second set of data pads.
[0019] In order to make the aforementioned features and advantages of the present invention more comprehensible, embodiments of the present invention are described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] Figure 1 It is a schematic diagram of the relationship between the read enable clock signal and the data signal when reading data in the conventional manner.
[0021] Figure 2 is a schematic diagram of a duty cycle correction device according to an embodiment of the present invention.
[0022] Figure 3 is a flow chart of a duty cycle correction method according to an embodiment of the present invention.
[0023] Figure 4 is a control flow chart of the control logic according to an embodiment of the present invention.
[0024] Figure 5 is a schematic diagram of a duty cycle correction device according to an embodiment of the present invention.
[0025] Description of Reference Numerals
[0026] 10: Clock signal generator
[0027] 20, 50: Duty cycle correction device
[0028] 22, 52: Duty cycle regulator
[0029] 24, 54: Detection circuit
[0030] 26, 58: Comparator
[0031] 28, 60: Control logic
[0032] 56: Switching Circuit
[0033] CLK, CLK': clock signal
[0034] CMPOUT: Comparison result
[0035] D0~D7:Detector
[0036] IDQ0~IDQ7, IDQx1~IDQx3: data signal
[0037] PAD_IO0~PAD_IO7: data pad
[0038] RE1~RE3: Read enable signal
[0039] SW0~SW7:Switch
[0040] S302~S308, S402~S410: Steps
[0041] Vavg1: First average DC voltage
[0042] Vavg2: Second average DC voltage DETAILED DESCRIPTION
[0043] An embodiment of the present invention is to divide two or an even number of data signals into two groups, and define data patterns that are inverted from each other. By using detectors such as low-pass filters and DC converters to detect the average DC voltages of the two groups of data signals and compare them, the duty cycle adjuster can be controlled to adjust the duty cycle of the clock signal based on the comparison results, thereby effectively correcting the skew of the clock signal.
[0044] Figure 2 is a schematic diagram of a duty cycle correction device according to an embodiment of the present invention. Figure 2 The duty cycle correction device 20 of the present embodiment is, for example, configured in a semiconductor product to correct the duty cycle of a clock signal provided to the semiconductor product. The semiconductor product is, for example, a high-capacity, high-performance 3D NAND flash, a non-volatile / volatile memory such as a dynamic random access memory (DRAM), or a logic device such as a microcontroller. The clock signal is, for example, a read enable (RE) signal for reading memory data, which is not limited in this article. The duty cycle correction device 20 includes a duty cycle adjuster 22, a detection circuit 24, a comparator 26, and a control logic 28.
[0045] The duty cycle adjuster 22 is used to adjust the duty cycle of the clock signal CLK generated by the clock signal generator 10, and input the adjusted clock signal CLK' into a plurality of data pads PAD_IO0-PAD_IO7 of a storage device to generate a plurality of data signals IDQ0-IDQ7. The storage device is, for example, a random access memory (SRAM), a dynamic random access memory (DRAM), a NAND flash memory, or a NOR flash memory, or a resistive random access memory (ReRAM) with a 2D or 3D structure, which is not limited in this article. In addition, the data pads PAD_IO0-PAD_IO7 are divided into at least two groups, and data patterns that are inverted from each other are defined.
[0046] In some embodiments, the data pads PAD_IO0-PAD_IO7 can be divided into two groups, and the number of data pads in the first group of data pads and the second group of data pads is the same, and data patterns that are inverted from each other are defined. In the above data patterns, the number of bits representing the value 0 is the same as the number of bits representing the value 1. For example, when the data pattern of the first group of data pads is 101010, the data pattern of the second group of data pads is inverted 010101, and the number of 0s and 1s in the above data patterns is both 3.
[0047] The detection circuit 24 includes a plurality of detectors D0-D7, which are respectively coupled to the data pads PAD_IO0-PAD_IO7 to detect the length of the high and low points of the waveforms of the data signals IDQ0-IDQ7 to calculate the DC voltage. The detectors D0-D7 are, for example, low-pass filters or DC converters, which are not limited in this article.
[0048] In this embodiment, the output terminals of the detectors D0-D3 are connected to the negative input terminal of the comparator 26, and the output terminals of the detectors D4-D7 are connected to the positive input terminal of the comparator 26. The DC voltages obtained by the detectors D0-D3 respectively detecting the data signals IDQ0-IDQ3 will become the first average DC voltage Vavg1 input to the negative input terminal of the comparator 26, and the DC voltages obtained by the detectors D4-D7 respectively detecting the data signals IDQ4-IDQ7 will become the second average DC voltage Vavg2 input to the positive input terminal of the comparator 26. In other embodiments, the detectors D0-D7 in the detection circuit 24 can be divided into two groups or even groups in other ways, which is not limited in this article.
[0049] The comparator 26 is, for example, an operational amplifier, and is configured to compare the first average DC voltage Vavg1 with the second average DC voltage Vavg2 to generate a comparison result CMPOUT, and output the comparison result CMPOUT to the control logic 28 .
[0050] The control logic 28 is used to control the duty cycle adjuster 22 to adjust the duty cycle of the clock signal CLK according to the comparison result CMPOUT output by the comparator 26 to correct the skew of the clock signal CLK. In this embodiment, the control logic 28 is an internal circuit of the semiconductor product, but in other embodiments, the control logic 28 can also be a chip external controller located outside the semiconductor device, which is not limited in this article.
[0051] In detail, Figure 3 is a flow chart of a working cycle correction method according to an embodiment of the present invention. Figure 2 and Figure 3 The following will describe the detailed steps of the duty cycle correction method of this embodiment with reference to various circuits and components of the duty cycle correction device 20.
[0052] In step S302, the duty cycle adjuster 22 is used to adjust the duty cycle of the clock signal CLK generated by the clock signal generator 10, and the adjusted clock signal CLK' is input to a plurality of data pads PAD_IO0-PAD_IO7 of the storage device to generate a plurality of data signals IDQ0-IDQ7. The data pads PAD_IO0-PAD_IO7 are divided into at least two groups and are defined with mutually inverted data patterns.
[0053] In step S304 , the detection circuit 24 detects the DC voltage of the data signal generated by the first set of data pads to generate a first average DC voltage Vavg1 , and detects the DC voltage of the data signal generated by the second set of data pads to generate a second average DC voltage Vavg2 .
[0054] In step S306, the comparator 26 is used to compare the first average DC voltage Vavg1 and the second average DC voltage Vavg2, and outputs a comparison result CMPOUT. If the first average DC voltage Vavg1 is greater than the second average DC voltage Vavg2, the comparator 26 outputs a logic low comparison result CMPOUT; otherwise, if the first average DC voltage Vavg1 is less than the second average DC voltage Vavg2, the comparator 26 outputs a logic high comparison result CMPOUT.
[0055] In step S308 , the control logic 28 controls the duty cycle adjuster 22 to adjust the duty cycle of the clock signal CLK according to the comparison result CMPOUT.
[0056] The control logic 28 will continue to control the duty cycle adjuster 22 to adjust the duty cycle of the clock signal CLK until the comparison result CMPOUT of the comparator 26 changes from logic low to logic high, or changes from logic high to logic low.
[0057] In detail, Figure 4 is a control flow chart of the control logic according to an embodiment of the present invention. Figure 2 and Figure 4 The control process of this embodiment will be described below with reference to various circuits and components of the duty cycle correction device 20.
[0058] In step S402 , the control logic 28 determines whether the comparison result CMPOUT of the comparator 26 is 0 (logic low).
[0059] If so, in step S404, the control logic 28 controls the duty cycle adjuster 22 to reduce the duty cycle of the clock signal CLK, and in step S406, determines whether the comparison result CMPOUT of the comparator 26 changes to 1 (logic high).
[0060] If it does not change to 1, it returns to step S404, and the control logic 28 controls the duty cycle adjuster 22 to reduce the duty cycle of the clock signal CLK again, and repeats steps S404 and S406 until the comparison result CMPOUT changes to 1, and the adjustment of the duty cycle of the clock signal CLK is completed.
[0061] In step S402, if the control logic 28 determines that the comparison result CMPOUT of the comparator 26 is not 0 (logic high), then in step S408, the control logic 28 controls the duty cycle adjuster 22 to extend the duty cycle of the clock signal CLK, and in step S410, determines whether the comparison result CMPOUT of the comparator 26 changes to 0 (logic low).
[0062] If it does not change to 0, it returns to step S408, and the control logic 28 controls the duty cycle adjuster 22 to extend the duty cycle of the clock signal CLK again, and repeats steps S408 and S410 until the comparison result CMPOUT changes to 0, thereby completing the adjustment of the duty cycle of the clock signal CLK.
[0063] By using the above method, the duty cycle of the clock signal CLK can be gradually adjusted back to 50%, thereby improving the data reading efficiency.
[0064] Figure 5 is a schematic diagram of a duty cycle correction device according to an embodiment of the present invention. Figure 5The duty cycle correction device 50 of this embodiment is, for example, configured in a semiconductor product to correct the duty cycle of a clock signal provided to the semiconductor product. The semiconductor product is, for example, a high-capacity, high-performance 3D NAND flash memory, a non-volatile / volatile memory such as a dynamic random access memory, or a logic device such as a microcontroller, and the clock signal is, for example, a read enable signal for reading memory data, which is not limited in this article.
[0065] The duty cycle correction device 50 includes a duty cycle adjuster 52, a detection circuit 54, a switching circuit 56, a comparator 58, and a control logic 60. The duty cycle adjuster 52, the detection circuit 54, the comparator 58, and the control logic 60 are the same or similar to the duty cycle adjuster 22, the detection circuit 24, the comparator 26, and the control logic 28 of the aforementioned embodiment, so their detailed functions are not repeated here.
[0066] Different from the above-mentioned embodiment, in this embodiment, the duty cycle correction device 50 additionally includes a switching circuit 56. The switching circuit 56 includes a plurality of switches SW0-SW7 respectively coupled to the detectors D0-D7. The switching circuit 56 connects the output end of the detector coupled to the first group of data pads to the first end of the comparator 58, and connects the output end of the detector coupled to the second group of data pads to the second end of the comparator 58 by switching the switches SW0-SW7.
[0067] In some embodiments, the switching circuit 56 can connect the output terminals of the detectors D0-D3 to the negative input terminal of the comparator 58 and connect the output terminals of the detectors D4-D7 to the positive input terminal of the comparator 58 by switching the switches SW0-SW7. The DC voltages obtained by the detectors D0-D3 respectively detecting the data signals IDQ0-IDQ3 are connected through the switches SW0-SW3 to become the first average DC voltage Vavg1 input to the negative input terminal of the comparator 58, while the DC voltages obtained by the detectors D4-D7 respectively detecting the data signals IDQ4-IDQ7 are connected through the switches SW4-SW7 to become the second average DC voltage Vavg2 input to the positive input terminal of the comparator 58.
[0068] The comparator 58 compares the first average DC voltage Vavg1 with the second average DC voltage Vavg2 to generate a comparison result CMPOUT, and outputs the comparison result CMPOUT to the control logic 60. The control logic 60 controls the duty cycle adjuster 52 to adjust the duty cycle of the clock signal CLK according to the comparison result CMPOUT output by the comparator 58 to correct the skew of the clock signal CLK.
[0069] In summary, according to an embodiment of the present invention, a duty cycle correction method and a duty cycle correction device are proposed, which divide the data path (DQ path) into two groups and define data patterns that are inverted from each other, so that the skew of the clock signal can be detected by comparing the average DC voltages of the two groups of data signals. In addition, by feeding back the comparison result to the control logic, the control logic controls the duty cycle adjuster accordingly, so that the duty cycle of the clock signal can be appropriately adjusted, thereby improving the data reading efficiency.
[0070] Although the present invention has been disclosed by the above-described embodiments, the embodiments are not intended to limit the present invention. It will be apparent to those skilled in the art that various modifications and changes may be made to the structure of the present invention without departing from the scope or spirit of the present invention. Therefore, the protection scope of the present invention falls within the scope of the appended claims.
Claims
1. A duty cycle correction device, characterized in that: include: a duty cycle adjuster, which adjusts the duty cycle of the clock signal generated by the clock signal generator, and inputs the adjusted clock signal to a plurality of data pads of the storage device to generate a plurality of data signals, wherein the plurality of data pads are divided into at least two groups and are defined with data patterns that are inverted from each other; A detection circuit, comprising a plurality of detectors respectively coupled to the plurality of data pads, detecting a DC voltage of the data signal generated by a first group of the data pads to generate a first average DC voltage, and detecting a DC voltage of the data signal generated by a second group of the data pads to generate a second average DC voltage; a comparator, coupled to the detection circuit, comparing the first average DC voltage and the second average DC voltage, and outputting a comparison result; as well as The control logic is coupled to the comparator, and controls the duty cycle adjuster to adjust the duty cycle of the clock signal according to the comparison result.
2. The duty cycle correction device according to claim 1, further comprising: The switching circuit includes a plurality of switches respectively coupled to the plurality of detectors, and switches the plurality of switches to connect the output ends of the detectors coupled to the first group of the data pads to the first end of the comparator, and connect the output ends of the detectors coupled to the second group of the data pads to the second end of the comparator.
3. The duty cycle correction device according to claim 1, wherein the comparator comprises: When it is determined that the first average DC voltage is higher than the second average DC voltage, outputting the comparison result of logic low; as well as When it is determined that the first average DC voltage is lower than the second average DC voltage, the comparison result of logic high is output.
4. The duty cycle correction device according to claim 3, wherein the control logic comprises: determining whether the comparison result is a logic low; If the comparison result is logic low, control the duty cycle adjuster to reduce the duty cycle of the clock signal, and determine whether the comparison result is changed to logic high, and when it is determined that the comparison result is not changed to logic high, repeatedly control the duty cycle adjuster to reduce the duty cycle of the clock signal and compare until the comparison result is changed to logic high; as well as If the comparison result is logic high, the duty cycle adjuster is controlled to extend the duty cycle of the clock signal, and it is determined whether the comparison result changes to logic low. When it is determined that the comparison result has not changed to logic low, the duty cycle adjuster is repeatedly controlled to extend the duty cycle of the clock signal and compare until the comparison result changes to logic low.
5. The duty cycle correction device according to claim 1, wherein the detector comprises detecting the lengths of the high point and the low point of the data signal waveform to calculate the DC voltage.
6. The duty cycle correction device according to claim 1, wherein the detector comprises a low pass filter or a DC converter.
7. The duty cycle correction device according to claim 1, wherein the comparator comprises an operational amplifier.
8. The duty cycle correction device of claim 1, wherein the control logic comprises a chip external controller or an internal circuit. 9 . The duty cycle correction device according to claim 1 , wherein the number of bits representing the value 0 and the number of bits representing the value 1 in the data pattern are the same. 10 . The duty cycle correction device according to claim 1 , wherein the number of the first group of data pads is the same as the number of the second group of data pads.
11. A duty cycle correction method, adapted to control a duty cycle adjuster to correct the duty cycle of a clock signal, the method comprising the following steps: The duty cycle adjuster is used to adjust the duty cycle of the clock signal generated by the clock signal generator, and the adjusted clock signal is input to a plurality of data pads of a storage device to generate a plurality of data signals, wherein the plurality of data pads are divided into at least two groups and are defined with data patterns that are inverted from each other; Using a detection circuit including a plurality of detectors respectively coupled to the plurality of data pads, detecting the DC voltage of the data signal generated by a first group of the data pads to generate a first average DC voltage, and detecting the DC voltage of the data signal generated by a second group of the data pads to generate a second average DC voltage; using a comparator coupled to the detection circuit to compare the first average DC voltage and the second average DC voltage, and output a comparison result; as well as The duty cycle adjuster is controlled to adjust the duty cycle of the clock signal according to the comparison result by using a control logic coupled to the comparator.
12. The duty cycle correction method according to claim 11, further comprising: Using a switching circuit including a plurality of switches respectively coupled to the plurality of detectors, the plurality of switches are switched to connect the output ends of the detectors coupled to the first group of the data pads to the first end of the comparator, and to connect the output ends of the detectors coupled to the second group of the data pads to the second end of the comparator.
13. The duty cycle correction method according to claim 11, wherein the step of using the comparator coupled to the detection circuit to compare the first average DC voltage and the second average DC voltage and outputting the comparison result comprises: When it is determined that the first average DC voltage is higher than the second average DC voltage, outputting the comparison result of logic low; as well as When it is determined that the first average DC voltage is lower than the second average DC voltage, the comparison result of logic high is output.
14. The duty cycle correction method according to claim 13, wherein the step of using the control logic coupled to the comparator to control the duty cycle adjuster to adjust the duty cycle of the clock signal according to the comparison result comprises: determining whether the comparison result is a logic low; If the comparison result is logic low, control the duty cycle adjuster to reduce the duty cycle of the clock signal, and determine whether the comparison result is changed to logic high, and when it is determined that the comparison result is not changed to logic high, repeatedly control the duty cycle adjuster to reduce the duty cycle of the clock signal and compare until the comparison result is changed to logic high; as well as If the comparison result is logic high, the duty cycle adjuster is controlled to extend the duty cycle of the clock signal, and it is determined whether the comparison result changes to logic low. When it is determined that the comparison result has not changed to logic low, the duty cycle adjuster is repeatedly controlled to extend the duty cycle of the clock signal and compare until the comparison result changes to logic low.
15. The duty cycle correction method according to claim 11, wherein the detector comprises detecting the length of the high point and the low point of the data signal waveform to calculate the DC voltage.
16. The duty cycle correction method of claim 11, wherein the detector comprises a low pass filter or a DC converter.
17. The duty cycle correction method of claim 11, wherein the control logic comprises a chip external controller or an internal circuit.
18. The duty cycle correction method of claim 11, wherein the comparator comprises an operational amplifier.
19. The duty cycle correction method according to claim 11, wherein the number of bits representing the value 0 and the number of bits representing the value 1 in the data pattern are the same. 20 . The duty cycle calibration method according to claim 11 , wherein the number of the first group of data pads is the same as the number of the second group of data pads.