Chip physical information acquisition method, device, electronic device and storage medium

Abstract

The present invention discloses a chip physical information acquisition method, device, electronic device and storage medium, which relates to the field of computer technology. The method is applied to a programmable logic integrated circuit, wherein the programmable logic integrated circuit includes a driving finite state machine module and a main device module. The method includes: when the programmable logic integrated circuit meets the information acquisition conditions, the current communication protocol and the current access rule of the target chip are acquired; based on the current communication protocol and the current access rule, the physical information of the target chip is acquired by using the driving finite state machine module and the main device module. Thus, by using the programmable logic integrated circuit as a coprocessor of the operating system, the physical information of the target chip is acquired, which solves the problem that when the operating system is used to directly acquire chip information, the central processing unit usage rate increases and the access speed decreases due to the need to develop non-standard drivers, thereby achieving the technical effect of improving the overall access efficiency.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a method, device, electronic device and storage medium for acquiring physical information of a chip. Background Art

[0002] With the rapid development of information technology, integrated circuits are increasingly used in electronic systems, especially in the fields of national defense, computers, communications, vehicles, and artificial intelligence. As semi-customized application-specific integrated circuits, CPLD (Complex Programmable Logic Device) and FPGA (Field Programmable Gate Array) have gradually become important components in electronic system design due to their advantages such as flexible programming, fast response, and high integration. In network devices such as switches and network cards, CPLD-FPGA is widely used in key links such as data management, equipment control, and system optimization.

[0003] In the related technology, the operating system interacts directly with the underlying chip, and a dedicated driver needs to be designed for each non-standard protocol or specific chip to implement data read and write operations. However, in this method, the interaction process between the operating system and the underlying chip frequently occupies the CPU (Central Processor Unit) resources, which leads to an increase in the CPU usage rate and a decrease in the access speed, which needs to be solved urgently. Summary of the invention

[0004] The present invention provides a chip physical information acquisition method, device, electronic device and storage medium, so as to at least solve the problem that when chip information is directly acquired using an operating system, the central processing unit usage rate increases and the access speed decreases due to the need to develop non-standard drivers, thereby achieving the technical effect of improving the overall access efficiency.

[0005] The present invention provides a method for acquiring chip physical information, the method being applied to a programmable logic integrated circuit, wherein the programmable logic integrated circuit comprises a driving finite state machine module and a main device module, wherein the method comprises:

[0006] Determining whether the programmable logic integrated circuit meets the information acquisition condition;

[0007] If the programmable logic integrated circuit meets the information acquisition condition, then the current communication protocol and current access rule of the target chip are acquired;

[0008] Based on the current communication protocol and the current access rule, the physical information of the target chip is acquired by using the driving finite state machine module and the main device module.

[0009] The present invention also provides a device for acquiring chip physical information, the device is applied to a programmable logic integrated circuit, wherein the programmable logic integrated circuit includes a driving finite state machine module and a main device module, wherein the device includes:

[0010] A judging module, used for judging whether the programmable logic integrated circuit meets the information acquisition condition;

[0011] A first acquisition module, configured to acquire a current communication protocol and a current access rule of a target chip when the programmable logic integrated circuit meets an information acquisition condition;

[0012] The second acquisition module is used to acquire the physical information of the target chip based on the current communication protocol and the current access rule by using the drive finite state machine module and the main device module.

[0013] The present invention also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of any of the above-mentioned chip physical information acquisition methods when executing the computer program.

[0014] The present invention also provides a computer-readable storage medium, in which a computer program is stored, wherein when the computer program is executed by a processor, the steps of any of the above-mentioned chip physical information acquisition methods are implemented.

[0015] The present invention also provides a computer program product, including a computer program, which implements the steps of any of the above-mentioned chip physical information acquisition methods when executed by a processor.

[0016] Through the present invention, when the programmable logic integrated circuit meets the information acquisition conditions, the current communication protocol and current access rules of the target chip are obtained, and based on the current communication protocol and current access rules, the physical information of the target chip is obtained by using the driver finite state machine module and the main device module. Therefore, the problem of increasing the CPU usage and reducing the access speed due to the need to develop non-standard drivers when directly obtaining chip information using the operating system can be solved, achieving the technical effect of improving the overall access efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1A flowchart of a chip physical information acquisition method provided by an embodiment of the present invention;

[0019] Figure 2 A schematic diagram of the principle of a chip physical information acquisition method provided by an embodiment of the present invention;

[0020] Figure 3 A schematic diagram of the principle of obtaining clock chip information by using a programmable logic integrated circuit provided in an embodiment of the present invention;

[0021] Figure 4 A block diagram of a device for acquiring physical information of a chip provided by an embodiment of the present invention;

[0022] Figure 5 A schematic diagram of the structure of an electronic device provided by an embodiment of the present invention.

[0023] Figure numerals: 10 - chip physical information acquisition device, 100 - judgment module, 200 - first acquisition module, 300 - second acquisition module; 501 - memory, 502 - processor, 503 - communication interface. DETAILED DESCRIPTION

[0024] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0025] It should be noted that, in the description of the present invention, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in the present invention are used to distinguish similar objects, and are not used to describe a specific order or sequence.

[0026] In order to enable those skilled in the art to better understand the scheme of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0027] An embodiment of the present invention provides a method for acquiring chip physical information. The method is described in detail in conjunction with the execution flow of the method for acquiring chip physical information.

[0028] Figure 1 It is a flow chart of a method for acquiring chip physical information according to an embodiment of the present invention.

[0029] Before introducing the chip physical information acquisition method proposed in the embodiment of the present invention, the relevant technical background is first introduced.

[0030] In the switch system, the data layer management of the entire switch system is mainly achieved through CPLD-FPGA. This process involves the coordination of multiple hardware devices, including I2C (Inter Integrated Circuit) devices, MDC (Management Data Clock) / MDIO (Management Data Input / Output) devices, SPI (Serial Peripheral Interface) devices, etc. As an important part of the switch, CPLD-FPGA is an important hub for information exchange between the upper system and the underlying devices or devices, and is also an important part of the control of the entire switch system.

[0031] Chips are vital components in computers and electronic devices. Basic information about chips, such as version number, temperature, etc., usually needs to be obtained through specific communication protocols. These protocols include I2C and MDC / MDIO, which are low-speed communication protocols. Since these protocols may be specific to a certain manufacturer (non-standard) or follow specific processes, the operating system (OS) often needs to develop corresponding non-standard drivers when interacting with these underlying chips. This interaction requires the operating system to communicate with the chip frequently, resulting in an increase in CPU usage, while the access speed may be reduced, affecting overall efficiency.

[0032] Based on the above problems, the present invention proposes a method for obtaining chip physical information in real time. With CPLD-FPGA as the coprocessor of the operating system, by designing some basic functional modules and trigger mechanisms, it is possible to obtain the information of peripheral chips according to predetermined steps, or pass the control instructions issued by the operating system to the chip, or execute the specific control process of the chip, thereby realizing precise control of the chip.

[0033] The chip physical information acquisition method proposed in the embodiment of the present invention will be described in detail below.

[0034] For example, Figure 1 As shown, the chip physical information acquisition method is used for a programmable logic integrated circuit, wherein the programmable logic integrated circuit includes a driving finite state machine module and a main device module, wherein the method includes the following steps:

[0035] In step S101, it is determined whether the programmable logic integrated circuit meets the information acquisition condition.

[0036] It is understandable that the programmable logic integrated circuit refers to a CPLD-FPGA combination, and the embodiment of the present invention can use the programmable logic integrated circuit as a coprocessor of the operating system to achieve the process of obtaining physical information of the chip. The information acquisition condition refers to the prerequisite that must be met for the chip to exchange, process or output data with the integrated circuit.

[0037] That is to say, in the process of executing the chip physical information acquisition method, it is necessary to first confirm whether the programmable logic integrated circuit is in a state where information can be acquired.

[0038] For ease of understanding, the following describes in detail how to determine whether a programmable logic integrated circuit meets the information acquisition conditions.

[0039] As a possible implementation method, in some embodiments, determining whether a programmable logic integrated circuit meets the information acquisition condition includes: determining whether the information acquisition of the target chip is triggered by a preset operating system; if the information acquisition of the target chip is not triggered by the preset operating system, then when the programmable logic integrated circuit detects a first trigger instruction, it is determined that the programmable logic integrated circuit meets the information acquisition condition.

[0040] Specifically, it can be determined first whether the information acquisition action of the target chip needs to be triggered by an instruction issued by a preset operating system (i.e., operating system OS). If the information acquisition action of the target chip is not initiated by the preset operating system, then the trigger condition (trigger instruction) can be detected in real time after the programmable logic integrated circuit starts working. When the programmable logic integrated circuit detects the first trigger instruction, it is considered that the programmable logic integrated circuit meets the information acquisition condition and can execute subsequent information acquisition tasks.

[0041] For example, for applications that do not require a preset operating system trigger (that is, the information acquisition action of the target chip is not initiated by the preset operating system), after the device is turned on, after a certain waiting time is met (equivalent to detecting the first trigger instruction), it indicates that the programmable logic integrated circuit has met the information acquisition conditions and can obtain the physical information of the target chip.

[0042] Therefore, by autonomously judging the information acquisition conditions within the programmable logic integrated circuit CPLD-FPGA, it is avoided to develop a special driver for each non-standard protocol or specific chip, reducing the number of interactions between the operating system and the chip, thereby reducing the CPU utilization rate and improving the overall access efficiency.

[0043] Optionally, in some other embodiments, after determining whether the information acquisition of the target chip is triggered by a preset operating system, it further includes: if the information acquisition of the target chip is triggered by a preset operating system, determining whether the programmable logic integrated circuit receives a second trigger instruction issued by the preset operating system; if the programmable logic integrated circuit receives the second trigger instruction issued by the preset operating system, determining that the programmable logic integrated circuit meets the information acquisition condition.

[0044] Specifically, if the information acquisition action of the target chip is initiated by a preset operating system, then subsequently, after the programmable logic integrated circuit starts to work, the trigger condition (trigger instruction) can be detected in real time. When the programmable logic integrated circuit detects the second trigger instruction issued by the preset operating system, it is considered that the programmable logic integrated circuit meets the information acquisition condition and can perform subsequent information acquisition tasks.

[0045] For example, for an application that requires triggering by a preset operating system (i.e., the case where the information acquisition action of the target chip is initiated by a preset operating system), the preset operating system can directly issue a trigger instruction for chip information acquisition (the second trigger instruction). After detecting the second trigger instruction issued by the preset operating system, it indicates that the programmable logic integrated circuit has met the information acquisition condition and can acquire the physical information of the target chip.

[0046] Thus, by autonomously judging the information acquisition condition inside the programmable logic integrated circuit CPLD - FPGA, it is avoided to develop dedicated driver programs for each non - standard protocol or specific chip, reducing the number of interactions between the operating system and the chip, thereby reducing the CPU usage rate and improving the overall access efficiency.

[0047] Further, in some embodiments, determining whether the information acquisition of the target chip is triggered by a preset operating system includes: determining whether the physical information of the target chip is information that meets a preset change condition; if the physical information of the target chip is information that meets the preset change condition, determining that the information acquisition of the target chip is triggered by a preset operating system, otherwise determining that the information acquisition of the target chip is not triggered by a preset operating system.

[0048] Among them, the preset change condition refers to the stability of the physical information of the target chip to be acquired, and the physical information is the basic information, such as the chip version number, temperature, etc.

[0049] Specifically, it is determined whether the information acquisition of the target chip is triggered by a preset operating system, that is, whether the physical information of the target chip is information that meets the preset change conditions. If the physical information to be acquired of the target chip is information that meets the preset change conditions, that is, the physical information is a variable quantity, such as chip temperature, then it can be determined that the information acquisition of the target chip is triggered by the preset operating system; conversely, if the physical information to be acquired of the target chip is not information that meets the preset change conditions, that is, the physical information is unchanged, such as chip version, then it can be determined that the information acquisition of the target chip is not triggered by the preset operating system.

[0050] Thus, by determining whether the physical information of the target chip meets the preset change conditions to decide whether to trigger information acquisition by the operating system, frequent queries of static information (such as chip version numbers) by the operating system can be avoided. Static information usually does not need to be updated in real time, while dynamic information (such as chip temperature) needs to be acquired in a timely manner according to changes. This method can significantly reduce the ineffective calls of the operating system and reduce the CPU usage rate, thereby improving the overall efficiency of the system.

[0051] It should be noted that according to actual needs, for information that does not meet the preset change conditions, such as chip version numbers, it can also be actively triggered by the preset operating system for acquisition, and no specific limitations are set here.

[0052] Thus, for static information, actively triggering acquisition by the operating system when necessary significantly improves the flexibility, reliability, and maintainability of the system.

[0053] In step S102, if the programmable logic integrated circuit meets the information acquisition conditions, the current communication protocol and current access rules of the target chip are acquired.

[0054] That is to say, when the programmable logic integrated circuit meets specific information acquisition conditions, in order to ensure the smooth progress of the subsequent chip information acquisition process, first, the communication protocol currently used by the target chip can be identified and confirmed. The communication protocol is the basis for data exchange and communication between chips. Secondly, the rules for currently accessing the target chip also need to be mastered, and these access rules involve specific access processes. By acquiring these key information, effective and secure access to the target chip can be ensured.

[0055] In step S103, based on the current communication protocol and current access rules, the physical information of the target chip is acquired by using the drive finite state machine module and the master device module.

[0056] It can be understood that the current communication protocol refers to the communication standard between the programmable logic integrated circuit and the target chip, and the current access rule refers to the access process when the programmable logic integrated circuit acquires the physical information of the target chip.

[0057] That is, after obtaining the current communication protocol and the current access rules, the physical information of the target chip can be obtained based on the current communication protocol and the current access rules using the driver finite state machine module and the main device module in the programmable logic integrated circuit.

[0058] Next, it is explained in detail how to obtain the physical information of the target chip using the driver finite state machine module and the main device module based on the current communication protocol and the current access rules.

[0059] As a possible implementation method, in some embodiments, based on the current communication protocol and the current access rules, the physical information of the target chip is obtained by using the driving finite state machine module and the main device module, including: using the driving finite state machine module to generate a read operation instruction; based on the read operation instruction, controlling the main device module to enter the read operation state to execute the read operation process on the target chip to obtain the physical information of the target chip; receiving the physical information of the target chip read by the main device module through the driving finite state machine module.

[0060] Specifically, by driving the finite state machine module, an instruction for a read operation can be generated; based on the read operation instruction, the main device module can be controlled to enter the corresponding read operation state, and then a series of read operation processes can be performed on the target chip, the purpose of which is to obtain the physical information of the target chip; after completing the read operation, the physical information read by the main device module from the target chip can be received by driving the finite state machine module again. Among them, the driving finite state machine module can realize the acquisition process of different chips according to actual requirements, which mainly controls the frequency bit (determines the chip operation rate), address bit (specifies the memory location or register of the operation), read and write indication bit (indicates whether the chip is performing a read or write operation) and operation enable bit (a signal that starts or activates an operation on the chip) of the main device module, thereby realizing precise control of the information acquisition operation of the target chip.

[0061] Therefore, by utilizing the driving finite state machine module to control the main device module to execute the action of acquiring physical information on the target chip, an efficient, flexible and reliable method for acquiring physical information is realized.

[0062] Furthermore, in some embodiments, after obtaining the physical information of the target chip by driving the finite state machine module and the main device module based on the current communication protocol and the current access rules, it also includes: determining whether the programmable logic integrated circuit has completed the read operation process; if the programmable logic integrated circuit has completed the read operation process, an interrupt instruction is generated, and the interrupt instruction is sent to the preset operating system.

[0063] Specifically, for situations that require a preset operating system trigger (i.e., the information acquisition action of the target chip is initiated by the preset operating system), when the programmable logic integrated circuit CPLD-FPGA completes the specified information reading operation, it can inform the preset operating system by generating an interrupt instruction.

[0064] Therefore, by informing the operating system of the completion of the information reading operation through the interrupt mechanism, the response speed, real-time performance and reliability of the system can be significantly improved, while reducing the burden on the operating system and the overall power consumption of the system.

[0065] Furthermore, in some embodiments, before using the driving finite state machine module and the main device module to obtain the physical information of the target chip based on the current communication protocol and the current access rules, it also includes: configuring the main device module based on the current communication protocol; and / or configuring the driving finite state machine module based on the current access rules.

[0066] It is understandable that if Figure 2 As shown, in order to realize the acquisition action of obtaining the physical information of the target chip by using the programmable logic integrated circuit, the embodiment of the present invention can configure the finite state machine module and the main device module in the programmable logic integrated circuit according to the requirements of the target chip, that is, configure the main device module according to the current communication protocol, and configure the driver finite state machine module according to the current access rule. Among them, the communication connection between the preset operating system and the programmable logic integrated circuit can be realized through different interface protocols, and these interfaces can include PCIe (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard), I2C (Inter-Integrated Circuit, interconnected integrated circuit) or LPC (Low Pin Count, low pin count interface); the communication pin connection between the programmable logic integrated circuit and the target chip can also be realized through different interface protocols, and these interfaces can be I2C, LPC or SPI (Serial Peripheral Interface, serial peripheral interface).

[0067] For example, for some chips, although they identify themselves as having interfaces such as I2C or MDC / MDIO, these interfaces may not fully comply with standard specifications. This means that if you want these chips to work properly, you need to use programmable logic integrated circuits to design dedicated driver finite state machine modules and master device modules. These custom modules can adapt and control interfaces according to the requirements of specific chips to ensure that the chips can correctly transmit and communicate data.

[0068] It should be noted that due to the reprogrammable characteristics of programmable logic integrated circuits, both the main device module and the driver finite state machine module can be configured and developed according to specific application requirements.

[0069] Therefore, by encapsulating complex communication protocols and access rules in programmable logic integrated circuits, the operating system only needs to interact with the programmable logic integrated circuits through simple interfaces without having to deeply understand the underlying hardware details. This design simplifies the system architecture and reduces the difficulty of development.

[0070] As a possible implementation method, in some embodiments, configuring the master device module based on the current communication protocol includes: determining the interface signal of the master device module based on the current communication protocol, wherein the interface signal includes at least one of a clock signal, a master device data output signal, a master device data input signal, a chip select signal and a reset signal.

[0071] Among them, the clock signal is responsible for synchronizing various operations during the data transmission process; the master device data output signal allows the master device to send data to other devices or systems; the master device data input signal enables the master device to receive data from other devices or systems; the chip select signal is used to select and activate a specific chip; the reset signal is used to reset the device or module to the initial state.

[0072] Specifically, in the process of building and configuring the master device module, the interface signals of the master device module can be accurately defined and set according to the current communication protocol. These interface signals are key elements for the master device module to exchange data and communicate with the outside world. Specifically, these interface signals include but are not limited to: clock signal, master device data output signal, master device data input signal, chip select signal and reset signal. These signals can ensure that the master device module can correctly communicate and exchange data with the driver finite state machine module or the target chip.

[0073] Therefore, configuring the main device module based on the current communication protocol can significantly improve the communication accuracy, flexibility, efficiency and stability of the system. This design method not only simplifies system design and development, but also reduces system power consumption and enhances system security.

[0074] As a possible implementation method, in other embodiments, the driving finite state machine module is configured based on the current access rules, including: determining multiple states of the driving finite state machine module based on the current access rules, wherein the multiple states include defining at least two of an idle state, a waiting trigger condition state, an initialization state, a read state, a write state, and an error handling state; determining the transition logic between the multiple states to control the driving finite state machine module to complete the transition between the multiple states based on the transition logic.

[0075] Among them, the idle state means that the driver finite state machine module is not currently performing any operation and is in a standby state. The waiting for trigger condition state means that in this state, the driver finite state machine module waits for specific conditions or instructions to occur in order to perform subsequent operations. The initialization state means that the driver finite state machine module may enter the initialization state before starting to work and perform necessary preparations, such as setting initial parameters or configurations. The read state refers to the driver finite state machine module performing the operation of reading data. The write state corresponds to the read state and refers to the process of the driver finite state machine module writing data. The error handling state means that when the driver finite state machine module encounters an error or abnormal situation, it can execute an error recovery or reporting mechanism.

[0076] Specifically, in the process of building and configuring the driver finite state machine module, the specific access steps and operation procedures can be determined according to the current access rules, and the multiple states contained in the driver finite state machine module can be further determined based on the access steps and operation procedures. These states include but are not limited to defining an idle state, a state waiting for a trigger condition, an initialization state, a read state, a write state, and an error handling state, which include at least two of the above states. Then, the conversion logic between these states is determined, and the driver finite state machine module can be controlled by the conversion logic to convert between different states according to specific access rules, thereby efficiently acquiring the physical information of the target chip.

[0077] Therefore, based on the current access rule configuration, the driver finite state machine module is configured and multiple states and their transition logic are defined. By adjusting the states and transition logic of the driver finite state machine module, the system can quickly adapt to new target chips and access rules without large-scale modifications to the hardware architecture, thereby improving the flexibility and adaptability of the system.

[0078] Furthermore, in some embodiments, before determining whether the programmable logic integrated circuit meets the information acquisition conditions, it also includes: configuring the register of the programmable logic integrated circuit to enable driving the finite state machine module through the register when the programmable logic integrated circuit receives a second trigger instruction issued by a preset operating system.

[0079] That is to say, the embodiment of the present invention can also configure a slave device module inside the programmable logic integrated circuit, which allows the preset operating system to pre-set a series of registers. For situations where the preset operating system needs to be triggered, when the programmable logic integrated circuit receives a second trigger instruction issued by the preset operating system, these registers can be used to control the startup of the driving finite state machine module.

[0080] Therefore, by indirectly controlling the driving finite state machine module through register configuration and trigger instructions, there is no need for the operating system to directly manage complex communication details, which can greatly reduce the CPU usage and allow the CPU to focus on other key tasks, thereby improving the overall efficiency of the system.

[0081] Furthermore, in some embodiments, before using the driving finite state machine module and the main device module to acquire the physical information of the target chip, it also includes: determining an acquisition cycle for acquiring the physical information of the target chip, and based on the acquisition cycle, using the driving finite state machine module and the main device module to acquire the physical information of the target chip.

[0082] It is understandable that before using the driver finite state machine module and the main device module to obtain the physical information of the target chip, an acquisition cycle can be determined, and the acquisition cycle can be set according to actual needs, that is, the acquisition process of the physical information of the target chip can be triggered once in a life cycle, or the acquisition process of the physical information of the target chip can be periodically triggered according to the set cycle. For example, some scenarios may only need to obtain the physical information of the target chip (such as the version number) once when the device is started, while other scenarios may require regular monitoring of the status of the target chip (such as temperature or voltage, etc.).

[0083] Therefore, the periodic trigger mechanism can ensure that the system can obtain the physical information of the target chip in a timely manner, which is especially important for application scenarios that require real-time monitoring (such as temperature monitoring, equipment status monitoring, etc.); at the same time, by reasonably setting the acquisition cycle, the system can avoid user waiting due to untimely data updates, thereby providing a smoother and more real-time interactive experience.

[0084] In addition, in some embodiments, it also includes: determining whether the programmable logic integrated circuit has received a write operation instruction from the target chip; if the programmable logic integrated circuit has received a write operation instruction from the target chip, based on the current communication protocol and the current access rules, utilizing the driving finite state machine module and the master device module to execute the write operation process on the target.

[0085] It should be noted that the programmable logic integrated circuit provided by the embodiment of the present invention can not only obtain the physical information of the target chip, but also realize the control operation on the target chip. That is, when the programmable logic integrated circuit receives the write operation instruction for the target chip, it can execute the write operation process for the target chip (that is, execute a specific control process for the target chip) by driving the collaborative work of the finite state machine module and the main device module according to the current communication protocol and the current access rules.

[0086] Thus, by driving the collaborative work of the finite state machine module and the master device module, the control operations of the target chip can be dynamically adjusted according to different communication protocols and access rules, realizing the control of the target chip. This flexibility enables the system to adapt to a variety of target chips and application scenarios.

[0087] To facilitate the further understanding of the chip physical information acquisition method proposed in the embodiments of the present invention by those skilled in the art, the following further elaboration is made in combination with specific embodiments.

[0088] As Figure 3 shown, Figure 3 The schematic diagram of the principle for obtaining the clock chip AU5329 by using the programmable logic integrated circuit in the chip physical information acquisition method proposed in the embodiments of the present invention is as follows:

[0089] Step 1, select Page0, and the corresponding command is to write 0 to the 0XFF register of this device.

[0090] That is to say, use the programmable logic integrated circuit to write 0 to the 0XFF register of the clock chip to select Page0. This step is part of the initialization process and is used to set the chip to a specific configuration page for subsequent read and write operations.

[0091] Step 2, enable the clock-related registers, and the corresponding command is to write 0X02 to both the 0XE0 register and the 0XE1 register of this device.

[0092] That is to say, use the programmable logic integrated circuit to write 0X02 to the 0XE0 register and the 0XE1 register of the clock chip to enable the relevant clock registers. This step is to activate or configure the registers responsible for the clock function in the clock chip.

[0093] Step 3, wait for the command and the chip to finish execution.

[0094] That is to say, after writing the enable command, the programmable logic integrated circuit needs to wait for a period of time to ensure that the chip has completed the processing and execution of these commands.

[0095] Step 4, select Page1, and the corresponding command is to write 0X01 to the 0XFF register of this device.

[0096] That is to say, use the programmable logic integrated circuit to write 0X01 to the 0XFF register to switch to Page1. This step is to access another configuration page of the chip, usually used to read the version information or other specific data of the chip.

[0097] Step 5, read the version number, and the corresponding command is to read the last four bits from the 0X12 register of this device.

[0098] That is to say, the programmable logic integrated circuit is used to read the last four bits from the 0X12 register to obtain the version number of the clock chip. This step is to communicate directly with the chip through the programmable logic integrated circuit, and the operating system directly obtains the version information stored inside the chip by reading the register.

[0099] Therefore, in the entire process of acquiring the physical information of the target chip or controlling the target chip, the operating system only needs to enable the module and receive the data read by the programmable logic integrated circuit. The signal waveform when communicating with the target chip can be generated and driven by the programmable logic integrated circuit, which greatly reduces the utilization rate of the operating system and improves the system access efficiency.

[0100] According to the chip physical information acquisition method proposed in the embodiment of the present invention, the current communication protocol and current access rules of the target chip are acquired when the programmable logic integrated circuit meets the information acquisition conditions, and based on the current communication protocol and current access rules, the physical information of the target chip is acquired by using the driver finite state machine module and the main device module. Therefore, the problem of increasing the CPU usage and reducing the access speed due to the need to develop non-standard drivers when directly acquiring chip information using the operating system can be solved, thereby achieving the technical effect of improving the overall access efficiency.

[0101] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method.

[0102] An embodiment of the present invention further provides a device for acquiring chip physical information.

[0103] Figure 4 It is a block diagram of a device for acquiring chip physical information according to an embodiment of the present invention.

[0104] like Figure 4 As shown, the chip physical information acquisition device 10 is applied to a programmable logic integrated circuit, wherein the programmable logic integrated circuit includes a driving finite state machine module and a main device module, wherein the chip physical information acquisition device 10 includes: a judgment module 100, a first acquisition module 200 and a second acquisition module 300.

[0105] The judging module 100 is used to judge whether the programmable logic integrated circuit meets the information acquisition condition;

[0106] The first acquisition module 200 is used to acquire the current communication protocol and current access rule of the target chip when the programmable logic integrated circuit meets the information acquisition condition;

[0107] The second acquisition module 300 is used to acquire physical information of the target chip based on the current communication protocol and the current access rule by using the driving finite state machine module and the main device module.

[0108] Furthermore, in some embodiments, the second acquisition module 300 is specifically configured to:

[0109] Generate a read operation instruction using a driver finite state machine module;

[0110] Based on the read operation instruction, the main device module is controlled to enter the read operation state to execute the read operation process on the target chip to obtain the physical information of the target chip;

[0111] The physical information of the target chip read by the main device module is received by the driving finite state machine module.

[0112] Further, in some embodiments, after obtaining the physical information of the target chip by using the driver finite state machine module and the master device module based on the current communication protocol and the current access rule, the second obtaining module 300 is further used to:

[0113] Determining whether the programmable logic integrated circuit has completed the read operation process;

[0114] If the programmable logic integrated circuit completes the read operation process, an interrupt instruction is generated and sent to the preset operating system.

[0115] Further, in some embodiments, before the driver finite state machine module and the master device module are used to acquire the physical information of the target chip based on the current communication protocol and the current access rule, the second acquisition module 300 further includes:

[0116] A first configuration unit, configured to configure a main device module based on a current communication protocol;

[0117] And / or, a second configuration unit, configured to drive the finite state machine module based on the current access rule configuration.

[0118] Further, in some embodiments, the first configuration unit is specifically configured to:

[0119] An interface signal of the master device module is determined based on the current communication protocol, wherein the interface signal includes at least one of a clock signal, a master device data output signal, a master device data input signal, a chip select signal, and a reset signal.

[0120] Furthermore, in some embodiments, the second configuration unit is specifically configured to:

[0121] Determine a plurality of states of the driving finite state machine module based on the current access rule, wherein the plurality of states include defining at least two of an idle state, a waiting trigger condition state, an initialization state, a read state, a write state, and an error handling state;

[0122] The conversion logic between the multiple states is determined to control the finite state machine module to complete the conversion between the multiple states based on the conversion logic.

[0123] Furthermore, in some embodiments, the determination module 100 includes:

[0124] A judging unit, used to judge whether the acquisition of information of the target chip is triggered by a preset operating system;

[0125] The determination unit is used to determine that the programmable logic integrated circuit meets the information acquisition condition when the programmable logic integrated circuit detects the first trigger instruction when the information acquisition of the target chip is not triggered by the preset operating system.

[0126] Furthermore, in some embodiments, after determining whether the acquisition of information of the target chip is triggered by a preset operating system, the determination unit is further configured to:

[0127] In the case where the information acquisition of the target chip is triggered by the preset operating system, determining whether the programmable logic integrated circuit receives a second trigger instruction issued by the preset operating system;

[0128] When the programmable logic integrated circuit receives the second trigger instruction issued by the preset operating system, it is determined that the programmable logic integrated circuit meets the information acquisition condition.

[0129] Furthermore, in some embodiments, the judging unit is specifically configured to:

[0130] Determining whether the physical information of the target chip satisfies a preset change condition;

[0131] If the physical information of the target chip is information that meets the preset change condition, it is determined that the information acquisition of the target chip is triggered by the preset operating system, otherwise it is determined that the information acquisition of the target chip is not triggered by the preset operating system.

[0132] Furthermore, in some embodiments, before determining whether the programmable logic integrated circuit meets the information acquisition condition, the determination module 100 is further configured to:

[0133] The register of the programmable logic integrated circuit is configured so that when the programmable logic integrated circuit receives a second trigger instruction issued by a preset operating system, the finite state machine module is enabled and driven through the register.

[0134] Furthermore, in some embodiments, before using the driving finite state machine module and the main device module to acquire the physical information of the target chip, the second acquisition module 300 is further used to:

[0135] An acquisition cycle for acquiring the physical information of the target chip is determined, so as to acquire the physical information of the target chip by using a driving finite state machine module and a main device module based on the acquisition cycle.

[0136] Furthermore, in some embodiments, the chip physical information acquisition device 10 is further used for:

[0137] Determining whether the programmable logic integrated circuit receives a write operation instruction from the target chip;

[0138] When the programmable logic integrated circuit receives a write operation instruction from a target chip, based on the current communication protocol and the current access rule, the drive finite state machine module and the master device module are used to execute the write operation process on the target.

[0139] For the description of the features in the embodiment corresponding to the chip physical information acquisition device, reference can be made to the relevant description of the embodiment corresponding to the chip physical information acquisition method, which will not be repeated here.

[0140] According to the chip physical information acquisition device proposed in the embodiment of the present invention, the current communication protocol and current access rules of the target chip are acquired when the programmable logic integrated circuit meets the information acquisition conditions, and based on the current communication protocol and current access rules, the physical information of the target chip is acquired by using the driver finite state machine module and the main device module. Therefore, the problem of increasing the CPU usage and reducing the access speed due to the need to develop non-standard drivers when directly acquiring chip information using the operating system can be solved, thereby achieving the technical effect of improving the overall access efficiency.

[0141] Figure 5 A schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. The electronic device may include:

[0142] A memory 501 , a processor 502 , and a computer program stored in the memory 501 and executable on the processor 502 .

[0143] When the processor 502 executes the program, the steps in any of the above chip physical information acquisition method embodiments are implemented.

[0144] Furthermore, the electronic device further comprises:

[0145] The communication interface 503 is used for communication between the memory 501 and the processor 502 .

[0146] The memory 501 is used to store computer programs that can be executed on the processor 502 .

[0147] The memory 501 may include a high-speed RAM (Random Access Memory) memory, and may also include a non-volatile memory, such as at least one disk memory.

[0148] If the memory 501, the processor 502 and the communication interface 503 are implemented independently, the communication interface 503, the memory 501 and the processor 502 can be connected to each other through a bus and communicate with each other. The bus can be an ISA (Industry Standard Architecture) bus, a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 5 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0149] Optionally, in a specific implementation, if the memory 501, the processor 502 and the communication interface 503 are integrated on a chip, the memory 501, the processor 502 and the communication interface 503 can communicate with each other through an internal interface.

[0150] The processor 502 may be a CPU (Central Processing Unit), or an ASIC (Application Specific Integrated Circuit), or one or more integrated circuits configured to implement the embodiments of the present invention.

[0151] An embodiment of the present invention further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above-mentioned chip physical information acquisition method embodiments when running.

[0152] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory, a mobile hard disk, a magnetic disk, or an optical disk.

[0153] An embodiment of the present invention further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in any of the above chip physical information acquisition method embodiments are implemented.

[0154] An embodiment of the present invention also provides another computer program product, including a non-volatile computer-readable storage medium, the non-volatile computer-readable storage medium storing a computer program, and when the computer program is executed by a processor, the steps in any of the above-mentioned chip physical information acquisition method embodiments are implemented.

[0155] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0156] The above is a detailed introduction to a chip physical information acquisition method provided by the present invention. This article uses specific examples to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. It should be pointed out that for ordinary technicians in this technical field, without departing from the principle of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

Claims

1. A method for obtaining physical information of a chip, characterized in that: The method is applied to a programmable logic integrated circuit, wherein the programmable logic integrated circuit includes a driving finite state machine module and a master device module, wherein the method includes: Determining whether the programmable logic integrated circuit meets the information acquisition condition; If the programmable logic integrated circuit meets the information acquisition condition, then the current communication protocol and current access rule of the target chip are acquired; Based on the current communication protocol and the current access rule, the physical information of the target chip is obtained by using the driver finite state machine module and the main device module, further comprising: using the driver finite state machine module to generate a read operation instruction, based on the read operation instruction, controlling the main device module to enter a read operation state, so as to perform a read operation process on the target chip to obtain the physical information of the target chip, and receiving the physical information of the target chip read by the main device module through the driver finite state machine module; The information acquisition condition is that the programmable logic integrated circuit detects a first trigger instruction or receives a second trigger instruction issued by a preset operating system.

2. The chip physical information acquisition method according to claim 1, characterized in that: After acquiring the physical information of the target chip by using the driving finite state machine module and the main device module based on the current communication protocol and the current access rule, the method further includes: Determining whether the programmable logic integrated circuit completes the read operation process; If the programmable logic integrated circuit completes the read operation process, an interrupt instruction is generated and sent to a preset operating system.

3. The chip physical information acquisition method according to claim 1, characterized in that: Before acquiring the physical information of the target chip by using the driving finite state machine module and the main device module based on the current communication protocol and the current access rule, the method further includes: Configuring the master device module based on the current communication protocol; And / or, configuring the driver finite state machine module based on the current access rule.

4. The chip physical information acquisition method according to claim 3, characterized in that: The configuring the main device module based on the current communication protocol includes: An interface signal of the master device module is determined based on the current communication protocol, wherein the interface signal includes at least one of a clock signal, a master device data output signal, a master device data input signal, a chip select signal, and a reset signal.

5. The chip physical information acquisition method according to claim 3, characterized in that: The configuring the driving finite state machine module based on the current access rule comprises: Determining a plurality of states of the driver finite state machine module based on the current access rule, wherein the plurality of states include defining at least two of an idle state, a trigger condition waiting state, an initialization state, a read state, a write state, and an error handling state; The conversion logic between the multiple states is determined to control the driving finite state machine module to complete the conversion between the multiple states based on the conversion logic.

6. The chip physical information acquisition method according to claim 1, characterized in that: The determining whether the programmable logic integrated circuit meets the information acquisition condition includes: Determining whether the information acquisition of the target chip is triggered by the preset operating system; If the information acquisition of the target chip is not triggered by the preset operating system, when the programmable logic integrated circuit detects the first trigger instruction, it is determined that the programmable logic integrated circuit meets the information acquisition condition.

7. The chip physical information acquisition method according to claim 6, characterized in that: After determining whether the acquisition of the target chip information is triggered by the preset operating system, the method further includes: If the acquisition of the information of the target chip is triggered by the preset operating system, determining whether the programmable logic integrated circuit receives a second trigger instruction issued by the preset operating system; If the programmable logic integrated circuit receives the second trigger instruction issued by the preset operating system, it is determined that the programmable logic integrated circuit meets the information acquisition condition.

8. The chip physical information acquisition method according to claim 6 or 7, characterized in that: The determining whether the acquisition of information of the target chip is triggered by a preset operating system includes: Determining whether the physical information of the target chip satisfies a preset change condition; If the physical information of the target chip is the information satisfying the preset change condition, it is determined that the information acquisition of the target chip is triggered by the preset operating system; otherwise, it is determined that the information acquisition of the target chip is not triggered by the preset operating system.

9. The chip physical information acquisition method according to claim 1, characterized in that: Before determining whether the programmable logic integrated circuit meets the information acquisition condition, the method further includes: The register of the programmable logic integrated circuit is configured so that when the programmable logic integrated circuit receives a second trigger instruction issued by a preset operating system, the driving finite state machine module is enabled through the register.

10. The chip physical information acquisition method according to claim 1, characterized in that: Before using the driving finite state machine module and the main device module to acquire the physical information of the target chip, the method further includes: An acquisition cycle for acquiring the physical information of the target chip is determined, so as to acquire the physical information of the target chip by using the driving finite state machine module and the main device module based on the acquisition cycle.

11. The chip physical information acquisition method according to claim 1, characterized in that: Also includes: Determining whether the programmable logic integrated circuit has received a write operation instruction from the target chip; If the programmable logic integrated circuit receives a write operation instruction from the target chip, the drive finite state machine module and the master device module are used to perform a write operation process on the target based on the current communication protocol and the current access rule.

12. A device for acquiring chip physical information, characterized in that: The device is applied to a programmable logic integrated circuit, wherein the programmable logic integrated circuit includes a driving finite state machine module and a main device module, wherein the device includes: A judging module, used for judging whether the programmable logic integrated circuit meets the information acquisition condition; A first acquisition module, configured to acquire a current communication protocol and a current access rule of a target chip when the programmable logic integrated circuit meets an information acquisition condition; a second acquisition module, used to acquire the physical information of the target chip based on the current communication protocol and the current access rule by using the driver finite state machine module and the main device module, and further used to generate a read operation instruction by using the driver finite state machine module, and control the main device module to enter a read operation state based on the read operation instruction, so as to execute a read operation process on the target chip, obtain the physical information of the target chip, and receive the physical information of the target chip read by the main device module through the driver finite state machine module; The information acquisition condition is that the programmable logic integrated circuit detects a first trigger instruction or receives a second trigger instruction issued by a preset operating system.

13. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, used to implement the steps of the chip physical information acquisition method as described in any one of claims 1 to 11 when executing the computer program.

14. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the step of acquiring chip physical information as described in any one of claims 1 to 11.

15. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the chip physical information acquisition method according to any one of claims 1 to 11 are implemented.

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