Calculation circuit and data calculation method

Abstract

The invention provides an arithmetic circuit with a de-identification architecture, a data arithmetic method, a data processing system and a data de-identification method. The operation circuit comprises an operation array and a de-identification circuit. The operation array performs accumulation operation on the input data to generate accumulated data. The de-identification circuit is coupled to the operation array and has an analog offset error determined based on the analog physical non-replicable function. The de-identification circuit calculates the accumulated data according to the analog offset error to generate de-identification data.

Description

Technical Field

[0001] The present invention relates to a circuit, and more particularly to a computing circuit with a de-identification architecture, a data computing method, a data processing system, and a data de-identification method. Background Art

[0002] Traditional privacy protection methods mainly manage relevant privacy protection through data collection centers. However, traditional privacy protection methods cannot guarantee the security of personal data or important data. In addition, there may often be information security risks of information leakage during data transmission. Therefore, it is particularly important to increase the privacy protection of data collection centers or terminal devices. Summary of the invention

[0003] The present invention provides a computing circuit, a data computing method, a data processing system and a data de-identification method with a de-identification architecture, which simulates a physical unclonable function (PUF) to perform computing in memory, utilizes the sensing drift error that already exists in the computing circuit and cannot be predicted, and applies this error to achieve data de-identification.

[0004] The computing circuit with a de-identification architecture of the present invention includes a computing array and a de-identification circuit. The computing array performs an accumulation operation on input data to generate accumulated data. The de-identification circuit is coupled to the computing array and has an analog offset error determined based on an analog physical non-copyable function. The de-identification circuit operates the accumulated data according to the analog offset error to generate de-identified data.

[0005] The de-identified data operation method of the present invention includes the following steps: performing accumulation operation on input data through an operation array to generate accumulated data; and performing operation on the accumulated data according to an analog offset error through a de-identification circuit to generate de-identified data, wherein the analog offset error is determined based on the analog physical non-copyable function of the de-identification circuit.

[0006] The data processing system of the present invention includes a processing unit, an input unit and an operation circuit. The input unit obtains input data. The operation circuit is coupled to the input unit. The operation circuit includes an operation array and a de-identification circuit. The operation array performs an accumulation operation on the input data to generate accumulated data. The de-identification circuit is coupled to the operation array and has an analog offset error determined based on an analog physical non-copyable function. The de-identification circuit operates the accumulated data according to the analog offset error to generate de-identified data, and outputs the de-identified data to the processing unit.

[0007] The data de-identification method of the present invention includes the following steps: obtaining input data through an input unit; performing accumulation operation on the input data through a calculation array to generate accumulated data; calculating the accumulated data according to an analog offset error through a de-identification circuit to generate de-identified data, wherein the analog offset error is determined based on the analog physical non-replicable function of the de-identification circuit; determining whether the privacy level of the de-identified data is sufficient; when the privacy level of the de-identified data is sufficient, outputting the de-identified data; and when the privacy level of the de-identified data is not sufficient, inputting the de-identified data as another input data into the calculation circuit.

[0008] Based on the above, the computing circuit with a de-identification architecture, the data computing method, the data processing system and the data de-identification method of the present invention can generate de-identified data by using the analog offset error through the de-identification circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a schematic diagram of a computing circuit according to an embodiment of the present invention;

[0010] Figure 2 is a flow chart of a data operation method according to an embodiment of the present invention;

[0011] Figure 3A is a schematic diagram of the architecture of a computing circuit according to an embodiment of the present invention;

[0012] Figure 3B is a schematic diagram of the architecture of a computing circuit according to another embodiment of the present invention;

[0013] Figure 4 is a circuit diagram of a computing circuit according to an embodiment of the present invention;

[0014] Figure 5 is a schematic diagram of the architecture of a de-identification circuit according to an embodiment of the present invention;

[0015] FIG. 6A to FIG. 6C is a circuit diagram of an amplifier circuit of multiple embodiments of the present invention;

[0016] Figure 7 is a schematic diagram of a computing circuit according to another embodiment of the present invention;

[0017] Figure 8 is a schematic diagram of the architecture of a de-identification circuit according to another embodiment of the present invention;

[0018] FIG. 9A to FIG. 9M is a circuit diagram of an amplifier circuit according to another embodiment of the present invention;

[0019] Fig.10 is a schematic diagram of a data computing system according to an embodiment of the present invention;

[0020] Fig.11 is a flow chart of a data de-identification method according to an embodiment of the present invention;

[0021] Fig.12 Schematic diagram of input data and de-identified data according to an embodiment of the present invention.

[0022] Description of Reference Numerals

[0023] 100,300,300',400,700,1100: operation circuit;

[0024] 101,301,301',401,701,1001,1220: input data;

[0025] 102,302_1~302_M,302',402_1,402_2,502_1,502_2,702,802_1,802_2,1002: accumulated data;

[0026] 103,303_1~303_M,303',403,503,703,807,1004,1231~1233: de-identified data;

[0027] 110,310,310',410,510,710,810,1110: operation array;

[0028] 120,320,320',420,520,720,820,1120: de-identification circuit;

[0029] 311_(1,1)~311_(M,N),311_1'~311_P',411_1~411_9: in-memory operation unit;

[0030] 321_1~321_M,321',421,620A~620C,920A~920M: amplifier circuit;

[0031] 521,621A~621C,821,921A~921M: signal conversion circuit;

[0032] 522,622A~622C,822,922A~922M: signal operation circuit;

[0033] 5211,5212,6211A~6211C,6212A~6212C,8211,8212,9211A~9211M,9212A~9212M: signal conversion unit;

[0034] 5213,5214,5221,5222,6213A~6213C,6214A~6214C,6221A~6221C,6222A~6222C,8213,8214,8221,8222,9213A~9213M,9214A~9214M,9221A~9221M,9222A~9222M: de-identification subcircuit;

[0035] 5223,8227:Comparator;

[0036] 602A_1~602C_1, 902A_1~902M_1: first signal;

[0037] 602A_1~602C_2, 902A_2~902M_2: second signal;

[0038] 623A_1, 623A_2, 623B, 623C, 923A_1~923A_4, 923B_1~923B_4, 923C_1, 923C_2, 923D_1~923D_4, 923E_1~923E_4, 923F, 923G, 923H, 923I, 923J, 923K, 923L, 923M: output terminal;

[0039] 624C, 924I~924M: reference current source;

[0040] 704, 804, 806: offset control signal;

[0041] 8223, 8224, 9223A to 9223M, 9224A to 9224M: de-identification offset circuit;

[0042] 8225, 8226, 9225A~9225D, 9225F~9225M, 9226A~9226D, 9226F~9226M: offset control circuit;

[0043] 803,805,903B~903D,903F~903M,904B~904D,904F~904M,1003: obfuscation code;

[0044] 1000: data computing system;

[0045] 1200: input unit;

[0046] 1300: processing unit;

[0047] 1210: image data;

[0048] T1A~T6A, T1B~T6B, T1C~T4C, T1C~T6C, T1D~T8D, T1E~T16E, T1F~T6F, T1G~T6G, T1H~T8H, T1I~T6I, T1J~T6J, T1K~T6K, T1L~T6L, T1M~T10M: transistor;

[0049] BL_1, BL_2: bit lines;

[0050] C1_1~C9_1, C1_2~C9_2: sub-operation circuit;

[0051] S210, S220, S1110-S1160: steps;

[0052] Vc1A~Vc1H, Vc2A~Vc2H: clamping voltage;

[0053] VDD: operating voltage. DETAILED DESCRIPTION

[0054] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0055] Figure 1 FIG. 1 is a schematic diagram of a computing circuit 100 according to an embodiment of the present invention. Figure 1The operation circuit 100 includes an operation array 110 and a de-identification circuit 120. The operation array 110 is coupled to the de-identification circuit 120. In the present embodiment, the operation array 110 may be an in-memory operation array of a memory capable of implementing in-memory operation (Computing in Memory, CIM), and may generate accumulated data 102 according to input data 101. In some embodiments, the above-mentioned memory may be a dynamic random access memory (DRAM), a static random access memory (SRAM), a flash memory (Flash Memory), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FRAM or FeRAM), or a resistive random access memory (ReRAM or RRAM), etc., but the present invention is not limited thereto. In some embodiments, the operation array 110 may be implemented in the form of a complementary in-memory operation architecture. The de-identification circuit 120 may be used to read the accumulated data 102 of the operation array 110 and perform a de-identification operation on the accumulated data 102 to generate de-identified data 103 .

[0056] Figure 2 This is a flow chart of a data calculation method according to an embodiment of the present invention. Figure 1 and Figure 2, the operation circuit 100 may execute the following steps S210 to S220. In the present embodiment, the operation circuit 100 may obtain input data 101. In some embodiments, the input data 101 may be image data, audio data, medical data, personal data or data with privacy, but the present invention is not limited thereto. In step S210, the operation array 110 may perform an accumulation operation on the input data 101 to generate accumulated data 102. In step S220, the de-identification circuit 120 may have an analog offset error determined based on an analog physically unclonable function (PUF), so the de-identification circuit 120 may calculate the accumulated data 102 according to the analog offset error, and de-identify the accumulated data 102 to generate de-identified data 103. In some embodiments, the analog offset error is caused by a process error of at least one transistor in the de-identification circuit 120. In some embodiments, the de-identification circuit 120 may further include an amplifier circuit, which may include at least one transistor. The analog offset error may be specifically generated by a process error of the transistor in the amplifier circuit, but the present invention is not limited thereto.

[0057] In some embodiments, the operation array 110 may include a plurality of in-memory operation units. The plurality of in-memory operation units may be used to receive input data 101 and perform in-memory operations. In some embodiments, the in-memory operations may be logic operations, vector-matrix multiplication, and neural network operations, etc., but the present invention is not limited thereto. In some embodiments, the in-memory operations may be multiplying the input data 101 by the plurality of corresponding weight values ​​through the plurality of in-memory operation units to generate a plurality of operation values, and accumulating the plurality of operation values ​​and outputting them to the de-identification circuit 120, but the present invention is not limited thereto.

[0058] More specifically, Figure 3A FIG. 3 is a schematic diagram of the structure of the computing circuit 300 according to an embodiment of the present invention. Figure 3A , the operation array and the de-identification circuit can achieve the following Figure 3AThe architecture shown in the figure is not limited thereto. In the present embodiment, the operation circuit 300 includes an operation array 310 and a de-identification circuit 320. The operation array 310 may include a plurality of in-memory operation units 311_(1,1) to 311_(M,N), where N and M are both positive integers. The in-memory operation units 311_(1,1) to 311_(M,N) may be arranged in an array to form the operation array 310. The in-memory operation units 311_(1,1) to 311_(M,N) may receive input data 301 and perform in-memory operations respectively to store a plurality of operation results.

[0059] In this embodiment, the de-identification circuit 320 may include a plurality of amplifier circuits 321_1-321_M. The amplifier circuits 321_1-321_M may receive the plurality of accumulated data 302_1-302_M output by the operation array 310, and output a plurality of de-identified data 303_1-303_M. Figure 3A As shown, in some embodiments, each row of in-memory operation units 311_(1,1) to 311_(M,N) can be coupled to an amplifier circuit. Specifically, the amplifier circuit 321_1 can be coupled to the in-memory operation unit 311_(1,N), and can receive the operation result of each in-memory operation unit 311_(1,1) to 311_(1,N), that is, the accumulated accumulated data 302_1. Similarly, the amplifier circuit 321_M can be coupled to the in-memory operation unit 311_(M,N), and can receive the operation result of each in-memory operation unit 311_(M,1) to 311_(M,N), that is, the accumulated accumulated data 302_M.

[0060] In this embodiment, each amplifier circuit 321_1~321_M may include at least one transistor, and the analog offset error of the de-identification circuit 320 includes at least one error coefficient, which is provided by the at least one transistor. The specific implementation of the amplifier circuits 321_1~321_M will be specifically described by the following multiple embodiments.

[0061] Figure 3B FIG. 3 is a schematic diagram of the structure of a computing circuit 300 ′ according to another embodiment of the present invention. Figure 3B , the operation array and the de-identification circuit can also be implemented as follows Figure 3B The architecture shown. In this embodiment, the operation circuit 300' includes an operation array 310' and a de-identification circuit 320'. The operation array 310' may include a plurality of in-memory operation units 311_1' to 311_P', where P is a positive integer. The in-memory operation units 311_1' to 311_P' may be coupled in sequence. The in-memory operation units 311_1' to 311_P' may receive input data 301' and perform in-memory operations respectively to store a plurality of operation results.

[0062] In this embodiment, the de-identification circuit 320' may include an amplifier circuit 321'. The amplifier circuit 321' may receive the accumulated data 302' output by the operation array 310' and output the de-identified data 303'. Figure 3B As shown, in some embodiments, the in-memory operation unit 311_1'-311_P' can be coupled to the amplifier circuit 321'. Specifically, the amplifier circuit 321' can be coupled to the in-memory operation unit 311_P' and can receive the operation result of each in-memory operation unit 311_1'-311_P', that is, the accumulated accumulated data 302'.

[0063] In this embodiment, the amplifier circuit 321' may include at least one transistor, and the analog offset error of the de-identification circuit 320' includes at least one error coefficient, which is provided by the at least one transistor. The specific implementation of the amplifier circuit 321' will be specifically described by the following multiple embodiments.

[0064] Figure 4 FIG. 4 is a circuit diagram of a computing circuit 400 according to an embodiment of the present invention. Figure 4 , the operation array and the de-identification circuit can also realize the following Figure 4 The circuit architecture shown in the figure is not limited thereto. In the present embodiment, the operation circuit 400 includes an operation array 410 and a de-identification circuit 420. The operation array 410 can be implemented in a complementary in-memory operation architecture. The operation array 410 may include in-memory operation units 411_1 to 411_9. The de-identification circuit 420 may include an amplifier circuit 421. The in-memory operation units 411_1 to 411_9 may include a plurality of sub-operation circuits C1_1 to C9_1, C1_2 to C9_2. The sub-operation circuits C1_1 to C9_1 are coupled in series to a first input terminal of the amplifier circuit 421 through a bit line (bit line) BL_1, and the sub-operation circuits C1_2 to C9_2 are coupled in series to a second input terminal of the amplifier circuit 421 through a bit line BL_2.

[0065] In this embodiment, the input data 401 may be binary data, for example: "111111111", and the input data 401 may be first written into a buffer (not shown) of the operation circuit 400. In some embodiments, the sub-operation circuits C1_1 to C9_1, C1_2 to C9_2 may obtain corresponding weight value data through the bit lines BL_1 and BL_2, respectively, and perform calculations based on the corresponding bit data in the input data 401 to store the corresponding operation results. Figure 4As shown, for example, the sub-operation circuits C1_1 ˜ C9_1 can sequentially store bit data “111110000”, and the sub-operation circuits C1_2 ˜ C9_2 can sequentially store bit data “000001111”.

[0066] More specifically, the sub-operation circuits C1_1 to C9_1 can perform cumulative calculations on a plurality of bit data, and output the first cumulative data 402_1 to the first end of the amplifier circuit 421. Similarly, the sub-operation circuits C1_2 to C9_2 can perform cumulative calculations on a plurality of bit data, and output the second cumulative data 402_2 to the second end of the amplifier circuit 421. In some embodiments, the first end and the partial circuits of the second end of the amplifier circuit 421 may include at least one transistor, and the analog offset error of the de-identification circuit 420 may include at least one error coefficient. The error coefficient is provided by the at least one transistor. It is worth noting that in some embodiments, the error coefficient may also be provided by at least one resistor, or a combination thereof, and the present invention is not limited thereto.

[0067] For example, the first end of the amplifier circuit 421 may receive an accumulation result corresponding to the bit data "111110000", for example: the accumulation result is a value of 5 (i.e., =1+1+1+1+1+0+0+0+0), and the second end of the amplifier circuit 421 may receive an accumulation result corresponding to the bit data "000001111", i.e., another accumulation result of a value of 4 (i.e., =0+0+0+0+0+1+1+1+1). In this regard, due to the influence of the corresponding analog offset error, the gain value of the first end of the amplifier circuit 421 may be, for example, 0.8, and the gain value of the second end of the amplifier circuit 421 may be, for example, 1.2. In this way, the first end of the amplifier circuit 421 may generate an input corresponding to a value of 4 (i.e., =5×0.8), and the second end of the amplifier circuit 421 may generate an input corresponding to a value of 4.8 (i.e., =4×1.2). In summary, the output terminal of the amplifier circuit 421 can be equivalent to an output bit value of 0, and the de-identified data 403 with good de-identification effect can be achieved.

[0068] It should be noted that if there is no influence of the analog offset error, the first end of the amplifier circuit 421 can generate an input corresponding to a value of 5, and the second end of the amplifier circuit 421 can generate an input corresponding to a value of 4. Therefore, the output end of the amplifier circuit 421 is equivalent to an output bit value of 1, which means that the result of directly accumulating the input data fails to achieve any de-identification effect. In other words, the amplifier circuit 421 can effectively generate the de-identified data 403 by utilizing the influence of the analog offset error.

[0069] Figure 5 FIG. 5 is a schematic diagram of the structure of the de-identification circuit 520 according to an embodiment of the present invention. Figure 5 , the de-identification circuit can be realized as follows Figure 5 The structure of the de-identification circuit 520 is shown in FIG. In this embodiment, the de-identification circuit 520 may be an amplifier circuit, and includes a signal conversion circuit 521 and a signal operation circuit 522. The signal conversion circuit 521 is coupled to the operation array 510. In this embodiment, the operation array 510 may implement the above-mentioned Figure 4 The complementary in-memory computing architecture described in the embodiment of FIG. 5 is taken as an example. The first input terminal and the second input terminal of the de-identification circuit 520 can be coupled to the computing array 510 and receive the first accumulated data 502_1 and the second accumulated data 502_2.

[0070] In the present embodiment, the signal conversion circuit 521 includes signal conversion units 5211 and 5212. The signal conversion units 5211 and 5212 have de-identification sub-circuits 5213 and 5214, respectively. The de-identification sub-circuit 5213 is coupled to the operation array 510 through the first input terminal of the signal conversion circuit 521, and receives the first accumulated data 502_1. The de-identification sub-circuit 5214 is coupled to the operation array 510 through the second input terminal of the signal conversion circuit 521, and receives the second accumulated data 502_2. In the present embodiment, the signal operation circuit 522 may include de-identification sub-circuits 5221, 5222 and a comparator 5223. The de-identification sub-circuit 5221 is coupled to the signal conversion unit 5211 of the signal conversion circuit 521 and the comparator 5223. The de-identification sub-circuit 5222 is coupled to the signal conversion unit 5112 of the signal conversion circuit 521 and the comparator 5223.

[0071] In some embodiments, the de-identification sub-circuits 5213, 5214, 5221, and 5222 may each include at least one transistor. Figure 5 As shown, for example, the signal conversion circuit 521 and the signal operation circuit 522 may include at least one de-identification sub-circuit.

[0072] For example, the de-identification subcircuits 5213 and 5214 may provide error coefficients "A1" and "A2" for signal conversion (i.e., data operation) through at least one transistor inside. The de-identification subcircuits 5221 and 5222 may provide error coefficients "A3" and "A4" for signal conversion through at least one transistor inside. The analog offset error of this embodiment may include error coefficients "A1" to "A4".

[0073] More specifically, the de-identification sub-circuit 5213 may receive a first signal (e.g., represented by the symbol “I1”) of the first accumulated data 502_1, and output a result of multiplying the first signal by the error coefficient “A1”, i.e., a first conversion signal (i.e., “I1×A1”) to the de-identification sub-circuit 5221. The de-identification sub-circuit 5214 may receive a second signal (represented by the symbol “I2”) of the second accumulated data 502_2, and output a result of multiplying the second signal by the error coefficient “A2”, i.e., a second conversion signal (i.e., “I2×A2”) to the de-identification sub-circuit 5222. Then, the de-identification sub-circuit 5221 and the de-identification sub-circuit 5222 may output conversion results to the comparator 5223 according to the first conversion signal and the second conversion signal, so that the comparator 5223 may generate de-identification data according to the conversion results.

[0074] More specifically, the de-identification sub-circuit 5221 may receive the first conversion signal, and output the result of multiplying the first conversion signal by the error coefficient “A3”, i.e., the third conversion signal (i.e., “I1×A1×A3”) to the comparator 5223. Similarly, the de-identification sub-circuit 5222 may receive the second conversion signal, and output the result of multiplying the second conversion signal by the error coefficient “A4”, i.e., the fourth conversion signal (i.e., “I2×A2×A4”) to the comparator 5223. In summary, the comparator 5223 may output the comparison result of the third conversion signal and the fourth conversion signal (i.e., “(I1×A1×A3)-(I2×A2×A4)”), i.e., the de-identification data 503.

[0075] FIG. 6A to FIG. 6C Schematic diagrams of amplifier circuits 620A, 620B, and 620C according to various embodiments of the present invention. Fig. 6A , the amplifier circuit can be realized as Fig. 6A The circuit architecture of the differential amplifier shown in FIG. 6 is shown. In this embodiment, the amplifier circuit 620A includes a signal conversion circuit 621A and a signal operation circuit 622A. The signal conversion circuit 621A includes a signal conversion unit 6211A and a signal conversion unit 6212A, and the signal conversion units 6211A and 6212A include de-identification sub-circuits 6213A and 6214A. The signal conversion circuit 622A includes a de-identification sub-circuit 6221A and a de-identification sub-circuit 6222A.

[0076] In this embodiment, the de-identification sub-circuits 6213A, 6214A, 6221A, and 6222A may include transistors T1A to T4A. In this embodiment, transistors T1A and T2A are N-type transistors, and transistors T3A and T4A are P-type transistors, but the present invention is not limited thereto and the design may be adjusted according to actual needs.

[0077] In the present embodiment, the first terminal of the transistor T1A is coupled to the second terminal of the transistor T3A and the output terminal 623A_1. The control terminal of the transistor T1A can receive the clamping voltage Vc1A. The second terminal of the transistor T1A receives the first signal 602A_1 of the accumulated data. The first terminal of the transistor T2A is coupled to the second terminal of the transistor T4A and the output terminal 623A_2. The control terminal of the transistor T2A can receive the clamping voltage Vc2A. The second terminal of the transistor T2A receives the second signal 602A_2 of the accumulated data. The first terminal of the transistor T3A is coupled to the operation voltage VDD. The second terminal of the transistor T3A is coupled to the control terminal of the transistor T3A, the first terminal of the transistor T1A, and the output terminal 623A_1. The first terminal of the transistor T4A is coupled to the operation voltage VDD. The second terminal of the transistor T4A is coupled to the control terminal of the transistor T4A, the first terminal of the transistor T2A, and the output terminal 623A_2.

[0078] In some embodiments, the first signal 602A_1 and the second signal 602A_2 may be current signals. In some embodiments, at least one of the transistors T1A-T4A may have different analog offset errors due to process errors, but the invention is not limited thereto.

[0079] In this embodiment, the first signal 602A_1 flows through the transistors T1A and T3A and is converted into a conversion signal with an analog offset error. The conversion signal can be output to the output terminal 623A_1. The second signal 602A_2 flows through the transistors T2A and T4A and is converted into another conversion signal with an analog offset error. The conversion signal can be output to the output terminal 623A_2. In summary, the output terminals 623A_1 and 623A_2 can output a differential signal of the conversion result with an analog offset error to a back-end comparator (for example: Figure 5 comparator 5223) so that the back-end comparator can perform operations to generate de-identified data.

[0080] Please refer to Figure 6B , the amplifier circuit can be realized as Figure 6B The circuit architecture of the current mirror type sense amplifier is shown. In this embodiment, the amplifier circuit 620B includes a signal conversion circuit 621B and a signal operation circuit 622B. The signal conversion circuit 621B includes a signal conversion unit 6211B and a signal conversion unit 6212B, and the signal conversion units 6211B and 6212B include de-identification sub-circuits 6213B and 6214B. The signal conversion circuit 622B includes a de-identification sub-circuit 6221B and a de-identification sub-circuit 6222B.

[0081] In this embodiment, the de-identification sub-circuits 6213B, 6214B, 6221B, and 6222B may include transistors T1B to T4B. In this embodiment, transistors T1B and T2B are N-type transistors, and transistors T3B and T4B are P-type transistors, but the present invention is not limited thereto and the design may be adjusted according to actual needs.

[0082] In the present embodiment, the first end of the transistor T1B is coupled to the second end and the control end of the transistor T3B. The control end of the transistor T1B can receive the clamping voltage Vc1B. The second end of the transistor T1B receives the first signal 602B_1 of the accumulated data. The first end of the transistor T2B is coupled to the second end of the transistor T4B and the output end 623B. The control end of the transistor T2B can receive the clamping voltage Vc2B. The second end of the transistor T2B receives the second signal 602B_2 of the accumulated data. The first end of the transistor T3B is coupled to the operation voltage VDD. The second end of the transistor T3B is coupled to the control end of the transistor T3B and the first end of the transistor T1B. The first end of the transistor T4B is coupled to the operation voltage VDD. The second end of the transistor T4B is coupled to the first end of the transistor T2B and the output end 623B.

[0083] In some embodiments, the first signal 602B_1 and the second signal 602B_2 may be current signals. In some embodiments, at least one of the transistors T1B-T4B may have different analog offset errors due to process errors, but the invention is not limited thereto.

[0084] In this embodiment, the first signal 602B_1 flows through the transistors T1B and T3B and is converted into a conversion signal with an analog offset error. The second signal 602B_2 flows through the transistors T2B and T4B and is converted into another conversion signal with an analog offset error. In summary, the output terminal 623B can output a voltage signal of a conversion result with an analog offset error (i.e., a result after the conversion signal is subtracted from another conversion signal) to a back-end comparator (e.g.: Figure 5 comparator 5223) so that the back-end comparator can perform operations to generate de-identified data.

[0085] Please refer to Figure 6C , the amplifier circuit can be realized as Figure 6CThe circuit architecture of the current mirror sense amplifier is shown. In the present embodiment, the amplifier circuit 620C includes a signal conversion circuit 621C and a signal operation circuit 622C. The signal conversion circuit 621C includes a signal conversion unit 6211C and a signal conversion unit 6212C, and the signal conversion units 6211C and 6212C include de-identification sub-circuits 6213C and 6214C. The signal conversion circuit 622C includes a de-identification sub-circuit 6221C and a de-identification sub-circuit 6222C. The de-identification sub-circuits 6213C, 6214C, 6221C, and 6222C include transistors T1C to T4C.

[0086] The circuit structure of the amplifier circuit 620C can be referred to Figure 6B More specifically, the architecture of the signal operation circuit 622C can refer to Figure 6B The signal operation circuit 622B described above, similar contents will not be repeated here.

[0087] It is worth noting that the control terminal of transistor T1C can receive the first signal 602C_1 of accumulated data. The second terminal of transistor T1C can be coupled to reference current source 624C. The control terminal of transistor T2C can receive the second signal 602C_2 of accumulated data. The second terminal of transistor T2C can be coupled to reference current source 624C.

[0088] In some embodiments, the first signal 602C_1 and the second signal 602C_2 may be voltage signals. In some embodiments, at least one of the transistors T1C-T4C may have different analog offset errors due to process errors, but the invention is not limited thereto.

[0089] In this embodiment, the first signal 602C_1 flows through the transistors T1C and T3C and is converted into a conversion signal with an analog offset error. The second signal 602C_2 flows through the transistors T2C and T4C and is converted into another conversion signal with an analog offset error. Therefore, the output terminal 623C can output a voltage signal of a conversion result with an analog offset error (i.e., a result after the conversion signal is subtracted from another conversion signal) to a back-end comparator (e.g.: Figure 5 comparator 5223) so that the back-end comparator can perform operations to generate de-identified data.

[0090] Figure 7 is a schematic diagram of a computing circuit 700 according to another embodiment of the present invention. Figure 7 The operation circuit 700 includes an operation array 710 and a de-identification circuit 720. The operation array 710 is coupled to the de-identification circuit 720. In this embodiment, the architecture of the operation circuit 700 can refer to Figure 1It is worth noting that the de-identification circuit 720 can be used to read the accumulated data 702 of the operation array 710 and receive the offset control signal 704. The de-identification circuit 720 can perform a de-identification operation on the accumulated data 702 according to the offset control signal 704 to generate the de-identified data 703.

[0091] More specifically, the operation circuit 700 may obtain input data 701. The operation array 710 may perform an accumulation operation on the input data 701 to generate accumulated data 702. Then, the de-identification circuit 720 may receive the offset control signal 704, and operate the accumulated data 702 according to the offset control signal 704 and the analog offset error to generate de-identified data 703. It should be noted that the analog offset error is generated by the process error of at least one transistor in the de-identification circuit 720, but the present invention is not limited thereto.

[0092] In some embodiments, the offset control signal 704 may be used to control at least another transistor in the de-identification circuit 720 to generate an additional analog offset error. Therefore, the de-identification circuit 720 may utilize the analog offset error determined based on the analog physical non-copyable function and the additional analog offset error generated based on the offset control signal 704 to de-identify the accumulated data 702 to generate de-identified data 703. In other words, the additional analog offset error may be changed according to different input offset control signals (or obfuscation codes). In summary, the degree of de-identification of the de-identified data 703 is adjustable. In some embodiments, when the de-identification circuit 720 does not receive the externally input offset control signal 704, the de-identification circuit 720 may still generate an additional analog offset error based on no pre-set fixed parameters (for example, the process error of the transistor), that is, Figure 1 The operation circuit 100 is provided.

[0093] In addition, for other technical features and implementation methods of the operation circuit 700 of this embodiment, reference may be made to the aforementioned Figures 1 to 4 The description of the embodiments can provide sufficient teachings, suggestions and implementation instructions, so no further details are given.

[0094] Figure 8 FIG. 8 is a schematic diagram of the structure of a de-identification circuit 820 according to another embodiment of the present invention. Figure 8 , the de-identification circuit can be realized as follows Figure 8 The structure of the de-identification circuit 820 is shown in FIG. In this embodiment, the de-identification circuit 820 may be an amplifier circuit, and includes a signal conversion circuit 821 and a signal operation circuit 822. The signal conversion circuit 821 is coupled to the operation array 810. In this embodiment, the operation array 810 may implement the above-mentioned Figure 4 The architecture of the de-identification circuit 820 can refer to Figure 5 The contents described in the embodiment of the de-identification circuit 520 are not repeated for the similar contents of the signal conversion circuit 821, the signal conversion units 8211, 8212, the de-identification sub-circuits 8213, 8214, 8221, 8222, and the signal operation circuit 822.

[0095] It is worth noting that the signal operation circuit 822 may further include de-identification offset circuits 8223, 8224 and offset control circuits 8225, 8226. The de-identification sub-circuit 8221 is coupled to the signal conversion unit 8211 of the signal conversion circuit 821, the de-identification offset circuit 8223 and the comparator 8227. The de-identification sub-circuit 8222 is coupled to the signal conversion unit 8112 of the signal conversion circuit 821, the de-identification offset circuit 8224 and the comparator 8227. The de-identification offset circuit 8223 is also coupled to the offset control circuit 8225. The de-identification offset circuit 8224 is also coupled to the offset control circuit 8226. In some embodiments, at least one of the signal conversion circuit 821 and the signal operation circuit 822 may include the de-identification offset circuits 8223, 8224, but is not limited to. Figure 8 As shown. In this regard, in some embodiments, all circuit components of the de-identification offset circuits 8223 and 8224 may be disposed in the signal conversion circuit 821 or the signal operation circuit 822. Alternatively, in other embodiments, a portion of the circuit components of the de-identification offset circuits 8223 and 8224 may be disposed in the signal conversion circuit 821, and another portion of the circuit components of the de-identification offset circuits 8223 and 8224 may be disposed in the signal operation circuit 822. In addition, it should be noted that Figure 8 The number and location of the signal conversion circuit and / or the de-identification sub-circuit, the de-identification offset circuit, and / or the offset control circuit of the embodiment are not limited to those shown in the drawings. In some embodiments of the present invention, Figure 8 The de-identification sub-circuit or the de-identification shift circuit of the signal conversion circuit and / or the signal operation circuit of the embodiment may also be based on the same or similar design concepts as above and below.

[0096] In some embodiments, the offset control circuits 8225 and 8226 may be configured to receive a digital aliasing code (digital code) and generate an analog control voltage according to the digital aliasing code to serve as an offset control signal.

[0097] In some embodiments, the de-identification sub-circuits 8213, 8214, 8221, 8222 and the de-identification offset circuits 8223, 8224 may each include at least one transistor. Figure 8 As shown, for example, the signal conversion circuit 821 and the signal operation circuit 822 may include at least one de-identification sub-circuit.

[0098] In this embodiment, the offset control circuit 8225 may receive the aliased code 803, and the offset control circuit 8225 may determine at least one offset control signal according to the aliased code 803. The offset control circuit 8225 may output the at least one offset control signal to at least one transistor in the de-identified offset circuit 8223. Similarly, the offset control circuit 8226 may receive the aliased code 805, and the offset control circuit 8226 may determine at least one offset control signal according to the aliased code 805. The offset control circuit 8226 may output the at least one offset control signal to at least one transistor in the de-identified offset circuit 8224. More specifically, the offset control circuit 8225 may output the offset control signal 804 to the de-identified offset circuit 8223, so that the de-identified offset circuit 8223 may generate an additional analog offset error according to the offset control signal 804. Similarly, the offset control circuit 8226 can output the offset control signal 806 to the de-identification offset circuit 8224 , so that the de-identification offset circuit 8224 can generate an additional analog offset error according to the offset control signal 806 .

[0099] In some embodiments, when the offset control circuits 8225 and 8226 do not receive the externally input obfuscated codes 803 and 805, the offset control circuits 8225 and 8226 can still generate additional analog offset errors according to fixed parameters without any pre-set parameters (e.g., process errors of transistors). In addition, the offset control circuits 8225 and 8226 can also be integrated into a single control circuit, not limited to Figure 8 The architecture shown.

[0100] For example, the de-identification sub-circuits 8213, 8214, 8221, and 8222 may provide error coefficients "A1", "A2", "A3", and "A4" for signal conversion through at least one transistor inside. The de-identification offset circuits 8223 and 8224 may provide error coefficients "A5" and "A6" according to the offset control signals 804 and 806 and at least one transistor inside. The analog offset error of this embodiment may include error coefficients "A1" to "A6".

[0101] More specifically, the de-identification sub-circuit 8213 may receive a first signal (e.g., represented by the symbol “I1”) of the first accumulated data 802_1, and output a result of multiplying the first signal by the error coefficient “A1”, i.e., a first conversion signal (i.e., “I1×A1”) to the de-identification sub-circuit 8221. The de-identification sub-circuit 8214 may receive a second signal (represented by the symbol “I2”) of the second accumulated data 802_2, and output a result of multiplying the second signal by the error coefficient “A2”, i.e., a second conversion signal (i.e., “I2×A2”) to the de-identification sub-circuit 8222. Then, the de-identification sub-circuit 8221 and the de-identification offset circuit 8223 may output a conversion result to the comparator 8227 according to the first conversion signal, and the de-identification sub-circuit 8222 and the de-identification offset circuit 8224 may output another conversion result to the comparator 8223 according to the second conversion signal, so that the comparator 8227 may generate de-identified data according to the conversion result.

[0102] More specifically, the de-identification sub-circuit 8221 can receive the first conversion signal, and cooperate with the de-identification offset circuit 8223 to output the result of multiplying the first conversion signal by the error coefficient "A3" and the error coefficient "A5", that is, the third conversion signal (i.e., "I1×A1×A3×A5") to the comparator 8227. Similarly, the de-identification sub-circuit 8222 can receive the second conversion signal, and cooperate with the de-identification offset circuit 8224 to output the result of multiplying the second conversion signal by the error coefficient "A4" and the error coefficient "A6", that is, the fourth conversion signal (i.e., "I2×A2×A4×A6") to the comparator 8227. In summary, the comparator 8227 can output the comparison result of the third conversion signal and the fourth conversion signal (i.e., "(I1×A1×A3×A5)-(I2×A2×A4×A6)"), that is, the de-identification data 807.

[0103] FIG. 9A to FIG. 9M 9 is a schematic diagram of a circuit of amplifier circuits 920A to 920M according to another embodiment of the present invention. It should be noted that: FIG. 9A to FIG. 9M The amplifier circuit architecture can be designed as a differential amplifier circuit architecture, a current mirror amplifier circuit architecture, etc. The present invention is not limited thereto and the design can be adjusted according to actual needs.

[0104] Please refer to Fig.9A , the amplifier circuit can be realized as Fig.9AThe circuit architecture shown. In this embodiment, the amplifier circuit 920A includes a signal conversion circuit 921A and a signal operation circuit 922A. The signal conversion circuit 921A includes a signal conversion unit 9211A and a signal conversion unit 9212A, and the signal conversion units 9211A and 9212A include de-identification sub-circuits 9213A and 9214A. The signal operation circuit 922A includes de-identification sub-circuits 9221A and 9222A, de-identification offset circuits 9223A and 9224A, and offset control circuits 9225A and 9226A.

[0105] In this embodiment, the de-identification sub-circuit 9213A may include a transistor T1A. The de-identification sub-circuit 9214A may include a transistor T2A. The de-identification sub-circuit 9221A may include a transistor T3A. The de-identification sub-circuit 9222A may include a transistor T4A. The de-identification offset circuit 9223A may include a transistor T5A. The de-identification offset circuit 9224A may include a transistor T6A. In some embodiments, the transistors T1A and T2A are N-type transistors, and the transistors T3A, T4A, T5A, and T6A are P-type transistors, but the present invention is not limited thereto, and the design may be adjusted according to actual needs.

[0106] In this embodiment, the transistor T5A is connected in series between the transistor T1A of the de-identification sub-circuit 9213A and the transistor T3A of the de-identification sub-circuit 9221A. The transistor T6A is connected in series between the transistor T2A of the de-identification sub-circuit 9214A and the transistor T4A of the de-identification sub-circuit 9222A.

[0107] In this embodiment, the first terminal of the transistor T1A is coupled to the second terminal of the transistor T5A and the output terminal 923A_1. The control terminal of the transistor T1A can receive the clamping voltage Vc1A. The second terminal of the transistor T1A can receive the first signal 902A_1 of the accumulated data. The first terminal of the transistor T2A is coupled to the second terminal of the transistor T6A and the output terminal 923A_2. The control terminal of the transistor T2A can receive the clamping voltage Vc2A. The second terminal of the transistor T2A can receive the second signal 902A_2 of the accumulated data. The first terminal of the transistor T5A is coupled to the second terminal of the transistor T3A, the control terminal of the transistor T3A, and the output terminal 923A_3. The control terminal of the transistor T5A is coupled to the offset control circuit 9225A. The second terminal of the transistor T5A is coupled to the output terminal 923A_1. The first terminal of the transistor T3A is coupled to the operating voltage VDD. The second terminal of the transistor T3A is coupled to the control terminal of the transistor T3A, the first terminal of the transistor T5A, and the output terminal 923A_3. The first terminal of the transistor T4A is coupled to the operation voltage VDD. The second terminal of the transistor T4A is coupled to the control terminal of the transistor T4A, the first terminal of the transistor T6A and the output terminal 923A_4.

[0108] In this embodiment, the first signal 902A_1 and the second signal 902A_2 may be current signals. In some embodiments, at least one of the transistors T1A-T6A may have different analog offset errors due to process errors, but the present invention is not limited thereto. In this embodiment, the offset control circuits 9225A and 9226A may be respectively preset to output fixed offset control signals to control the conduction degree of the transistors T5A and T6A (for example, the current flowing through the transistors T5A and T6A is 1.1 times or 0.9 times the first signal 902A_1 and the second signal 902A_2, but the present invention is not limited thereto), so as to provide additional adjustable analog offset errors.

[0109] In the present embodiment, the first signal 902A_1 flows through transistors T1A, T3A, and T5A and is converted into a conversion signal with an analog offset error. The aforementioned conversion signal can be output to output terminals 923A_1 and 923A_3. The second signal 902A_2 flows through transistors T2A, T4A, and T6A and is converted into another conversion signal with an analog offset error. The aforementioned conversion signal can be output to output terminals 923A_2 and 923A_4. In summary, the output terminals 923A_1 to 923A_4 can output the conversion results with the analog offset error to the back-end comparator (for example, the conversion results with the analog offset error can be output to Figure 8 comparator 8227) so that the back-end comparator can perform operations to generate de-identified data.

[0110] Please refer to 9B, the amplifier circuit can be realized as follows Fig. 9B The circuit architecture shown. In this embodiment, the amplifier circuit 920B includes a signal conversion circuit 921B and a signal operation circuit 922B. The signal conversion circuit 921B includes a signal conversion unit 9211B and a signal conversion unit 9212B, and the signal conversion units 9211B and 9212B include de-identification sub-circuits 9213B and 9214B. The signal operation circuit 922B includes de-identification sub-circuits 9221B and 9222B, de-identification offset circuits 9223B and 9224B, and offset control circuits 9225B and 9226B. The de-identification sub-circuits 9213B, 9214B, 9221B, 9222B, and the de-identification offset circuits 9223B and 9224B include transistors T1B to T6B.

[0111] The circuit structure of the amplifier circuit 920B can be referred to Fig.9A More specifically, the architecture of the signal conversion circuit 921B and the signal operation circuit 922B can refer to Fig.9A The signal conversion circuit 921A and the signal operation circuit 922A described above are not described in detail here.

[0112] In this embodiment, the control terminal of transistor T1B can receive the clamping voltage Vc1B. The second terminal of transistor T1B can receive the first signal 902B_1 of accumulated data. The control terminal of transistor T2B can receive the clamping voltage Vc2B. The second terminal of transistor T2B can receive the second signal 902B_2 of accumulated data.

[0113] In some embodiments, the first signal 902B_1 and the second signal 902B_2 may be current signals. At least one of the transistors T1B-T6B may have different analog offset errors due to process errors, but the present invention is not limited thereto. It is worth noting that the amplifier circuit 920B of this embodiment is Fig.9A The difference between the embodiments is that the offset control circuit 9225B can also receive the confusion code 903B to output the corresponding offset control signal to control the transistor T5B, and the offset control circuit 9226B can also receive the confusion code 904B to output the corresponding offset control signal to control the transistor T6B, so that additional analog offset errors can be provided respectively.

[0114] In this embodiment, the first signal 902B_1 flows through the transistors T1B, T3B, and T5B to be converted into a conversion signal with an analog offset error, and is output to the output terminals 923B_1 and 923B_3. The second signal 902B_2 flows through the transistors T2B, T4B, and T6B to be converted into another conversion signal with an analog offset error, and is output to the output terminals 923B_2 and 923B_4. In summary, the output terminals 923B_1 to 923B_4 can output the conversion results with the analog offset error to the back-end comparator (for example, outputting the aforementioned conversion results to Figure 8 The comparator 8227 is used to enable the back-end comparator to perform operations and generate de-identified data. More specifically, by controlling the obfuscation codes 903B and 904B to affect the transistors T5B and T6B, the output terminals 923B_1 to 923B_4 will output differential signals of conversion results with sufficient privacy levels in response to the additional analog offset error. In other words, the present invention can generate adjustable analog offset errors by controlling the obfuscation codes 903B and 904B, and further control the output terminals 923B_1 to 923B_4 to output conversion results with sufficient privacy levels.

[0115] Please refer to Fig. 9C , the amplifier circuit can be realized as Fig. 9CThe circuit architecture shown. In this embodiment, the amplifier circuit 920C includes a signal conversion circuit 921C and a signal operation circuit 922C. The signal conversion circuit 921C includes a signal conversion unit 9211C and a signal conversion unit 9212C. The signal conversion units 9211C and 9212C include de-identification sub-circuits 9213C and 9214C. The signal operation circuit 922C includes de-identification sub-circuits 9221C and 9222C, de-identification offset circuits 9223C and 9224C, and offset control circuits 9225C and 9226C. In this embodiment, the de-identification sub-circuits 9213C, 9214C, 9221C, 9222C, and the de-identification offset circuits 9223C and 9224C include transistors T1C to T6C. In some embodiments, the transistors T1C and T2C may be N-type transistors, and the transistors T3C, T4C, T5C, and T6C may be P-type transistors, but the present invention is not limited thereto and the design may be adjusted according to actual needs.

[0116] The circuit structure of the amplifier circuit 920C can be referred to Fig.9A , 9B More specifically, the architecture of the signal conversion circuit 921C and the signal operation circuit 922C can refer to Fig.9A , 9B The signal conversion circuits 921A, 921B and the signal operation circuits 922A, 922B described above are not described in detail. In this embodiment, the transistor T5C is connected in parallel with the transistor T3C of the de-identification sub-circuit 9221C, and the transistor T6C is connected in parallel with the transistor T4C of the de-identification sub-circuit 9222C, but the present invention is not limited to this. It is worth noting that the amplifier circuit 920C of this embodiment is connected in parallel with the Fig.9A , 9BThe difference between the embodiments is that the first end of the transistor T1C is coupled to the second end of the transistor T3C, the control end of the transistor T3C, the second end of the transistor T5C, the control end of the transistor T5C, and the output end 923C_1. The control end of the transistor T1C can receive the clamping voltage Vc1C. The second end of the transistor T1C can receive the first signal 902C_1 of the accumulated data. The first end of the transistor T2C is coupled to the second end of the transistor T4C, the control end of the transistor T4C, the second end of the transistor T6C, the control end of the transistor T6C, and the output end 923C_2. The control end of the transistor T2C can receive the clamping voltage Vc2C. The second end of the transistor T2C can receive the second signal 902C_2 of the accumulated data. The first end of the transistor T3C can be coupled to the operating voltage VDD. The first end of the transistor T4C can be coupled to the operating voltage VDD. The first end of the transistor T5C can be coupled to the offset control circuit 9225C. The control end of the transistor T5C is coupled to the second end of the transistor T5C. The second end of the transistor T5C is also coupled to the output end 923C_1. The second end of the transistor T3C is coupled to the control end of the transistor T3C, the second end of the transistor T5C, the control end of the transistor T5C, and the output end 923C_1. The first end of the transistor T6C can be coupled to the offset control circuit 9226C. The control end of the transistor T6C is coupled to the second end of the transistor T6C. The second end of the transistor T6C is also coupled to the output end 923C_2. The second end of the transistor T4C is coupled to the control end of the transistor T4C, the second end of the transistor T6C, the control end of the transistor T6C, and the output end 923C_2.

[0117] In some embodiments, the first signal 902C_1 and the second signal 902C_2 may be current signals. At least one of the transistors T1C-T6C may have different analog offset errors due to process errors, but the present invention is not limited thereto. In some embodiments, the offset control circuit 9225C may also receive the aliasing code 903C to output a corresponding offset control signal to control the transistor T5C, and the offset control circuit 9226C may also receive the aliasing code 904C to output a corresponding offset control signal to control the transistor T6C, so that additional analog offset errors can be provided respectively.

[0118] In this embodiment, the first signal 902C_1 flows through the transistors T1C, T3C, and T5C and is converted into a conversion signal with an analog offset error. The conversion signal can be output to the output terminal 923C_1. The second signal 902C_2 flows through the transistors T2C, T4C, and T6C and is converted into another conversion signal with an analog offset error. The conversion signal can be output to the output terminal 923C_2. In summary, the output terminals 923C_1 and 923C_2 can output the conversion result with the analog offset error to the back-end comparator (for example, output the conversion result to Figure 8The comparator 8227 of the embodiment of the present invention is used to enable the back-end comparator to perform operations and generate de-identified data. More specifically, by controlling the obfuscation codes 903C and 904C to affect the transistors T5C and T6C, the output terminals 923C_1 and 923C_2 will output differential signals of conversion results with sufficient privacy levels in response to the additional analog offset error. In other words, the present invention can generate adjustable analog offset errors by controlling the obfuscation codes 903C and 904C, and further control the output terminals 923C_1 and 923C_2 to output conversion results with sufficient privacy levels.

[0119] Please refer to Fig.9D , the amplifier circuit can be realized as Fig.9D Circuit architecture shown. In this embodiment, the amplifier circuit 920D includes a signal conversion circuit 921D and a signal operation circuit 922D. The signal conversion circuit 921D includes a signal conversion unit 9211D and a signal conversion unit 9212D. The signal conversion units 9211D and 9212D include de-identification sub-circuits 9213D and 9214D. The signal operation circuit 922D includes de-identification sub-circuits 9221D and 9222D, de-identification offset circuits 9223D and 9224D, and offset control circuits 9225D and 9226D. The de-identification sub-circuits 9213D, 9214D, 9221D, and 9222D include transistors T1D to T4D. The de-identification offset circuit 9223D includes transistors T5D and T7D. The de-identification offset circuit 9224D includes transistors T6D and T8D. In some embodiments, the transistors T1D and T2D may be N-type transistors, and the transistors T3D, T4D, T5D, T6D, T7D, and T8D may be P-type transistors, but the present invention is not limited thereto and the design may be adjusted according to actual needs.

[0120] The circuit structure of the amplifier circuit 920D can be referred to Figures 9A to 9C More specifically, the architecture of the transistors T1D to T6D of the signal conversion circuit 921D and the signal operation circuit 922D can refer to Figures 9A to 9C The signal conversion circuits 921A to 921C and the signal operation circuits 922A to 922C described above are not described in detail. It is worth noting that the transistor T5D is connected in series between the transistor T1D of the de-identification sub-circuit 9213D and the transistor T3D of the de-identification sub-circuit 9221D. The transistor T6D is connected in series between the transistor T2D of the de-identification sub-circuit 9214D ​​and the transistor T4D of the de-identification sub-circuit 9222D. Among them, the circuit structure of the transistors T3D, T4D, T7D, and T8D is similar to Fig. 9CThe transistor T7D is connected in parallel with the transistor T3D of the de-identification sub-circuit 9221D, and the transistor T8D is connected in parallel with the transistor T4D of the de-identification sub-circuit 9222D. In the present embodiment, the first end of the transistor T7D is coupled to the offset control circuit 9225D. The control end of the transistor T7D is coupled to the second end of the transistor T7D. The second end of the transistor T7D is also coupled to the output end 923D_3. The first end of the transistor T8D is coupled to the offset control circuit 9226D. The control end of the transistor T8D is coupled to the second end of the transistor T8D. The second end of the transistor T8D is also coupled to the output end 923D_4.

[0121] In this embodiment, the control terminal of the transistor T1D can receive the clamping voltage Vc1D. The second terminal of the transistor T1D can receive the first signal 902D_1 of the accumulated data. The control terminal of the transistor T2D can receive the clamping voltage Vc2D. The second terminal of the transistor T2D can receive the second signal 902D_2 of the accumulated data.

[0122] In some embodiments, the first signal 902D_1 and the second signal 902D_2 may be current signals. At least one of the transistors T1D-T8D may have different analog offset errors due to process errors, but the present invention is not limited thereto. In some embodiments, the offset control circuit 9225D may receive the aliasing code 903D to output the same or different offset control signals to control the transistors T5D and T7D, and the offset control circuit 9226D may receive the aliasing code 904D to output the same or different offset control signals to control the transistors T6D and T8D, so as to provide additional analog offset errors respectively.

[0123] In this embodiment, the first signal 902D_1 flows through the transistors T1D, T3D, T5D, and T7D to be converted into a conversion signal with an analog offset error, and is output to the output terminals 923D_1 and 923D_3. The second signal 902D_2 flows through the transistors T2D, T4D, T6D, and T8D to be converted into another conversion signal with an analog offset error, and is output to the output terminals 923D_2 and 923D_4. In summary, the output terminals 923D_1 to 923D_4 can output the conversion results with the analog offset error to the back-end comparator (for example, outputting the aforementioned conversion results to Figure 8The comparator 8227 of the embodiment of the present invention is used to enable the back-end comparator to perform operations and generate de-identified data. More specifically, by controlling the obfuscation codes 903D and 904D to affect the transistors T5D to T8D, the output terminals 923D_1 to 923D_4 will output differential signals of conversion results with sufficient privacy levels in response to the additional analog offset error. In other words, the present invention can generate adjustable analog offset errors by controlling the obfuscation codes 903D and 904D, and further control the output terminals 923D_1 to 923D_4 to output conversion results with sufficient privacy levels.

[0124] Please refer to Fig.9E , the amplifier circuit can be realized as Fig.9E The circuit architecture of the differential amplifier shown in FIG. 1 is a circuit diagram of a differential amplifier. In the present embodiment, the amplifier circuit 920E includes a signal conversion circuit 921E and a signal operation circuit 922E. The signal conversion circuit 921E includes a signal conversion unit 9211E, a signal conversion unit 9212E, and transistors T15E and T16E of a de-identification offset circuit 9223E and 9224E. The signal conversion units 9211E and 9212E include de-identification sub-circuits 9213E and 9214E. The signal operation circuit 922E includes de-identification sub-circuits 9221E and 9222E, transistors T3E to T14E of de-identification offset circuits 9223E and 9224E, and an offset control circuit (not shown). The de-identification sub-circuits 9213E, 9214E, 9221E, and 9222E include transistors T1E to T4E. The de-identification shift circuit 9223E includes transistors T5E, T7E, T9E, T11E, T13E, and T15E, wherein the transistor T15E in this embodiment is designed in the signal conversion circuit 921E. The de-identification shift circuit 9224E includes transistors T6E, T8E, T10E, T12E, T14E, and T16E, wherein the transistor T16E in this embodiment is designed in the signal conversion circuit 921E, but the transistors of the present invention are not limited thereto. In some embodiments, the transistors T1E and the transistor T2E are N-type transistors, and the transistors T3E to T16E are P-type transistors, but the present invention is not limited thereto and the design can be adjusted according to actual needs.

[0125] The circuit structure of the amplifier circuit 920E can be referred to Figures 9A to 9D More specifically, the architecture of the transistors T1E-T6E of the signal conversion circuit 921E and the signal operation circuit 922E can refer to Figures 9A to 9DThe signal conversion circuits 921A to 921D and the signal operation circuits 922A to 922D described herein are not described in detail. It is worth noting that transistors T1E, T3E, and T5E are connected in series. Transistors T2E, T4E, and T6E are connected in series. Transistor T5E and transistor T7E are connected in parallel. Transistor T6E and transistor T8E are connected in parallel. Transistor T15E and transistor T1E are connected in parallel. Transistor T16E and transistor T2E are connected in parallel. Transistor T3E, transistor T9E, transistor T11E, and transistor T13E are connected in parallel. Transistor T4E, transistor T10E, transistor T12E, and transistor T14E are connected in parallel. The control terminals of transistors T9E to T14E are respectively coupled to their respective second terminals. In some embodiments, the control terminals of the transistors T5E-T8E, T15E, T16E and the first terminals of the transistors T9E-T14E may be coupled to the same or different offset control circuits (not shown).

[0126] In this embodiment, the control terminal of transistor T1E can receive clamping voltage Vc1E. The control terminal of transistor T2E can receive clamping voltage Vc2E. The circuit structures of transistors T3E, T4E, T9E to T14E are similar to Fig.9D It is worth noting that the amplifier circuit 920E of this embodiment is similar to the transistors T3D, T4D, T7D, and T8D in FIG. Figures 9A to 9D The difference between the embodiments is that the first terminals of transistors T3E, T4E, T9E-T14E are all coupled to an offset control circuit (not shown). The control terminals of transistors T3E, T4E, T9E-T14E are respectively coupled to the second terminals of transistors T3E, T4E, T9E-T14E. The second terminals of transistors T3E, T9E, T11E, T13E are also coupled to the output terminal 923E_3, the first terminal of transistor T5E, and the first terminal of transistor T7E. The second terminals of transistors T4E, T10E, T12E, T14E are also coupled to the output terminal 923E_4, the first terminal of transistor T6E, and the first terminal of transistor T8E. The control terminals of transistors T5E-T8E are coupled to an offset control circuit (not shown). The second terminals of transistors T5E and T7E are also coupled to the output terminal 923E_1, the first terminal of transistor T1E, and the first terminal of transistor T15E. The second terminals of transistors T6E and T8E are also coupled to the output terminal 923E_2, the first terminal of transistor T2E, and the first terminal of transistor T16E. The control terminals of transistors T15E and T16E are coupled to an offset control circuit (not shown). The second terminals of transistors T1E and T15E can receive a first signal 902E_1 of accumulated data. The second terminals of transistors T2E and T16E can receive a second signal 902E_2 of accumulated data.

[0127] In some embodiments, the first signal 902E_1 and the second signal 902E_2 may be current signals. At least one of the transistors T1E-T16E may have different analog offset errors due to process errors, but the present invention is not limited thereto. In some embodiments, the offset control circuit (not shown) of the amplifier circuit 920E may also receive a garbled code to output the same or different offset control signals to control the transistors T5E-T14E, so that additional analog offset errors can be provided respectively.

[0128] In this embodiment, the first signal 902E_1 flows through transistors T1E, T3E, T5E, T7E, T9E, T11E, T13E, and T15E and is converted into a conversion signal with an analog offset error. The aforementioned conversion signal can be output to output terminals 923E_1 and 923E_3. The second signal 902E_2 flows through transistors T2E, T4E, T6E, T8E, T10E, T12E, T14E, and T16E and is converted into another conversion signal with an analog offset error. The aforementioned conversion signal can be output to output terminals 923E_2 and 923E_4. In summary, the output terminals 923E_1 to 923E_4 can output the conversion results with the analog offset error to the comparator at the back end (for example, outputting the aforementioned conversion results to Figure 8 The comparator 8227 of the embodiment of the present invention is used to enable the back-end comparator to perform operations and generate de-identified data. In some embodiments, the transistors T5E-T16E may be affected by receiving an obfuscation code (not shown), and the output terminals 923E_1-923E_4 may output differential signals of conversion results with sufficient privacy levels in response to additional analog offset errors. In other words, the present invention may generate adjustable analog offset errors by controlling the obfuscation code, and further control the output terminals 923E_1-923E_4 to output conversion results with sufficient privacy levels.

[0129] Please refer to Fig.9F , the amplifier circuit can be realized as Fig.9FCircuit architecture shown. In this embodiment, the amplifier circuit 920F includes a signal conversion circuit 921F and a signal operation circuit 922F. The signal conversion circuit 921F includes a signal conversion unit 9211F and a signal conversion unit 9212F. The signal conversion units 9211F and 9212F include de-identification sub-circuits 9213F and 9214F. The signal operation circuit 922F includes de-identification sub-circuits 9221F and 9222F, de-identification offset circuits 9223F and 9224F, and offset control circuits 9225F and 9226F. The de-identification sub-circuits 9213F, 9214F, 9221F, and 9222F include transistors T1F to T4F. The de-identification offset circuit 9223F includes a transistor T5F. The de-identification offset circuit 9224F includes a transistor T6F. In some embodiments, the transistors T1F and T2F are N-type transistors, and the transistors T3F, T4F, T5F, and T6F are P-type transistors, but the present invention is not limited thereto and the design can be adjusted according to actual needs.

[0130] In this embodiment, transistor T5F is connected in series between transistor T1F of de-identification sub-circuit 9213F and transistor T3F of de-identification sub-circuit 9221F. Transistor T6F is connected in series between transistor T2F of de-identification sub-circuit 9214F and transistor T4F of de-identification sub-circuit 9222F.

[0131] It is worth noting that in this embodiment, the first end of the transistor T1F is coupled to the second end of the transistor T5F and the control ends of the transistors T3F and T4F. The control end of the transistor T1F can receive the clamping voltage Vc1F. The second end of the transistor T1F can receive the first signal 902F_1 of the accumulated data. The first end of the transistor T2F is coupled to the second end of the transistor T6F and the output end 923F. The control end of the transistor T2F can receive the clamping voltage Vc2F. The second end of the transistor T2F can receive the second signal 902F_2 of the accumulated data. The first end of the transistor T5F is coupled to the second end of the transistor T3F. The control end of the transistor T5F is coupled to the offset control circuit 9225F. The second end of the transistor T5F is coupled to the first end of the transistor T1F and the control ends of the transistors T3F and T4F. The first end of the transistor T3F can be coupled to the operating voltage VDD. The second end of the transistor T3F is coupled to the first end of the transistor T5F. The first end of the transistor T4F can be coupled to the operating voltage VDD. The second terminal of the transistor T4F is coupled to the first terminal of the transistor T6F. The first terminal of the transistor T6F is coupled to the second terminal of the transistor T4F. The control terminal of the transistor T6F is coupled to the offset control circuit 9226F.

[0132] In some embodiments, the first signal 902F_1 and the second signal 902F_2 may be current signals. At least one of the transistors T1F-T6F may have different analog offset errors due to process errors, but the present invention is not limited thereto. In some embodiments, the offset control circuit 9225F may also receive the aliasing code 903F to output a corresponding offset control signal to control the transistor T5F, and the offset control circuit 9226F may also receive the aliasing code 904F to output a corresponding offset control signal to control the transistor T6F, so that additional analog offset errors can be provided respectively.

[0133] In this embodiment, the first signal 902F_1 flows through the transistors T1F, T3F, and T5F and is converted into a conversion signal with an analog offset error. The second signal 902F_2 flows through the transistors T2F, T4F, and T6F and is converted into another conversion signal with an analog offset error. In summary, the output terminal 923F can output a voltage signal of a conversion result with an analog offset error (i.e., a result after the conversion signal is subtracted from another conversion signal) to a back-end comparator (e.g., outputting the aforementioned conversion result to Figure 8 The comparator 8227 of the embodiment of the present invention is used to enable the back-end comparator to perform operations and generate de-identified data. More specifically, by controlling the obfuscation codes 903F and 904F to affect the transistors T5F and T6F, the output terminal 923F will output a conversion result with a sufficient privacy level in response to the additional analog offset error. In other words, the present invention can generate an adjustable analog offset error by controlling the obfuscation codes 903F and 904F, and further control the output terminal 923F to output a conversion result with a sufficient privacy level.

[0134] Please refer to Figure 9G , the amplifier circuit can be realized as Figure 9G Circuit architecture shown. In this embodiment, the amplifier circuit 920G includes a signal conversion circuit 921G and a signal operation circuit 922G. The signal conversion circuit 921G includes a signal conversion unit 9211G and a signal conversion unit 9212G. The signal conversion units 9211G and 9212G include de-identification sub-circuits 9213G and 9214G. The signal operation circuit 922G includes de-identification sub-circuits 9221G and 9222G, de-identification offset circuits 9223G and 9224G, and offset control circuits 9225G and 9226G. In this embodiment, the de-identification sub-circuits 9213G, 9214G, 9221G, 9222G, and the de-identification offset circuits 9223G and 9224G include transistors T1G to T6G. In some embodiments, the transistors T1G and T2G may be N-type transistors, and the transistors T3G, T4G, T5G, and T6G may be P-type transistors, but the present invention is not limited thereto and the design may be adjusted according to actual needs.

[0135] The circuit structure of the amplifier circuit 920G can be referred to Fig.9F More specifically, the architecture of the transistors T1G to T4G of the signal conversion circuit 921G and the signal operation circuit 922G can refer to Fig.9F The signal conversion circuit 921F and the signal operation circuit 922F described above are similar to each other and are not described in detail. In this embodiment, the transistor T5G is connected in parallel with the transistor T3G of the de-identification sub-circuit 9221G, and the transistor T6G is connected in parallel with the transistor T4G of the de-identification sub-circuit 9222G, but the present invention is not limited thereto. It is worth noting that the amplifier circuit 920G of this embodiment is connected in parallel with the Fig.9F The difference between the embodiments is that the first end of the transistor T1G is coupled to the second end of the transistor T3G, the control ends of the transistors T3G and T4G, and the control end and the second end of the transistor T5G. The first end of the transistor T2G is coupled to the second end of the transistor T4G, the second end of the transistor T6G, and the output end 923G. The first end of the transistor T5G is coupled to the offset control circuit 9225G. The first end of the transistor T6G is coupled to the operating voltage VDD and the first end of the transistor T4G. The control end of the transistor T6G is coupled to the offset control circuit 9226G. The second end of the transistor T6G is coupled to the output end 923G and the second end of the transistor T4G.

[0136] In some embodiments, the first signal 902G_1 and the second signal 902G_2 may be current signals. At least one of the transistors T1G-T6G may have different analog offset errors due to process errors, but the present invention is not limited thereto. In some embodiments, the offset control circuit 9225G may receive the aliasing code 903G to output a corresponding offset control signal to control the transistor T5G, and the offset control circuit 9226G may receive the aliasing code 904G to output a corresponding offset control signal to control the transistor T6G, so that additional analog offset errors can be provided respectively.

[0137] In this embodiment, the first signal 902G_1 flows through the transistors T1G, T3G, and T5G and is converted into a conversion signal with an analog offset error. The second signal 902G_2 flows through the transistors T2G, T4G, and T6G and is converted into another conversion signal with an analog offset error. In summary, the output terminal 923G can output a voltage signal of a conversion result with an analog offset error (i.e., a result after the conversion signal is subtracted from another conversion signal) to a back-end comparator (e.g., outputting the aforementioned conversion result to Figure 8The comparator 8227 of the embodiment of the present invention is used to enable the back-end comparator to perform operations and generate de-identified data. More specifically, by controlling the obfuscation codes 903G and 904G to affect the transistors T5G and T6G, the output terminal 923G will output a conversion result with a sufficient privacy level in response to the additional analog offset error. In other words, the present invention can generate an adjustable analog offset error by controlling the obfuscation codes 903G and 904G, and further control the output terminal 923G to output a conversion result with a sufficient privacy level.

[0138] Please refer to Figure 9H , the amplifier circuit can be realized as Figure 9H The circuit architecture shown. In this embodiment, the amplifier circuit 920H includes a signal conversion circuit 921H and a signal operation circuit 922H. The signal conversion circuit 921H includes a signal conversion unit 9211H and a signal conversion unit 9212H. The signal conversion units 9211H and 9212H include de-identification sub-circuits 9213H and 9214H. The signal operation circuit 922H includes de-identification sub-circuits 9221H and 9222H, de-identification offset circuits 9223H and 9224H, and offset control circuits 9225H and 9226H. In this embodiment, the de-identification sub-circuits 9213H, 9214H, 9221H, and 9222H include transistors T1H to T4H. The de-identification offset circuit 9223H includes transistors T5H and T7H. The de-identification offset circuit 9224H includes transistors T6H and T8H. In some embodiments, the transistors T1H and T2H are N-type transistors, and the transistors T3H, T4H, T5H, T6H, T7H, and T8H are P-type transistors, but the present invention is not limited thereto and the design can be adjusted according to actual needs.

[0139] The circuit structure of the amplifier circuit 920H can be referred to Fig.9F , 9G More specifically, the architecture of the transistors T1H to T6H of the signal conversion circuit 921H and the signal operation circuit 922H can refer to Fig.9F , 9G The signal conversion circuits 921F, 921G and signal operation circuits 922F, 922G described above are not described in detail. It is worth noting that the transistor T5H is connected in series between the transistor T1H of the de-identification sub-circuit 9213H and the transistor T3H of the de-identification sub-circuit 9221H. The transistor T6H is connected in series between the transistor T2H of the de-identification sub-circuit 9214H and the transistor T4H of the de-identification sub-circuit 9222H. Among them, the transistor T7H is connected in parallel with the transistor T3H of the de-identification sub-circuit 9221H, and the transistor T8H is connected in parallel with the transistor T4H of the de-identification sub-circuit 9222H.

[0140] In this embodiment, the control terminal of the transistor T1H can receive the clamping voltage Vc1H. The second terminal of the transistor T1H can receive the first signal 902H_1 of the accumulated data. The control terminal of the transistor T2H can receive the clamping voltage Vc2H. The second terminal of the transistor T2H can receive the second signal 902H_2 of the accumulated data. It is worth noting that the amplifier circuit 920H of this embodiment is Fig.9F , 9G The difference between the embodiments is that the first end of the transistor T5H is coupled to the second end of the transistor T3H, the control ends of the transistors T3H, T4H, and T7H, and the second end of the transistor T7H. The control end of the transistor T5H and the first end of the transistor T7H are coupled to the offset control circuit 9225H. The second end of the transistor T5H is coupled to the first end of the transistor T1H. The first end of the transistor T6H is coupled to the second end of the transistor T4H and the second end of the transistor T8H. The control ends of the transistors T6H and T8H are coupled to the offset control circuit 9226H. The second end of the transistor T6H is coupled to the first end of the transistor T2H and the output end 923H. The first end of the transistor T4H is coupled to the operating voltage VDD. The second end of the transistor T4H is coupled to the first end of the transistor T6H and the second end of the transistor T8H.

[0141] In some embodiments, the first signal 902H_1 and the second signal 902H_2 may be current signals. At least one of the transistors T1H-T8H may have different analog offset errors due to process errors, but the present invention is not limited thereto. In some embodiments, the offset control circuit 9225H may also receive the aliasing code 903H to output the same or different offset control signals to control the transistors T5H and T7H, and the offset control circuit 9226H may also receive the aliasing code 904H to output the same or different offset control signals to control the transistors T6H and T8H, so as to provide additional analog offset errors respectively.

[0142] In this embodiment, the first signal 902H_1 flows through the transistors T1H, T3H, T5H, and T7H and is converted into a conversion signal with an analog offset error. The second signal 902H_2 flows through the transistors T2H, T4H, T6H, and T8H and is converted into another conversion signal with an analog offset error. In summary, the output terminal 923H can output a voltage signal of a conversion result with an analog offset error (i.e., a result after the conversion signal is subtracted from another conversion signal) to a back-end comparator (e.g., outputting the aforementioned conversion result to Figure 8The comparator 8227 is used to enable the back-end comparator to perform operations and generate de-identified data. More specifically, by controlling the obfuscation codes 903H and 904H to affect transistors T5H to T8H, the output terminal 923H will output a conversion result with a sufficient privacy level in response to the additional analog offset error. In other words, the present invention can generate an adjustable analog offset error by controlling the obfuscation codes 903H and 904H, and further control the output terminal 923H to output a conversion result with a sufficient privacy level.

[0143] Please refer to Fig.9I , the amplifier circuit can be realized as Fig.9I Circuit architecture shown. In this embodiment, the amplifier circuit 920I includes a signal conversion circuit 921I, a signal operation circuit 922I and a reference current source 924I. The signal conversion circuit 921I includes a signal conversion unit 9211I and a signal conversion unit 9212I. The signal conversion units 9211I and 9212I include de-identification sub-circuits 9213I and 9214I. The signal operation circuit 922I includes de-identification sub-circuits 9221I and 9222I, de-identification offset circuits 9223I and 9224I and offset control circuits 9225I and 9226I. In this embodiment, the de-identification sub-circuits 9213I, 9214I, 9221I and 9222I include transistors T1I to T4I. The de-identification offset circuits 9223I and 9224I include transistors T5I and T6I. In some embodiments, the transistors T1I and T2I are N-type transistors, and the transistors T3I, T4I, T5I, and T6I are P-type transistors, but the present invention is not limited thereto and the design can be adjusted according to actual needs.

[0144] In this embodiment, the transistor T5I is connected in series between the transistor T1I of the de-identification sub-circuit 9213I and the transistor T3I of the de-identification sub-circuit 9221I. The transistor T6I is connected in series between the transistor T2I of the de-identification sub-circuit 9214I and the transistor T4I of the de-identification sub-circuit 9222I.

[0145] In this embodiment, the control terminal of the transistor T1I can receive the first signal 902I_1 of the accumulated data. The second terminal of the transistor T1I can be coupled to the reference current source 924I. The first terminal of the transistor T2I is coupled to the second terminal of the transistor T6I and the output terminal 923I. The control terminal of the transistor T2I can receive the second signal 902I_2 of the accumulated data. The second terminal of the transistor T2I is coupled to the reference current source 924I. The first terminal of the transistor T5I is coupled to the second terminal of the transistor T3I. The control terminal of the transistor T5I is coupled to the offset control circuit 9225I. The second terminal of the transistor T5I is coupled to the first terminal of the transistor T1I, the control terminal of the transistor T3I, and the control terminal of the transistor T4I. The first terminal of the transistor T3I is coupled to the operating voltage VDD. The second terminal of the transistor T3I is coupled to the first terminal of the transistor T5I. The first terminal of the transistor T4I is coupled to the operating voltage VDD. The second terminal of the transistor T4I is coupled to the first terminal of the transistor T6I.

[0146] In some embodiments, the first signal 902I_1 and the second signal 902I_2 may be voltage signals. At least one of the transistors T1I-T6I may have different analog offset errors due to process errors, but the present invention is not limited thereto. In some embodiments, the offset control circuit 9225I may also receive the aliasing code 903I to output a corresponding offset control signal to control the transistor T5I, and the offset control circuit 9226I may also receive the aliasing code 904I to output a corresponding offset control signal to control the transistor T6I, so that additional analog offset errors can be provided respectively.

[0147] In the present embodiment, the transistor T1I is controlled by the first signal 902I_1 to determine the current signal flowing through the transistor T1I, and the current signal flows through the transistors T1I, T3I, and T5I to be converted into a conversion signal having an analog offset error. The transistor T2I is controlled by the second signal 902I_2 to determine another current signal flowing through the transistor T2I, and the other current signal flows through the transistors T2I, T4I, and T6I to be converted into another conversion signal having an analog offset error. In summary, the output terminal 923I can output a voltage signal of a conversion result having an analog offset error (i.e., a result after the conversion signal is subtracted from another conversion signal) to a back-end comparator (e.g., outputting the aforementioned conversion result to Figure 8 The comparator 8227 of FIG. 1 is used to enable the back-end comparator to perform operations and generate de-identified data. More specifically, by controlling the obfuscation codes 903I and 904I to affect the transistors T5I and T6I, the output terminal 923I will output a conversion result with a sufficient privacy level in response to the additional analog offset error. In other words, the present invention can generate an adjustable analog offset error by controlling the obfuscation codes 903I and 904I, and further control the output terminal 923I to output a conversion result with a sufficient privacy level.

[0148] Please refer to Figure 9J , the amplifier circuit can be realized as Figure 9J The circuit architecture shown. In this embodiment, the amplifier circuit 920J includes a signal conversion circuit 921J, a signal operation circuit 922J and a reference current source 924J. The signal conversion circuit 921J includes a signal conversion unit 9211J and a signal conversion unit 9212J. The signal conversion units 9211J and 9212J include de-identification sub-circuits 9213J and 9214J. The signal operation circuit 922J includes de-identification sub-circuits 9221J and 9222J, de-identification offset circuits 9223J and 9224J and offset control circuits 9225J and 9226J. In this embodiment, the de-identification sub-circuits 9213J, 9214J, 9221J and 9222J include transistors T1J to T4J. The de-identification offset circuits 9223J and 9224J include transistors T5J and T6J. In some embodiments, the transistors T1J and T2J are N-type transistors, and the transistors T3J, T4J, T5J, and T6J are P-type transistors, but the present invention is not limited thereto and the design can be adjusted according to actual needs.

[0149] The circuit structure of the amplifier circuit 920J can be referred to Fig.9I More specifically, the architecture of the transistors T1I-T4I of the signal conversion circuit 921I and the signal operation circuit 922I can refer to Fig.9I The signal conversion circuit 921I and the signal operation circuit 922I described above are not described in detail. In this embodiment, the transistor T5J is connected in parallel with the transistor T3J of the de-identification sub-circuit 9221J, and the transistor T6J is connected in parallel with the transistor T4J of the de-identification sub-circuit 9222J.

[0150] It is worth noting that the amplifier circuit 920J of this embodiment is Fig.9I The difference between the embodiments is that the first terminal of transistor T1J is coupled to the second terminal of transistor T3J, the control terminals of transistors T3J, T4J, and T5J, and the second terminal of transistor T5J. The first terminal of transistor T2J is coupled to the second terminal of transistor T4J, the second terminal of transistor T6J, and the output terminal 923J. The first terminal of transistor T5J is coupled to the offset control circuit 9225J. The first terminal of transistor T6J is coupled to the operating voltage VDD and the first terminal of transistor T4J. The control terminal of transistor T6J is coupled to the offset control circuit 9226J.

[0151] In some embodiments, the first signal 902J_1 and the second signal 902J_2 may be voltage signals. At least one of the transistors T1J-T4J may have different analog offset errors due to process errors, but the present invention is not limited thereto. In some embodiments, the offset control circuit 9225J may also receive the aliasing code 903J to output a corresponding offset control signal to control the transistor T5J, and the offset control circuit 9226J may also receive the aliasing code 904J to output a corresponding offset control signal to control the transistor T6J, so that additional analog offset errors can be provided respectively.

[0152] In the present embodiment, the transistor T1I is controlled by the first signal 902I_1 to determine the current signal flowing through the transistor T1I, and the current signal flows through the transistors T1J, T3J, and T5J to be converted into a conversion signal with an analog offset error. The transistor T2J is controlled by the second signal 902J_2 to determine another current signal flowing through the transistor T2J, and the other current signal flows through the transistors T2J, T4J, and T6J to be converted into another conversion signal with an analog offset error. In summary, the output terminal 923J can output a voltage signal of a conversion result with an analog offset error (i.e., the result after the conversion signal is subtracted from the other conversion signal) to a back-end comparator (e.g., outputting the aforementioned conversion result to Figure 8 The comparator 8227 of the embodiment of the present invention is used to enable the back-end comparator to perform operations and generate de-identified data. More specifically, by controlling the obfuscation codes 903J and 904J to affect the transistors T5J and T6J, the output terminal 923J will output a conversion result with a sufficient privacy level in response to the additional analog offset error. In other words, the present invention can generate an adjustable analog offset error by controlling the obfuscation codes 903J and 904J, and further control the output terminal 923J to output a conversion result with a sufficient privacy level.

[0153] Please refer to Figure 9K The amplifier circuits of the various embodiments of the present invention can be implemented as follows: Figure 9K The circuit architecture shown. In this embodiment, the amplifier circuit 920K includes a signal conversion circuit 921K, a signal operation circuit 922K and a reference current source 924K. The signal conversion circuit 921K includes a signal conversion unit 9211K and a signal conversion unit 9212K. The signal conversion units 9211K and 9212K include de-identification sub-circuits 9213K and 9214K. The signal operation circuit 922K includes de-identification sub-circuits 9221K and 9222K, de-identification offset circuits 9223K and 9224K and offset control circuits 9225K and 9226K.

[0154] In this embodiment, the de-identification sub-circuits 9213K, 9214K, 9221K, and 9222K include transistors T1K to T4K. The de-identification offset circuits 9223K and 9224K include transistors T5K and T6K. In some embodiments, transistors T1K and T2K are N-type transistors, and transistors T3K, T4K, T5K, and T6K are P-type transistors, but the present invention is not limited thereto and the design can be adjusted according to actual needs.

[0155] The circuit structure of the amplifier circuit 920K can be referred to Fig.9I , 9J More specifically, the architecture of the transistors T1K to T6K of the signal conversion circuit 921K and the signal operation circuit 922K can refer to Fig.9I , 9J The signal conversion circuits 921I, 921J and the signal operation circuits 922I, 922J described above are not described in detail. In this embodiment, the transistor T5K is connected in series between the transistor T1K of the de-identification sub-circuit 9213K and the transistor T3K of the de-identification sub-circuit 9221K. The transistor T6K is connected in series between the transistor T2K of the de-identification sub-circuit 9214K and the transistor T4K of the de-identification sub-circuit 9222K.

[0156] It is worth noting that the amplifier circuit 920K of this embodiment is Fig.9I , 9J The difference between the embodiments is that the first terminal of the transistor T5K is coupled to the second terminal of the transistor T3K, the control terminal of the transistor T3K and the control terminal of the transistor T4K, and the second terminal of the transistor T5K is coupled to the first terminal of the transistor T1K.

[0157] In some embodiments, the first signal 902K_1 and the second signal 902K_2 may be voltage signals. At least one of the transistors T1K-T6K may have different analog offset errors due to process errors, but the present invention is not limited thereto. In some embodiments, the offset control circuit 9225K may also receive the aliasing code 903K to output a corresponding offset control signal to control the transistor T5K, and the offset control circuit 9226K may also receive the aliasing code 904K to output a corresponding offset control signal to control the transistor T6K, so that additional analog offset errors can be provided respectively.

[0158] In the present embodiment, the transistor T1K is controlled by the first signal 902K_1 to determine the current signal flowing through the transistor T1K, and the current signal flows through the transistors T1K, T3K, and T5K to be converted into a conversion signal with an analog offset error. The transistor T2K is controlled by the second signal 902K_2 to determine another current signal flowing through the transistor T2K, and the other current signal flows through the transistors T2K, T4K, and T6K to be converted into another conversion signal with an analog offset error. In summary, the output terminal 923K can output a voltage signal of a conversion result with an analog offset error (i.e., a result after the conversion signal is subtracted from another conversion signal) to a back-end comparator (e.g., outputting the aforementioned conversion result to Figure 8 The comparator 8227 of the embodiment of the present invention is used to enable the back-end comparator to perform operations and generate de-identified data. More specifically, by controlling the obfuscation codes 903K and 904K to affect the transistors T5K and T6K, the output terminal 923K will output a conversion result with a sufficient privacy level in response to the additional analog offset error. In other words, the present invention can generate an adjustable analog offset error by controlling the obfuscation codes 903K and 904K, and further control the output terminal 923K to output a conversion result with a sufficient privacy level.

[0159] Please refer to Figure 9L , the amplifier circuit can be realized as Figure 9L The circuit architecture shown. In the present embodiment, the amplifier circuit 920L includes a signal conversion circuit 921L, a signal operation circuit 922L and a reference current source 924L. The signal conversion circuit 921L includes signal conversion units 9211L, 9212L and de-identification offset circuits 9223L, 9224L. The signal conversion units 9211L, 9212L include de-identification sub-circuits 9213L, 9214L. The signal operation circuit 922L includes de-identification sub-circuits 9221L, 9222L and offset control circuits 9225L, 9226L. In some embodiments, the offset control circuits 9225L, 9226L may also be disposed in the signal conversion circuit 921L, but the present invention is not limited thereto.

[0160] In this embodiment, the de-identification sub-circuits 9213L, 9214L, 9221L, and 9222L include transistors T1L to T4L. The de-identification offset circuits 9223L and 9224L include transistors T5L and T6L. In some embodiments, the transistors T1L, T2L, T5L, and T6L are N-type transistors, and the transistors T3L and T4L are P-type transistors, but the present invention is not limited thereto and the design can be adjusted according to actual needs.

[0161] The circuit structure of the amplifier circuit 920L can be referred to Figures 9I to 9KMore specifically, the architecture of the transistors T1L to T4L of the signal conversion circuit 921L and the signal operation circuit 922L can refer to Figures 9I to 9K The signal conversion circuits 921I-921K and signal operation circuits 922I-922K described above are not described in detail. In this embodiment, the transistor T5L is connected in parallel with the transistor T1L of the de-identification sub-circuit 9211L. The transistor T6L is connected in parallel with the transistor T2L of the de-identification sub-circuit 9212L.

[0162] It is worth noting that the amplifier circuit 920L of this embodiment is Figures 9I to 9K The difference between the embodiments is that the first end of the transistor T1L is coupled to the first end of the transistor T5L, the second end of the transistor T3L, the control end of the transistor T3L, and the control end of the transistor T4L. The control end of the transistor T1L can receive the first signal 902L_1 of the accumulated data. The second end of the transistor T1L is coupled to the second end of the transistor T5L and the reference current source 924L. The first end of the transistor T2L is coupled to the first end of the transistor T6L, the second end of the transistor T4L, and the output end 923L. The control end of the transistor T2L can receive the second signal 902L_2 of the accumulated data. The second end of the transistor T2L is coupled to the second end of the transistor T6L and the reference current source 924L. The control end of the transistor T5L is coupled to the offset control circuit 9225L of the signal operation circuit 922L. The control end of the transistor T6L is coupled to the offset control circuit 9226L of the signal operation circuit 922L.

[0163] In some embodiments, the first signal 902L_1 and the second signal 902L_2 may be voltage signals. At least one of the transistors T1L-T6L may have different analog offset errors due to process errors, but the present invention is not limited thereto. In some embodiments, the offset control circuit 9225L may also receive the aliasing code 903L to output a corresponding offset control signal to control the transistor T5L, and the offset control circuit 9226L may also receive the aliasing code 904L to output a corresponding offset control signal to control the transistor T6L, so that additional analog offset errors can be provided respectively.

[0164] In this embodiment, the transistor T1L is controlled by the first signal 902L_1 to determine the current signal flowing through the transistor T1L, and the current signal flows through the transistors T1K, T3K, and T5K to be converted into a conversion signal with an analog offset error. The transistor T2L is controlled by the second signal 902L_2 to determine another current signal flowing through the transistor T2L, and the other current signal flows through the transistors T2K, T4K, and T6K to be converted into another conversion signal with an analog offset error. In summary, the output terminal 923L can output a voltage signal of a conversion result with an analog offset error (i.e., a result after the conversion signal is subtracted from another conversion signal) to a back-end comparator (e.g., outputting the aforementioned conversion result to Figure 8 The comparator 8227 of the embodiment of the present invention is used to enable the back-end comparator to perform operations and generate de-identified data. More specifically, by controlling the obfuscation codes 903L and 904L to affect the transistors T5L and T6L, the output terminal 923L will output a conversion result with a sufficient privacy level in response to the additional analog offset error. In other words, the present invention can generate an adjustable analog offset error by controlling the obfuscation codes 903L and 904L, and further control the output terminal 923L to output a conversion result with a sufficient privacy level.

[0165] Please refer to Figure 9M , the amplifier circuit can be realized as Figure 9M Circuit architecture shown. In this embodiment, the amplifier circuit 920M includes a signal conversion circuit 921M, a signal operation circuit 922M and a reference current source 924M. The signal conversion circuit 921M includes a signal conversion unit 9211M, a signal conversion unit 9212M and transistors T5M and T6M of a de-identification offset circuit 9223M and 9224M. The signal conversion units 9211M and 9212M include de-identification sub-circuits 9213M and 9214M. The signal operation circuit 922M includes de-identification sub-circuits 9221M, 9222M, transistors T7M to T10M of de-identification offset circuits 9223M and 9224M and offset control circuits 9225M and 9226M. Among them, the signal conversion circuit 921M and the signal operation circuit 922M may simultaneously include some transistors of the de-identification offset circuits 9223M and 9224M.

[0166] In this embodiment, the de-identification sub-circuits 9213M, 9214M, 9221M, and 9222M include transistors T1M to T4M. The de-identification offset circuit 9223M may include transistors T5M, T7M, and T9M. The de-identification offset circuit 9224M may include transistors T6M, T8M, and T10M. In some embodiments, transistors T1M, T2M, T5M, and T6M are N-type transistors, and transistors T3M, T4M, T7M, T8M, T9M, and T10M are P-type transistors, but the present invention is not limited thereto and the design may be adjusted according to actual needs.

[0167] The circuit structure of the amplifier circuit 920M can be referred to Figures 9I to 9L More specifically, the architecture of the transistors T1M-T4M of the signal conversion circuit 921M and the signal operation circuit 922M can refer to Figures 9I to 9L The signal conversion circuits 921I~921L and signal operation circuits 922I~922L described, similar contents are not repeated. It is worth noting that the transistor T5M is connected in parallel with the transistor T1M of the de-identification sub-circuit 9211M. The transistor T6M is connected in parallel with the transistor T2M of the de-identification sub-circuit 9212M. The transistor T7M is connected in series between the transistor T1M of the de-identification sub-circuit 9213M and the transistor T3M of the de-identification sub-circuit 9221M. The transistor T8H is connected in series between the transistor T2M of the de-identification sub-circuit 9214M and the transistor T4M of the de-identification sub-circuit 9222M. The transistor T9M is connected in parallel with the transistor T3M of the de-identification sub-circuit 9221M, and the transistor T10M is connected in parallel with the transistor T4M of the de-identification sub-circuit 9222M.

[0168] In the present embodiment, the first terminal of the transistor T1M is coupled to the first terminal of the transistor T5M and the second terminal of the transistor T7M. The control terminal of the transistor T1M receives the first signal 902M_1 of the accumulated data. The second terminal of the transistor T1M is coupled to the second terminal of the transistor T5M and the reference current source 924M. The first terminal of the transistor T2M is coupled to the first terminal of the transistor T6M, the second terminal of the transistor T8M and the output terminal 923M. The control terminal of the transistor T2M can receive the second signal 902M_2 of the accumulated data. The second terminal of the transistor T2M is coupled to the second terminal of the transistor T6M and the reference current source 924M. The control terminals of the transistors T5M and T7M and the first terminal of the transistor T9M are coupled to the offset control circuit 9225M. The control terminals of the transistors T6M, T8M and T10M are coupled to the offset control circuit 9226M. The first terminal of the transistor T7M is coupled to the control terminal and the second terminal of the transistor T9M, the second terminal of the transistor T3M, the control terminal of the transistor T3M and the control terminal of the transistor T4M. The first terminal of the transistor T8M is coupled to the second terminal of the transistor T10M and the second terminal of the transistor T4M. The first terminal of the transistor T3M is coupled to the operation voltage VDD. The first terminal of the transistor T4M is coupled to the operation voltage VDD and the first terminal of the transistor T10M.

[0169] In some embodiments, the first signal 902M_1 and the second signal 902M_2 may be voltage signals. At least one of the transistors T1M-T10M may have different analog offset errors due to process errors, but the present invention is not limited thereto. In some embodiments, the offset control circuit 9225M may also receive the aliasing code 903M to output the same or different multiple offset control signals to control the transistors T5M, T7M, and T9M, and the offset control circuit 9226M may also receive the aliasing code 904M to output the same or different multiple offset control signals to control the transistors T6M, T8M, and T10M, so as to provide additional analog offset errors respectively.

[0170] In the present embodiment, the transistor T1M is controlled by the first signal 902M_1 to determine the current signal flowing through the transistor T1M, and the transistor T5M is controlled by the corresponding offset control signal to determine the current signal flowing through the transistor T5M. In this regard, the two current signals are combined and flow through the transistors T3M, T7M, and T9M to be converted into a conversion signal with an analog offset error. The transistor T2M is controlled by the second signal 902M_2 to determine the current signal flowing through the transistor T2M, and the transistor T6M is controlled by the corresponding offset control signal to determine the current signal flowing through the transistor T6M. In this regard, the two current signals are combined and flow through the transistors T4M, T8M, and T10M to be converted into another conversion signal with an analog offset error. In summary, the output terminal 923M can output a voltage signal of a conversion result with an analog offset error (i.e., the result after the conversion signal is subtracted from the other conversion signal) to the back-end comparator (for example, outputting the conversion result to Figure 8 The comparator 8227 is used to enable the back-end comparator to perform operations and generate de-identified data. More specifically, by controlling the obfuscation codes 903M and 904M to affect transistors T5M to T10M, the output terminal 923M will output a conversion result with a sufficient privacy level in response to the additional analog offset error. In other words, the present invention can generate an adjustable analog offset error by controlling the obfuscation codes 903M and 904M, and further control the output terminal 923M to output a conversion result with a sufficient privacy level.

[0171] In addition, it should be noted that FIG. 9A to FIG. 9M The number and position of transistors in the de-identification shift circuit in the embodiment are not limited to those shown in the figure. In some embodiments of the present invention, FIG. 9A to FIG. 9M The transistors of the de-identification shift circuit of the embodiment may also have different number of configurations and / or different configuration positions according to the same or similar design concepts in the above and below. In addition, it should be noted that in some embodiments, the above Figures 9C to 9M At least one of the offset control circuits 9225C, 9225D, 9225F to 9225M, 9226C, 9226D, 9226F to 9226M (wherein Fig.9E The offset control circuit (not shown) can also output one or more fixed offset control signals by default to control the corresponding transistors to generate additional analog offset errors without receiving the external input confusion code.

[0172] Fig.10 FIG. 1 is a schematic diagram of a data computing system 1000 according to an embodiment of the present invention. Fig.10The data operation system 1000 includes an operation circuit 1100 having a de-identification architecture, an input unit 1200, and a processing unit 1300. The operation circuit 1100 is coupled to the input unit 1200 and the processing unit 1300. The operation circuit 1100 includes an operation array 1110 and a de-identification circuit 1120. In this embodiment, the operation array 1110 can receive input data 1001 provided by the input unit 1200, and perform in-memory operation on the input data 1001 to generate accumulated data 1002.

[0173] In this embodiment, the de-identification circuit 1120 can receive the obfuscated code 1003. The de-identification circuit 1120 can calculate the accumulated data 1002 according to the analog offset error, perform de-identification processing on the accumulated data 1002 to generate de-identified data 1004, and then output the de-identified data 1004 to the processing unit 1300. More specifically, the circuit architecture, implementation and technical details of the operation array 1110 and the de-identification circuit 1120 can be referred to in the aforementioned Figures 1 to 9M The description of the embodiments can provide sufficient teachings, suggestions and implementation instructions, so no further details are given.

[0174] In one embodiment, the input unit 1200 may be a sensor, a camera, a microphone, a data storage unit, or a related electronic device that can be used as a data source. In one embodiment, the processing unit 1300 may be a processor, a controller, or a related circuit with data processing functions. In another embodiment, the processing unit 1300 may also be a cloud server, but the present invention is not limited thereto. In some embodiments, the operation circuit 1100, the input unit 1200, and the processing unit 1300 may be integrated into the same electronic device or the same sensor. In another embodiment, the processing unit 1300 may be integrated into a cloud server (Cloud Server), and the operation circuit 1100 may transmit the de-identified data 1004 to the processing unit 1300 via a wired or wireless communication method. In another embodiment, the operation circuit 1100 and the input unit 1200 may be integrated into a cloud server (Cloud Server), and the operation circuit 1100 may transmit the de-identified data 1004 to the processing unit 1300 via a wired or wireless communication method. In another embodiment, the operation circuit 1100 and the input unit 1300 can be integrated in a cloud server (Cloud Server), and the input unit 1200 can transmit the input data 1001 to the operation circuit 1100 through wired or wireless communication methods, and then the operation circuit 1100 in the cloud server performs de-identification operations.

[0175] For example, the operation circuit 1100, the input unit 1200 and the processing unit 1300 can be integrated into the same image sensor. After the image sensor obtains the image data, the image sensor can perform de-identification data processing on the image data in real time to directly output the de-identified image data to a cloud server or other back-end electronic device. Or, for another example, the input unit 1200 can be an image capture device (e.g., a camera), and the operation circuit 1100 and the processing unit 1300 can be integrated in a cloud server. The input unit 1200 can obtain the image data and provide it to the cloud server, so that the cloud server can perform de-identification processing on the image data through the operation circuit 1100 to generate de-identified image data, so as to perform subsequent data application on the de-identified image data.

[0176] Fig.11 This is a flow chart of a data de-identification method according to an embodiment of the present invention. Fig.10 and Fig.11 , the data operation system 1000 may perform the following steps S1110 to S1160. In step S1110, the operation circuit 1100 may obtain the input data 1001 through the input unit 1200. In step S1120, the operation circuit 1100 may perform an accumulation operation on the input data 1001 through the operation array 1110 to generate the accumulated data 1002. In step S1130, the operation circuit 1100 may receive the aliasing code 1003 through the de-identification circuit 1120, and may calculate the accumulated data 1002 according to the analog offset error. The de-identification circuit 1120 may perform a de-identification process on the accumulated data 1002 to generate the de-identified data 1004. In this embodiment, the analog offset error may be provided by the amplifier circuit of the de-identification circuit 1120, and also includes an additional analog offset error generated by the aliasing code. Then, the operation circuit 1100 outputs the de-identified data 1004 to the processing unit 1300.

[0177] In step S1140, the processing unit 1300 may determine whether the privacy level of the de-identified data 1004 is sufficient. When the processing unit 1300 determines that the privacy level of the de-identified data 1004 is sufficient, the processing unit 1300 may proceed to step S1160, and the processing unit 1300 directly outputs the de-identified data 1004. On the contrary, when the processing unit 1300 determines that the privacy level of the de-identified data 1004 is not sufficient, the processing unit 1300 may proceed to step S1150, and the processing unit 1300 may adjust the obfuscation code 1003 input to the de-identification circuit 1120, and re-proceed to step S1130, and the operation circuit 1100 may receive the aforementioned obfuscation code 1003 through the de-identification circuit 1120 again, and may calculate the accumulated data 1002 according to the analog offset error caused by the aforementioned obfuscation code 1003. The de-identification circuit 1120 may re-de-identify the accumulated data 1002 to regenerate the de-identified data 1004 to improve the degree of de-identification. In addition, in another embodiment, the de-identification circuit 1120 may not receive the obfuscation code 1003 or provide a fixed analog offset error with a fixed obfuscation code. In summary, the data operation system 1000 of this embodiment can automatically and effectively perform data de-identification processing.

[0178] In this embodiment, the processing unit 1300 may perform error calculation on the de-identified data 1004 to generate error parameters, wherein the error parameters may be derived and described by the following equations (1) to (4). is the value after error verification. It shows the influence of the process error on at least one transistor in the de-identification circuit 1120 . represents the effect of the offset control on at least one transistor in the de-identification circuit 1120. SAm represents the Gaussian distribution of the effect of the process error on at least one transistor in the de-identification circuit 1120, where the mean is 0 and the variance is 0.03 as an example. CV represents the Gaussian distribution of the effect of the offset control on at least one transistor in the de-identification circuit 1120, where the mean is 0 and the variance is 0.3 as an example. The error parameter is N(0, 0.3571).

[0179]

[0180] SAm=a (x，y) *[1+N(0,0.03)]............Formula (2)

[0181] CV=a (x，y) *[1+N(0,0.3)]............Formula (3)

[0182]

[0183] In this embodiment, the processing unit 1300 may perform an inverse transformation operation of the Gaussian distribution as shown in the following formula (5) on the error parameter N(0, 0.3571) to generate a privacy level. Taking the error parameter N(0, 0.3571) as an example, the processing unit 1300 may calculate the privacy level to be ε=7.5, where the variation δ is 10-5 (δ=10-5), and the variable s is It should be noted that the privacy level is negatively correlated with the degree of data protection, that is, the higher the privacy level, the worse the data protection, and vice versa.

[0184]

[0185] Fig.12 is a schematic diagram of input data and de-identified data according to an embodiment of the present invention. Fig.10 and Fig.12 , the input unit 1200 may obtain the image data 1210, and first perform a binary process on the image data 1210 to generate input data 1220. In some embodiments, the input unit 1200 may provide the input data 1220 to the operation circuit 1100, and the operation circuit 1100 may perform a convolutional neural network (CNN) operation on the input data 1220, but the present invention is not limited thereto.

[0186] like Fig.12 As shown, when no aliasing code is used to generate additional analog offset errors (the aliasing code at this time can be regarded as 0), the operation circuit 1100 can perform de-identification operation on the result (i.e., feature data or feature map) of the input data 1220 after the convolutional neural network operation according to the analog offset error generated by the process error of at least one transistor in the de-identification circuit 1120 during the convolutional neural network operation to generate de-identified data 1231. Accordingly, the de-identified data 1231 can have fewer image features than the image data 1210 and the input data 1220, that is, it has a reduced identifiable effect.

[0187] In contrast, when the obfuscation code is used to generate additional analog offset errors, the operation circuit 1100 may perform a de-identification operation on the result (i.e., feature data or feature map) of the convolutional neural network operation of the input data 1220 according to the process error of at least one transistor in the de-identification circuit 1120 and the analog offset error generated by at least another transistor after error offset control during the convolutional neural network operation to generate de-identified data 1232. Accordingly, the de-identified data 1232 may have fewer image features than the image data 1210, the input data 1220, and the de-identified data 1231, i.e., the de-identified data 1231 is reduced to a lower degree of identifiability. For example, the privacy level of the de-identified data 1232 may be, for example, ε=7.5.

[0188] At the same time, if the privacy level is to be increased, the degree of de-identification (ie, image blur) can be increased by adjusting the obfuscation code input to the de-identification circuit 1120. Fig.12 As shown, the operation circuit 1100 can perform a de-identification operation on the result of the convolutional neural network operation of the input data 1220 in combination with the setting of the obfuscation code to generate de-identified data 1233. Accordingly, the de-identified data 1233 can have fewer image features than the image data 1210, the input data 1220, and the de-identified data 1231 and 1232, that is, the degree of identifiability of the de-identified data 1231 and 1232 is reduced to a lower level. For example, the privacy level of the de-identified data 1233 can be, for example, ε=4.4. In other words, the data operation system 1000 of this embodiment can achieve a good data de-identification function, and can also provide a function of dynamically adjusting the privacy level.

[0189] In summary, the computing circuit, data computing method, data processing system and data de-identification method with a de-identification architecture of the present invention can effectively de-identify data through analog offset errors generated by the circuit component manufacturing process. Furthermore, additional analog offset errors can be provided by the de-identification offset circuit to increase the degree of de-identification of data.

[0190] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A computing circuit with a de-identification architecture, characterized in that: include: The operation array performs accumulation operation on the input data to generate accumulated data; and A de-identification circuit is coupled to the operation array and has an analog offset error determined based on an analog physical non-copyable function. The de-identification circuit operates the accumulated data according to the analog offset error to generate de-identified data.

2. The operation circuit according to claim 1, characterized in that: The operation array includes a plurality of in-memory operation units, and the plurality of in-memory operation units are used to receive the input data and perform in-memory operation.

3. The operation circuit according to claim 1, characterized in that: The de-identification circuit comprises: an amplifier circuit coupled to the operational array, wherein the amplifier circuit comprises at least one transistor, The analog offset error includes at least one error coefficient provided by the at least one transistor.

4. The operation circuit according to claim 3, characterized in that: The amplifier circuit comprises: a signal conversion circuit coupled to the operational array and comprising a first signal conversion unit and a second signal conversion unit, wherein the first signal conversion unit has a first de-identification sub-circuit and is coupled to the operational array via a first input terminal of the amplifier circuit, and the second signal conversion unit has a second de-identification sub-circuit and is coupled to the operational array via a second input terminal of the amplifier circuit; and The signal operation circuit includes a third de-identification sub-circuit, a fourth de-identification sub-circuit and a comparator, wherein the third de-identification sub-circuit is coupled to the signal conversion circuit and the comparator, and the fourth de-identification sub-circuit is coupled to the signal conversion circuit and the comparator.

5. The operation circuit according to claim 4, characterized in that: The first de-identification sub-circuit receives a first signal of the accumulated data and outputs a first conversion signal to the first de-identification sub-circuit, The second de-identification sub-circuit receives a second signal of the accumulated data and outputs a second conversion signal to the second de-identification sub-circuit, The third de-identification sub-circuit and the fourth de-identification sub-circuit output conversion results to the comparator according to the first conversion signal and the second conversion signal, so that the comparator generates the de-identification data according to the conversion results.

6. The operation circuit according to claim 5, characterized in that: The first de-identification sub-circuit includes a first transistor, the second de-identification sub-circuit includes a second transistor, the third de-identification sub-circuit includes a third transistor, and the fourth de-identification sub-circuit includes a fourth transistor. The first terminal of the first transistor is coupled to the third transistor, and the second terminal or the control terminal of the first transistor receives the first signal. The first terminal of the second transistor is coupled to the fourth transistor, and the second terminal or the control terminal of the second transistor receives the second signal. A first terminal of the third transistor is coupled to an operating voltage, a second terminal of the third transistor is coupled to the first terminal of the first transistor, and A first terminal of the fourth transistor is coupled to the operation voltage, and a second terminal of the fourth transistor is coupled to the first terminal of the second transistor.

7. The operation circuit according to claim 6, characterized in that: The control terminal of the first transistor receives a first clamping voltage, and the second terminal of the first transistor receives the first signal. The control terminal of the second transistor receives a second clamping voltage, and the second terminal of the second transistor receives the second signal. The control end of the third transistor is coupled to the second end of the third transistor, and the control end of the fourth transistor is coupled to the second end of the fourth transistor.

8. The operation circuit according to claim 6, characterized in that: The control terminal of the first transistor receives a first clamping voltage, and the second terminal of the first transistor receives the first signal. The control terminal of the second transistor receives a second clamping voltage, the second terminal of the second transistor receives the second signal, and The control terminal of the third transistor is coupled to the second terminals of the three transistors and the control terminal of the fourth transistor.

9. The operation circuit according to claim 6, characterized in that: The control terminal of the first transistor receives a first signal, and the second terminal of the first transistor is coupled to a reference current source. The control terminal of the second transistor receives a second signal, the second terminal of the second transistor is coupled to the reference current source, and The control terminal of the third transistor is coupled to the second terminals of the three transistors and the control terminal of the fourth transistor.

10. The operation circuit according to claim 6, characterized in that: The first transistor and the second transistor are N-type transistors, and the third transistor and the fourth transistor are P-type transistors.

11. The operation circuit according to claim 4, characterized in that: At least one of the signal conversion circuit and the signal operation circuit further includes a de-identification offset circuit, wherein the de-identification offset circuit includes at least one fifth transistor, and The analog offset error includes at least one other error coefficient provided by the at least one fifth transistor.

12. The operation circuit according to claim 11, characterized in that: The de-identification offset circuit is connected in series between the first de-identification sub-circuit and the third de-identification sub-circuit, and the de-identification offset circuit is connected in series between the second de-identification sub-circuit and the fourth de-identification sub-circuit.

13. The operation circuit according to claim 11, characterized in that: The de-identification offset circuit is connected in parallel with the first de-identification sub-circuit, and the de-identification offset circuit is connected in parallel with the second de-identification sub-circuit.

14. The operation circuit according to claim 11, characterized in that: The de-identification offset circuit is connected in parallel with the third de-identification sub-circuit, and the de-identification offset circuit is connected in parallel with the fourth de-identification sub-circuit.

15. The operation circuit according to claim 11, characterized in that: The de-identification offset circuit includes a plurality of fifth transistors, and the plurality of fifth transistors are connected in parallel.

16. The operation circuit according to claim 11, characterized in that: The de-identification offset circuit includes a plurality of fifth transistors, and the plurality of fifth transistors are connected in series.

17. The operation circuit according to claim 11, characterized in that: The signal operation circuit further includes an offset control circuit, wherein the offset control circuit is coupled to the at least one fifth transistor. The offset control circuit outputs at least one offset control signal to the at least one fifth transistor to determine the at least another error coefficient.

18. The operation circuit according to claim 17, characterized in that: The offset control circuit receives a scrambled code, and the offset control circuit determines the at least one offset control signal according to the scrambled code.

19. The operation circuit according to claim 18, characterized in that: The analog offset error includes an analog offset error additionally generated by the aliasing code.

20. The operation circuit according to claim 1, characterized in that: The de-identification circuit receives an obfuscated code, and the de-identification circuit generates an additional analog offset error according to the obfuscated code.

21. A de-identified data computing method, characterized in that: include: Performing accumulation operation on input data through the operation array to generate accumulated data; and The accumulated data is operated by a de-identification circuit according to an analog offset error to generate de-identified data, The analog offset error is determined based on an analog physical non-copyable function of the de-identification circuit.

22. The data operation method according to claim 21, characterized in that: The steps of generating the de-identified data include: The de-identification circuit operates the accumulated data according to the analog offset error and at least one aliasing code to generate the de-identified data.

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