Binary translation method, binary translator, electronic device and readable storage medium

Abstract

The embodiment of the present invention provides a binary translation method, a binary translator, an electronic device and a readable storage medium, the method comprising: when translating an indirect jump instruction in a client program, obtaining the thread mode of the client program; generating a target search code sequence according to the thread mode; wherein different thread modes correspond to different target search code sequences; the target search code sequence is used to search a target jump table based on the jump target address of the indirect jump instruction to obtain the cache start address of the translated basic block corresponding to the jump target address; if the target search code sequence is successfully searched, then jump to the cache start address of the translated basic block corresponding to the jump target address. The embodiment of the present invention can optimize the translation of the indirect jump instruction, improve the efficiency of searching the indirect jump table, and thus improve the running efficiency of the translated program.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a binary translation method, a binary translator, an electronic device and a readable storage medium. Background Art

[0002] Binary translation can convert the binary code of one ISA (Instruction Set Architecture) into the binary code of another instruction set architecture. Through binary translation technology, an application of one ISA (source architecture) can run on another ISA (target architecture).

[0003] An indirect jump instruction means that the target address of the instruction jump is not a fixed address, but is determined by the value in the register or memory during operation. In binary translation, an indirect jump table can be used to implement indirect jump instructions; specifically, an indirect jump table is a data structure with a small capacity and a fast search speed, usually a hash table. Using an indirect jump table, the jump target address is used as the key, and the most recently used translated code block is stored as the value. In this way, when the same jump target address is encountered again, the corresponding translated code block can be quickly obtained directly from the indirect jump table, avoiding repeated translation and improving translation efficiency. The process of searching the indirect jump table directly affects the efficiency of binary translation. Summary of the invention

[0004] In view of the above problems, an embodiment of the present invention is proposed to provide a binary translation method that overcomes the above problems or at least partially solves the above problems, which can optimize the translation of indirect jump instructions, improve the efficiency of searching the indirect jump table, and further improve the running efficiency of the translated program.

[0005] Correspondingly, the embodiment of the present invention also provides a binary translator, an electronic device, and a computer program product to ensure the implementation and application of the above method.

[0006] In a first aspect, an embodiment of the present invention discloses a binary translation method, which is applied to a binary translator. The method includes:

[0007] When translating an indirect jump instruction into a client program, obtaining a thread mode of the client program;

[0008] Generate a target search code sequence according to the thread mode; the target search code sequence is used to search a target jump table based on the jump target address of the indirect jump instruction to obtain a cache start address of a translated basic block corresponding to the jump target address; wherein different thread modes correspond to different target search code sequences;

[0009] If the target search code sequence is successfully found, the jump is made to the cache start address of the translated basic block corresponding to the jump target address.

[0010] In a second aspect, an embodiment of the present invention discloses a binary translator, the binary translator comprising:

[0011] A thread mode acquisition module, used for acquiring the thread mode of the client program when translating an indirect jump instruction into the client program;

[0012] A code sequence generation module, used for generating a target search code sequence according to the thread mode; the target search code sequence is used for searching a target jump table based on the jump target address of the indirect jump instruction to obtain a cache start address of a translated basic block corresponding to the jump target address; wherein different thread modes correspond to different target search code sequences;

[0013] The target address jump module is used to jump to the cache start address of the translated basic block corresponding to the jump target address if the target search code sequence is successfully found.

[0014] In the third aspect, an embodiment of the present invention discloses an electronic device, comprising: a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction enables the processor to execute the steps of the binary translation method as described in any of the above.

[0015] In a fourth aspect, an embodiment of the present invention discloses a readable storage medium, on which a program or instruction is stored, and when the program or instruction is executed by a processor, the binary translation method as described in any of the above can be implemented.

[0016] In a fifth aspect, an embodiment of the present invention discloses a computer program product, including a computer program, which, when executed by a processor, performs the steps of any of the aforementioned binary translation methods.

[0017] The embodiments of the present invention include the following advantages:

[0018] In the binary translation process, when translating an indirect jump instruction into a client program, the embodiment of the present invention dynamically obtains the thread mode of the client program, such as a single-thread mode or a multi-thread mode. According to the current thread mode of the client program, a corresponding target search code sequence is generated. According to different thread modes, the embodiment of the present invention generates different target search code sequences, and different target search code sequences use different target jump tables. By designing different fast search tables (such as a first jump table and a second jump table) for different thread modes, the translation of the indirect jump instruction is optimized. Since there are differences in execution characteristics and resource competition between single-thread programs and multi-thread programs, the jump conditions to be satisfied by the fast search are also different. Therefore, using different fast search strategies for different thread modes to optimize the execution of the indirect jump instruction can bring significant performance improvement. For example, for the single-thread mode, a simpler and faster target jump table can be used to further improve the efficiency of searching for "the cache start address of the translated basic block corresponding to the jump target address of the indirect jump instruction". Therefore, through the embodiments of the present invention, for single-threaded programs and multi-threaded programs in the single-threaded stage, more concise instructions can be used to optimize translation, improve the efficiency of searching the indirect jump table, and then improve the operating efficiency of the translated program, thereby improving the performance of the translation system. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a schematic diagram of a binary translation architecture of the present invention;

[0020] Figure 2 is a flowchart of a binary translation method embodiment of the present invention;

[0021] Figure 3 It is a schematic diagram of the present invention using the target search code sequence as a common code sequence;

[0022] Figure 4 is a structural block diagram of a binary translator embodiment of the present invention;

[0023] Figure 5 It is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0024] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0025] The terms "first", "second", etc. in the specification and claims of the present invention are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable when appropriate, so that the embodiments of the present invention can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, the term "and / or" in the specification and claims is used to describe the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. In the embodiments of the present invention, the term "multiple" refers to two or more, and other quantifiers are similar.

[0026] Binary translation technology can solve the problem of binary-level applications running across instruction set architectures. Specifically, binary translation technology can convert instruction sequences in one instruction set architecture into instruction sequences in another instruction set architecture.

[0027] Reference Figure 1 , shows a schematic diagram of a binary translation architecture, which includes a disassembler, an optimizer, a translator, and an assembler. First, the source program is input into the disassembler for disassembly and cutting into basic blocks, and the information of each instruction in each basic block is obtained; the optimizer analyzes the information obtained after disassembly, finds out the possible instruction sequences to be optimized, and marks them; the translator translates each instruction according to the information obtained after disassembly, and performs some optimizations during the translation process with the assistance of the marking information provided by the optimizer; the optimized translated instructions are finally sent to the assembler for assembly. A basic block (Translation Block, TB) usually ends with a control flow changing instruction (such as an indirect jump instruction, a function call instruction, etc.).

[0028] In an embodiment of the present invention, the source platform is also referred to as a client platform, and the target platform is also referred to as a host platform or a local platform. The processor of the source platform may be a processor based on a first instruction set architecture. The processor of the target platform may be a processor based on a second instruction set architecture. The second instruction set architecture is a different instruction set architecture from the first instruction set architecture.

[0029] Binary translation includes static binary translation and dynamic binary translation. Static binary translation is to translate binary program A (source program) on the source platform before it is executed, so as to translate binary program A into binary program B (target program) on the target platform. Dynamic binary translation is to translate the executed code fragments when the binary program is running. The binary translation method of the embodiment of the present invention can be applied to the scenario of dynamic binary translation, and the binary translator of the embodiment of the present invention refers to a dynamic binary translator.

[0030] Dynamic binary translation refers to the translation of the executed fragments when translating and executing the client program on the host platform (HOST platform), translating the guest instructions (GUEST instructions) into TB of host instructions (HOST instructions) in TB units, saving them in the code cache, and then executing the translated TB. A TB usually ends with a control flow change instruction (such as an indirect jump instruction, a function call instruction, etc.).

[0031] Reference Figure 2 , shows a flowchart of a binary translation method embodiment of the present invention, the method is applied to a binary translator, and the method may include the following steps:

[0032] Step 101: when translating an indirect jump instruction into a client program, obtaining the thread mode of the client program;

[0033] Step 102: Generate a target search code sequence according to the thread mode; the target search code sequence is used to search a target jump table based on the jump target address of the indirect jump instruction to obtain a cache start address of a translated basic block corresponding to the jump target address; wherein different thread modes correspond to different target search code sequences;

[0034] Step 103: If the target search code sequence is successfully found, jump to the cache start address of the translated basic block corresponding to the jump target address.

[0035] The binary translation method provided by the embodiment of the present invention can be applied to a dynamic binary translator to optimize the execution efficiency of indirect jump instructions during the binary translation process.

[0036] In the binary translation process, when translating an indirect jump instruction into a client program, the embodiment of the present invention dynamically obtains the thread mode of the client program, such as a single-thread mode or a multi-thread mode.

[0037] According to the current thread mode of the client program, a corresponding target search code sequence is generated, wherein the target search code sequence is used to search a target jump table based on the jump target address of the indirect jump instruction to obtain a cache start address of a translated basic block corresponding to the jump target address.

[0038] The target search code sequence is a binary code based on the second instruction set architecture. In a specific implementation, the client program can be run on the client platform using a source binary code. The source binary code is a code based on the first instruction set architecture. A binary translator can translate the source binary code into a target binary code, which is a code based on the second instruction set architecture, so that the target binary code can be run on the client platform.

[0039] In the embodiment of the present invention, the untranslated basic block is referred to as the client basic block. After translating the client basic block, a translated host code instruction stream (referred to as a translated basic block) is obtained, and the translated basic block is stored in the code cache. The cache start address of the translated basic block refers to the start address of the translated basic block in the code cache obtained after translating the client basic block.

[0040] The jump target address of the indirect jump instruction is dynamically determined by the value in the register or memory when the program is running, and is a client virtual address.

[0041] The target jump table is a data structure with a small capacity and a fast search speed, such as a hash table. The target jump table is used to cache the corresponding relationship between the jump target address and the translated basic block of the indirect jump instruction recently executed by the current CPU, so as to obtain the cache start address of the translated basic block corresponding to the jump target address, that is, the start address of the translated basic block in the code cache area.

[0042] In an embodiment of the present invention, different thread modes may correspond to different target search code sequences. The target search code sequence is used to search the target jump table based on the jump target address of the indirect jump instruction to obtain the cache start address of the translated basic block corresponding to the jump target address. In different thread modes, different target jump tables may be used, and the methods of searching the cache start address of the translated basic block corresponding to the jump target address are different.

[0043] If the target search code sequence fails to search, a common search code sequence is executed, and the common search code sequence is used to perform a slow search based on the jump target address of the indirect jump instruction. In an embodiment of the present invention, the target search code sequence is used to perform a fast search based on the target jump table, and the common search code sequence is used to perform a slow search based on the translation block table. The slow search refers to searching for the cache start address of the translated basic block corresponding to the jump target address based on the translation block table, and the translation block table is used to record the cache start addresses of all translated basic blocks.

[0044] During the binary translation process, the binary translator translates the client instructions in the client program in basic blocks to obtain translated basic blocks. The instructions in the translated basic blocks are host machine instructions. The information of these translated basic blocks is stored in a data structure so that it can be searched and used later. This data structure is called a translation block table.

[0045] The table entries of the target jump table are composed of the most recently used table entries in the translation block table. Each table entry in the translation block table may include a cache start address of a translated basic block, a structure pointer of the translated basic block, and other related information.

[0046] The translation block table is used to comprehensively record all translated basic block information to ensure the integrity of the information; while the target jump table focuses on improving the search speed and is used to store the most recently hit basic block information, using the locality principle of the program to reduce the search time.

[0047] When the binary translation system is started, the translation block table can be initialized as an empty data structure for subsequent storage of information of all translated basic blocks. The information of the translated basic blocks stored in the translation block table may include: the virtual address of the client basic block in the client program (referred to as the client virtual address), and the starting address of the translated basic block in the code cache of the host machine (referred to as the host machine virtual address). The translation block table can be an array, a linked list, or a tree structure, etc., depending on the design and requirements of the system.

[0048] The target jump table can also be initialized when the system starts. The target jump table can select an efficient data structure, such as a hash table, to support fast search operations. Initially, the target jump table is also empty, and as the binary translation is executed, it is gradually filled with the information of the most recently hit translated basic blocks.

[0049] Since the translation block table is used to record the information of all translated basic blocks, it will be completely recorded regardless of whether the translated basic block will be frequently accessed later. The target jump table will prioritize the information of the most recently translated or most recently hit translated basic blocks so that it can be quickly searched later.

[0050] In the embodiment of the present invention, the target jump table (such as the first jump table and the second jump table) is also called a fast lookup table or an indirect jump table, and the translation block table is also called a slow lookup table.

[0051] Furthermore, the embodiment of the present invention generates different target search code sequences for different thread modes, and different target search code sequences use different target jump tables. Exemplarily, the binary translator can maintain a pointer variable for pointing to the target jump table. Under different thread modes (such as single-thread mode or multi-thread mode), the pointer variable points to different target jump tables.

[0052] The embodiment of the present invention optimizes the translation of indirect jump instructions by designing different fast lookup tables (such as a first jump table and a second jump table) for different thread modes. Since there are differences in execution characteristics and resource competition between single-threaded programs and multi-threaded programs, the jump conditions to be satisfied by fast lookups are also different. Therefore, using different fast lookup strategies for different thread modes to optimize the execution of indirect jump instructions can bring significant performance improvements. For example, for a single-threaded mode, a simpler and faster target jump table can be used to further improve the efficiency of searching for "the cache start address of the translated basic block corresponding to the jump target address of the indirect jump instruction".

[0053] The target jump table can be established at the beginning of translating the client program. For example, after reading the binary file of the client program from a storage medium (such as a hard disk, a flash memory, etc.), the target jump table is established when the translation begins, and the target jump table is continuously inserted or deleted during the translation process. Exemplarily, the table entries of the target jump table are composed of the most recently used table entries in the translation block table. The update strategy of the target jump table can be based on the least recently used (Least Recently Used, LRU) principle or other similar strategies. When a translated basic block is hit, its corresponding table entry information can be added to the target jump table. If the target jump table is full, the table entry that has not been used for the longest time is replaced.

[0054] In an optional embodiment of the present invention, generating a target search code sequence according to the thread mode may include:

[0055] If the thread mode is a single-thread mode, a first search code sequence is generated; the first search code sequence is used to search a first jump table based on the jump target address of the indirect jump instruction; the first jump table contains a mapping relationship between the jump target address and the cache start address of the translated basic block.

[0056] In a specific implementation, if the thread mode of the client program is a single-thread mode, a basic block will only be executed by a single thread, and there is no situation where the basic block will be modified by other threads. Therefore, in the single-thread mode, the condition for the first search code sequence to successfully search only needs to meet the jump target address of the indirect jump instruction hitting the target jump table. Therefore, in the single-thread mode, a simpler and faster first jump table can be used.

[0057] Referring to Table 1, a schematic diagram of a first jump table in an embodiment of the present invention is shown.

[0058] Table 1

[0059]

[0060] As shown in Table 1, the key of the first jump table is the jump target address of the indirect jump instruction, that is, the starting address of the target basic block (a client basic block) to which the indirect jump instruction is to jump, and the starting address is a client virtual address. The value of the first jump table is the cache starting address of the translated basic block obtained after the client basic block is translated, which is a host virtual address. In single-threaded mode, when an indirect jump instruction is translated, the first jump table is searched based on the jump target address of the indirect jump instruction to obtain the cache starting address of the translated basic block corresponding to the jump target address.

[0061] Further, if the target search code sequence is successfully searched, jumping to the cache start address of the translated basic block corresponding to the jump target address may include:

[0062] If the jump target address hits the first jump table, the first search code sequence is successfully searched and jumps to the cache start address of the translated basic block corresponding to the jump target address.

[0063] In single-threaded mode, when an indirect jump instruction is translated, the jump target address of the indirect jump instruction is used as the key to search the first jump table. If the jump target address hits the first jump table, it is considered that the first search code sequence has successfully searched, and the value of the hit table entry is directly taken out as the jump target for jumping. If it does not hit, it is considered that the first search code sequence has failed to search, and the slow search logic is executed.

[0064] In an optional embodiment of the present invention, generating a target search code sequence according to the thread mode may include:

[0065] If the thread mode is a multi-thread mode, a second search code sequence is generated; the second search code sequence is used to search a second jump table based on the jump target address of the indirect jump instruction; the second jump table contains a mapping relationship between the jump target address and the structure pointer of the translated basic block; the structure pointer of the translated basic block points to the structure of the translated basic block, and the structure of the translated basic block contains the cache start address of the translated basic block and the status information of the translated basic block.

[0066] In a specific implementation, if the thread mode of the client program is a multi-threaded mode, a basic block may be executed by multiple threads, and there may be a situation where the basic block will be modified by other threads. For example, after the translation of the client basic block A is completed, the translated basic block A is obtained. Thread 1 modifies the client basic block A through self-modification code, such as modifying it to the client basic block A', and invalidates the translated basic block A. When thread 2 executes an indirect jump instruction, if the jump target address of the indirect jump instruction is the starting address of the client basic block A, since the translated basic block A has been invalidated, if the cached starting address of the translated basic block A recorded in the target jump table is directly used, it will lead to the execution of an invalidated basic block, which will cause an error.

[0067] Therefore, in multi-threaded mode, the conditions for the successful search of the second search code sequence include not only that the jump target address of the indirect jump instruction hits the target jump table, but also that the status information of the hit translated basic block needs to be judged. Only when the status information meets the jump condition, the quick search is considered successful.

[0068] Referring to Table 2, a schematic diagram of a second jump table in an embodiment of the present invention is shown.

[0069] Table 2

[0070]

[0071] As shown in Table 2, the key of the second jump table is the jump target address of the indirect jump instruction, such as the starting address of a client basic block, which is a client virtual address. The value of the second jump table is the structure pointer of the translated basic block obtained after the client basic block is translated. The structure pointer of the translated basic block (such as TB1ptr) points to the structure of the translated basic block (such as the translated basic block TB1), and the structure of the translated basic block contains the cache starting address of the translated basic block and the status information of the translated basic block.

[0072] In the multi-threaded mode, when an indirect jump instruction is translated, the second jump table is searched based on the jump target address of the indirect jump instruction to obtain the cache start address of the translated basic block.

[0073] Furthermore, if the target search code sequence is successfully searched, jumping to the cache start address of the translated basic block corresponding to the jump target address may include:

[0074] If the jump target address of the indirect jump instruction hits the second jump table, determining whether the state information of the translated basic block that hits satisfies the jump condition;

[0075] If the state information of the hit translated basic block meets the jump condition, the second search code sequence searches successfully, obtains the cache start address of the hit translated basic block from the structure of the hit translated basic block, and jumps.

[0076] In multi-threaded mode, the second jump table is first searched based on the jump target address of the indirect jump instruction. If the jump target address of the indirect jump instruction hits the second jump table, it is necessary to further determine whether the status information of the hit translated basic block meets the jump condition. If the jump condition is met, the second search code sequence is considered to have successfully searched, and the cache start address of the hit translated basic block is obtained from the structure of the hit translated basic block, and a jump is performed.

[0077] If the jump target address of the indirect jump instruction does not hit the second jump table, or the status information of the translated basic block that hits does not meet the jump condition, it is considered that the second search code sequence fails to search, and the slow search logic is executed.

[0078] In an optional embodiment of the present invention, the state information may include a valid flag bit, and the determining whether the state information of the hit translated basic block satisfies the jump condition may include:

[0079] It is determined whether the valid flag is valid; if the valid flag is valid, it is determined that the state information of the hit translated basic block meets the jump condition.

[0080] In multi-threaded mode, if there is self-modifying code, the basic block executed by multiple threads together may be invalidated after being modified, so it is necessary to determine whether the state information of the translated basic block meets the jump condition. For example, it is determined whether the valid flag bit of the translated basic block meets the jump condition. If the valid flag bit is valid, it means that the translated basic block is consistent with the client basic block and the client basic block has not been modified. The translated basic block can be used to determine whether the state information of the translated basic block meets the jump condition.

[0081] It should be noted that the state information includes but is not limited to the valid flag bit of the translated basic block, and may also include other states or flags, which may represent information such as the CPU state, characteristics or context relied upon in the translation process. For example, the jump condition may also include that these state or flag information matches the target basic block currently to be jumped to.

[0082] In an optional embodiment of the present invention, the method may further include:

[0083] When starting to translate the client program, setting the thread mode flag of the client program to single thread mode;

[0084] When translating to a system call function for creating a thread, updating the thread mode mark of the client program from a single-thread mode to a multi-thread mode;

[0085] When the system call function of the exit thread is translated, the thread mode flag of the client program is updated from the multi-thread mode to the single-thread mode.

[0086] The thread mode is used to indicate whether the client program is a single-thread program or a multi-thread program. The single-thread mode indicates that the client program is a single-thread program, and the multi-thread mode indicates that the client program is a multi-thread program.

[0087] When a multithreaded program starts, like most programs, initially only one thread is executing, which is called the main thread. The main thread is the entry point of the program and is responsible for the initialization of the program, such as loading necessary libraries, allocating initial resources, parsing command line parameters, etc. The execution of the main thread starts from the program's main function (in C / C++) or a similar entry function.

[0088] When the main thread executes the code that needs to create a new thread, a thread can be created through the corresponding system call. Creating a thread refers to creating a child thread. For example, in the Linux system, a child thread can be created through the clone system call. If a single-threaded client program creates a child thread through the clone system call, the client program changes from a single-threaded program to a multi-threaded program. The child thread created by the clone system call shares some resources with the main thread, such as code segments, global variables, etc., and at the same time has its own independent resources, such as stack space, register status, etc. This sharing and independence mechanism allows threads to collaborate efficiently while ensuring a certain degree of independence.

[0089] System calls are interfaces between applications and operating systems, and key operations such as thread creation need to be completed through system calls. Therefore, the embodiment of the present invention monitors and analyzes the behavior of the client program during its operation, and can dynamically analyze the current thread mode of the client program by monitoring system calls.

[0090] For the binary translator, when a client program is translated, the thread mode of the client program is set to single-thread mode by default. This is because at the beginning of the program startup, there is only one main thread executing, and at this time, the thread mode flag of the client program can be set to single-thread mode. For example, after reading the binary file of the client program from a storage medium (such as a hard disk, flash memory, etc.), when the translation starts, the thread mode flag of the client program is set to single-thread mode.

[0091] Further, the obtaining the thread mode of the client program may include:

[0092] The thread mode of the client program is obtained by reading the thread mode flag.

[0093] During the translation process, the binary translator can scan and analyze the client program code. When translating to a system call function that creates a child thread (such as clone), the thread mode mark of the client program is updated from single-thread mode to multi-thread mode. When translating to a system call function that exits a thread (such as exit in the Linux system), the thread mode mark of the client program is updated from multi-thread mode to single-thread mode. When translating to an indirect jump instruction, the thread mode of the client program can be obtained in real time by reading the thread mode mark.

[0094] The binary translation method provided by the embodiment of the present invention selects different target jump tables based on the current thread mode of the client program and executes different optimization methods. For single-threaded programs and multi-threaded programs in single-threaded mode, a more concise host machine instruction (such as a first search code sequence) can be used to optimize the translation of indirect jump instructions, improve the efficiency of executing indirect jump instructions, and thus improve binary translation performance.

[0095] In an optional embodiment of the present invention, the method may further include:

[0096] When it is monitored that the thread mode of the client program is updated from the single-thread mode to the multi-thread mode, all cached translated basic blocks are invalidated.

[0097] In the embodiment of the present invention, different target jump tables are used in the single-thread mode and the multi-thread mode. If the client program switches the thread mode during operation, the single-thread mode is changed to the multi-thread mode. If the target jump table (such as the first jump table) in the single-thread mode is continued to be used at this time, it may cause a program execution error. Therefore, it is necessary to invalidate all translated basic blocks of the cache and then translate them again.

[0098] The embodiment of the present invention does not limit the method for invalidating all translated basic blocks in the cache. For example, the valid flag bits of all translated basic blocks in the cache can be set to invalid. Alternatively, all fast lookup tables (such as the first jump table and the second jump table) and slow lookup tables (such as the translation block table) can be cleared.

[0099] In a specific implementation, when monitoring that the client program is updated from single-thread mode to multi-thread mode, all translated basic blocks are invalidated to prevent program execution errors caused by subsequent use of the first jump table optimized by the present invention.

[0100] In the Linux system, a multi-threaded client program can exit the thread through the exit system call, and the client program may change from a multi-threaded program to a single-threaded program. In the embodiment of the present invention, considering the overall performance of the program, if a multi-threaded program becomes a single-threaded program during operation, the translation optimization method in the single-threaded mode of the present invention may no longer be used for optimization.

[0101] There may be two situations when the client program changes from multi-threaded mode to single-threaded mode. One situation is that the client program exits, and it may exit thread by thread. In this case, the client program is executing the exit logic, so there is no need to use the optimization logic in the single-threaded mode. Another situation is that a multi-threaded program frequently switches back and forth between multi-threaded and single-threaded. In this case, frequent clearing of the fast lookup table and the slow lookup table will lead to frequent re-translation, which may affect the overall performance of the program. Therefore, when the client program changes from multi-threaded mode to single-threaded mode, it is not necessary to invalidate all cached translated basic blocks, that is, it is not necessary to clear the fast lookup table and the slow lookup table, and the simpler fast lookup table (first lookup table) is no longer used. Only when the single-threaded program and the multi-threaded program are changed to the single-threaded program for the first time, the first jump table is used for optimized translation, and the efficiency of executing indirect jump instructions is improved while ensuring the overall performance of the program, and the binary translation performance is improved.

[0102] It is understandable that, in a specific implementation, when the client program changes from a multi-threaded mode to a single-threaded mode, it can be selected whether to use the first jump table to perform translation optimization on the indirect jump instruction according to actual needs.

[0103] In a specific implementation, when the target search code sequence searches for the target jump table, it is necessary to use one or more conditional branch instructions (such as if-else statements, etc.) to determine whether the search is successful. Conditional branch instructions usually have two execution paths, namely, the branch is taken (taken) or not taken (not taken). When the condition of the conditional branch instruction is met, the program will jump to the specified target address to continue execution. This situation is called the branch is "taken", that is, the branch is taken or the jump operation is performed. For example, for the JZ (Jump if Zero) instruction, if the current zero flag is 1 (indicating that the result is zero), then the program will jump to the target address specified by the JZ instruction, and the conditional branch is in the "taken" state. When the condition of the conditional branch instruction is not met, the program will not jump, but continue to execute the next instruction sequentially. This situation is called the branch "not taken", that is, the branch is not taken or the jump operation is not performed. For example, for the JNZ (Jump if Not Zero) instruction, if the current zero flag is 1 (indicating that the result is zero), the condition is not met and the program will continue to execute the next instruction after the JNZ instruction. At this time, the conditional branch is in the "not taken" state.

[0104] In a computer program, a conditional branch instruction determines the execution path of the program based on certain conditions. It may jump to a different instruction address to continue execution (the branch is "taken"), or it may execute the next instruction in sequence (the branch is "not taken"). However, processors usually use pipeline technology, which will fetch, decode, and execute subsequent instructions in advance while executing the current instruction. When encountering a branch instruction, if you have to wait until the branch condition is determined before determining the address of the next instruction, it will cause the pipeline to pause, waste a lot of time, and reduce the performance of the processor.

[0105] The role of the branch predictor is to predict the execution path of the branch instruction in advance (i.e., predict whether the branch is "taken" or "not taken") before the branch condition judgment result comes out, so that the processor can continue to fetch and execute according to the predicted path, avoiding pipeline pauses, thereby improving the execution efficiency of the processor. However, if a branch prediction error is found, the intermediate results of the predicted execution in the pipeline need to be abandoned, and the instructions on the correct branch route need to be retrieved and executed again, which will lead to a decrease in program execution efficiency.

[0106] Dynamic branch prediction can make predictions based on the historical information of the transfer of conditional branch instructions, and dynamically adjust the prediction strategy according to the actual execution situation to improve the accuracy of branch prediction.

[0107] In the embodiment of the present invention, the target processor refers to the processor of the host machine. The binary translator translates the instruction sequence of the client program into TB of host machine instructions in units of TB, and stores it in the code cache, and the translated TB is executed by the processor of the host machine. The translated TB may contain branch instructions, and the processor can use a branch predictor to dynamically predict the execution path of the branch instruction to improve the execution efficiency of the processor.

[0108] The embodiment of the present invention uses a target jump table to optimize the translation of indirect jump instructions, and searches for different target jump tables in different thread modes. In the process of searching the target jump table, one or more conditional branch instructions need to be used, and a branch predictor is used to predict which branch will be executed before the branch instruction is executed, so as to improve the performance of the instruction pipeline of the processor. The accuracy of branch prediction directly affects the execution efficiency of the translated program.

[0109] In an embodiment of the present invention, the target search code sequence includes one or more conditional branch instructions for determining whether the search is successful, and the target processor of the host machine where the binary translator is located uses a branch predictor to predict the execution path of each conditional branch instruction.

[0110] In single-thread mode, when an indirect jump instruction is translated, a first search code sequence is used to search the first jump table. The first search code sequence includes a conditional branch instruction for determining whether the first jump table is successfully searched, that is, determining whether the jump target address hits the first jump table. If it hits, the search is successful, the branch is "taken", and jumps to the cache start address of the translated basic block that hits; if it does not hit, the search fails, the branch is "not taken", and the next instruction is executed to perform a slow search.

[0111] In multi-threaded mode, when an indirect jump instruction is translated, a second search code sequence is used to search the second jump table. The second search code sequence includes multiple conditional branch instructions, which are used to determine whether the second jump table is successfully searched, that is, to determine whether the jump target address of the indirect jump instruction hits the second jump table, and to determine whether the state information of the translated basic block that hits meets the jump condition. During the execution of the second search code sequence, if the jump target address does not hit the second jump table, or the condition of any conditional branch instruction is not met, the search fails and jumps to the slow search execution path.

[0112] In an embodiment of the present invention, determining whether the jump target address of the indirect jump instruction hits the target jump table (such as the first jump table or the second jump table) may include:

[0113] According to the jump target address of the indirect jump instruction, a hash value is calculated according to a preset hash algorithm; the key value in the table item corresponding to the hash value is read from the target jump table, and if the read key value is consistent with the jump target address of the indirect jump instruction, it is determined that the jump target address of the indirect jump instruction hits the target jump table. In the above process, it is necessary to determine whether the read key value is consistent with the jump target address of the indirect jump instruction, and the determination process requires the use of a conditional branch instruction.

[0114] It should be noted that the target jump table (such as the first jump table or the second jump table) can be a hash table. When inserting an entry into the hash table, a hash value can be calculated according to a preset hash algorithm. This hash value indicates the position of the entry to be inserted into the hash table. For example, if the hash value calculated according to the key is h, the entry corresponding to the key is attempted to be inserted into the hth position of the hash table.

[0115] In an embodiment of the present invention, the key of the target jump table is the jump target address of the indirect jump instruction, that is, the starting address (client virtual address) of the client basic block to which the indirect jump instruction is to jump. When searching the target jump table, the hash value is calculated using the same preset hash algorithm according to the jump target address, and the corresponding position in the hash table (target jump table) is located according to the calculated hash value. Due to the existence of hash conflicts, the table entry read from the corresponding position in the target jump table according to the hash value is not necessarily the target basic block, so it is necessary to compare the key in the table entry (that is, the jump target address recorded in the target jump table) with the jump target address currently being searched. If the two are consistent, it is determined that the jump target address of the indirect jump instruction hits the target jump table.

[0116] In a specific implementation, the code for searching the target jump table (i.e., the target search code sequence, such as the first search code sequence or the second search code sequence) can be pre-placed into a common basic block, and all TBs ending with an indirect jump instruction jump to the common basic block to complete the target jump table search process when their indirect jump instructions are executed.

[0117] Reference Figure 3, showing a schematic diagram of using the target search code sequence as a common code sequence. The common code sequence may include a target search code sequence and a slow search code sequence. All TBs ending with an indirect jump instruction jump to the common basic block when executing their indirect jump instructions, and execute the target search code sequence first. The first search code sequence is executed in single-threaded mode, and the second search code sequence is executed in multi-threaded mode. If the target search code sequence is successfully found, jump directly. If the target search code sequence fails to find, the slow search code sequence is executed for slow search. If the slow search code sequence is successfully found, jump directly. If the slow search code sequence fails to find, it means that the target basic block (client basic block) to be jumped to has not been translated, then enter the translation state for translation. After the translation is completed, the translated basic block is stored in the code cache area, and a new table entry is inserted in the target jump table.

[0118] Figure 3 In the scheme shown, when translating an indirect jump instruction into a client program, the indirect jump instruction is translated into a host instruction sequence, and the host instruction sequence may include a host jump instruction for jumping to the starting address of a common search code sequence; the common search code sequence includes a target search code sequence and a slow search code sequence, and the slow search code sequence is used to perform a slow search based on the jump target address of the indirect jump instruction.

[0119] Branch predictors usually rely on historical information for prediction. If the target search code sequence is placed in a common basic block, when the target search code sequence is called by multiple basic blocks, the historical information of the conditional branch instruction in the target search code sequence of the common basic block is the historical information of the execution of all basic blocks using the target search code sequence. This makes the result of the conditional branch instruction highly random. The branch predictor may be difficult to predict accurately due to the mixing of different call paths, which may affect the accuracy of the branch predictor and thus affect the efficiency of program execution.

[0120] For a single basic block ending with an indirect jump instruction, its call target search code sequence usually has a high degree of regularity in searching the target jump table. That is, in a certain basic block over a period of time, in the process of searching the target jump table, the conditional branch instruction always tends to jump to a certain branch.

[0121] In one example, in single-thread mode, when a basic block ending with an indirect jump instruction executes the indirect jump instruction, the first jump table is searched using the first search code sequence, and only one conditional branch instruction is required. If the jump target address of the indirect jump instruction hits the first jump table, then for a period of time, the conditional branch instruction always jumps to the taken branch.

[0122] In another example, in multi-threaded mode, a basic block ending with an indirect jump instruction is recorded as TB1. When the indirect jump instruction is executed, the second search code sequence is used to search the second jump table, and at least two conditional branch instructions are required. If the jump target address of the indirect jump instruction hits the second jump table, and the state information of the translated basic block that hits meets the jump condition, then for TB1, it will always jump to the taken branch. Assume that TB1 has N taken branch jumps in a period of time. For another basic block ending with an indirect jump instruction, such as TB2, the second search code sequence is also used to search the second jump table. Assume that TB2 has M not taken branch jumps in a period of time. If the indirect jump instructions of TB1 and TB2 both use the target search code sequence in the common basic block to search the target jump table, then in the past period of time, a total of N+M jumps have occurred. The branch predictor will make predictions based on the historical information of these N+M jumps. The branch predictor may be difficult to accurately predict due to the mixing of different basic block call paths.

[0123] In this example, if TB1 and TB2 each have their own target search code sequence, the branch predictor can make predictions based on the historical information of TB1's own N jumps, and based on the historical information of TB2's own M jumps. The jump paths of different basic blocks will not be confused, which can improve the accuracy of the prediction.

[0124] Therefore, the embodiment of the present invention proposes a method for searching an indirect jump table for basic block privatization, so as to further optimize the translation process of the indirect jump instruction.

[0125] In an optional embodiment of the present invention, the method may further include:

[0126] When translating an indirect jump instruction in a client program, the indirect jump instruction is translated into a host instruction sequence, wherein the host instruction sequence includes a host jump instruction for jumping to a starting address of a common search code sequence; the common search code sequence is used to perform a slow search based on a jump target address of the indirect jump instruction; the slow search refers to searching for a cached starting address of a translated basic block corresponding to the jump target address based on a translation block table, wherein the translation block table is used to record the cached starting addresses of all translated basic blocks;

[0127] The target search code sequence is inserted before the host machine jump instruction.

[0128] The embodiment of the present invention provides a private target search code sequence for each basic block ending with an indirect jump instruction, and places the target search code sequence inside each translated basic block. Specifically, when translating to an indirect jump instruction, the indirect jump instruction is translated into a host instruction sequence, the host instruction sequence may include a host jump instruction, and the host jump instruction is used to jump to the starting address of the public search code sequence; in addition to the host jump instruction, the host instruction sequence may also include the logic of the indirect jump instruction itself; the public search code sequence is used to perform a slow search based on the jump target address of the indirect jump instruction; and the target search code sequence is inserted before the host jump instruction.

[0129] That is, the target search code sequence originally located in the public search code sequence is extracted and placed before the host machine jump instruction, thereby privatizing it inside the translated basic block. In single-threaded mode, the target search code sequence is the first search code sequence; in multi-threaded mode, the target search code sequence is the second search code sequence.

[0130] The embodiment of the present invention privatizes the target search code sequence, and each translated basic block corresponding to a client basic block ending with an indirect jump instruction has its own private target search code sequence. The privatized target search code sequence has the historical information of the branch jump of its own basic block, and the branch predictor can better learn and adapt to the behavior of the specific jump path of each basic block, reduce the interference between different basic blocks, and the branch predictor can more effectively use the historical information for prediction, thereby improving the accuracy of the prediction.

[0131] The embodiment of the present invention adds a repeated target search code sequence in the translated basic block corresponding to each basic block ending with an indirect jump instruction, which can improve the translation efficiency. The main reasons are as follows:

[0132] Each basic block adds a private target search code sequence. Although the static expansion rate of the translated code is increased, the dynamic expansion rate remains unchanged. When the machine memory is sufficient, increasing the static expansion rate has no effect on efficiency. Secondly, the accuracy of branch prediction by the branch predictor can be improved through the private target search code sequence, and the accuracy of branch prediction has a direct impact on the execution efficiency of the binary translator, which can improve the efficiency of executing indirect jump instructions, thereby improving the performance of the program. Furthermore, through the private target search code sequence, the efficiency of executing indirect jump instructions can be improved in single-threaded mode or multi-threaded mode, thereby improving the performance of the program. Furthermore, in single-threaded mode, since the structure of the first jump table is relatively simple, the number of instructions used to search the first jump table is relatively small; therefore, the translation efficiency is improved more significantly in single-threaded mode.

[0133] In summary, in the binary translation process, when translating the indirect jump instruction into the client program, the embodiment of the present invention dynamically obtains the thread mode of the client program, such as single-thread mode or multi-thread mode. According to the current thread mode of the client program, a corresponding target search code sequence is generated. According to different thread modes, the embodiment of the present invention generates different target search code sequences, and different target search code sequences use different target jump tables. By designing different fast search tables (such as the first jump table and the second jump table) for different thread modes, the translation of the indirect jump instruction is optimized. Since there are differences in execution characteristics and resource competition between single-threaded programs and multi-threaded programs, the jump conditions to be satisfied by the fast search are also different. Therefore, using different fast search strategies for different thread modes to optimize the execution of indirect jump instructions can bring significant performance improvement. For example, for the single-thread mode, a simpler and faster target jump table can be used to further improve the efficiency of searching for "the cache start address of the translated basic block corresponding to the jump target address of the indirect jump instruction". Therefore, through the embodiments of the present invention, for single-threaded programs and multi-threaded programs in the single-threaded stage, more concise instructions can be used to optimize translation, improve the efficiency of searching the indirect jump table, and then improve the operating efficiency of the translated program, thereby improving the performance of the translation system.

[0134] It should be noted that, for the sake of simplicity, the method embodiments are described as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0135] Reference Figure 4 , shows a structural block diagram of a binary translator embodiment of the present invention, the binary translator may include:

[0136] The thread mode acquisition module 401 is used to acquire the thread mode of the client program when translating the indirect jump instruction into the client program;

[0137] A code sequence generation module 402 is used to generate a target search code sequence according to the thread mode; the target search code sequence is used to search a target jump table based on the jump target address of the indirect jump instruction to obtain a cache start address of a translated basic block corresponding to the jump target address; wherein different thread modes correspond to different target search code sequences;

[0138] The target address jump module 403 is used to jump to the cache start address of the translated basic block corresponding to the jump target address if the target search code sequence is successfully found.

[0139] Optionally, the code sequence generation module is specifically used to:

[0140] If the thread mode is a single-thread mode, a first search code sequence is generated; the first search code sequence is used to search a first jump table based on the jump target address of the indirect jump instruction; the first jump table includes a mapping relationship between the jump target address and the cache start address of the translated basic block;

[0141] The target address jump module is specifically used for:

[0142] If the jump target address hits the first jump table, the first search code sequence is successfully searched and jumps to the cache start address of the translated basic block corresponding to the jump target address.

[0143] Optionally, the code sequence generation module is specifically used to:

[0144] If the thread mode is a multi-thread mode, a second search code sequence is generated; the second search code sequence is used to search a second jump table based on the jump target address of the indirect jump instruction; the second jump table contains a mapping relationship between the jump target address and the structure pointer of the translated basic block; the structure pointer of the translated basic block points to the structure of the translated basic block, and the structure of the translated basic block contains the cache start address of the translated basic block and the status information of the translated basic block;

[0145] The target address jump module includes:

[0146] A conditional judgment submodule, configured to judge whether the state information of the translated basic block hit satisfies the jump condition if the jump target address of the indirect jump instruction hits the second jump table;

[0147] The target jump submodule is used to obtain the cache start address of the translated basic block from the structure of the translated basic block if the state information of the translated basic block meets the jump condition, and then the second search code sequence is successfully searched, and jump is performed.

[0148] Optionally, the state information includes a valid flag, and the conditional judgment submodule is specifically used to: judge whether the valid flag is valid, and if the valid flag is valid, determine that the state information of the hit translated basic block meets the jump condition.

[0149] Optionally, the binary translator further includes:

[0150] A mark setting module, used for setting the thread mode mark of the client program to the single thread mode when starting to translate the client program;

[0151] A tag updating module, used for updating the thread mode tag of the client program from the single-thread mode to the multi-thread mode when translating to a system call function for creating a thread; and updating the thread mode tag of the client program from the multi-thread mode to the single-thread mode when translating to a system call function for exiting a thread;

[0152] The thread mode acquisition module is specifically used for:

[0153] The thread mode of the client program is obtained by reading the thread mode flag.

[0154] Optionally, the binary translator further includes:

[0155] The invalidation operation module is used to invalidate all cached translated basic blocks when monitoring that the thread mode of the client program is updated from the single-thread mode to the multi-thread mode.

[0156] Optionally, the binary translator further includes:

[0157] A code insertion module is used to translate an indirect jump instruction into a host instruction sequence when translating the indirect jump instruction into a client program, wherein the host instruction sequence includes a host jump instruction for jumping to a starting address of a common search code sequence; the common search code sequence is used to perform a slow search based on a jump target address of the indirect jump instruction; the target search code sequence is inserted before the host jump instruction; the slow search refers to searching for a cached starting address of a translated basic block corresponding to the jump target address based on a translation block table, wherein the translation block table is used to record the cached starting addresses of all translated basic blocks.

[0158] Optionally, the target search code sequence includes one or more conditional branch instructions, and the target processor of the host machine where the binary translator is located uses a branch predictor to predict the execution path of each conditional branch instruction.

[0159] The binary translator provided by the embodiment of the present invention dynamically obtains the thread mode of the client program, such as single-thread mode or multi-thread mode, when translating the indirect jump instruction in the client program during the binary translation process. According to the current thread mode of the client program, a corresponding target search code sequence is generated. According to the embodiment of the present invention, different target search code sequences are generated for different thread modes, and different target search code sequences use different target jump tables. By designing different fast search tables (such as the first jump table and the second jump table) for different thread modes, the translation of the indirect jump instruction is optimized. Since there are differences in execution characteristics and resource competition between single-thread programs and multi-thread programs, the jump conditions to be satisfied by the fast search are also different. Therefore, using different fast search strategies for different thread modes to optimize the execution of the indirect jump instruction can bring significant performance improvement. For example, for the single-thread mode, a simpler and faster target jump table can be used to further improve the efficiency of searching for "the cache start address of the translated basic block corresponding to the jump target address of the indirect jump instruction". Therefore, through the embodiments of the present invention, for single-threaded programs and multi-threaded programs in the single-threaded stage, more concise instructions can be used to optimize translation, improve the efficiency of searching the indirect jump table, and then improve the operating efficiency of the translated program, thereby improving the performance of the translation system.

[0160] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0161] Reference Figure 5 , is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. Figure 5 As shown, the electronic device includes: a processor, a memory, a communication interface and a communication bus, and the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction enables the processor to execute the steps of the binary translation method of the above-mentioned embodiment.

[0162] An embodiment of the present invention provides a non-transitory computer-readable storage medium. When instructions in the storage medium are executed by a program or a processor of a terminal, the terminal is enabled to perform the steps of the binary translation method of the aforementioned embodiment.

[0163] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0164] Those skilled in the art will appreciate that the embodiments of the embodiments of the present invention may be provided as methods, binary translators, or computer program products. Therefore, the embodiments of the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0165] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0166] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing terminal device to operate in a predictable manner, so that the instructions stored in the computer readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0167] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0168] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0169] Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A binary translation method, characterized in that: Applied to a binary translator, the method comprises: When translating an indirect jump instruction into a client program, obtaining a thread mode of the client program; Generate a target search code sequence according to the thread mode; the target search code sequence is used to search a target jump table based on the jump target address of the indirect jump instruction to obtain a cache start address of a translated basic block corresponding to the jump target address; wherein different thread modes correspond to different target search code sequences; If the target search code sequence is successfully found, jump to the cache start address of the translated basic block corresponding to the jump target address; Among them, the thread mode includes a single-thread mode or a multi-thread mode, and the single-thread mode and the multi-thread mode use different target jump tables; the conditions for the successful search of the target search code sequence corresponding to the single-thread mode include: the jump target address of the indirect jump instruction hits the target jump table corresponding to the single-thread mode; the conditions for the successful search of the target search code sequence corresponding to the multi-thread mode include: the jump target address of the indirect jump instruction hits the target jump table corresponding to the multi-thread mode, and the status information of the translated basic block that hits meets the jump condition.

2. The method according to claim 1, characterized in that The step of generating a target search code sequence according to the thread mode includes: If the thread mode is a single-thread mode, a first search code sequence is generated; the first search code sequence is used to search a first jump table based on the jump target address of the indirect jump instruction; the first jump table includes a mapping relationship between the jump target address and the cache start address of the translated basic block; If the target search code sequence is successfully searched, jumping to the cache start address of the translated basic block corresponding to the jump target address includes: If the jump target address hits the first jump table, the first search code sequence is successfully searched and jumps to the cache start address of the translated basic block corresponding to the jump target address.

3. The method according to claim 1, characterized in that The step of generating a target search code sequence according to the thread mode includes: If the thread mode is a multi-thread mode, a second search code sequence is generated; the second search code sequence is used to search a second jump table based on the jump target address of the indirect jump instruction; the second jump table contains a mapping relationship between the jump target address and the structure pointer of the translated basic block; the structure pointer of the translated basic block points to the structure of the translated basic block, and the structure of the translated basic block contains the cache start address of the translated basic block and the status information of the translated basic block; If the target search code sequence is successfully searched, jumping to the cache start address of the translated basic block corresponding to the jump target address includes: If the jump target address of the indirect jump instruction hits the second jump table, determining whether the state information of the translated basic block that hits satisfies the jump condition; If the state information of the hit translated basic block meets the jump condition, the second search code sequence searches successfully, obtains the cache start address of the hit translated basic block from the structure of the hit translated basic block, and jumps.

4. The method according to claim 3, characterized in that The state information includes a valid flag bit, and the step of judging whether the state information of the translated basic block meets the jump condition includes: It is determined whether the valid flag is valid; if the valid flag is valid, it is determined that the state information of the hit translated basic block meets the jump condition.

5. The method according to claim 1, characterized in that The method further comprises: When starting to translate the client program, setting the thread mode flag of the client program to single thread mode; When translating to a system call function for creating a thread, updating the thread mode mark of the client program from a single-thread mode to a multi-thread mode; When translating to the system call function of the exit thread, updating the thread mode mark of the client program from the multi-thread mode to the single-thread mode; The obtaining of the thread mode of the client program comprises: The thread mode of the client program is obtained by reading the thread mode flag.

6. The method according to claim 1, characterized in that The method further comprises: When it is monitored that the thread mode of the client program is updated from the single-thread mode to the multi-thread mode, all cached translated basic blocks are invalidated.

7. The method according to any one of claims 1 to 6, characterized in that: The method further comprises: When translating an indirect jump instruction in a client program, the indirect jump instruction is translated into a host instruction sequence, wherein the host instruction sequence includes a host jump instruction for jumping to a starting address of a common search code sequence; the common search code sequence is used to perform a slow search based on a jump target address of the indirect jump instruction; the slow search refers to searching for a cached starting address of a translated basic block corresponding to the jump target address based on a translation block table, wherein the translation block table is used to record the cached starting addresses of all translated basic blocks; The target search code sequence is inserted before the host machine jump instruction.

8. The method according to any one of claims 1 to 6, characterized in that: The target search code sequence includes one or more conditional branch instructions, and the target processor of the host machine where the binary translator is located uses a branch predictor to predict the execution path of each conditional branch instruction.

9. A binary translator, characterized in that: The binary translator comprises: A thread mode acquisition module, used for acquiring the thread mode of the client program when translating an indirect jump instruction into the client program; A code sequence generation module, used for generating a target search code sequence according to the thread mode; the target search code sequence is used for searching a target jump table based on the jump target address of the indirect jump instruction to obtain a cache start address of a translated basic block corresponding to the jump target address; wherein different thread modes correspond to different target search code sequences; A target address jump module, used for jumping to the cache start address of the translated basic block corresponding to the jump target address if the target search code sequence is successfully found; Among them, the thread mode includes a single-thread mode or a multi-thread mode, and the single-thread mode and the multi-thread mode use different target jump tables; the conditions for the successful search of the target search code sequence corresponding to the single-thread mode include: the jump target address of the indirect jump instruction hits the target jump table corresponding to the single-thread mode; the conditions for the successful search of the target search code sequence corresponding to the multi-thread mode include: the jump target address of the indirect jump instruction hits the target jump table corresponding to the multi-thread mode, and the status information of the translated basic block that hits meets the jump condition.

10. The binary translator according to claim 9, characterized in that: The code sequence generation module is specifically used for: If the thread mode is a single-thread mode, a first search code sequence is generated; the first search code sequence is used to search a first jump table based on the jump target address of the indirect jump instruction; the first jump table includes a mapping relationship between the jump target address and the cache start address of the translated basic block; The target address jump module is specifically used for: If the jump target address hits the first jump table, the first search code sequence is successfully searched and jumps to the cache start address of the translated basic block corresponding to the jump target address.

11. The binary translator according to claim 9, characterized in that: The code sequence generation module is specifically used for: If the thread mode is a multi-thread mode, a second search code sequence is generated; the second search code sequence is used to search a second jump table based on the jump target address of the indirect jump instruction; The second jump table includes a mapping relationship between a jump target address and a structure pointer of a translated basic block; the structure pointer of the translated basic block points to a structure of the translated basic block, and the structure of the translated basic block includes a cache start address of the translated basic block and status information of the translated basic block; The target address jump module includes: A conditional judgment submodule, configured to judge whether the state information of the translated basic block hit satisfies the jump condition if the jump target address of the indirect jump instruction hits the second jump table; The target jump submodule is used to obtain the cache start address of the translated basic block from the structure of the translated basic block if the state information of the translated basic block meets the jump condition, and then the second search code sequence is successfully searched, and jump is performed.

12. The binary translator according to claim 11, characterized in that: The state information includes a valid flag bit, and the condition judgment submodule is specifically used for: It is determined whether the valid flag is valid; if the valid flag is valid, it is determined that the state information of the hit translated basic block meets the jump condition.

13. The binary translator according to claim 9, characterized in that: The binary translator also includes: A mark setting module, used for setting the thread mode mark of the client program to the single thread mode when starting to translate the client program; A tag updating module, used for updating the thread mode tag of the client program from the single-thread mode to the multi-thread mode when translating to a system call function for creating a thread; and updating the thread mode tag of the client program from the multi-thread mode to the single-thread mode when translating to a system call function for exiting a thread; The thread mode acquisition module is specifically used for: The thread mode of the client program is obtained by reading the thread mode flag.

14. The binary translator according to claim 9, characterized in that: The binary translator also includes: The invalidation operation module is used to invalidate all cached translated basic blocks when monitoring that the thread mode of the client program is updated from the single-thread mode to the multi-thread mode.

15. The binary translator according to any one of claims 9 to 14, characterized in that: The binary translator also includes: A code insertion module is used to translate an indirect jump instruction into a host instruction sequence when translating the indirect jump instruction into a client program, wherein the host instruction sequence includes a host jump instruction for jumping to a starting address of a common search code sequence; the common search code sequence is used to perform a slow search based on a jump target address of the indirect jump instruction; the target search code sequence is inserted before the host jump instruction; the slow search refers to searching for a cached starting address of a translated basic block corresponding to the jump target address based on a translation block table, wherein the translation block table is used to record the cached starting addresses of all translated basic blocks.

16. The binary translator according to any one of claims 9 to 14, characterized in that: The target search code sequence includes one or more conditional branch instructions, and the target processor of the host machine where the binary translator is located uses a branch predictor to predict the execution path of each conditional branch instruction.

17. An electronic device, characterized in that: include: A processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other via the communication bus; The memory is used to store at least one executable instruction, and the executable instruction enables the processor to execute the steps of the binary translation method according to any one of claims 1 to 8.

18. A readable storage medium, characterized in that: The readable storage medium stores a program or instruction, and when the program or instruction is executed by a processor, the steps of the binary translation method according to any one of claims 1 to 8 are implemented.

19. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the binary translation method according to any one of claims 1 to 8 are implemented.

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