Binary translation method, electronic equipment, readable storage medium and program product

Abstract

The embodiment of the invention provides a binary translation method, electronic equipment, a readable storage medium and a program product, the method is applied to a translator, and after a client instruction stream is translated into a host instruction stream, a first class of instructions contained in the host instruction stream are obtained; the first type of instruction is a stack pointer calculation instruction, and a source operand of the first type of instruction comprises a stack pointer register and an immediate operand; under the condition that the number of the first-class instructions is M, combining the M first-class instructions into N first-class instructions based on the source operands of the first-class instructions; m is a positive integer larger than 1, and N is a positive integer smaller than M. Therefore, according to the embodiment of the invention, the host machine instructions after translation and before execution can be processed, the M first-class instructions are merged and processed into N instructions, the number of the first-class instructions after translation is reduced, the instruction expansion rate after translation is reduced, and the execution efficiency of a translator is improved.

Description

Technical Field

[0001] The present invention belongs to the field of computer technology, and in particular relates to a binary translation method, device, electronic equipment and readable storage medium. Background Art

[0002] In the field of computer technology, binary translation technology is usually used, that is, a translator translates client instructions into host instructions, so that a program compiled for one architecture can also run on a hardware platform of another architecture.

[0003] At present, most translators tend to adopt the "translate and execute" method, and the architectures used by the client and host are usually different, which often leads to a greatly increased number of host instructions obtained after translation compared to the original number of client instructions, resulting in lower execution efficiency of the translator. Summary of the invention

[0004] The present invention provides a binary translation method, electronic equipment, readable storage medium and program product to solve the problem of low execution efficiency of a translator.

[0005] In order to solve the above-mentioned technical problems, the present invention is achieved as follows: In a first aspect, the present invention provides a binary translation method, which is applied to a translator, and comprises: After translating the client instruction stream into a host instruction stream, obtaining a first type of instruction contained in the host instruction stream; the first type of instruction is a stack pointer calculation instruction and the source operand of the first type of instruction includes a stack pointer register and an immediate operand; When the number of the first category instructions is M, based on the source operands of each of the first category instructions, the M first category instructions are merged into N first category instructions; M is a positive integer greater than 1, and N is a positive integer less than M.

[0006] In a second aspect, the present invention provides a binary translation method for translating client instructions of a complex instruction set architecture into host instructions of a reduced instruction set according to basic blocks, comprising: Translate each of the plurality of client stack operation instructions in the basic block into a combination of a stack access instruction of the host machine and a stack pointer calculation instruction for adjusting the stack top, wherein source operands of the stack access instruction and the stack pointer calculation instruction include a stack pointer register and an immediate value; removing at least some stack pointer calculation instructions from the host instruction stream; Modifying the immediate offset in the stack access instruction to make the stack access operation point to the top of the stack to compensate for the top of the stack adjustment of the removed stack pointer calculation instruction; and The stack pointer adjustment accumulated by the removed stack pointer instructions is implemented with a stack pointer calculation instruction.

[0007] In a third aspect, the present invention provides an electronic device, comprising: a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the processor implements the above-mentioned binary translation method when executing the program.

[0008] In a fourth aspect, the present invention provides a readable storage medium, which, when instructions in the storage medium are executed by a processor of an electronic device, enables the electronic device to perform the above-mentioned binary translation method.

[0009] The binary translation method provided in the embodiment of the present invention is applied to a translator, and after translating a client instruction stream into a host instruction stream, the first-class instructions contained in the host instruction stream are obtained; the first-class instructions are stack pointer calculation instructions and the source operands of the first-class instructions include stack pointer registers and immediate operands; when the number of the first-class instructions is M, based on the source operands of each of the first-class instructions, the M first-class instructions are merged into N first-class instructions; M is a positive integer greater than 1, and N is a positive integer less than M. In this way, the embodiment of the present invention can process the host instructions after translation and before execution, merge the M first-class instructions into N, reduce the number of translated first-class instructions, and reduce the instruction expansion rate after translation, thereby improving the execution efficiency of the translator. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0011] Figure 1 is a flowchart of a binary translation method provided by an embodiment of the present invention; Figure 2 It is a flowchart of binary translation provided by an embodiment of the present invention; Figure 3 is a schematic diagram of a basic block provided by an embodiment of the present invention; Figure 4 is a flowchart of another binary translation method provided by an embodiment of the present invention; Figure 5 is a structural diagram of an instruction processing device provided by an embodiment of the present invention; Figure 6It is a structural diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0012] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0013] Figure 1 is a flowchart of a binary translation method provided by an embodiment of the present invention, the method is applied to a translator, such as Figure 1 As shown, the method may include the following steps: Step 101, after translating the client instruction stream into a host instruction stream, obtain the first type of instructions contained in the host instruction stream; the first type of instructions are stack pointer calculation instructions and the source operands of the first type of instructions include a stack pointer register and an immediate operand.

[0014] Step 102: When the number of the first category instructions is M, based on the source operands of each of the first category instructions, merge the M first category instructions into N first category instructions; M is a positive integer greater than 1, and N is a positive integer less than M.

[0015] Among them, the above-mentioned translator (also known as a binary translator) is used to translate the source program A in the client (GUEST) into the target program B in the host (HOST), and execute the target program B in the host. The instructions in the source program A can be called client instructions, and the instructions in the target program B can be called host instructions. Correspondingly, the above-mentioned client instruction stream refers to an instruction stream composed of multiple client instructions, and the above-mentioned host instruction stream refers to an instruction stream composed of multiple host instructions. Optionally, since the translator usually uses intermediate codes to represent the details of the translated instructions in the process of translating client instructions into host instructions, and then converts the intermediate codes into real host instructions and stores them in the memory, on this basis, the host instructions in the embodiment of the present invention can be real host instructions that have been stored in the memory, or they can be intermediate codes obtained after the host instructions translate the client instructions before. They can be selected according to the actual instruction processing requirements, and the embodiment of the present invention does not limit this.

[0016] It should be noted that the client in the embodiment of the present invention adopts the CISC architecture, and the host adopts the RISC architecture. Exemplarily, the client in the embodiment of the present invention can adopt the x86 architecture, and the host can adopt the Loong Arch. The RISC architecture can only operate the memory through load / store, and the memory cannot be used as the operand of other instructions. CISC can use the memory as the operand of pop, push and other instructions. Therefore, a pop or push instruction of CISC will be translated into a load / store instruction in RISC plus an instruction to adjust the top pointer of the stack, which may lead to the problem of instruction redundancy and expansion.

[0017] Furthermore, the translator in the embodiment of the present invention may be a dynamic binary translator, which generally translates the instructions of the client architecture into host architecture instructions at runtime and runs them. After the translator reads the binary file, it generally translates and executes it in units of basic blocks (TB). Therefore, the above-mentioned client instruction stream and host instruction stream may be instructions contained in a basic block.

[0018] Figure 2 FIG. 1 is a flowchart of a binary translation provided by an embodiment of the present invention. Figure 2 As shown in the figure, after the translator reads the executable program of the client platform, that is, the binary file, it usually translates and executes it according to the granularity of basic blocks. Before executing a basic block, the target program is first read from the code cache. If a translated basic block is found, the code block is executed. If the basic block is not found in the code cache, the translation operation is performed and the translated code is placed in the code cache, and then the basic block is executed. After executing a basic block, the code cache is searched for the next basic block, and this cycle is repeated until the program execution ends.

[0019] Furthermore, since binary translation technology is to run the source program of one CPU architecture under another CPU architecture, the client and host use two different architectures, and the instruction sets of different architectures are quite different. During the translation process, multiple host instructions may be required to express one client instruction, resulting in the client instruction being translated into more host instructions. Figure 2 It can be seen that the more instructions are translated, the lower the execution efficiency of the translator will be, and the overall translation efficiency of the program will be reduced to a certain extent.

[0020] On this basis, the embodiment of the present invention can process the instructions of the host instruction stream after translating the client instruction stream into the host instruction stream.

[0021] Among them, the above-mentioned stack pointer register is a register used to point to the top of the stack, and the stack is particularly important in the program execution process. For example, in function calls, local variable management and context switching, it is necessary to accurately use the stack data structure through the stack pointer register to achieve efficient memory management and control flow. Therefore, there are often many instructions in the program for operating the stack pointer register. The embodiment of the present invention can optimize the number of such instructions.

[0022] Among them, the above-mentioned first-category instruction refers to a stack pointer calculation instruction whose source operand includes a stack pointer register and an immediate operand, which is used to calculate and update the value of the stack pointer register, and its destination operand is the stack pointer register, one source operand is the stack pointer register, and at least one source operand is an immediate number. Exemplarily, taking the host machine as LoongArch as an example, if there is a host machine instruction: addi.d sp, sp, 8, the instruction means adding 8 to the stack pointer register sp and storing it in sp, which is used to calculate and update the value of the stack pointer register based on the immediate number and the current value of the stack pointer register, and is a first-category instruction.

[0023] Specifically, the embodiment of the present invention can traverse the host machine instructions in the host machine instruction stream, determine whether the destination operand of each host machine instruction is the stack pointer register corresponding to the host machine platform, and if so, further determine whether the source operand of each host machine instruction includes the stack pointer register and the immediate operand, and if so, it can be determined that it is a first-class instruction. Correspondingly, if the destination operand is not the stack pointer register or the source operand does not include the stack pointer register and the immediate operand, it can be determined that it is not a first-class instruction.

[0024] Wherein, the above M is a positive integer greater than 1, and the above N is a positive integer less than M. Specifically, when the number of first-category instructions is M, it indicates that there are at least two first-category instructions for calculating the stack pointer register in the host machine instruction stream. At this time, the embodiment of the present invention can merge the M first-category instructions into N first-category instructions. Wherein, the above N can be set according to actual conditions. In one case, N can be 1, and the embodiment of the present invention does not limit this.

[0025] Specifically, the above-mentioned merging operation can be implemented based on the source operands of each first-category instruction, and can be implemented based on the immediate operands in the source operands of the first-category instruction. Specifically, the immediate operands of each first-category instruction can be merged into N immediate numbers, and N first-category instructions can be generated based on the N immediate numbers.

[0026] Specifically, since the stack pointer calculation instruction is used to update the stack pointer register, and the stack pointer calculation instruction realizes the update of the stack top position by adding or subtracting the stack pointer register, the embodiment of the present invention can directly merge the M updates of the stack pointer register in the host machine instruction stream into N updates by merging the first type of instructions, which can reduce the number of host machine instructions to be executed to a certain extent and improve the execution efficiency of the translator. At the same time, the overall program translation efficiency can also be improved to a certain extent for the dynamic translator.

[0027] In summary, after translating the client instruction stream into the host instruction stream, the embodiment of the present invention obtains the first-category instructions included in the host instruction stream; the first-category instructions are stack pointer calculation instructions and the source operands of the first-category instructions include stack pointer registers and immediate operands; when the number of the first-category instructions is M, based on the source operands of each of the first-category instructions, the M first-category instructions are merged into N first-category instructions; M is a positive integer greater than 1, and N is a positive integer less than M. In this way, the embodiment of the present invention can process the host instructions after translation and before execution, merge the M first-category instructions into N, reduce the number of translated first-category instructions, reduce the instruction expansion rate after translation, and thus improve the execution efficiency of the translator.

[0028] Optionally, the operation of merging the M first-category instructions into N first-category instructions based on the source operands of the first-category instructions may specifically include: S21. Obtain host machine instructions from the host machine instruction stream as instructions to be processed according to the instruction execution order.

[0029] S22. If the instruction to be processed is an instruction of the first category, update the parameter value of the preset parameter based on the immediate operand of the instruction to be processed, and delete the instruction to be processed from the host machine instruction stream; the initial value of the preset parameter is 0.

[0030] S23. Execute the operation of obtaining the host machine instruction from the host machine instruction stream as the instruction to be processed again until the current instruction to be processed is a logical end instruction, generate a first-category instruction based on the current parameter value of the preset parameter, and insert the generated first-category instruction as the previous instruction of the logical end instruction.

[0031] The above instruction execution order refers to the logical execution order of the host machine instructions in the instruction stream, and the instructions in the later logical execution order usually depend on the execution results of the previous instructions. On this basis, the embodiment of the present invention can sequentially obtain the host machine instructions from the host machine instruction stream as the instructions to be processed according to the instruction execution order.

[0032] Among them, the above-mentioned preset parameter can be a preset variable parameter, and its initial value can be 0. The embodiment of the present invention can pre-assign a value of 0 to the preset parameter before executing the above step 102. Specifically, since the immediate value in the stack pointer calculation instruction is often a signed immediate value, the above-mentioned preset parameter can also be a variable of a signed type. Furthermore, in the case where the instruction to be processed is a first-class instruction, the embodiment of the present invention can update the parameter value of the preset parameter based on the instruction to be processed. Specifically, since the first-class instruction is a stack pointer calculation instruction, the above-mentioned update operation can be implemented based on the immediate operand of the instruction to be processed, and can be to add the immediate operand of the instruction to be processed to the parameter value of the preset parameter. Exemplarily, taking the preset parameter as off as an example, if the immediate operand of the instruction to be processed is imm, the above-mentioned update operation can be off=off+imm.

[0033] Furthermore, the embodiment of the present invention updates the parameter value of the preset parameter based on the immediate operand of the instruction to be processed, and the change value of the stack pointer register in the current instruction stream can be transmitted through the preset parameter. On this basis, the embodiment of the present invention can directly delete the above-mentioned instruction to be processed from the host machine instruction stream.

[0034] Furthermore, the above step S21 can be executed again, and the operation of the above step S22 can be performed on the first type of instructions in the host instruction stream in turn. In this way, the stack pointer calculation instructions in the host instruction stream can be converted into parameter value updates without reflecting each stack pointer calculation instruction in the host instruction stream.

[0035] Among them, the above-mentioned logical end instruction refers to the last instruction executed in the instruction stream according to the instruction execution order, which can be a jump instruction or a basic block end instruction. Further, the operation of the above-mentioned step S22 is performed on the first-category instructions in the host machine instruction stream in sequence until the acquired instruction to be processed is a logical end instruction. At this time, a first-category instruction can be generated based on the current parameter value of the preset parameter, and the generated first-category instruction can be inserted as the previous instruction of the logical end instruction. Specifically, the above-mentioned operation of generating a first-category instruction can be to use the current parameter value of the preset parameter as the immediate operand of the first-category instruction, thereby generating a first-category instruction for calculating the stack pointer register.

[0036] Through the above operations, multiple first-category instructions in the host machine instruction stream can be merged into one first-category instruction, that is, the stack pointer register does not need to be calculated in sequence, but the stack pointer register is delayed and merged by accumulating immediate operands.

[0037] The embodiment of the present invention obtains the host machine instruction from the host machine instruction stream as the pending instruction according to the instruction execution order; if the pending instruction is the first type of instruction, the parameter value of the preset parameter is updated based on the immediate operand of the pending instruction, and the pending instruction is deleted from the host machine instruction stream; the initial value of the preset parameter is 0; the operation of obtaining the host machine instruction from the host machine instruction stream as the pending instruction is performed again, until the current pending instruction is a logical end instruction, a first type of instruction is generated based on the current parameter value of the preset parameter, and the generated first type of instruction is inserted as the previous instruction of the logical end instruction. In this way, the change value of the stack pointer register in the host machine instruction stream can be transmitted through the preset parameter, so that there is no need to reflect each stack pointer calculation instruction in the host machine instruction stream, and only one first type of instruction needs to be inserted before the logical end instruction of the host machine instruction stream, which can realize the delayed merging calculation of the stack pointer register, and can greatly reduce the number of host machine instructions, thereby improving the operation efficiency of the translator.

[0038] Optionally, after the above operation of obtaining a host instruction from the host instruction stream as an instruction to be processed, the embodiment of the present invention may further include: S31. If the instruction to be processed is a second-category instruction, and the source operand of the instruction to be processed includes an immediate operand, the immediate operand of the instruction to be processed is updated based on the current parameter value of the preset parameter; the second-category instruction is an instruction other than the first-category instruction whose source operand includes a stack pointer register.

[0039] S32, executing again the operation of obtaining the host machine instruction from the host machine instruction stream as the instruction to be processed.

[0040] Among them, the above-mentioned second-category instructions refer to instructions whose source operands include the stack pointer register and are not first-category instructions, whose destination operands are any operands, and whose source operands include the stack pointer register. Taking the host machine as LoongArch as an example, if there is a host machine instruction: addi.d t0, sp, 8, this instruction means adding 8 to the sp register and storing it in the register t0, and it needs to perform corresponding operations based on the value of the stack pointer register, which is a second-category instruction. In this case, the execution of the second-category instructions depends on the value of the stack pointer register, and because the embodiment of the present invention deletes the first-category instructions in the host machine instruction stream, that is, before the second-category instructions are executed, the stack pointer register is not updated to an accurate value. In this case, in order to ensure the execution accuracy of the second-category instructions, the embodiment of the present invention can update the immediate operand of the instruction to be processed based on the current parameter value of the preset parameter.

[0041] Specifically, the source operand of the second category of instructions includes the stack pointer register. If the source operand of the second category of instructions also includes an immediate operand, the execution of the second category of instructions depends on both the stack pointer register and the immediate operand. Since the embodiment of the present invention deletes the first category of instructions in the aforementioned steps, the value of the stack pointer register is not accurate at this time, which will affect the execution result of the second category of instructions. At this time, the current parameter value of the preset parameter can represent the value to be updated of the stack pointer register. Therefore, the embodiment of the present invention can directly add the current parameter value of the preset parameter based on the immediate operand of the instruction to be processed, so as to ensure the accuracy of the execution of the second category of instructions.

[0042] Exemplarily, taking the instruction to be processed as the second type of instruction, whose source operand includes an immediate operand imm, and the preset parameter is off as an example, the above update operation can be imm=imm+off.

[0043] Furthermore, after the immediate operand of the second type of instruction is updated, the operation of obtaining the instruction to be processed may be performed again, that is, the next host machine instruction may be processed.

[0044] In an embodiment of the present invention, if the instruction to be processed is a second-category instruction, when the source operand of the instruction to be processed includes an immediate operand, the immediate operand is updated based on the current parameter value of the preset parameter; the second-category instruction is an instruction other than the first-category instruction whose source operand includes a stack pointer register; and the operation of obtaining the host instruction from the host instruction stream as the instruction to be processed is performed again. In this way, while reducing the number of translated host instructions, the immediate operand of the second-category instruction that depends on the stack pointer register can be updated by the current parameter value of the preset parameter, thereby avoiding the problem of inaccurate execution results of the second-category instruction caused by deleting the first-category instruction.

[0045] Optionally, the operation of updating the immediate operand of the instruction to be processed based on the current parameter value of the preset parameter may specifically include: S41. Obtain the sum of the current parameter value and the current value of the immediate operand of the instruction to be processed as the value to be updated.

[0046] S42: When the value to be updated does not exceed the range of the immediate operand of the instruction to be processed, update the immediate operand of the instruction to be processed to the value to be updated.

[0047] Specifically, since the operands of instructions often have corresponding expression ranges, the operands cannot exceed their corresponding expression ranges. If they exceed, the instructions may fail to execute or execute incorrectly. On this basis, before updating the immediate operands of the instructions to be processed, the embodiments of the present invention may first determine whether the updated immediate operands exceed the expression range of the corresponding operands.

[0048] Specifically, the sum of the current parameter value of the preset parameter and the current value of the immediate operand of the instruction to be processed can be used as the value to be updated, and this value is the value that will replace the original immediate operand. Specifically, the operand range of an instruction is often fixed, which is often related to the bit width of the register contained in the instruction to be processed or the instruction function. The operand range of the instruction is often specified by the instruction manual. On this basis, the embodiment of the present invention can determine the immediate operand range of the instruction to be processed based on the description in the instruction manual corresponding to the instruction set architecture of the host machine, or it can also be calculated based on the number of bits (bits) of the immediate threshold in the instruction to be processed. Alternatively, the immediate operand range of the instruction to be processed can be obtained by accepting input information from relevant personnel, which can be set according to the actual situation, and the embodiment of the present invention does not limit this.

[0049] Specifically, when the value to be updated does not exceed the immediate operand range of the instruction to be processed, the immediate operand of the instruction to be processed can be updated to the value to be updated, that is, the value to be updated is used as the immediate operand in the source operand of the instruction to be processed.

[0050] In the embodiment of the present invention, the sum of the current parameter value and the current value of the immediate operand of the pending instruction is obtained as the value to be updated; when the value to be updated does not exceed the range of the immediate operand of the pending instruction, the immediate operand of the pending instruction is updated to the value to be updated. In this way, while updating the immediate operand of the second type of instruction, it is ensured that the updated immediate operand does not exceed the range of the immediate operand of the pending instruction, thereby ensuring the normal execution of the instruction.

[0051] Optionally, the embodiment of the present invention may further include: S51. When the current parameter value of the preset parameter is not 0, executing the operation of updating the immediate operand of the instruction to be processed based on the current parameter value of the preset parameter.

[0052] Specifically, an embodiment of the present invention can determine whether the current parameter value of the preset parameter is 0 before updating the immediate operand of the instruction to be processed. If it is not 0, it indicates that there is a value to be calculated in the stack pointer register. At this time, the value of the stack pointer register is inaccurate, and the immediate operand of the second type of instruction needs to be corrected. At this time, the above-mentioned operation of updating the immediate operand of the instruction to be processed based on the current parameter value of the preset parameter can be executed.

[0053] Correspondingly, if the current parameter value of the preset parameter is 0, it indicates that there is no value to be calculated in the stack pointer register. At this time, the value of the stack pointer register is accurate, so there is no need to correct the immediate operand of the second type of register, and the next host machine instruction can be directly obtained as the instruction to be processed.

[0054] In the embodiment of the present invention, when the current parameter value of the preset parameter is not 0, the operation of updating the immediate operand of the instruction to be processed based on the current parameter value of the preset parameter is performed. In this way, by judging whether the stack pointer register has a value to be calculated by checking whether the current parameter value of the preset parameter is 0, and then performing the operation of updating the immediate operand when it is not 0, unnecessary immediate operand update operations can be reduced, thereby reducing the amount of data processing.

[0055] Optionally, when the above-mentioned instruction to be processed is the second type of instruction, the embodiment of the present invention may further include: S61. If the source operand of the instruction to be processed does not include an immediate operand, or the value to be updated exceeds the immediate operand range of the instruction to be processed, a first-category instruction is generated based on the current parameter value of the preset parameter.

[0056] S62: Insert the generated first-category instruction as the previous instruction of the instruction to be processed, and update the parameter value of the preset parameter to 0.

[0057] Among them, when the source operand of the instruction to be processed does not contain an immediate operand, it indicates that the execution of the second type of instruction is often implemented based on the stack pointer register and other registers. At this time, the second type of instruction cannot be corrected by updating the immediate operand. Therefore, a first type of instruction can be generated to calculate and update the stack pointer register. Correspondingly, when the above-mentioned value to be updated exceeds the immediate operand range of the instruction to be processed, it indicates that if the immediate operand is updated using the value to be updated, it may cause the second type of instruction to fail to execute or fail to execute. At this time, the immediate operand of the second type of instruction may not be updated, and a first type of instruction is generated based on the current parameter value of the preset parameter to calculate and update the stack pointer register.

[0058] Specifically, the current parameter value of the preset parameter can be used as the immediate operand of the first-category instruction, and the stack pointer register can be used as the destination operand and a source operand to obtain a first-category instruction.

[0059] Furthermore, after the first-category instruction is generated, the first-category instruction can be inserted as the previous instruction of the instruction to be processed, that is, the first-category instruction can be inserted into the host machine instruction stream before the instruction to be processed. In this way, it can be ensured that before the second-category instruction is executed, the stack pointer register is updated to an accurate value by generating the inserted first-category instruction, thereby ensuring the execution accuracy of the second-category instruction.

[0060] In an embodiment of the present invention, if the source operand of the instruction to be processed does not include an immediate operand, or the value to be updated exceeds the immediate operand range of the instruction to be processed, a first-class instruction is generated based on the current parameter value of the preset parameter; the generated first-class instruction is inserted as the previous instruction of the instruction to be processed, and the parameter value of the preset parameter is updated to 0. In this way, when the immediate operand of the instruction to be processed cannot be updated, the generated stack pointer calculation instruction can be inserted before the instruction to be processed, and the stack pointer register can be updated to an accurate value by generating the inserted first-class instruction before the execution of the second-class instruction, thereby ensuring the execution accuracy of the second-class instruction and avoiding the problem of inaccurate instruction execution caused by merging the first-class instruction.

[0061] Optionally, the operation of generating a first-category instruction based on the current parameter value of the preset parameter may be: When the current parameter value of the preset parameter is not 0, a first-category instruction is generated based on the current parameter value of the preset parameter.

[0062] It can be understood that when the current parameter value of the preset parameter is 0, it indicates that there is no value to be updated in the stack pointer register, that is, the current value of the stack pointer register is an accurate value and does not need to be updated, so there is no need to generate and insert the first type of instruction to update the stack pointer register, which can avoid unnecessary instruction generation and insertion operations. Correspondingly, when the current parameter value of the preset parameter is not 0, it indicates that there is a value to be updated in the stack pointer register, which needs to be calculated and updated, so in this case, the first type of instruction is generated and inserted to update the stack pointer register.

[0063] It should be noted that there are many differences in the instructions that can be supported by the hardware design of different instruction set architectures (ISA), which leads to the incompatibility of executable files compiled based on one ISA instruction set with other platforms. It is necessary to use binary translation technology to enable programs compiled with one architecture to run on hardware platforms with another architecture. With the continuous improvement of microprocessor performance, the feasibility of running source programs of another CPU architecture under one CPU architecture through binary translation is becoming stronger and stronger, which has led to more development of binary translation technology. However, this technology still has technical problems such as low translation efficiency and too many redundant operations. For example: when translating from CISC to reduced instruction set RISC, due to the powerful instructions of CISC architecture, one instruction can perform complex operations, such as memory access arithmetic operations and logical operations. However, RISC architecture tends to use simple fixed-length instructions, and each instruction usually only performs a simple operation. In order to realize complex functions, multiple instructions need to be combined and implemented under RISC architecture. Therefore, for binary translators translating from CISC architecture to RISC, the instructions of the original instruction set will be converted into more instructions, resulting in low execution efficiency of the binary translator.

[0064] Exemplarily, taking the x86 architecture as the GUEST platform and the LoongArch (LA) architecture as the HOST platform as examples, in the x86 architecture, RSP, ESP, and SP are all registers used to represent the stack pointer (i.e., the stack pointer register), but they are suitable for different bit widths. RSP is used to represent a 64-bit register, ESP represents a 32-bit register, and SP represents a 16-bit register. RSP is a 64-bit register that can handle a 64-bit address space, and ESP is a 32-bit register that can handle a 32-bit address space. SP is a 16-bit register. The following descriptions all use ESP to refer to the stack pointer register in the x86 architecture.

[0065] Taking the x86 architecture as an example, stack operation instructions involving ESP register calculation generally include the instructions shown in Table 1 below: Table 1

[0066] Take the translation of client instructions using the Quick EMUlator User Mode Emulation (QEMU) as an example. Figure 3 is a schematic diagram of a basic block provided by an embodiment of the present invention, such as Figure 3As shown, it contains a TB of instructions. These 8 instructions all involve the calculation of the stack pointer register in the x86 architecture. Qemu's processing is to calculate the stack pointer register truthfully in each x86 instruction translation.

[0067] The following table is a related art Figure 3 The instructions obtained after the instructions shown are translated are shown in Table 2 below: Table 2

[0068] Among them, "inst_xx" in the table represents other instructions, "reg_*" represents registers unrelated to the stack pointer register, and $s4 represents the stack pointer register of x86 after register mapping. Among them, "addi.drd, rj, si12" in the above host machine instruction represents adding the [63:0] bit data in the general register rj to the 64-bit data after the sign extension of the 12-bit immediate value si12, and writing the result to the general register rd. "add.d rd, rj, rk" represents adding the [63:0] bit data in the general register rj to the [63:0] bit data in the general register rk, and writing the result to the general register rd. "ld.d rd, rj, si12" represents retrieving a double word of data from the memory and writing it to the general register rd. The memory access address calculation method of the instruction is to add the value in the general register rj to the 12-bit immediate value si12 after the sign extension. It can be seen that the translated code has 7 instructions involving the calculation of the stack pointer register (addi.d $s4, $s4, 8) and the source operands of these 7 instructions all include the stack pointer register and immediate operands, that is, the above translated instruction stream contains 7 first-category instructions.

[0069] The X86 client program basic block in the above example only contains POP and RET instructions involving stack pop operations. For 64-bit registers, the stack pointer is increased by 8 by the stack pop instruction. Therefore, in the LA host basic block, addi.d $s4, $s4,8 is used as the stack pointer calculation instruction (first type of instruction) to calculate the stack pointer. Those skilled in the art will understand that for PUSH and CALL instructions involving stack push operations, the stack pointer is reduced, and addi.d becomes a sub.d subtraction instruction. Figure 4 FIG. 1 is a flow chart of another binary translation method provided by an embodiment of the present invention. Figure 4As shown, in an embodiment of the present invention, for a host machine instruction stream contained in a basic block obtained after translation, a preset parameter off can be set, and the initial value of off can be set to 0, and a pending instruction is obtained from the host machine instruction stream, and it is determined whether the pending instruction is an end instruction (logical end instruction). If not, it indicates that there are still unprocessed host machine instructions. At this time, it can be determined whether the pending instruction is a first-category instruction. If so, the parameter value of the preset parameter off is updated, and the instruction is removed from the host machine instruction stream, and the next host machine instruction is obtained again as the pending instruction.

[0070] Accordingly, if the instruction to be processed is a logical end instruction, that is, there is no instruction to be processed, it can be determined whether the preset parameter off is 0. If not, it is necessary to insert an instruction to correct the stack pointer register, that is: generate a first-class instruction based on the current parameter value of the preset parameter and insert it before the logical end instruction. If off is 0, it means that the stack pointer register does not need to be updated and corrected, and the instruction processing flow can be directly ended.

[0071] Accordingly, if the instruction to be processed is not a first-class instruction, it can be determined whether the instruction to be processed is a second-class instruction, and whether the preset parameter off is not 0. If the instruction to be processed is not a second-class instruction or the current parameter value of the preset parameter is 0, there is no need to process the instruction to be processed, and the next host machine instruction can be directly obtained as the instruction to be processed. If the instruction to be processed is a second-class instruction and off is not 0, it is further determined whether the source operand of the instruction to be processed includes the immediate operand imm, and whether the sum of off and imm (off+imm) is within the expression range of the immediate operand imm. If so, the immediate operand of the instruction to be processed is updated, and imm=imm+off is updated, and the next host machine instruction is obtained again as the instruction to be processed. Correspondingly, if not, that is, if the source operand of the instruction to be processed does not include the immediate operand imm, or off+imm is not within the expression range of imm (off+imm exceeds the expression range of imm), it is necessary to insert an instruction to correct the stack pointer register, that is: generate a first-class instruction based on the current parameter value of the preset parameter and insert it before the instruction to be processed. Afterwards, the parameter values ​​of the preset parameters are reinitialized to 0.

[0072] After the above instruction processing, the embodiment of the present invention can Figure 3 The host instruction stream after the client instruction stream is translated is optimized as shown in Table 3 below: Table 3

[0073] It can be seen from the above table that the embodiment of the present invention can delay the merging calculation of stack pointer calculation instructions whose source operands include stack pointer registers and immediate operands, optimize the 7 stack pointer calculation instructions in the above example into 1, delete some stack pointer calculation instructions, reduce the number of code instructions generated after translation, reduce the instruction expansion rate after translation, and thus improve the operating efficiency of the binary translator.

[0074] In another embodiment, a binary translation method is provided, which translates client instructions of a complex instruction set architecture into host instructions of a reduced instruction set according to basic blocks, including the following operations: Translating each of a plurality of client stack operation instructions in a basic block into a combination of a stack access instruction of a host machine and a stack pointer calculation instruction for adjusting a stack top, wherein source operands of the stack access instruction and the stack pointer calculation instruction include a stack pointer register and an immediate value; removing at least some stack pointer calculation instructions from the host instruction stream; Modifying the immediate offset in the stack access instruction to make the stack access operation point to the top of the stack to compensate for the top of the stack adjustment of the removed stack pointer calculation instruction; and The stack pointer adjustment accumulated by the removed stack pointer instructions is implemented with a stack pointer calculation instruction.

[0075] As shown in Table 2, the POP instruction of X86 includes the operations of loading and adjusting the stack pointer, and is translated into a combination of the ld.d memory access instruction and the addi addition instruction including LA. The ld.d instruction loads the top data of the stack into the stack pointer register $s4. The addi.d $s4, $s4, 8 instruction is used to adjust the stack pointer. The adjusted stack pointer is used for the next ld.d operation.

[0076] There is redundancy in the LA instruction sequence of Table 2. To optimize the redundancy, as shown in Table 3, the addi.d $s4, $s4, 8 instructions corresponding to each POP instruction are removed from the LA instruction sequence. On the other hand, the immediate offset in the stack access instruction is modified to make the stack access operation point to the top of the stack to ensure the accuracy of the operation. In the embodiments of Tables 2 and 3, corresponding to the POP instruction, the immediate offset of the ld.d instruction in LA is incremented by 8 to compensate for the stack pointer adjustment operation of addi.d $s4, $s4, 8. It can be understood that for the PUSH instruction, subi.d $s4, $s4, 8 can be used to compensate for the stack pointer adjustment operation.

[0077] Before the end of the basic block, $s4 is corrected uniformly, and all removed stack pointer calculation instructions are compensated by an addi instruction to ensure the correctness of the data in the stack pointer register $s4 at the end of the basic block.

[0078] The instruction used for compensation can be a stack pointer calculation instruction remaining in the basic block. For example, in Table 3, the LA stack pointer calculation instruction addi corresponding to ret is not removed, but its immediate offset is adjusted to 56, accumulating the stack pointer adjustments of all removed instructions.

[0079] Alternatively, instead of using addi corresponding to ret, a stack pointer calculation instruction is inserted before ret which is the end mark of the basic block, so as to implement the cumulative stack pointer adjustment of all removed stack pointer instructions in the basic block.

[0080] The X86 client stack operation instructions include the pop instruction POP, the push instruction PUSH, the function call CALL and the return instruction RET in Table 1, and the stack management instructions ENTER and LEAVE. For instructions including the pop operation, in addition to POP and RET in the example of Table 2, there are also CALL and LEAVE. The pop operation increases the stack pointer, and the stack pointer calculation instruction in LA is the addition instruction addi; for instructions including the push operation, the stack pointer decreases, and the stack pointer calculation instruction is the subtraction instruction.

[0081] In the above embodiment, each of the multiple X86 client stack operation instructions in the basic block is translated into a combination of a stack access instruction of the host machine and a stack pointer calculation instruction for adjusting the stack top, and then the redundancy in the translated instruction sequence is optimized.

[0082] In another embodiment, multiple client stack operation instructions in a basic block are translated into multiple host stack memory access instructions and a stack pointer calculation instruction, and the source operands of the stack memory access instructions and the stack pointer calculation instruction include a stack pointer register and an immediate value. For example, the X86 instruction sequence in the first column of Table 3 is directly translated into the LA instruction in the third column, rather than translated into the second column and then optimized.

[0083] Based on the type of each client stack operation instruction, the immediate offset of the host stack access instruction is adjusted so that each stack access operation points to the top of the stack. For example, for a POP instruction, the immediate offset of the stack access instruction is incremented.

[0084] The immediate offset of the stack pointer calculation instruction reflects the accumulation of the immediate offsets of multiple host memory access instructions. Similarly, before the end of the basic block, $s4 is uniformly corrected to ensure the correctness of the data in the stack pointer register $s4 at the end of the basic block. For example, in Table 3, addi.d $s4, $s4, 56, the immediate offset reflects the accumulation of the immediate offsets of 7 X86 stack operation instructions.

[0085] Figure 5 is a structural diagram of an instruction processing device provided by an embodiment of the present invention, wherein the device is applied to a translator, such as Figure 5 As shown, the device 20 may include: A first acquisition module 201 is used to acquire a first type of instruction included in the host instruction stream after translating the client instruction stream into the host instruction stream; the first type of instruction is a stack pointer calculation instruction and the source operand of the first type of instruction includes a stack pointer register and an immediate operand; The merging module 202 is used to merge the M first-category instructions into N first-category instructions based on the source operands of each of the first-category instructions when the number of the first-category instructions is M; M is a positive integer greater than 1, and N is a positive integer less than M.

[0086] Optionally, the merging module includes: A second acquisition submodule, used for acquiring host machine instructions from the host machine instruction stream as instructions to be processed according to the instruction execution order; A first updating submodule, configured to update a parameter value of a preset parameter based on an immediate operand of the instruction to be processed if the instruction to be processed is an instruction of the first category, and delete the instruction to be processed from the host machine instruction stream; an initial value of the preset parameter is 0; The first execution submodule is used to re-execute the operation of obtaining the host machine instruction from the host machine instruction stream as the instruction to be processed, until the current instruction to be processed is a logical end instruction, generate a first-category instruction based on the current parameter value of the preset parameter, and insert the generated first-category instruction as the previous instruction of the logical end instruction.

[0087] Optionally, the device further comprises: a second updating module, configured to update the immediate operand of the instruction to be processed based on the current parameter value of the preset parameter if the instruction to be processed is a second type of instruction and the source operand of the instruction to be processed includes an immediate operand; the second type of instruction is an instruction other than the first type of instruction whose source operand includes a stack pointer register; The second execution module is used to re-execute the operation of obtaining the host machine instruction from the host machine instruction stream as the instruction to be processed.

[0088] Optionally, the second updating module includes: A second acquisition submodule, used for acquiring the sum of the current parameter value and the current value of the immediate operand of the instruction to be processed as the value to be updated; The third updating submodule is used to update the immediate operand of the instruction to be processed to the value to be updated if the value to be updated does not exceed the immediate operand range of the instruction to be processed.

[0089] Optionally, the device further comprises: The third execution module is used for executing the operation of updating the immediate operand of the instruction to be processed based on the current parameter value of the preset parameter when the current parameter value of the preset parameter is not 0.

[0090] Optionally, the device further comprises: a generating module, configured to generate a first-category instruction based on a current parameter value of the preset parameter when the instruction to be processed is the second-category instruction and if the source operand of the instruction to be processed does not include an immediate operand, or the value to be updated exceeds a range of immediate operands of the instruction to be processed; An insertion module is used to insert the generated first-category instruction as the previous instruction of the instruction to be processed, and update the parameter value of the preset parameter to 0.

[0091] In summary, after translating the client instruction stream into the host instruction stream, the embodiment of the present invention obtains the first-category instructions included in the host instruction stream; the first-category instructions are stack pointer calculation instructions and the source operands of the first-category instructions include stack pointer registers and immediate operands; when the number of the first-category instructions is M, based on the source operands of each of the first-category instructions, the M first-category instructions are merged into N first-category instructions; M is a positive integer greater than 1, and N is a positive integer less than M. In this way, the embodiment of the present invention can process the host instructions after translation and before execution, merge the M first-category instructions into N, reduce the number of translated first-category instructions, reduce the instruction expansion rate after translation, and thus improve the execution efficiency of the translator.

[0092] The present application also provides an electronic device, see Figure 6 , including: a processor 701, a memory 702, and a computer program 7021 stored in the memory and executable on the processor, wherein the processor implements the binary translation method of the aforementioned embodiment when executing the program.

[0093] The present application also provides a readable storage medium. When the instructions in the storage medium are executed by a processor of an electronic device, the electronic device can execute the binary translation method of the aforementioned embodiment.

[0094] The present application also provides a binary translator program product, which, when running on a host machine, executes the binary translation methods of the embodiments of the present application.

[0095] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0096] The algorithm and display provided herein are not inherently related to any particular computer, virtual system or other device. Various general purpose systems can also be used together with the teachings based on this. According to the above description, it is obvious that the structure required for constructing such systems. In addition, the present invention is not directed to any specific programming language either. It should be understood that various programming languages ​​can be utilized to realize the content of the present invention described herein, and the description of the above specific languages ​​is for disclosing the best mode of the present invention.

[0097] In the description provided herein, a large number of specific details are described. However, it is understood that embodiments of the present invention can be practiced without these specific details. In some instances, well-known methods, structures and techniques are not shown in detail so as not to obscure the understanding of this description.

[0098] Similarly, it should be understood that in order to streamline the present invention and aid in understanding one or more of the various inventive aspects, in the above description of exemplary embodiments of the present invention, the various features of the present invention are sometimes grouped together into a single embodiment, figure, or description thereof. However, this disclosed method should not be interpreted as reflecting the following intention: that the claimed invention requires more features than the features explicitly recited in each claim. More specifically, as reflected in the claims below, inventive aspects lie in less than all the features of the individual embodiments disclosed above. Therefore, the claims that follow the specific embodiment are hereby expressly incorporated into the specific embodiment, with each claim itself serving as a separate embodiment of the present invention.

[0099] Those skilled in the art will appreciate that the modules in the devices in the embodiments may be adaptively changed and arranged in one or more devices different from the embodiments. The modules or units or components in the embodiments may be combined into one module or unit or component, and further may be divided into a plurality of submodules or subunits or subcomponents. All features disclosed in this specification (including the accompanying claims, abstracts and drawings) and all processes or units of any method or device so disclosed may be combined in any combination, except that at least some of such features and / or processes or units are mutually exclusive. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying claims, abstracts and drawings) may be replaced by an alternative feature that provides the same, equivalent or similar purpose.

[0100] The various component embodiments of the present invention may be implemented in hardware, or in software modules running on one or more processors, or in a combination thereof. It should be understood by those skilled in the art that a microprocessor or a digital signal processor (DSP) may be used in practice to implement some or all of the functions of some or all of the components in the sorting device according to the present invention. The present invention may also be implemented as a device or apparatus program for executing part or all of the methods described herein. Such a program for implementing the present invention may be stored on a computer-readable medium, or may be in the form of one or more signals. Such a signal may be downloaded from an Internet website, or provided on a carrier signal, or provided in any other form.

[0101] It should be noted that the above embodiments illustrate the present invention rather than limit it, and that those skilled in the art may devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference symbol between brackets shall not be construed as a limitation on the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "one" or "an" preceding an element does not exclude the presence of a plurality of such elements. The present invention may be implemented by means of hardware comprising a number of different elements and by means of a suitably programmed computer. In a unit claim enumerating a number of devices, several of these devices may be embodied by the same hardware item. The use of the words first, second, and third, etc., does not indicate any order. These words may be interpreted as names.

[0102] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0103] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

[0104] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A binary translation method, characterized in that: The method is applied to a translator, and the method comprises: After translating the client instruction stream into a host instruction stream, obtaining a first type of instruction contained in the host instruction stream; the first type of instruction is a stack pointer calculation instruction and the source operand of the first type of instruction includes a stack pointer register and an immediate operand; When the number of the first category instructions is M, based on the source operands of each of the first category instructions, the M first category instructions are merged into N first category instructions; M is a positive integer greater than 1, and N is a positive integer less than M.

2. The method according to claim 1, characterized in that The step of merging the M first-category instructions into N first-category instructions based on the source operands of the first-category instructions comprises: Obtaining host machine instructions from the host machine instruction stream as instructions to be processed according to the instruction execution order; If the instruction to be processed is an instruction of the first category, updating a parameter value of a preset parameter based on an immediate operand of the instruction to be processed, and deleting the instruction to be processed from the host machine instruction stream; an initial value of the preset parameter is 0; The operation of obtaining the host machine instruction from the host machine instruction stream as the instruction to be processed is performed again until the current instruction to be processed is a logical end instruction, a first-class instruction is generated based on the current parameter value of the preset parameter, and the generated first-class instruction is inserted as the previous instruction of the logical end instruction.

3. The method according to claim 2, characterized in that After obtaining the host machine instruction from the host machine instruction stream as the instruction to be processed, the method further includes: If the instruction to be processed is a second type of instruction, when the source operand of the instruction to be processed includes an immediate operand, the immediate operand of the instruction to be processed is updated based on the current parameter value of the preset parameter; the second type of instruction is an instruction other than the first type of instruction whose source operand includes a stack pointer register; The operation of obtaining the host machine instruction from the host machine instruction stream as the instruction to be processed is performed again.

4. The method according to claim 3, characterized in that: The updating of the immediate operand of the instruction to be processed based on the current parameter value of the preset parameter includes: Obtaining the sum of the current parameter value and the current value of the immediate operand of the instruction to be processed as the value to be updated; When the value to be updated does not exceed the range of the immediate operand of the instruction to be processed, the immediate operand of the instruction to be processed is updated to the value to be updated.

5. The method according to claim 3, characterized in that: The method further comprises: When the current parameter value of the preset parameter is not 0, the operation of updating the immediate operand of the instruction to be processed based on the current parameter value of the preset parameter is performed.

6. The method according to claim 4, characterized in that When the instruction to be processed is the second type of instruction, the method further includes: If the source operand of the instruction to be processed does not include an immediate operand, or the value to be updated exceeds the immediate operand range of the instruction to be processed, then generating a first-category instruction based on the current parameter value of the preset parameter; The generated first-category instruction is inserted as the previous instruction of the instruction to be processed, and the parameter value of the preset parameter is updated to 0.

7. The method according to claim 1, characterized in that The client is a complex instruction set architecture, and the host is a reduced instruction set architecture.

8. A binary translation method for translating client instructions of a complex instruction set architecture into host instructions of a reduced instruction set according to basic blocks, comprising: Translate each of the plurality of client stack operation instructions in the basic block into a combination of a stack access instruction of the host machine and a stack pointer calculation instruction for adjusting the stack top, wherein source operands of the stack access instruction and the stack pointer calculation instruction include a stack pointer register and an immediate value; removing at least some stack pointer calculation instructions from the host instruction stream; Modify the immediate offset in the stack access instruction to make the stack access operation point to the top of the stack to compensate for the stack top adjustment of the removed stack pointer calculation instruction; as well as The stack pointer adjustment accumulated by the removed stack pointer instructions is implemented with a stack pointer calculation instruction.

9. The method according to claim 8, wherein: The client stack operation instructions include pop instructions, push instructions, function call and return instructions, and stack management instructions; the stack pointer calculation instructions include addition instructions or subtraction instructions.

10. The method according to claim 8, wherein: The remaining unremoved stack pointer calculation instructions are used to implement the cumulative stack pointer adjustment of the removed stack pointer instructions.

11. The method according to claim 8, wherein: Before the end of the basic block, a stack pointer calculation instruction is inserted to implement the cumulative stack pointer adjustment of all removed stack pointer instructions in the basic block.

12. A binary translation method for translating client instructions of a complex instruction set architecture into host instructions of a reduced instruction set according to basic blocks, the method comprising: Translating a plurality of client stack operation instructions in a basic block into a plurality of host stack memory access instructions and a stack pointer calculation instruction, wherein source operands of the stack memory access instruction and the stack pointer calculation instruction include a stack pointer register and an immediate value; Based on the type of each client stack operation instruction, the immediate offset of each host stack access instruction is adjusted so that each stack access operation points to the top of the stack; and The immediate offset of the stack pointer calculation instruction reflects the accumulation of the immediate offsets of the plurality of host stack memory access instructions.

13. An electronic device, characterized in that: include: A processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the processor implements the method according to any one of claims 1 to 12 when executing the program.

14. A readable storage medium, characterized in that: When the instructions in the storage medium are executed by a processor of an electronic device, the electronic device is enabled to execute the method according to any one of claims 1 to 12.

15. A binary translation program product, comprising instructions, which, when executed by a processor, cause the processor to execute the method according to any one of claims 1 to 12.

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