Binary translation method, electronic device, readable storage medium and program product

Abstract

Embodiments of the present application provide a binary translation method, an electronic device, a readable storage medium and a program product. The method is applied to a translator. After translating a client instruction stream into a host instruction stream, a first type of instruction included in the host instruction stream is obtained. The first type of instruction is a stack pointer calculation instruction, and a source operand of the first type of instruction includes a stack pointer register and an immediate number operand. In a case where a number of the first type of instructions is M, the M first type of instructions are combined into N first type of instructions based on the source operand of each of the first type of instructions. The M is a positive integer greater than 1, and the N is a positive integer less than M. In this way, embodiments of the present application can process the host instruction after translation but before execution, combine the M first type of instructions into the N first type of instructions, reduce the number of the first type of instructions after translation, reduce the instruction inflation rate after translation, and thus improve the execution efficiency of the translator.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of computer, in particular relates to a binary translation method and device, electronic equipment and readable storage medium. BACKGROUND

[0002] In the field of computer technology, a binary translation technology is usually used, that is, a translator is used to translate client instructions into host instructions, so that a program compiled in one architecture can run on a hardware platform of another architecture.

[0003] At present, most translators usually use the method of "translation while execution", and the architectures used by the client and the host are usually different, which often leads to a great increase in the number of host instructions obtained after translation compared with the number of original client instructions, thereby reducing the execution efficiency of the translator. SUMMARY

[0004] The present application provides a binary translation method, electronic equipment, readable storage medium and program product, in order to solve the problem of low execution efficiency of the translator.

[0005] In order to solve the above technical problems, the present application is implemented as follows:

[0006] In a first aspect, the present application provides a binary translation method, which is applied to a translator, and the method comprises:

[0007] After translating the client instruction stream into the host instruction stream, a first type of instruction contained in the host instruction stream is obtained; the first type of instruction is a stack pointer calculation instruction, and the source operand of the first type of instruction contains a stack pointer register and an immediate number operand;

[0008] In the case where the number of the first type of instructions is M, the M first type of instructions are combined into N first type of instructions based on the source operand of each first type of instruction; M is a positive integer greater than 1, and N is a positive integer less than M.

[0009] In a second aspect, the present application provides a binary translation method for translating client instructions of a complex instruction set architecture into host instructions of a reduced instruction set architecture according to basic blocks, which comprises:

[0010] Each of a plurality of client stack operation instructions in a basic block is translated into a combination of a stack memory access instruction and a stack pointer calculation instruction for adjusting the top of the stack of the host, and the source operand of the stack memory access instruction and the stack pointer calculation instruction includes a stack pointer register and an immediate number;

[0011] At least part of the stack pointer calculation instructions are removed from the host instruction stream;

[0012] modify the immediate offset in the stack access instruction to point the stack access operation to the top of the stack to compensate for the stack top adjustment of the removed stack pointer calculation instruction; and

[0013] implement the stack pointer adjustment accumulated by the removed stack pointer instruction with one stack pointer calculation instruction.

[0014] In a third aspect, the present application provides an electronic device, comprising a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the processor implements the binary translation method when executing the program.

[0015] In a fourth aspect, the present application provides a readable storage medium, which, when the instructions in the storage medium are executed by a processor of an electronic device, enables the electronic device to perform the binary translation method.

[0016] The binary translation method provided by the embodiments of the present application is applied to a translator, and after translating a client instruction stream into a host instruction stream, a first type of instruction contained in the host instruction stream is acquired; the first type of instruction is a stack pointer calculation instruction, and a source operand of the first type of instruction contains a stack pointer register and an immediate number operand; in a case where a number of the first type of instructions is M, the M first type of instructions are merged into N first type of instructions based on the source operand of each first type of instruction; the M is a positive integer greater than 1, and the N is a positive integer less than M. In this way, the embodiments of the present application can process the host instruction after translation but before execution, and merge and process the M first type of instructions into the N first type of instructions, so as to reduce the number of the first type of instructions after translation, reduce the instruction inflation rate after translation, and thus improve the execution efficiency of the translator. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are some embodiments of the present application, and those skilled in the art can also obtain other drawings according to these drawings without any creative effort.

[0018] Figure 1 is a step flowchart of a binary translation method provided by the embodiments of the present application;

[0019] Figure 2 is a flowchart of a binary translation provided by the embodiments of the present application;

[0020] Figure 3 is a schematic diagram of a basic block provided by the embodiments of the present application;

[0021] Figure 4is a flow diagram of another binary translation method provided by the embodiment of the present application;

[0022] Figure 5 is a structural diagram of an instruction processing device provided by the embodiment of the present application.

[0023] Figure 6 is a structural diagram of an electronic device provided by the embodiment of the present application. DETAILED DESCRIPTION

[0024] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of the present application.

[0025] Figure 1 is a step flow diagram of a binary translation method provided by the embodiment of the present application. The method is applied to a translator, such as Figure 1 As shown in the figure, the method can include the following steps:

[0026] Step 101: After translating a client instruction stream into a host instruction stream, a first type of instruction contained in the host instruction stream is acquired; the first type of instruction is a stack pointer calculation instruction, and a source operand of the first type of instruction contains a stack pointer register and an immediate number operand.

[0027] Step 102: In a case where a number of the first type of instructions is M, the M first type of instructions are merged into N first type of instructions based on source operands of each of the first type of instructions; M is a positive integer greater than 1, and N is a positive integer less than M.

[0028] The above translator (may also be referred to as a binary translator) is used to translate a source program A in a guest (GUEST) into a target program B in a host (HOST), and execute the target program B in the host. Instructions in the source program A can be referred to as guest instructions, and instructions in the target program B can be referred to as host instructions. Accordingly, the above guest instruction stream refers to an instruction stream composed of a plurality of guest instructions, and the above host instruction stream refers to an instruction stream composed of a plurality of host instructions. Optionally, since the translator usually uses an intermediate code to represent the details of the translated instructions in the process of translating the guest instructions into the host instructions, and then converts the intermediate code into real host instructions and stores the real host instructions in the memory, the host instructions in the embodiment of the present application can be the real host instructions that have been stored in the memory, or can be the intermediate code obtained by translating the guest instructions, which can be selected according to actual instruction processing requirements, and the embodiment of the present application does not limit this.

[0029] It should be noted that the guest in the embodiment of the present application adopts a CISC architecture, and the host adopts a RISC architecture. Illustratively, the guest in the embodiment of the present application can adopt an x86 architecture, and the host can adopt a LoongArch architecture. The RISC architecture can only operate the memory through load / store, and the memory cannot be used as an operand of other instructions. The CISC can use the memory as an operand of pop, push and other instructions. Therefore, one pop or push instruction of the CISC will be translated into one load / store instruction and one instruction for adjusting the stack pointer in the RISC, which may cause the problems of instruction redundancy and expansion.

[0030] Further, the translator in the embodiment of the present application can be a dynamic binary translator, which usually translates the instructions of the guest architecture into the instructions of the host architecture and runs at runtime. After reading the binary file, the translator usually translates and executes in the unit of a basic block (Translation Block, TB). Therefore, the above guest instruction stream and host instruction stream can be the instructions contained in one basic block.

[0031] Figure 2 is a flowchart of binary translation provided by the embodiment of the present application, as Figure 2As shown, after the translator reads the executable program, i.e. binary file, of the client platform, it usually translates and executes in the granularity of basic blocks. Before executing a basic block, the target program is first read in the code cache. If a basic block that has been translated is found, the code block is executed. If the basic block is not found in the code cache, a translation operation is performed and the translated code is placed in the code cache, and then the basic block is executed. After executing a basic block, the next basic block is searched in the code cache, and the cycle continues until the program execution ends.

[0032] Further, since the binary translation technology is used to run a source program of one CPU architecture on another CPU architecture, the client and the host use two different architectures, and the instruction sets of different architectures are quite different. In the translation process, a plurality of host instructions may be required to express one client instruction, thereby causing the client instruction to be translated into more host instructions. Figure 2 It can be seen that the more instructions after translation, the lower the execution efficiency of the translator, and the overall translation efficiency of the program is also reduced to some extent.

[0033] On this basis, the embodiment of the present application can process the instructions of the host instruction stream after translating the client instruction stream into the host instruction stream.

[0034] The stack pointer register is a register for pointing to the top of the stack, and the stack is particularly important in the program execution process, such as function calling, local variable management, and context switching, which all require the stack to be accurately used through the stack pointer register to achieve efficient memory management and control flow. Therefore, the instructions for operating the stack pointer register in the program are usually more, and the embodiment of the present application can optimize the number of instructions.

[0035] The first type of instruction refers to a stack pointer calculation instruction whose source operand contains a stack pointer register and an immediate number operand. It is used to calculate and update the value of the stack pointer register, and the destination operand is the stack pointer register, one source operand is the stack pointer register, and at least one source operand is an immediate number. For example, if there is a host instruction addi.d sp, sp, 8, which means that the stack pointer register sp is added by 8 and stored in sp, it is used to calculate and update the value of the stack pointer register based on the immediate number and the current value of the stack pointer register, and it is the first type of instruction.

[0036] Specifically, the embodiment of the present application can traverse the host instructions in the host instruction stream, determine whether the destination operand of each host instruction is the stack pointer register corresponding to the host platform, if yes, further determine whether the source operand of each host instruction contains the stack pointer register and the immediate number operand, if yes, it can be determined that it is the first type of instruction. Correspondingly, if the destination operand is not the stack pointer register or the source operand does not contain the stack pointer register and the immediate number operand, it can be determined that it is not the first type of instruction.

[0037] Wherein, the above M is a positive integer greater than 1, and the above N is a positive integer less than M. Specifically, in the case that the number of the first type of instructions is M, it indicates that there are at least two first type of instructions for calculating the stack pointer register in the host instruction stream, at this time the embodiment of the present application can combine the M first type of instructions into N first type of instructions. Wherein, the above N can be set according to the actual situation, in one case, N can be 1, which is not limited by the embodiment of the present application.

[0038] Specifically, the above combination operation can be implemented based on the source operand of each first type of instruction, which can be implemented based on the immediate number operand in the source operand of the first type of instruction, specifically, the immediate number operands of each first type of instruction can be combined into N immediate numbers, and N first type of instructions can be generated based on the N immediate numbers.

[0039] Specifically, since the stack pointer calculation instruction is used to update the stack pointer register, and the stack pointer calculation instruction updates the top position of the stack by adding and subtracting the stack pointer register, the embodiment of the present application can combine the first type of instructions to combine the M times of updating the stack pointer register in the host instruction stream into N times, which can reduce the number of host instructions required to be executed to a certain extent, and improve the execution efficiency of the translator. At the same time, for dynamic translator, the overall program translation efficiency can also be improved to a certain extent.

[0040] In summary, after the embodiment of the present application translates the client instruction stream into the host instruction stream, it obtains the first type of instructions contained in the host instruction stream; the first type of instruction is a stack pointer calculation instruction and the source operand of the first type of instruction contains a stack pointer register and an immediate number operand; in the case that the number of the first type of instructions is M, the M first type of instructions are combined into N first type of instructions based on the source operand of each first type of instruction; the M is a positive integer greater than 1, and the N is a positive integer less than M. In this way, the embodiment of the present application can process the M first type of instructions to N first type of instructions before execution after translation, reduce the number of first type of instructions after translation, reduce the instruction inflation rate after translation, and thus improve the execution efficiency of the translator.

[0041] Optionally, the operation of merging the M first-type instructions into N first-type instructions based on the source operand of each first-type instruction can specifically include the following operations performed by the processor:

[0042] S21, obtaining a host instruction from the host instruction stream as a to-be-processed instruction according to an instruction execution order.

[0043] S22, if the to-be-processed instruction is the first-type instruction, updating a parameter value of a preset parameter based on an immediate number operand of the to-be-processed instruction, and deleting the to-be-processed instruction from the host instruction stream; an initial value of the preset parameter is 0.

[0044] S23, repeatedly performing the operation of obtaining a host instruction from the host instruction stream as a to-be-processed instruction until a current to-be-processed instruction is a logical end instruction, generating a first-type instruction based on a current parameter value of the preset parameter, and inserting the generated first-type instruction as a previous instruction of the logical end instruction.

[0045] The instruction execution order refers to a logical execution order of the host instructions in the instruction stream, and an instruction after the logical execution order usually depends on an execution result of a previous instruction. On this basis, the embodiment of the present application can sequentially obtain host instructions from the host instruction stream as to-be-processed instructions according to the instruction execution order.

[0046] The preset parameter can be a variable parameter set in advance, and the initial value thereof can be 0. The embodiment of the present application can assign the preset parameter a value of 0 in advance before performing the above step 102. Specifically, since the immediate number in the stack pointer calculation instruction is usually a signed immediate number, the preset parameter can also be a signed variable. Further, in the case where the to-be-processed instruction is the first-type instruction, the embodiment of the present application can update the parameter value of the preset parameter based on the to-be-processed instruction. Specifically, since the first-type instruction is the stack pointer calculation instruction, the updating operation can be implemented based on the immediate number operand of the to-be-processed instruction, and can be adding the immediate number operand of the to-be-processed instruction to the parameter value of the preset parameter. For example, if the preset parameter is off, and the immediate number operand of the to-be-processed instruction is imm, the updating operation can be off = off + imm.

[0047] Further, the embodiment of the present application can update the parameter value of the preset parameter based on the immediate number operand of the to-be-processed instruction, and can pass the change value of the stack pointer register in the current instruction stream through the preset parameter. On this basis, the embodiment of the present application can directly delete the to-be-processed instruction from the host instruction stream.

[0048] Further, the step S21 can be performed again, and the operation of the step S22 can be performed on the first type of instructions in the host instruction stream in sequence, so that the stack pointer calculation instructions in the host instruction stream can be converted into the update of the parameter value, and each stack pointer calculation instruction in the host instruction stream does not need to be embodied.

[0049] The last instruction in the instruction stream according to the instruction execution order can be a jump instruction or a basic block end instruction. Further, the operation of the step S22 can be performed on the first type of instructions in the host instruction stream in sequence, and when the obtained to-be-processed instruction is the last instruction, a first type of instruction can be generated based on the current parameter value of the preset parameter, and the generated first type of instruction is inserted as the last instruction. Specifically, the operation of generating a first type of instruction can be that the current parameter value of the preset parameter is taken as an immediate number operand of the first type of instruction, so that the first type of instruction for calculating the stack pointer register is generated.

[0050] Through the above operation, the plurality of first type of instructions in the host instruction stream can be combined into one first type of instruction, that is, the stack pointer register is not calculated in sequence, but is calculated by accumulation of the immediate number operand.

[0051] The embodiment of the present application obtains a host instruction from the host instruction stream as a to-be-processed instruction according to the instruction execution order; if the to-be-processed instruction is the first type of instruction, the parameter value of the preset parameter is updated based on the immediate number operand of the to-be-processed instruction, and the to-be-processed instruction is deleted from the host instruction stream; the initial value of the preset parameter is 0; the operation of obtaining a host instruction from the host instruction stream as a to-be-processed instruction is performed again, and when the current to-be-processed instruction is the last instruction, a first type of instruction is generated based on the current parameter value of the preset parameter, and the generated first type of instruction is inserted as the last instruction. In this way, the change value of the stack pointer register in the host instruction stream can be transmitted through the preset parameter, so that each stack pointer calculation instruction in the host instruction stream does not need to be embodied, and only one first type of instruction needs to be inserted before the last instruction in the host instruction stream, so that the delay combined calculation of the stack pointer register can be realized, the number of host instructions can be greatly reduced, and the running efficiency of the translator can be improved.

[0052] Optionally, after the operation of obtaining a host instruction from the host instruction stream as a to-be-processed instruction, the embodiment of the present application can further include:

[0053] S31, if the to-be-processed instruction is a second type of instruction, and the source operand of the to-be-processed instruction contains an immediate number operand, updating the immediate number operand of the to-be-processed instruction based on the current parameter value of the preset parameter; the second type of instruction is an instruction whose source operand contains a stack pointer register and which is other than the first type of instruction.

[0054] S32, performing again the operation of obtaining a host machine instruction from the host machine instruction stream as a to-be-processed instruction.

[0055] The second type of instruction refers to an instruction whose source operand contains a stack pointer register and which is other than the first type of instruction, and the destination operand of the second type of instruction is any operand, and the source operand of the second type of instruction contains a stack pointer register. Taking a host machine as an example of LoongArch, if there is a host machine instruction: addi.d t0, sp, 8, which indicates that the value of the sp register is added by 8 and then stored in the register t0, the instruction needs to be executed based on the value of the stack pointer register, and is a second type of instruction. In this case, the execution of the second type of instruction depends on the value of the stack pointer register, and since the first type of instruction in the host machine instruction stream is deleted by the embodiment of the application, that is, before the execution of the second type of instruction, the stack pointer register is not updated to an accurate value. In this case, in order to ensure the accuracy of the execution of the second type of instruction, the embodiment of the application can update the immediate number operand of the to-be-processed instruction based on the current parameter value of the preset parameter.

[0056] Specifically, the source operand of the second type of instruction contains a stack pointer register, and if the source operand of the second type of instruction also contains an immediate number operand, the execution of the second type of instruction depends on both the stack pointer register and the immediate number operand. Since the first type of instruction is deleted by the embodiment of the application in the foregoing step, the value of the stack pointer register is not accurate at this time, which will affect the execution result of the second type of instruction. At this time, the current parameter value of the preset parameter can represent the to-be-updated value of the stack pointer register, so that the embodiment of the application can directly add the current parameter value of the preset parameter to the immediate number operand of the to-be-processed instruction, to ensure the accuracy of the execution of the second type of instruction.

[0057] For example, taking the to-be-processed instruction as a second type of instruction, the source operand of the to-be-processed instruction containing an immediate number operand imm, and the preset parameter being off as an example, the updating operation can be imm = imm + off.

[0058] Further, after updating the immediate number operand of the second type of instruction, the operation of obtaining a to-be-processed instruction can be performed again, that is, the next host machine instruction is processed.

[0059] In the embodiment of the present application, if the to-be-processed instruction is a second type of instruction, and the source operand of the to-be-processed instruction contains an immediate number operand, the immediate number operand is updated based on the current parameter value of the preset parameter; the second type of instruction is an instruction whose source operand contains a stack pointer register, in addition to the first type of instruction; and the operation of obtaining a host machine instruction from the host machine instruction stream as a to-be-processed instruction is performed again. In this way, the number of translated host machine instructions can be reduced, and the immediate number operand of the second type of instruction that depends on the stack pointer register can be updated based on the current parameter value of the preset parameter, thereby avoiding the problem of inaccurate execution result of the second type of instruction caused by deletion of the first type of instruction.

[0060] Optionally, the operation of updating the immediate number operand of the to-be-processed instruction based on the current parameter value of the preset parameter can specifically include the following operations in the embodiment of the present application:

[0061] S41, obtaining the sum of the current parameter value and the current numerical value of the immediate number operand of the to-be-processed instruction as a to-be-updated numerical value.

[0062] S42, updating the immediate number operand of the to-be-processed instruction to the to-be-updated numerical value in a case where the to-be-updated numerical value does not exceed the range of the immediate number operand of the to-be-processed instruction.

[0063] Specifically, since the operand of an instruction often has a corresponding expression range, the operand cannot exceed the corresponding expression range, and if it exceeds, the instruction can not be executed or can be executed incorrectly. On this basis, the embodiment of the present application can first determine whether the updated immediate number exceeds the expression range of the corresponding operand before updating the immediate number operand of the to-be-processed instruction.

[0064] Specifically, the sum of the current parameter value of the preset parameter and the current numerical value of the immediate number operand of the to-be-processed instruction can be taken as a to-be-updated numerical value, which is the numerical value to be replaced by the original immediate number operand. Specifically, the operand range of an instruction is often fixed, which is often related to the bit width of the register contained in the to-be-processed instruction or the instruction function, and the operand range of the instruction is often specified in the instruction manual. On this basis, the embodiment of the present application can determine the immediate number operand range of the to-be-processed instruction based on the description in the instruction manual corresponding to the instruction set architecture of the host machine, or can be calculated according to the bit of the immediate number threshold in the to-be-processed instruction. Alternatively, the immediate number operand range of the to-be-processed instruction can also be obtained by accepting input information of relevant personnel, which can be set according to actual conditions, and the embodiment of the present application does not limit this.

[0065] Specifically, in a case that the to-be-updated value does not exceed the range of the immediate number operand of the to-be-processed instruction, the immediate number operand of the to-be-processed instruction is updated as the to-be-updated value, that is, the to-be-updated value is used as the immediate number operand in the source operand of the to-be-processed instruction.

[0066] In the embodiment of the present application, the sum of the current parameter value of the preset parameter and the current value of the immediate number operand of the to-be-processed instruction is obtained as the to-be-updated value, and in a case that the to-be-updated value does not exceed the range of the immediate number operand of the to-be-processed instruction, the immediate number operand of the to-be-processed instruction is updated as the to-be-updated value. In this way, the immediate number operand of the second type of instruction can be updated, and meanwhile, it is ensured that the updated immediate number does not exceed the range of the immediate number operand of the to-be-processed instruction, thereby ensuring the normal execution of the instruction.

[0067] Optionally, the embodiment of the present application can further include the following steps.

[0068] S51, in a case that the current parameter value of the preset parameter is not 0, performing the operation of updating the immediate number operand of the to-be-processed instruction based on the current parameter value of the preset parameter.

[0069] Specifically, the embodiment of the present application can judge whether the current parameter value of the preset parameter is 0 before updating the immediate number operand of the to-be-processed instruction. If the current parameter value of the preset parameter is not 0, it indicates that the stack pointer register has a value to be calculated, and the value of the stack pointer register at this time is inaccurate, so the immediate number operand of the second type of instruction needs to be corrected. At this time, the operation of updating the immediate number operand of the to-be-processed instruction based on the current parameter value of the preset parameter can be performed.

[0070] Correspondingly, if the current parameter value of the preset parameter is 0, it indicates that the stack pointer register does not have a value to be calculated, and the value of the stack pointer register at this time is accurate, so the immediate number operand of the second type of register does not need to be corrected, and the next host instruction can be directly obtained as the to-be-processed instruction.

[0071] In the embodiment of the present application, in a case that the current parameter value of the preset parameter is not 0, the operation of updating the immediate number operand of the to-be-processed instruction based on the current parameter value of the preset parameter is performed. In this way, whether the stack pointer register has a value to be calculated is judged by whether the current parameter value of the preset parameter is 0, and in a case that the current parameter value of the preset parameter is not 0, the operation of updating the immediate number operand is performed. This can reduce unnecessary immediate number operand updating operation and reduce data processing amount.

[0072] Optionally, in a case that the to-be-processed instruction is the second type of instruction, the embodiment of the present application can further include the following steps.

[0073] S61, if the source operand of the to-be-processed instruction does not contain an immediate number operand, or the to-be-updated value is out of the range of the immediate number operand of the to-be-processed instruction, generating a first type of instruction based on the current parameter value of the preset parameter.

[0074] S62, inserting the generated first type of instruction as the last instruction of the to-be-processed instruction, and updating the parameter value of the preset parameter to 0.

[0075] In the case that the source operand of the to-be-processed instruction does not contain an immediate number operand, the execution of the second type of instruction is usually implemented based on the stack pointer register and other registers, and at this time, the second type of instruction cannot be corrected by updating the immediate number operand, and therefore, a first type of instruction can be generated to update the stack pointer register. Correspondingly, in the case that the to-be-updated value is out of the range of the immediate number operand of the to-be-processed instruction, if the immediate number operand is updated by the to-be-updated value, the second type of instruction may be executed incorrectly or cannot be executed, and therefore, the immediate number operand of the second type of instruction can not be updated, and a first type of instruction can be generated based on the current parameter value of the preset parameter to update the stack pointer register.

[0076] Specifically, the current parameter value of the preset parameter can be taken as the immediate number operand of the first type of instruction, and the stack pointer register can be taken as a destination operand and a source operand, so as to obtain a first type of instruction.

[0077] Further, after the first type of instruction is generated, the first type of instruction can be inserted as the last instruction of the to-be-processed instruction, that is, the first type of instruction is inserted into the host instruction stream before the to-be-processed instruction. In this way, the stack pointer register can be updated to an accurate value by the generated and inserted first type of instruction before the execution of the second type of instruction, so as to ensure the execution accuracy of the second type of instruction.

[0078] In the embodiment of the application, if the source operand of the to-be-processed instruction does not contain an immediate number operand, or the to-be-updated value is out of the range of the immediate number operand of the to-be-processed instruction, a first type of instruction is generated based on the current parameter value of the preset parameter; the generated first type of instruction is inserted as the last instruction of the to-be-processed instruction, and the parameter value of the preset parameter is updated to 0. In this way, when the immediate number operand of the to-be-processed instruction cannot be updated, the stack pointer register can be updated to an accurate value by the generated and inserted first type of instruction before the execution of the second type of instruction, so as to ensure the execution accuracy of the second type of instruction and avoid the problem of inaccurate instruction execution caused by the merging of the first type of instruction.

[0079] Optionally, the operation of generating a first-type instruction based on the preset parameter value of the current parameter value can be:

[0080] In a case where the preset parameter value of the current parameter value is not 0, a first-type instruction is generated based on the preset parameter value of the current parameter value.

[0081] It can be understood that, in a case where the preset parameter value of the current parameter value is 0, it indicates that the stack pointer register does not have a value to be updated, i.e., the current value of the stack pointer register is an accurate value, and it is not necessary to update the stack pointer register, so that the generation and insertion of the first-type instruction are not necessary, and unnecessary instruction generation and insertion operations can be avoided. Accordingly, in a case where the preset parameter value of the current parameter value is not 0, it indicates that the stack pointer register has a value to be updated, and it is necessary to update the stack pointer register, so that the generation and insertion of the first-type instruction are necessary to update the stack pointer register.

[0082] It should be noted that there are many differences in instructions supported by hardware design of different Instruction Set Architecture (ISA), which leads to incompatibility of executable files compiled based on an ISA instruction set and other platforms, and binary translation technology is needed to enable programs compiled on one architecture to run on hardware platforms of another architecture. With the continuous improvement of microprocessor performance, the feasibility of running source programs of another CPU architecture under a CPU architecture through binary translation is getting stronger and stronger, which makes the binary translation technology develop more. However, the technology still has technical problems such as low translation efficiency and too many redundant operations. For example: when translating from CISC to RISC, since the instruction function of CISC architecture is powerful, a single instruction can perform complex operations such as memory access, arithmetic operations and logical operations. In the RISC architecture, simple fixed-length instructions are used, and each instruction usually only performs a simple operation. In order to achieve complex functions, multiple instructions need to be combined to achieve them under the RISC architecture. Therefore, for the binary translator from CISC architecture to RISC, the instructions of the original instruction set will be converted into more instructions, resulting in low execution efficiency of the binary translator.

[0083] Exemplarily, taking the x86 architecture as the GUEST platform and the LoongArch (LA) architecture as the HOST platform as examples, in the x86 architecture, RSP, ESP and SP are all registers for representing stack pointers (i.e., stack pointer registers), but they are suitable for different bit widths. RSP is used to represent a 64-bit register, ESP represents a 32-bit register, and SP represents a 16-bit register. RSP is a 64-bit register and can process a 64-bit address space. ESP is a 32-bit register and can process a 32-bit address space. SP is a 16-bit register. The following description all uses ESP to represent the stack pointer register in the x86 architecture.

[0084] Taking the x86 architecture as an example, the stack operation instructions related to the calculation of the ESP register generally include the instructions shown in Table 1 below:

[0085] Table 1

[0086]

[0087] Taking the translation of the guest machine instructions by the user mode emulator (Quick EMUlator User Mode Emulation, QEMU) as an example, Figure 3 is a schematic diagram of a basic block provided by an embodiment of the present application, as shown in Figure 3 , which contains the instructions of one TB. The eight instructions all involve the calculation of the stack pointer register in the x86 architecture. The processing of Qemu is to calculate the stack pointer register in each x86 instruction translation.

[0088] The following table is the instruction translation of Figure 3 shown in the related art, and the obtained instruction schematic after the instruction translation is shown in Table 2 below:

[0089] Table 2

[0090]

[0091] In the table, "inst_xx" represents other instructions, "reg_*" represents registers unrelated to the stack pointer register, and $s4 represents the x86 stack pointer register after register mapping. Specifically, the host instruction "addi.drd, rj, si12" adds the [63:0] bits of data in general-purpose register rj to the 64-bit sign-extended immediate value si12, and writes the result to general-purpose register rd. "add.d rd, rj, rk" adds the [63:0] bits of data in general-purpose register rj to the [63:0] bits of data in general-purpose register rk, and writes the result to general-purpose register rd. "ld.d rd, rj, si12" retrieves a double word of data from memory and writes it to general-purpose register rd; the memory access address is calculated by adding the value in general-purpose register rj to the sign-extended 12-bit immediate value si12. As can be seen, the translated code has 7 instructions involving the calculation of the stack pointer register (addi.d $s4, $s4, 8), and the source operands of these 7 instructions all include the stack pointer register and immediate operands. That is, the translated instruction stream contains 7 first-class instructions.

[0092] The x86 guest program basic block in the example above only contains POP and RET instructions involving stack pop operations. For 64-bit registers, the pop instruction increments the stack pointer by 8. Therefore, in the LA host basic block, `addi.d $s4, $s4,8` is used as the stack pointer calculation instruction (Type 1 instruction) to calculate the stack pointer. Those skilled in the art will understand that for PUSH and CALL instructions involving push operations, the stack pointer decreases, and `addi.d` becomes a sub.d subtraction instruction. Figure 4 This is a flowchart illustrating another binary translation method provided in an embodiment of the present invention, as shown below. Figure 4 As shown, in this embodiment of the invention, for the host instruction stream contained in a basic block obtained after translation, a preset parameter 'off' can be set. The initial value of 'off' can be set to 0. The instruction to be processed is obtained from the host instruction stream, and it is determined whether the instruction to be processed is an end instruction (logical end instruction). If not, it indicates that there are still unprocessed host instructions. At this time, it can be determined whether the instruction to be processed is a first type instruction. If so, the parameter value of the preset parameter 'off' is updated, the instruction is removed from the host instruction stream, and the next host instruction is obtained as the instruction to be processed.

[0093] Correspondingly, if the to-be-processed instruction is a logical end instruction, i.e., there is no to-be-processed instruction, it can be judged whether the preset parameter off is 0, if not, a first type instruction is inserted to correct the stack pointer register, i.e., a first type instruction is generated based on the current parameter value of the preset parameter and is inserted before the logical end instruction. If off is 0, it indicates that the stack pointer register does not need to be updated, at this time, the instruction processing flow can be directly ended.

[0094] Correspondingly, if the to-be-processed instruction is not a first type instruction, it can be judged whether the to-be-processed instruction is a second type instruction, and whether the preset parameter off is not 0, if the to-be-processed instruction is not a second type instruction or the current parameter value of the preset parameter is 0, the to-be-processed instruction does not need to be processed, and the next host instruction can be directly obtained as the to-be-processed instruction. If the to-be-processed instruction is a second type instruction and off is not 0, it is further judged whether the source operand of the to-be-processed instruction contains an immediate number operand imm, and whether the sum (off+imm) of off and imm is within the expression range of the immediate number operand imm, if yes, the immediate number operand of the to-be-processed instruction is updated, imm=imm+off is updated, and the next host instruction is obtained again as the to-be-processed instruction. Correspondingly, if no, i.e., if the source operand of the to-be-processed instruction does not contain the immediate number operand imm, or off+imm is not within the expression range of imm (off+imm exceeds the expression range of imm), a first type instruction is inserted to correct the stack pointer register, i.e., a first type instruction is generated based on the current parameter value of the preset parameter and is inserted before the to-be-processed instruction. Then, the parameter value of the preset parameter is reinitialized to 0.

[0095] After the above instruction processing, the embodiment of the present application can optimize the translated host instruction stream of the client instruction stream shown in Table 2 to Table 3 as shown in the following table: Figure 3

[0096] Table 3

[0097]

[0098] As can be seen from the above table, the embodiment of the present application can delay the combined calculation of the stack pointer calculation instruction whose source operand contains the stack pointer register and the immediate number operand, optimize the 7 stack pointer calculation instructions of the above example into 1, delete part of the stack pointer calculation instruction, reduce the number of generated code instructions after translation, and reduce the instruction inflation rate after translation, thereby improving the running efficiency of the binary translator.

[0099] In another embodiment, a binary translation method is provided, which translates a client instruction of a complex instruction set architecture into a host instruction of a simplified instruction set according to a basic block, including the following operations:

[0100] ​Each of the multiple guest stack operation instructions in the basic block is translated into a combination of a host stack memory access instruction and a stack pointer calculation instruction for adjusting the top of the stack, wherein the source operands of the stack memory access instruction and the stack pointer calculation instruction include the stack pointer register and an immediate value.

[0101] Remove at least a portion of the stack pointer from the host instruction stream to compute instructions;

[0102] Modify the immediate offset in the stack memory access instruction to make the stack memory access operation point to the top of the stack, in order to compensate for the stack top adjustment of the removed stack pointer calculation instruction; and

[0103] The stack pointer adjustment accumulated from the removed stack pointer instructions is implemented using a single stack pointer calculation instruction.

[0104] As shown in Table 2, the x86 POP instruction includes operations to load and adjust the stack pointer. It is translated into a combination of the ld.d memory access instruction containing LA and the addi addition instruction. ld.d loads the data at the top of the stack into the stack pointer register $s4. The addi.d $s4, $s4, 8 instruction is used to adjust the stack pointer. The adjusted stack pointer is used for the next ld.d operation.

[0105] The LA instruction sequence in Table 2 contains redundancy. To optimize this redundancy, as shown in Table 3, the instructions `addi.d $s4, $s4, 8` corresponding to each POP instruction are removed from the LA instruction sequence. Furthermore, the immediate offsets in the stack access instructions are modified to ensure the stack access operation points to the top of the stack, guaranteeing operational accuracy. In the embodiments of Tables 2 and 3, corresponding to the POP instruction, the immediate offset of the `ld.d` instruction in the LA is incremented by 8, compensating for the stack pointer adjustment operation of `addi.d $s4, $s4, 8`. It can be understood that for the PUSH instruction, `subi.d $s4, $s4, 8` can be used to compensate for the stack pointer adjustment operation.

[0106] Before the basic block ends, $s4 is uniformly corrected. An addi instruction is used to compensate for all the removed stack pointer calculation instructions, ensuring the correctness of the data in the stack pointer register $s4 when the basic block ends.

[0107] The instruction used for compensation can be the remaining stack pointer calculation instruction in the basic block. For example, in Table 3, the LA stack pointer calculation instruction addi corresponding to ret was not removed, but its immediate offset was adjusted to 56, accumulating the stack pointer adjustments of all removed instructions.

[0108] Alternatively, instead of using the addi corresponding to ret, a stack pointer calculation instruction is inserted before ret, which serves as the end marker of the basic block, to achieve cumulative stack pointer adjustment for all removed stack pointer instructions in the basic block.

[0109] The X86 guest stack manipulation instructions include the pop instruction POP, the push instruction PUSH, the function call instruction CALL, and the return instruction RET in Table 1, as well as the stack management instructions ENTER and LEAVE. For instructions containing pop operations, in addition to POP and RET in the example of Table 2, there are also CALL and LEAVE, the pop operation increases the stack pointer, and the stack pointer calculation instruction in LA is the addition instruction addi; for instructions containing push operations, the stack pointer decreases, and the stack pointer calculation instruction is the subtraction instruction.

[0110] In the above embodiment, each of the multiple X86 guest stack manipulation instructions in a basic block is translated into a combination of a host stack access instruction and a stack pointer calculation instruction for adjusting the stack top, and then the redundancies in the translated instruction sequence are optimized.

[0111] In another embodiment, the multiple guest stack manipulation instructions in a basic block are translated into multiple host stack access instructions and one stack pointer calculation instruction, the source operands of the stack access instructions and the stack pointer calculation instruction include the stack pointer register and an immediate number. For example, the X86 instruction sequence in Table 3, Column 1 is directly translated into the LA instruction in Column 3, instead of being translated into Column 2 and then optimized.

[0112] Based on the type of each guest stack manipulation instruction, the immediate number offset of the host stack access instruction is adjusted so that each stack access operation points to the stack top. For example, for the POP instruction, the immediate number offset of the stack access instruction is incremented.

[0113] The immediate number offset of the stack pointer calculation instruction reflects the accumulation of the immediate number offsets of the multiple host access instructions. Similarly, before the end of the basic block, the stack pointer register $s4 is uniformly corrected to ensure the correctness of the data in the stack pointer register $s4 at the end of the basic block. For example, in Table 3, addi.d $s4, $s4, 56, the immediate number offset reflects the accumulation of the immediate number offsets of the 7 X86 stack manipulation instructions.

[0114] Figure 5 is a structural diagram of an instruction processing apparatus provided by an embodiment of the present application, and the apparatus is applied to a translator, such as Figure 5 As shown in the figure, the apparatus 20 can include:

[0115] A first obtaining module 201 is configured to, after translating a guest instruction stream into a host instruction stream, obtain a first type of instruction contained in the host instruction stream; the first type of instruction is a stack pointer calculation instruction, and the source operand of the first type of instruction contains a stack pointer register and an immediate number operand.

[0116] The merging module 202 is configured to merge M first-type instructions into N first-type instructions based on source operands of the M first-type instructions, where M is a positive integer greater than 1, and N is a positive integer less than M.

[0117] Optionally, the merging module comprises:

[0118] The second obtaining sub-module is configured to obtain a host instruction from the host instruction stream as a to-be-processed instruction according to an instruction execution order.

[0119] The first updating sub-module is configured to update a parameter value of a preset parameter based on an immediate operand of the to-be-processed instruction, and delete the to-be-processed instruction from the host instruction stream if the to-be-processed instruction is the first-type instruction; an initial value of the preset parameter is 0.

[0120] The first executing sub-module is configured to perform again the operation of obtaining a host instruction from the host instruction stream as a to-be-processed instruction until the current to-be-processed instruction is a logical end instruction, generate a first-type instruction based on a current parameter value of the preset parameter, and insert the generated first-type instruction as a previous instruction of the logical end instruction.

[0121] Optionally, the apparatus further comprises:

[0122] The second updating module is configured to update an immediate operand of the to-be-processed instruction based on a current parameter value of the preset parameter if the to-be-processed instruction is a second-type instruction and the source operand of the to-be-processed instruction contains the immediate operand; the second-type instruction is an instruction whose source operand contains a stack pointer register, except the first-type instruction.

[0123] The second executing module is configured to perform again the operation of obtaining a host instruction from the host instruction stream as a to-be-processed instruction.

[0124] Optionally, the second updating module comprises:

[0125] The second obtaining sub-module is configured to obtain a sum of the current parameter value and a current numerical value of the immediate operand of the to-be-processed instruction as a to-be-updated numerical value.

[0126] The third updating sub-module is configured to update the immediate operand of the to-be-processed instruction as the to-be-updated numerical value if the to-be-updated numerical value does not exceed a range of the immediate operand of the to-be-processed instruction.

[0127] Optionally, the apparatus further comprises:

[0128] The third executing module is configured to, when the current parameter value of the preset parameter is not 0, execute the operation of updating the immediate number operand of the to-be-processed instruction based on the current parameter value of the preset parameter.

[0129] Optionally, the apparatus further comprises:

[0130] The generating module is configured to, when the to-be-processed instruction is the second type of instruction, if the source operand of the to-be-processed instruction does not contain an immediate number operand, or the to-be-updated value is out of the range of the immediate number operand of the to-be-processed instruction, generate a first type of instruction based on the current parameter value of the preset parameter.

[0131] The inserting module is configured to insert the generated first type of instruction as the last instruction of the to-be-processed instruction, and update the parameter value of the preset parameter to 0.

[0132] In summary, the embodiment of the application obtains the first type of instruction contained in the host instruction stream after translating the client instruction stream into the host instruction stream; the first type of instruction is a stack pointer calculation instruction, and the source operand of the first type of instruction contains a stack pointer register and an immediate number operand; when the number of the first type of instructions is M, the M first type of instructions are merged into N first type of instructions based on the source operand of each first type of instruction; M is a positive integer greater than 1, and N is a positive integer less than M. In this way, the embodiment of the application can process the host instruction after translation before execution, merge M first type of instructions into N first type of instructions, reduce the number of first type of instructions after translation, reduce the instruction inflation rate after translation, and thus improve the execution efficiency of the translator.

[0133] The application further provides an electronic device, referring to Figure 6 , comprising a processor 701, a memory 702, and a computer program 7021 stored in the memory and executable on the processor, and the processor implements the binary translation method of the foregoing embodiment when executing the program.

[0134] The application further provides a readable storage medium, when the instructions in the storage medium are executed by the processor of the electronic device, the electronic device can execute the binary translation method of the foregoing embodiment.

[0135] The application further provides a binary translator program product, when running on a host machine, executing the binary translation method of the embodiments of the application.

[0136] For the apparatus embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the related parts refer to the part of the method embodiment.

[0137] The algorithms and displays presented herein are not inherently related to any particular computer, virtual system, or other apparatus. Various general purpose systems can be used with programs in accordance with the teachings herein, or it can prove convenient to construct more specialized apparatus to perform the required method steps. The required structure for a variety of these systems will be apparent from the description above. In addition, the present application is not intended to be limited to any particular programming language. It will be appreciated that there are many programming languages that can be used to implement the teachings herein, and any specific language can be chosen for use in this application.

[0138] In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the application can be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been described in detail in order to not obscure the understanding of this description.

[0139] Similarly, it is to be understood that the mechanical details of the application sometimes are presented in terms of certain spatially-related or geometrical configurations and / or descriptions. It will be appreciated by those skilled in the art that the application can be practiced without such specifically-named spatial / geometrical configurations and / or descriptions. Furthermore, it is to be understood that the use of certain specific language or terminology in the specification is merely to further aid a state of the art and is not intended to limit the scope of the application.

[0140] Those skilled in the art will appreciate that the modules in the apparatuses in the embodiments can be adapted and placed in one or more apparatuses other than the embodiments. The modules or units or components in the embodiments can be combined into one module or unit or component, and further can be divided into more sub-modules or sub-units or sub-components. Except that at least some of such features and / or processes or units are mutually exclusive, any combination of all the features disclosed in the specification (including the accompanying claims, abstract and drawings), and all processes or units of any methods or apparatuses disclosed so far can be adopted. Unless explicitly stated otherwise, each feature disclosed in the specification (including the accompanying claims, abstract and drawings) can be replaced by an alternative feature providing the same, equivalent or similar function.

[0141] The various component embodiments of the present application can be implemented in hardware, or as software modules running in one or more processors, or in combinations thereof. As will be appreciated by one skilled in the art, a microprocessor or digital signal processor (DSP) can be used in practice to implement some or all of the functionality of some or all of the components in the sequencing apparatus according to the present application. The present application can also be implemented as a program for executing part or all of the methods described herein on a device or apparatus. Such program(s) can be stored on computer readable media or can be transmitted over a network using any communication protocol.

[0142] It should be noted that the above-mentioned embodiments illustrate rather than limit the application, and that one skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word 'comprising' does not exclude the presence of elements or steps other than those listed in a claim. The word 'a' or 'an' preceding an element does not exclude the presence of a plurality of such elements. The application can be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the claims, the word 'first','second', 'third', etc. does not imply any order. These words are to be interpreted as names.

[0143] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the described system, device and unit can refer to the corresponding processes in the foregoing method embodiments, which will not be described here.

[0144] The above description is merely preferred embodiments of the present application, but not to limit the present application, any modification, equivalent replacement and improvement made within the spirit and principle of the present application shall be included in the protection scope of the present application.

[0145] The above description is merely preferred embodiments of the present application, but not to limit the present application, any modification, equivalent replacement and improvement made within the spirit and principle of the present application shall be included in the protection scope of the present application.

[0145] The above description is merely preferred embodiments of the present application, but not to limit the present application, any modification, equivalent replacement and improvement made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A binary translation method, characterized by, The method is applied to a translator, and the method comprises: After translating a client instruction stream into a host instruction stream, a first type of instruction contained in the host instruction stream is obtained; the first type of instruction is a stack pointer calculation instruction, and a source operand of the first type of instruction comprises a stack pointer register and an immediate number operand; the first type of instruction is used to update a value of the stack pointer register; In a case where a number of the first type of instruction is M, the M first type of instructions are combined into N first type of instructions based on source operands of the first type of instructions; the combining comprises removing part of the first type of instructions from the M first type of instructions, retaining N first type of instructions, and using the N first type of instructions to realize stack pointer adjustment accumulated by the removed first type of instructions; the M is a positive integer greater than 1, and the N is a positive integer less than M; the host instruction stream further comprises a stack memory access instruction; The method further comprises modifying an immediate number offset in the stack memory access instruction to make a stack memory access operation point to a stack top, so as to compensate for stack top adjustment of the removed first type of instruction.

2. The method of claim 1, wherein, The combining the M first type of instructions into the N first type of instructions based on the source operands of the first type of instructions comprises: According to an instruction execution order, a host instruction is obtained from the host instruction stream as a to-be-processed instruction; If the to-be-processed instruction is the first type of instruction, a parameter value of a preset parameter is updated based on an immediate number operand of the to-be-processed instruction, and the to-be-processed instruction is deleted from the host instruction stream; an initial value of the preset parameter is 0; The operation of obtaining a host instruction from the host instruction stream as a to-be-processed instruction is executed again until a current to-be-processed instruction is a logical end instruction, a first type of instruction is generated based on a current parameter value of the preset parameter, and the generated first type of instruction is inserted as a previous instruction of the logical end instruction.

3. The method of claim 2, wherein, After the obtaining of the host instruction from the host instruction stream as the to-be-processed instruction, the method further comprises: If the to-be-processed instruction is a second type of instruction, an immediate number operand of the to-be-processed instruction is updated based on the current parameter value of the preset parameter in a case where the source operand of the to-be-processed instruction comprises the immediate number operand; the second type of instruction is an instruction whose source operand comprises a stack pointer register but is not the first type of instruction; The operation of obtaining a host instruction from the host instruction stream as a to-be-processed instruction is executed again.

4. The method of claim 3, wherein, The updating of the immediate number operand of the to-be-processed instruction based on the current parameter value of the preset parameter comprises: A sum of the current parameter value and a current numerical value of the immediate number operand of the to-be-processed instruction is obtained as a to-be-updated numerical value; In a case where the to-be-updated numerical value does not exceed a range of the immediate number operand of the to-be-processed instruction, the immediate number operand of the to-be-processed instruction is updated as the to-be-updated numerical value.

5. The method of claim 3, wherein, The method further comprises: In a case where the current parameter value of the preset parameter is not 0, the operation of updating the immediate number operand of the to-be-processed instruction based on the current parameter value of the preset parameter is executed.

6. The method of claim 4, wherein, In the case that the to-be-processed instruction is the second type of instruction, the method further comprises: if the source operand of the to-be-processed instruction does not contain an immediate number operand, or the to-be-updated value exceeds the range of the immediate number operand of the to-be-processed instruction, generating a first type of instruction based on the current parameter value of the preset parameter; inserting the generated first type of instruction as the last instruction of the to-be-processed instruction, and updating the parameter value of the preset parameter to 0.

7. The method of claim 1, wherein, The client is a complex instruction set architecture, and the host is a reduced instruction set architecture.

8. A binary translation method for translating client instructions of a complex instruction set architecture into host instructions of a reduced instruction set architecture on a basic block basis, comprising: translating each of a plurality of client stack operation instructions in a basic block into a combination of a stack memory access instruction and a stack pointer calculation instruction for adjusting the top of the stack, the source operands of the stack memory access instruction and the stack pointer calculation instruction comprising a stack pointer register and an immediate number; removing at least part of the stack pointer calculation instructions from the host instruction stream; modifying the immediate number offset in the stack memory access instruction to make the stack memory access operation point to the top of the stack to compensate for the top of stack adjustment of the removed stack pointer calculation instructions; and accumulating the stack pointer adjustments of the removed stack pointer instructions with a stack pointer calculation instruction. The client stack operation instructions comprise pop instructions, push instructions, function call and return instructions, and stack management instructions; and the stack pointer calculation instructions comprise addition instructions or subtraction instructions.

9. The method of claim 8, wherein, The accumulated stack pointer adjustments of the removed stack pointer instructions are implemented with the remaining unremoved stack pointer calculation instructions.

10. The method of claim 8, wherein, A stack pointer calculation instruction is inserted before the end of the basic block to implement the accumulated stack pointer adjustments of all the removed stack pointer instructions in the basic block.

11. The method of claim 8, wherein, 12. A binary translation method for translating client instructions of a complex instruction set architecture into host instructions of a reduced instruction set architecture on a basic block basis, the method comprising: translating a plurality of client stack operation instructions in a basic block into a plurality of host stack memory access instructions and a stack pointer calculation instruction, the source operands of the stack memory access instructions and the stack pointer calculation instruction comprising a stack pointer register and an immediate number; based on the type of each client stack operation instruction, the immediate number offset of each host stack memory access instruction is adjusted to make each stack memory access operation point to the top of the stack; and the immediate number offset of the stack pointer calculation instruction reflects the accumulation of the immediate number offsets of the plurality of host stack memory access instructions. comprising:

13. An electronic device, comprising: a processor, a memory, and a computer program stored on the memory and executable on the processor, wherein the processor implements the method of any one of claims 1-12 when executing the program. The instructions in the storage medium, when executed by a processor of an electronic device, enable the electronic device to perform the method of any one of claims 1-12.

14. A readable storage medium, characterized by, 15. A binary translation program product comprising instructions which, when executed by a processor, cause the processor to perform the method of any one of claims 1-12. ​

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