Distribution network monitoring control edge computing chip system and method based on multi-core heterogeneity

Abstract

The embodiment of the invention provides a distribution network monitoring and controlling edge computing chip system and method based on multi-core heterogeneity, and belongs to the technical field of edge computing chips. The distribution network monitoring and controlling edge computing chip system based on multi-core heterogeneity comprises a main system and a subsystem, the main system comprises a plurality of processors and a power algorithm acceleration module; the subsystems comprise an MCU (Microprogrammed Control Unit) real-time subsystem, an Ethernet subsystem and an embedded security subsystem; the embedded security subsystem comprises a hardware algorithm module and an embedded security module; the main system is used for operating software applications and algorithm programs in the power distribution network; the MCU real-time subsystem is used for processing on-line tasks of electricity saving and voltage monitoring; the Ethernet subsystem is used for communicating with an external chip; and the embedded security subsystem is used for integrating an encryption algorithm. According to the method, the problem that tensor calculation kernels and floating point operation involved in part of specific power algorithms consume a large number of instruction periods during operation can be solved, and the stability of a distribution network system is facilitated.

Description

Technical Field

[0001] The present application relates to the field of edge computing chip technology, and in particular to a distribution network monitoring and control edge computing chip system and method based on multi-core heterogeneity. Background Art

[0002] At present, most of the monitoring and control chips for distribution networks in my country use single-core microcontrollers, which cannot effectively meet the growing demand for edge computing and high-concurrency applications. With the rapid increase in data volume, single-core chips cannot efficiently handle a large number of parallel tasks, resulting in slow system response.

[0003] At present, the edge computing chips on the market are mainly focused on edge intelligent reasoning, lacking support for multiple computing modes for the specific needs of distribution networks, which limits their flexibility and adaptability in complex application scenarios.

[0004] Existing monitoring and control chips are relatively single in function and cannot meet multiple requirements such as edge computing, intelligent reasoning, data encryption, and real-time control. This decentralization of functions may lead to complex system architecture and increase the difficulty of maintenance and upgrades. Summary of the invention

[0005] The main purpose of the embodiments of the present application is to provide a distribution network monitoring and control edge computing chip system and method based on multi-core heterogeneity.

[0006] The technical solution adopted by the present invention is:

[0007] On the one hand, an embodiment of the present invention provides a distribution network monitoring and control edge computing chip system based on multi-core heterogeneity, the system comprising a main system and a subsystem;

[0008] The main system includes several processors and a power algorithm acceleration module; the subsystem includes an MCU real-time subsystem, an Ethernet subsystem and an embedded security subsystem; the embedded security subsystem includes a hardware algorithm module and an embedded security module;

[0009] The main system is used to run software applications and algorithm programs in the distribution network;

[0010] The MCU real-time subsystem is used to handle online tasks such as power conservation and voltage monitoring;

[0011] The Ethernet subsystem is used to communicate with an external chip;

[0012] The embedded security subsystem is used to integrate encryption algorithms.

[0013] Furthermore, the main system communicates with the subsystem via an AMBA bus to control non-encrypted communication between the Ethernet subsystem and the embedded security subsystem.

[0014] Furthermore, the MCU real-time subsystem runs first at startup to provide initialization and peripheral configuration management for the main system;

[0015] The MCU real-time subsystem cooperates with the main system and supports encrypted communication through the AMBA bus.

[0016] Furthermore, the Ethernet subsystem is controlled by the main system and the MCU real-time subsystem through AMBA bus scheduling; the data transmission of the Ethernet subsystem includes encrypted communication and non-encrypted communication, and the sending and receiving of non-encrypted data is directly controlled by the main system.

[0017] Furthermore, the embedded security subsystem performs secure transmission of data between the main system and the MCU real-time subsystem.

[0018] Furthermore, the power algorithm acceleration module includes an ASIP module, a power algorithm task acceleration module, and a power communication task acceleration module;

[0019] The ASIP module is used to expand the C-SKY instruction set and optimize the control of the power algorithm acceleration module;

[0020] The power algorithm task acceleration module includes a digital signal processor and a tensor processing unit; the power algorithm task acceleration module is used to perform hardware acceleration on power system computing tasks;

[0021] The power communication task acceleration module is used to implement the hardware of the encryption algorithm.

[0022] On the other hand, an embodiment of the present invention further provides a multi-core heterogeneous distribution network monitoring and control edge computing method, which is implemented by the multi-core heterogeneous distribution network monitoring and control edge computing chip system as described above, and the method includes the following steps:

[0023] The distribution network monitoring and control edge computing is performed through the main system, MCU real-time subsystem, Ethernet subsystem, and embedded security subsystem;

[0024] Run software applications and algorithmic programs in the distribution network;

[0025] Handle online tasks of power conservation and voltage monitoring;

[0026] Communicate with external chips;

[0027] Integrated encryption algorithm.

[0028] Furthermore, the multi-core heterogeneous distribution network monitoring and control edge computing method further includes the following steps:

[0029] Load the main system program, receive OTA updates, flash firmware, and handle peripheral interrupts;

[0030] Utilize different types of CPU cores to handle high-performance computing and tasks;

[0031] Power algorithms and communication tasks are optimized through acceleration modules.

[0032] On the other hand, an embodiment of the present invention also provides a distribution network monitoring and control edge computing device based on multi-core heterogeneity, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the distribution network monitoring and control edge computing method based on multi-core heterogeneity as described above.

[0033] On the other hand, an embodiment of the present invention also provides a computer-readable storage medium, which stores computer-executable instructions, and the computer-executable instructions are used to enable a computer to execute the distribution network monitoring and control edge computing method based on multi-core heterogeneity as described above.

[0034] The embodiments of the present application include at least the following beneficial effects: The present application provides a distribution network monitoring and control edge computing chip system and method based on multi-core heterogeneity. The distribution network monitoring and control edge computing chip system based on multi-core heterogeneity of the present invention includes a main system and a subsystem; the main system includes several processors and a power algorithm acceleration module; the subsystem includes an MCU real-time subsystem, an Ethernet subsystem and an embedded security subsystem; the embedded security subsystem includes a hardware algorithm module and an embedded security module; the main system is used to run software applications and algorithm programs in the distribution network; the MCU real-time subsystem is used to process online tasks of power preservation and voltage monitoring; the Ethernet subsystem is used to communicate with external chips; the embedded security subsystem is used to integrate encryption algorithms. The present invention can solve the problem that tensor computing cores and floating-point operations involved in some specific power algorithms consume a large number of instruction cycles during operation, which is beneficial to the stability of the distribution network system. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 is a schematic diagram of a multi-core heterogeneous distribution network monitoring chip system provided by an embodiment of the present invention;

[0036] Figure 2 It is a schematic diagram of a data encryption and sending process provided by an embodiment of the present invention;

[0037] Figure 3 is a schematic diagram of a data encryption receiving process provided by an embodiment of the present invention;

[0038] Figure 4 is an ASIP module execution flow chart provided by an embodiment of the present invention;

[0039] Figure 5 It is a schematic diagram of the initialization startup sequence of a multi-core heterogeneous CPU provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0040] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below in conjunction with the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the embodiments of the present application. They are only examples of devices and methods consistent with some aspects of the embodiments of the present application as detailed in the attached claims.

[0041] It is understood that the terms "first", "second", etc. used in this application can be used to describe various concepts in this article, but unless otherwise specified, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another concept. For example, without departing from the scope of the embodiment of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the words "if" and "if" as used herein can be interpreted as "at the time of" or "when" or "in response to determination".

[0042] The terms "at least one", "multiple", "each", "any", etc. used in this application, at least one includes one, two or more, multiple includes two or more, each refers to each of the corresponding multiple, and any refers to any one of the multiple.

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0044] The present invention takes into account the computing tasks such as demand response, energy efficiency evaluation, low-carbon monitoring, intelligent control, AI / ML training and reasoning faced in the edge computing of the distribution network, and designs a power-specific edge computing chip based on software and hardware collaboration. In view of the characteristics of large data volume, multiple types of data and dispersion on the edge side, a domestic high-performance CPU core is adopted to realize fast and efficient chip data processing; in view of the real-time processing requirements of high-concurrency power applications, a special instruction set ASIP module is customized to realize targeted acceleration of power algorithms and ensure real-time response of power services; in view of the security requirements of power data, an embedded security module that supports the national secret algorithm IPSec network protocol and resists DPA attacks is designed to realize high-level security protection for data encryption processing; in view of the intelligent processing requirements of massive data on the edge side, a lightweight neural network processor is designed to realize flexible and efficient intelligent processing.

[0045] Before describing the embodiments of the present application in detail, some nouns and terms involved in the embodiments of the present application are first described. The nouns and terms involved in the embodiments of the present application are subject to the following explanations.

[0046] 1) MCU (Microcontroller Unit), is a microcontroller unit;

[0047] 2) AMBA (Advanced Microcontroller Bus Architecture), is an open system bus architecture;

[0048] 3) ASIP (Application-Specific Instruction-set Processor) module is a specific application processor;

[0049] 4) C-SKY instruction set, a microprocessor instruction set architecture (ISA);

[0050] 5) OTA update (Over-The-Air Update) refers to a technology that pushes software or firmware updates to devices via wireless networks (such as Wi-Fi, mobile data or Bluetooth);

[0051] 6) CK860 core, a high-performance processor core based on its C-SKY instruction set architecture (ISA);

[0052] 7) CK810 core, a processor core based on its own instruction set architecture (ISA);

[0053] 8) MCUSS (Microcontroller Unit Security Subsystem) is a secure microcontroller unit;

[0054] 9) ETHSS (Ethernet Security Subsystem) is a subsystem used for Ethernet communication security;

[0055] 10) MAC controller (Media Access Control Controller) is a hardware or software component used to manage and control media access in network communications;

[0056] 11) RMII / RGMII, RMII (Reduced Media-Independent Interface) and RGMII (Reduced Gigabit Media-Independent Interface) are two interface standards for Ethernet communication. They are mainly used for data transmission between network devices (such as Ethernet controllers and physical layer devices);

[0057] 12) External PHY Chip: an integrated circuit dedicated to physical layer (PHY) processing;

[0058] 13) IPsec (Internet Protocol Security) is a protocol used to protect IP communications;

[0059] 14) AES (Advanced Encryption Standard) is a widely used symmetric encryption algorithm;

[0060] 15) Anti-DPA attack (Differential Power Analysis, DPA), which is a security measure for cryptographic devices;

[0061] 16) DSP (Digital Signal Processing) is a technology for analyzing, modifying and synthesizing digital signals;

[0062] 17) TPU (Tensor Processing Unit), a hardware accelerator designed specifically to accelerate machine learning tasks;

[0063] 18) SM2 / SM3 / SM4 algorithms. SM2, SM3 and SM4 are the three core algorithms of China's national cryptographic algorithm (or China's commercial cryptographic algorithm);

[0064] 19) BOOT (boot) refers to the process of loading and starting the operating system after the computer system completes the post-power-on self-test (POST, Power-On Self-Test);

[0065] 20) FLASH, FLASH storage is a non-volatile storage technology;

[0066] 21) EMMC is a storage solution based on NAND Flash;

[0067] 22) SD card is a removable storage medium;

[0068] 23) DDR RAM Address refers to the specific address where data is stored in the dynamic random access memory (DDR RAM);

[0069] 24)SMP (Symmetric Multi-Processing) is a multi-processor architecture.

[0070] The embodiments of the present invention are further described below in conjunction with the accompanying drawings.

[0071] On the one hand, an embodiment of the present invention provides a distribution network monitoring and control edge computing chip system based on multi-core heterogeneity, the system includes a main system and a subsystem;

[0072] The main system includes several processors and power algorithm acceleration modules; the subsystems include MCU real-time subsystem, Ethernet subsystem and embedded security subsystem; the embedded security subsystem includes hardware algorithm module and embedded security module;

[0073] The main system is used to run software applications and algorithm programs in the distribution network;

[0074] The MCU real-time subsystem is used to handle online tasks such as power conservation and voltage monitoring;

[0075] The Ethernet subsystem is used to communicate with external chips;

[0076] Embedded security subsystem is used to integrate encryption algorithms.

[0077] The main system disclosed in the embodiment of the present invention communicates with the subsystem via the AMBA bus, and controls the non-encrypted communication between the Ethernet subsystem and the embedded security subsystem.

[0078] The MCU real-time subsystem disclosed in the embodiment of the present invention runs first at startup to provide initialization for the main system and configuration management of peripherals;

[0079] The MCU real-time subsystem collaborates with the main system to support encrypted communication through the AMBA bus.

[0080] The Ethernet subsystem disclosed in the embodiment of the present invention is controlled by the main system and the MCU real-time subsystem through AMBA bus scheduling; the data transmission of the Ethernet subsystem includes encrypted communication and non-encrypted communication, and the sending and receiving of non-encrypted data is directly controlled by the main system.

[0081] The embedded security subsystem disclosed in the embodiment of the present invention performs secure data transmission between the main system and the MCU real-time subsystem.

[0082] The power algorithm acceleration module disclosed in the embodiment of the present invention includes an ASIP module, a power algorithm task acceleration module, and a power communication task acceleration module;

[0083] The ASIP module is used to expand the C-SKY instruction set and optimize the control of the power algorithm acceleration module;

[0084] The power algorithm task acceleration module includes a digital signal processor and a tensor processing unit; the power algorithm task acceleration module is used to perform hardware acceleration on power system computing tasks;

[0085] The power communication task acceleration module is used to implement the hardware of the encryption algorithm.

[0086] As an optional implementation, in the design of the distribution network intelligent monitoring and control edge computing chip, the system structure is divided into a main system and multiple subsystems. The modules achieve efficient power monitoring and control through precise functional division and collaborative work. The following is a detailed expansion of the system structure.

[0087] 1. Main system

[0088] The main system is the core part of the multi-core heterogeneous chip, which is mainly responsible for running complex software applications and algorithm programs in the distribution network. It includes the following important components:

[0089] Multi-core processor: The main system is equipped with multiple CK860 cores. These high-performance CPU cores are designed to support ultra-high-performance computing tasks, especially when executing complex power-related algorithms. These processors can not only effectively run the software of the distribution network, but also handle advanced data analysis and AI algorithms, allowing the system to respond to changing power demand and fault conditions in real time.

[0090] Power algorithm acceleration module: This module is optimized for typical computing tasks in power systems. By integrating a lightweight tensor unit processor, this acceleration module can process large-scale data with higher parallelism and efficiency. This dedicated computing circuit enables the main system to provide significant performance improvements when facing power algorithms. Compared with traditional general-purpose computing units, the power algorithm acceleration circuit has obvious advantages in processing speed and calculation accuracy.

[0091] 2. Subsystem

[0092] The functions of the main system are supported and supplemented by multiple subsystems, including:

[0093] MCU Real-time Subsystem (MCUSS): This subsystem consists of two CK810 cores and focuses on handling real-time tasks such as power-off data preservation and voltage monitoring. MCUSS is the first system to start after the distribution network monitoring control chip is powered on. It is responsible for loading the main system program and performing necessary initialization. This subsystem is also responsible for receiving OTA update messages, flashing firmware, and processing interrupt requests from external devices to ensure that the main system can run smoothly.

[0094] Ethernet subsystem (ETHSS): The Ethernet subsystem achieves high-speed communication with external devices through multiple Ethernet MAC controllers, supporting data transmission rates up to 1000Mbps. This subsystem is responsible for connecting the main system to the external network, ensuring real-time upload of power data and immediate issuance of control commands, and has efficient data interaction capabilities.

[0095] Embedded security subsystem: This subsystem contains multiple modules related to communication security, mainly used to integrate the encryption algorithms required in power communication. It integrates the hardware algorithm module of the national secret algorithm, the 256-bit AES encryption algorithm, and the embedded security module against DPA attacks, providing high-security encryption services to ensure the security and integrity of data during transmission.

[0096] 3. Embedded security subsystem

[0097] The embedded security subsystem is an important component of the distribution network monitoring and control chip, including:

[0098] Hardware algorithm module: This module implements hardware acceleration of multiple encryption algorithms, supports national encryption algorithms such as SM2 / SM3 / SM4, and improves the efficiency and security of the encryption process. Through dedicated hardware implementation, it ensures that the system can respond quickly when encrypting and decrypting data, ensuring real-time performance and security.

[0099] Embedded security module: This module has a design that resists side-channel attacks, enhancing the security of the system. It protects cryptographic operations and prevents potential attackers from obtaining sensitive information through physical means, thereby ensuring the safe operation of the entire distribution network monitoring system.

[0100] 4. Overall functionality and collaboration

[0101] The entire system realizes comprehensive monitoring and control of the electrical parameters of access nodes through the collaborative work of the above modules, and has complex functions such as demand response, energy efficiency evaluation, low-carbon monitoring and intelligent regulation. The main system is decoupled from the underlying hardware by running the Linux operating system, achieving flexible software updates and user interaction; while the MCU real-time subsystem ensures the stability and real-time response capability of the system during operation.

[0102] The Ethernet subsystem and embedded security subsystem provide powerful communication and security guarantees, so that data can always remain safe and reliable during collection, transmission and storage. This hardware and software collaborative design enables the entire distribution network monitoring and control edge computing chip to work efficiently and stably when processing complex tasks, providing a solid foundation for the intelligent development of modern power systems.

[0103] On the other hand, an embodiment of the present invention further provides a multi-core heterogeneous distribution network monitoring and control edge computing method, which is implemented by a multi-core heterogeneous distribution network monitoring and control edge computing chip system as described above, and the method includes the following steps:

[0104] The distribution network monitoring and control edge computing is performed through the main system, MCU real-time subsystem, Ethernet subsystem, and embedded security subsystem;

[0105] Run software applications and algorithmic programs in the distribution network;

[0106] Handle online tasks of power conservation and voltage monitoring;

[0107] Communicate with external chips;

[0108] Integrated encryption algorithm.

[0109] The multi-core heterogeneous distribution network monitoring and control edge computing method disclosed in the embodiment of the present invention also includes the following steps:

[0110] Load the main system program, receive OTA updates, flash firmware, and handle peripheral interrupts;

[0111] Utilize different types of CPU cores to handle high-performance computing and tasks;

[0112] Power algorithms and communication tasks are optimized through acceleration modules.

[0113] As an optional implementation, the functional system structure of the distribution network intelligent monitoring and control edge computing chip in the embodiment of the present invention is:

[0114] Multi-core heterogeneous chip systems such as Figure 1As shown. The multi-core heterogeneous system consists of 1 main system and 3 subsystems. The main system is mainly used to process the main workload of the system, perform high-level control work, and run the Linux operating system. These tasks are completed by the 4 CK860 cores in the main system, and all system IPs and peripheral IPs are located in the main system. The 3 subsystems are used to implement specific functions. The MCU real-time subsystem (MCUSS) is a coprocessor subsystem that is mainly responsible for running the embedded real-time operating system. It can be used to handle real-time tasks such as power-off preservation and voltage monitoring. The computing tasks of this subsystem are mainly completed by 2 CK810 cores. The Ethernet subsystem (ETHSS) contains multiple Ethernet MAC controllers, which communicate with external PHY chips through RMII / RGMII, and the operating rate can be as high as 1000Mbps. The embedded security subsystem includes multiple communication security-related modules such as the national secret algorithm IPsec, the hardware algorithm module of the 256bit-AES encryption algorithm, and the embedded security module that resists DPA attacks.

[0115] In the main system, the CK860 core is a high-performance CPU core, mainly for ultra-high-performance computing, including AI algorithms and DSP-optimized instruction sets, capable of running complex software applications and algorithm programs in the distribution network. The power-specific algorithm acceleration module is a dedicated computing circuit processing unit, such as a lightweight tensor unit processor. Compared with general-purpose computing units, the power-specific algorithm acceleration circuit has stronger pertinence, higher parallelism and massive data processing capabilities for typical computing tasks in the power system.

[0116] In the MCU real-time subsystem, the CK810 core is a high-performance CPU core with strong DSP processing capabilities and complete peripheral functions. The MCU real-time subsystem is the first system to be started when the distribution network monitoring control chip is powered on. It is responsible for loading the main system program, receiving OTA update messages, flashing firmware, handling peripheral interrupts, and other tasks that have high real-time requirements and assist the normal operation of the main system.

[0117] The Ethernet subsystem and embedded security subsystem are controlled by the main system and MCU real-time subsystem through the AMBA bus. The main system directly controls the reception and transmission of non-encrypted communication through the AMBA bus. The encrypted communication is encrypted by the main system and MCU real-time subsystem through the security subsystem. The main system extracts the encrypted data and then controls the Ethernet subsystem to send data. The data receiving process is that the main system and MCU real-time subsystem obtain data from the Ethernet subsystem, and then send it to the security subsystem for decryption. Finally, the main system extracts the decrypted data.

[0118] The heterogeneous forms of the power algorithm acceleration module of the embodiment of the present invention are:

[0119] 1. Application-specific instruction set ASIP module

[0120] Figure 1 Application specific instruction set ASIP modules such as Figure 2 As shown in the figure, based on the basic C-SKY instruction set, according to the typical computing tasks in the power application scenario, the ASIP instruction subset is added to realize the control of the power algorithm acceleration module. When the calculation that the software application needs to complete involves the power algorithm, the preset instruction is sent to execute the initialization of the power algorithm acceleration module, and then the CPU continues to execute subsequent instructions until the corresponding power algorithm calculation is processed and the CPU core is requested to respond. The CPU core retrieves the calculation result in the idle state and completes the accelerated calculation of the power algorithm.

[0121] During the accelerated calculation of the power algorithm, the CPU only completes the initialization and receiving actions of the power algorithm module, and the calculation action does not require the direct participation of the CPU. Figure 3 Data encryption receiving process, Figure 4 ASIP module execution process.

[0122] 2. Power algorithm task acceleration module

[0123] The function of the distribution network monitoring and control terminal based on the distribution network monitoring and control edge computing chip of the present invention is mainly to monitor the electrical parameters of the access node, and at the same time, it has complex edge decision-making and monitoring and control functions such as demand response, energy efficiency evaluation, low-carbon monitoring, and intelligent regulation, which involve complex calculations such as data collection processing and electrical parameter processing. In order to complete the corresponding computing tasks, the present invention involves special hardware acceleration modules for complex computing tasks, and realizes the chipization and hardwareization of power algorithms. The power algorithm acceleration module is mainly composed of a DSP digital signal processor unit and a TPU tensor processing unit.

[0124] 3. Power communication task acceleration module

[0125] Power communication encryption mainly uses the national secret algorithm and AES encryption algorithm. The encryption algorithms supported by the present invention include the national secret SM2 / SM3 / SM4 algorithm and the 256-bit AES encryption algorithm. The encryption algorithm is hardware-based through a dedicated encryption algorithm module to ensure the reliability and stability of the encryption process.

[0126] The hardware and software collaborative system design based on multi-core heterogeneous CPU in the embodiment of the present invention:

[0127] 1. Initialization startup method

[0128] The chip in the present invention includes two different CPU cores, and different CPU cores run different program systems. When the chip is initialized and the program is loaded, the designated CPU core (CK810.0) needs to boot the BOOT program from the external FLASH, EMMC, and SD card according to the BOOT configuration pin level, and load each program from the memory to the DDR running address of CK810.1 and CK860, such as Figure 5 shown.

[0129] 2. Software system function distribution

[0130] The multi-core heterogeneous chip in the present invention includes two CPU cores of different specifications, CK860 and CK810, which are responsible for completing the execution tasks of the main system and the MCU real-time subsystem respectively. The main system runs the Linux operating system, decouples software application development from the underlying chip architecture, and achieves target functions through high-level control of underlying peripherals and interfaces. Online software application updates and user interactions can be achieved through the running Linux operating system.

[0131] The MCU real-time subsystem runs an embedded real-time operating system, implements the coprocessor system functions of the main system's power-on initialization configuration and main system version management, handles real-time tasks with high response speed requirements such as external interrupts, main system operation status monitoring, power-off data protection, and is responsible for system resource management measures such as configuration of basic peripherals, management of peripherals and communication interface occupancy rights.

[0132] The key points of the present invention are:

[0133] 1) A distribution network monitoring and control edge computing chip system based on multi-core heterogeneity supporting edge computing is proposed;

[0134] 2) A method for integrating power algorithm acceleration modules based on ASIP modules is proposed;

[0135] 3) A power communication encryption method using the national secret algorithm encryption and decryption module is proposed;

[0136] 4) A hardware-software collaborative system structure based on multi-core heterogeneous architecture chips is proposed.

[0137] The present invention proposes a distribution network edge computing chip system architecture based on a multi-core heterogeneous architecture. Aiming at computing tasks with different computing characteristics of the distribution network, CPU cores of different specifications are used in the chip system in a targeted manner. The multi-core heterogeneous architecture complements the functional shortcomings of different CPU cores and meets the needs of different power computing loads. In order to solve the problem that tensor computing cores and floating-point operations involved in some specific power algorithms consume a large number of instruction cycles during operation, the distribution network monitoring and control edge computing chip in the present invention adds a tensor processing unit TPU and a digital signal processor unit DSP to optimize the execution efficiency of complex calculations, uses an ASIP module to organize a subset of instructions related to specific forms of calculations, and integrates the power algorithm acceleration module into the instruction processing system.

[0138] Due to the use of multi-core heterogeneous and integrated dedicated computing unit architecture, the distribution network monitoring and control edge computing chip of the present invention has a higher performance-to-power ratio in distribution network application scenarios than general embedded edge computing chips. At the same time, it has faster computing speed and higher real-time performance in some application scenarios that require a large number of floating-point numbers and tensor processing.

[0139] The present invention uses multiple types of processor cores in the chip architecture, so the software system architecture is different from the current SMP homogeneous multi-core architecture edge computing chips that generally run on a single operating system. According to the different real-time requirements of different tasks in power application scenarios, the present invention distributes these tasks to the real-time operating system and the Linux operating system according to the attributes and real-time requirements. The MCU real-time subsystem provides real-time response speed for edge control transactions, which is beneficial to the stability of the distribution network system. At the same time, the dual operating system decomposes the distribution network monitoring and control tasks, and configures applications with low coupling in different software systems, forming a low-coupling, high-cohesion software system architecture, which is beneficial to the rapid development of distribution network applications.

[0140] On the other hand, an embodiment of the present invention also provides a distribution network monitoring and control edge computing device based on multi-core heterogeneity, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the distribution network monitoring and control edge computing method based on multi-core heterogeneity as described above.

[0141] The processor may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc.

[0142] The memory may include various types of storage units, such as system memory, read-only memory (ROM), and permanent storage. Among them, ROM can store static data or instructions required by the processor or other modules of the computer. The permanent storage device may be a readable and writable storage device. The permanent storage device may be a non-volatile storage device that does not lose the stored instructions and data even after the computer is powered off. In some embodiments, the permanent storage device uses a large-capacity storage device (such as a magnetic or optical disk, flash memory) as a permanent storage device. In some other embodiments, the permanent storage device may be a removable storage device (such as a floppy disk, optical drive). The system memory may be a readable and writable storage device or a volatile readable and writable storage device, such as a dynamic random access memory. The system memory may store some or all instructions and data required by the processor at run time. In addition, the memory may include any combination of computer-readable storage media, including various types of semiconductor memory chips (DRAM, SRAM, SDRAM, flash memory, programmable read-only memory), and disks and / or optical disks may also be used. In some embodiments, the memory may include a readable and / or writable removable storage device, such as a laser disc (CD), a read-only digital versatile disc (e.g., DVD-ROM, double-layer DVD-ROM), a read-only Blu-ray disc, an ultra-density optical disc, a flash memory card (e.g., SD card, mini SD card, Micro-SD card, etc.), a magnetic floppy disk, etc. The computer-readable storage medium does not include carrier waves and transient electronic signals transmitted wirelessly or wired.

[0143] The memory stores executable codes, and when the executable codes are processed by the processor, the processor can execute part or all of the methods described above.

[0144] On the other hand, an embodiment of the present invention further provides a computer-readable storage medium, which stores computer-executable instructions, and the computer-executable instructions are used to enable a computer to execute the above-mentioned multi-core heterogeneous distribution network monitoring and control edge computing method.

[0145] It will be appreciated by those skilled in the art that all or some of the steps and systems in the disclosed method above may be implemented as software, firmware, hardware and appropriate combinations thereof. Some physical components or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor or a microprocessor, or may be implemented as hardware, or may be implemented as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or a non-transitory medium) and a communication medium (or a temporary medium). As known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, disk storage or other magnetic storage devices, or any other medium that may be used to store desired information and may be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically embodies computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0146] In the above description of this specification, the description with reference to the terms "one embodiment / example", "another embodiment / example" or "certain embodiments / examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0147] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

[0148] The above is a specific description of the preferred implementation of the present invention, but the present invention is not limited to the embodiments. Those skilled in the art may make various equivalent modifications or substitutions without violating the spirit of the present invention. These equivalent modifications or substitutions are all included in the scope defined by the claims of this application.

Claims

1. A multi-core heterogeneous distribution network monitoring and control edge computing chip system, characterized in that: The system includes a main system and a subsystem; The main system includes several processors and a power algorithm acceleration module; the subsystem includes an MCU real-time subsystem, an Ethernet subsystem and an embedded security subsystem; the embedded security subsystem includes a hardware algorithm module and an embedded security module; The main system is used to run software applications and algorithm programs in the distribution network; The MCU real-time subsystem is used to handle online tasks such as power conservation and voltage monitoring; The Ethernet subsystem is used to communicate with an external chip; The embedded security subsystem is used to integrate encryption algorithms.

2. The system according to claim 1, characterized in that The main system communicates with the subsystem via an AMBA bus to control the non-encrypted communication between the Ethernet subsystem and the embedded security subsystem.

3. The system according to claim 1, characterized in that The MCU real-time subsystem runs first at startup to provide initialization and peripheral configuration management for the main system; The MCU real-time subsystem cooperates with the main system and supports encrypted communication through the AMBA bus.

4. The system according to claim 1, characterized in that The Ethernet subsystem is controlled by the main system and the MCU real-time subsystem through AMBA bus scheduling; the data transmission of the Ethernet subsystem includes encrypted communication and non-encrypted communication, and the sending and receiving of non-encrypted data is directly controlled by the main system.

5. The system according to claim 1, characterized in that The embedded security subsystem performs secure data transmission between the main system and the MCU real-time subsystem.

6. The system according to claim 1, characterized in that The power algorithm acceleration module includes an ASIP module, a power algorithm task acceleration module, and a power communication task acceleration module; The ASIP module is used to expand the C-SKY instruction set and optimize the control of the power algorithm acceleration module; The power algorithm task acceleration module includes a digital signal processor and a tensor processing unit; the power algorithm task acceleration module is used to perform hardware acceleration on power system computing tasks; The power communication task acceleration module is used to implement the hardware of the encryption algorithm.

7. A distribution network monitoring and control edge computing method based on multi-core heterogeneity, which is implemented by a distribution network monitoring and control edge computing chip system based on multi-core heterogeneity as described in any one of claims 1 to 6, characterized in that: The method comprises the following steps: The distribution network monitoring and control edge computing is performed through the main system, MCU real-time subsystem, Ethernet subsystem, and embedded security subsystem; Run software applications and algorithmic programs in the distribution network; Handle online tasks of power conservation and voltage monitoring; Communicate with external chips; Integrated encryption algorithm.

8. The method according to claim 7, characterized in that The method further comprises the following steps: Load the main system program, receive OTA updates, flash firmware, and handle peripheral interrupts; Utilize different types of CPU cores to handle high-performance computing and tasks; Power algorithms and communication tasks are optimized through acceleration modules.

9. A distribution network monitoring and control edge computing device based on multi-core heterogeneity, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the distribution network monitoring and control edge computing method based on multi-core heterogeneity is implemented as described in any one of claims 7 to 8.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are used to enable a computer to execute the multi-core heterogeneous distribution network monitoring and control edge computing method as described in any one of claims 7 to 8.

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