Data processing method and device, electronic equipment and computer readable storage medium

Abstract

The embodiment of the invention provides a data processing method and device, electronic equipment and a computer readable storage medium, and the data processing method comprises the steps: carrying out the decoding operation of M groups of error correction code words, and obtaining corresponding M groups of syndromes, where M is an integer greater than or equal to 1; and in response to the existence of correctable errors in the M groups of error correction code words, encoding the target information of the M groups of syndromes to obtain encoded syndromes, the encoded syndromes representing error physical positions and error degrees of error code elements in the M groups of error correction code words. According to the data processing method, on the premise of limited storage resources, more correctable errors can be reported, and the utilization rate of the storage resources is increased.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a data processing method and apparatus, an electronic device, and a computer-readable storage medium. Background Art

[0002] Machine Check Architecture (MCA) is a mechanism in a computer system that detects and reports hardware errors or failures. It aims to improve the reliability and availability of the system by monitoring the health of various hardware components. When a processor (such as a CPU) detects hardware errors, such as system bus errors, errors found by error correcting codes (ECC), and parity errors, the processor reports these errors to the operating system through the MCA mechanism. The MCA mechanism mainly includes a series of specific registers for recording detected errors. When the MCA system detects, for example, memory errors using an error correcting code (ECC) algorithm, the ECC algorithm is able to automatically detect and correct these errors if these errors are within the error correction capability of the error correcting code algorithm. If the error exceeds the error correction capability of the ECC algorithm, the error will be reported to the MCA system as an uncorrectable error (UE), so that appropriate measures can be taken to improve the reliability and stability of the system.

[0003] In an 8-bit symbol (also called "symbol") environment, for example, the Single Symbol Correction (SSC) algorithm can usually only correct a single erroneous symbol, and these SSC error correction codes are generally arranged in a serial manner without using interleaving technology. Therefore, in this case, the error is reported by directly storing the syndrome. With the advancement of technology, for example, Double Symbol Correction (DSC) can not only correct multiple errors, but also use interleaving technology, that is, multiple error correction codes are interleaved to improve error correction performance. In this case, the error reporting method of directly storing the syndrome will take up a lot of register space, increase system costs, and it is difficult to accurately indicate which group of error correction codeword data in the interleaving based only on the stored syndrome. Therefore, there are certain difficulties in locating and repairing the error. Summary of the invention

[0004] At least one embodiment of the present disclosure provides a data processing method, comprising: performing a decoding operation on M groups of error correction codewords to obtain corresponding M groups of syndromes, wherein M is an integer greater than or equal to 1; and in response to the presence of correctable errors in the M groups of error correction codewords, encoding target information of the M groups of syndromes to obtain encoded syndromes, wherein the encoded syndromes represent the erroneous physical position and error degree of erroneous code elements in the M groups of error correction codewords.

[0005] For example, in the data processing method provided by at least one embodiment of the present disclosure, the target information includes the error position of the error codeword and the error value in the error codeword, and the target information of M groups of syndromes is encoded to obtain the encoded syndrome, including: for each group of syndromes in the M groups of syndromes, the error position of the error codeword is encoded to obtain the error physical position of the error codeword, and the number of error values ​​in the error codeword is counted to obtain the number of errors in the error codeword, wherein the number of errors in the error codeword represents the error degree of the error codeword; wherein the encoded syndrome includes the error physical position of the error codeword in the M groups of error correction codewords and the number of errors in the error codeword.

[0006] For example, in a data processing method provided by at least one embodiment of the present disclosure, encoding the error position of an error symbol to obtain the error physical position of the error symbol includes: determining the error physical position corresponding to the error position according to a lookup table.

[0007] For example, in the data processing method provided in at least one embodiment of the present disclosure, the error code element includes a first error code element, and the number of error values ​​in the error code element is counted to obtain the number of errors in the error code element, including: each time one error value is detected in the first error code element, the number of errors in the first error code element is increased by 1; or, each time two error values ​​are detected in the first error code element, the number of errors in the first error code element is increased by 1.

[0008] For example, in the data processing method provided in at least one embodiment of the present disclosure, the M groups of error correction codewords include a first group of error correction codewords, and the data processing method further includes: in response to the presence of uncorrectable errors in the first group of error correction codewords, directly storing the syndrome corresponding to the first group of error correction codewords.

[0009] For example, in the data processing method provided by at least one embodiment of the present disclosure, M groups of error correction codewords come from storage particles, and the error physical position represents the pin position of the storage particle where a symbol error exists, and the error degree represents the number of error bits in the symbol error; or M groups of error correction codewords come from a communication system, and the error physical position represents a channel in the communication system where a transmission error exists, and the error degree represents the number of error symbols on the channel where a transmission error exists.

[0010] For example, in the data processing method provided by at least one embodiment of the present disclosure, M=2, the M groups of error correction codewords include a first group of error correction codewords and a second group of error correction codewords, the first group of error correction codewords are read from a first group of pins of the storage particles, and the second group of error correction codewords are read from a second group of pins of the storage particles that are different from the first group of pins.

[0011] For example, in the data processing method provided by at least one embodiment of the present disclosure, all pins of the storage particle are numbered in sequence, the first group of pins includes pins with even numbers, and the second group of pins includes pins with odd numbers.

[0012] For example, in the data processing method provided by at least one embodiment of the present disclosure, in response to the presence of correctable errors in M ​​groups of error correction codewords, encoding target information of the M groups of syndromes to obtain encoded syndromes includes: in response to the presence of correctable errors in both the first group of error correction codewords and the second group of error correction codewords, encoding target information of a first group of syndromes corresponding to the first group of error correction codewords and target information of a second group of syndromes corresponding to the second group of error correction codewords, respectively, to obtain first encoded syndromes and second encoded syndromes, wherein the encoded syndromes include the first encoded syndromes and the second encoded syndromes.

[0013] For example, in the data processing method provided by at least one embodiment of the present disclosure, each of the first group of error correction codewords and the second group of error correction codewords includes N error correction codewords, N is an integer greater than or equal to 1, and in response to the presence of correctable errors in both the first group of error correction codewords and the second group of error correction codewords, target information of a first group of syndromes corresponding to the first group of error correction codewords and target information of a second group of syndromes corresponding to the second group of error correction codewords are respectively encoded, including, for each group of error correction codewords: in response to the number of error code elements in the N error correction codewords being less than or equal to a preset number, determining that the N error correction codewords have correctable errors; encoding the error positions of the error code elements in the N error correction codewords to obtain the error physical positions of the error code elements, and counting the number of error values ​​in the error code elements to obtain the number of errors in the error code elements; wherein the preset number is the maximum number of error code elements in the N error correction codewords that can be corrected simultaneously.

[0014] At least one embodiment of the present disclosure further provides a data processing device, including: a decoding module, configured to perform decoding operations on M groups of error correction codewords to obtain corresponding M groups of syndromes, wherein M is an integer greater than or equal to 1; and a syndrome encoding module, configured to encode target information of the M groups of syndromes in response to the presence of correctable errors in the M groups of error correction codewords to obtain encoded syndromes, wherein the encoded syndromes represent the erroneous physical positions and error degrees of erroneous code elements in the M groups of error correction codewords.

[0015] For example, in a data processing device provided in at least one embodiment of the present disclosure, a syndrome coding module includes M coding sub-modules, and the coding sub-module includes a position conversion unit and a bit accumulation unit. For each group of syndromes in the M groups of syndromes, the position conversion unit in the corresponding coding sub-module is configured to encode the error position of the error codeword to obtain the error physical position of the error codeword, and the bit accumulation unit in the corresponding coding sub-module is configured to count the number of error values ​​in the error codeword to obtain the number of errors in the error codeword.

[0016] For example, in a data processing device provided by at least one embodiment of the present disclosure, when the error position of an error code element is encoded to obtain the error physical position of the error code element, the position conversion unit is configured to determine the error physical position corresponding to the error position according to a lookup table.

[0017] For example, in a data processing device provided by at least one embodiment of the present disclosure, the error code element includes a first error code element. When counting the number of error values ​​in the error code element to obtain the number of errors in the error code element, the bit accumulation unit is configured as follows: for each time one error value is detected in the first error code element, the number of errors in the first error code element is increased by 1; or, for each time two error values ​​are detected in the first error code element, the number of errors in the first error code element is increased by 1.

[0018] At least one embodiment of the present disclosure further provides an electronic device, comprising: at least one processor; and at least one memory having instructions stored thereon, wherein when the instructions are executed by the at least one processor, the at least one processor executes the data processing method provided by any of the above embodiments.

[0019] At least one embodiment of the present disclosure further provides a computer-readable storage medium having computer-readable instructions stored thereon, wherein when the computer-readable instructions are executed by a processor, the processor executes the data processing method provided by any of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0021] Figure 1 A schematic structural diagram of an exemplary MCA error reporting mechanism based on the SSC algorithm is shown;

[0022] Figure 2 Schematic diagrams of exemplary error correction based on the SSC algorithm and the DSC algorithm are shown;

[0023] Figure 3A schematic diagram showing an exemplary error correction based on a DSC algorithm and using a 2-line interleaving strategy;

[0024] Figure 4 A schematic structural diagram of an exemplary MCA error reporting mechanism based on the DSC algorithm is shown;

[0025] Figure 5 A schematic diagram showing a data processing method according to at least one embodiment of the present disclosure is shown;

[0026] Figure 6 A schematic diagram of the structure of an MCA error reporting mechanism using a DSC algorithm and a 2-line interleaving strategy according to at least one embodiment of the present disclosure is shown;

[0027] Figure 7 Shows Figure 6 The structural diagram of the MCA encoding module;

[0028] Figure 8 A schematic diagram showing the occurrence of 4 error symbols according to at least one embodiment of the present disclosure is shown;

[0029] Fig. 9 A schematic diagram showing a data processing device according to at least one embodiment of the present disclosure;

[0030] Fig.10 A schematic diagram showing an electronic device according to at least one embodiment of the present disclosure; and

[0031] Fig.11 A schematic diagram of a non-transitory readable storage medium according to at least one embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0032] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0033] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0034] Flowcharts are used in this disclosure to illustrate the operations performed by the system according to the embodiments of the present application. It should be understood that the preceding or following operations are not necessarily performed precisely in order. On the contrary, various steps may be processed in reverse order or simultaneously as required. At the same time, other operations may also be added to these processes, or one or more operations may be removed from these processes.

[0035] First, the abbreviations and related terms involved in this application are defined and explained.

[0036] Machine Check Architecture (MCA): A mechanism used by computer systems to detect and handle hardware errors, which can self-diagnose and record when hardware errors occur in the system.

[0037] Error Correcting Code (ECC): A coding technique used to detect and correct errors in data transmission. By adding redundant information to the data, ECC can improve the system's tolerance to errors and ensure that possible errors are detected and corrected during the transmission process.

[0038] Single Symbol Correction (SSC): A form of ECC that corrects errors in a single symbol. SSC can correct a single symbol when an error is found without retransmitting the entire data block.

[0039] Double-Symbol Correction (DSC): A form of ECC that can correct errors in two symbols at once. DSC can correct both symbols when an error is found without retransmitting the entire data block.

[0040] Memory channel: abbreviated as channel. Each memory controller can have multiple memory channels. These memory channels are the data transmission paths between the memory and the memory controller on the processor (such as CPU). For example, common memory channels include memory channel 0 and memory channel 1.

[0041] UE (Uncorrectable Error): Uncorrectable error.

[0042] CE (Correctable Error): Correctable error.

[0043] Data Device: A storage device that stores data. In DDR memory, it is also called a data memory device.

[0044] ECC Device: A storage device that stores check bits. In DDR memory, it is also called a check memory device.

[0045] Storage particles: Data storage particles and verification storage particles are collectively referred to as storage particles. Storage particles are also called memory particles in DDR memory, and can be used as a general term for data memory particles and verification memory particles.

[0046] Symbol: Also called "code element", the smallest unit of ECC error correction, usually with x4 and x8 particles, corresponding to 4 bits and 8 bits of data.

[0047] ECC Word: also known as "error correction code word", the object data for performing ECC operation, in the form of data information + check information in a memory architecture that supports ECC.

[0048] It is understandable that the terms defined above are only exemplary definitions in specific application scenarios to facilitate a better understanding of the present application. For example, the exemplary definitions for specific memory described above can be extended to other types of memory.

[0049] Figure 1 A structural schematic diagram of an MCA error reporting mechanism based on the SSC algorithm is shown.

[0050] like Figure 1As shown, the MCA error reporting mechanism based on the SSC algorithm adopts the ECC error correction mechanism. First, the error correction codeword (hereinafter also referred to as "ECC word") is read from the storage particle (for example, the memory particle, etc.), wherein the error correction codeword includes data information and verification information, that is, the error correction codeword includes code element and ECC error correction code, and the ECC error correction code is obtained based on the code element and the corresponding encoding rule. Then the decoder performs an ECC decoding operation on the read ECC word based on the ECC error correction code to obtain the syndrome corresponding to the ECC word, and at the same time, it can be determined whether there is an error in the code element based on the syndrome. If there is an error, the syndrome is directly written into the MCA register, and the code element is corrected based on the syndrome to obtain the error-corrected code element. Finally, the error-corrected code element and the syndrome written into the MCA register can be sent to the software together, so that the software can analyze and count the errors in the storage particles later.

[0051] As mentioned above, when a symbol is wrong, the SSC algorithm can only correct a single error symbol (or a single error symbol). In the context of pursuing higher data reliability, the SSC algorithm has limited performance in dealing with complex error patterns and multi-bit errors. In order to overcome this limitation, the design of error correction codes generally adopts the more advanced DSC algorithm. The DSC algorithm has a more powerful multi-bit error correction capability and can more effectively detect and correct multi-bit errors, thereby improving the data reliability of the entire system.

[0052] For example, Figure 2 Schematic diagrams of error correction based on the SSC algorithm and the DSC algorithm are shown. Figure 2 As shown, data segment 0 and data segment 1 are code elements, and check 0 and check 1 are error correction codes. When the SSC algorithm is used, check 0 protects data segment 0, and check 1 protects data segment 1, that is, only data segment 0 and data segment 1 can be corrected separately. When the DSC algorithm is used, check 0 and check 1 jointly protect data segment 0 and data segment 1, that is, data segment 0 and data segment 1 can be corrected at the same time.

[0053] In addition, in order to further enhance the error correction performance, a strategy of interleaving multiple error correction codes is usually adopted. For example, a multi-line interleaving strategy can be adopted while adopting the DSC algorithm.

[0054] For example, Figure 3 A schematic diagram of error correction based on a DSC algorithm and using a 2-line interleaving strategy is shown.

[0055] like Figure 3 As shown, taking a memory channel of DDR5 as an example, the memory channel corresponds to 8 x4 data memory particles ( Figure 3 The first row of the 8 memory chips numbered 0-7) and 2 x4 check memory chips ( Figure 3 Receive or read eight bursts of data Burst0-Burst7 from the storage channel. The eight bursts of data include 256 bits of data information (data bit_0 to data bit_255) and 64 bits of check information (ECC bit_0 to ECCbit_63). The 256 bits of data information and the 64 bits of check information form two groups of ECC words (i.e., two groups of error correction code words), namely ECCgroup_0 and ECC group_1, and both use the DSC algorithm for error correction.

[0056] like Figure 3 As shown, data bit_0 to data bit_127 and ECC bit_0 to ECC bit_31 ( Figure 3 Indicated in white in the figure) belongs to ECC group_0, data bit_128 to data bit_255 and ECC bit_32 to ECC bit_63 ( Figure 3 In gray, it belongs to ECC group_1. Specifically, each 8-bit constitutes a symbol, for example, data bit_0 to data bit_7 constitute a data symbol, data bit_128 to data bit_135 constitute another data symbol, ECC bit_0 to ECC bit_7 constitute a check symbol, and ECC bit_32 to ECC bit_39 constitute another check symbol. ECC group_0 and ECCgroup_1 each include 16 data symbols and 4 check symbols, respectively. The 4 check symbols of ECC group_0 are used to correct the errors of the 16 data symbols in ECC group_0, and the 4 check symbols of ECC group_1 are used to correct the errors of the 16 data symbols in ECC group_1.

[0057] like Figure 3As shown, each memory cell includes 4 pins, 8 data memory cells and 2 check memory cells include a total of 40 pins, and the 40 pins are uniformly numbered. For example, the data memory cell numbered 0 includes pins pin0-pin3, and the data memory cell numbered 1 includes pins pin4-pin7. When the 256-bit data information and the 64-bit check information are divided into two groups of error correction codewords (i.e., ECC group_0 and ECC group_1), the data symbols or check symbols corresponding to the even-numbered pins (i.e., the pins are numbered as even numbers, such as pin_2n, n=0, 1, ... 19.) can be divided into ECCgroup_0, and the data symbols or check symbols corresponding to the odd-numbered pins (i.e., the pins are numbered as odd numbers, such as pin_2(n+1), n=0, 1, ... 19.) can be divided into ECC group_1. This division method makes the memory system more efficient while providing comprehensive error detection and correction capabilities.

[0058] exist Figure 3 In the error correction mode shown, the DSC algorithm is used to check and correct ECC group_0 and ECC group_1 at the same time. Since the DSC algorithm can correct up to 2 symbol errors at the same time, when the number of erroneous data symbols or the number of erroneous pins in ECC group_0 and ECC group_1 does not exceed 2 respectively, these symbol errors are within the correctable range and are correctable errors, then these erroneous data symbols can be corrected at the same time, that is, Figure 3 The error correction mode shown can correct up to 4 symbol errors simultaneously, improving the error tolerance of the memory system, thereby ensuring the reliability and stability of the entire memory system.

[0059] For example, Figure 4A structural schematic diagram of an MCA error reporting mechanism based on a DSC algorithm is shown. First, error correction code words (hereinafter also referred to as "ECC words") are read from storage particles (e.g., memory particles, memory bars, etc.), and the read error correction code words are divided into two groups of ECC words, namely ECC group_0 and ECC group_1, wherein ECC group_0 and ECC group_1 both include code elements and ECC error correction codes. Then decoder 1 decodes the ECC words in ECC group_0 based on the ECC error correction code in ECC group_0 and obtains syndrome 1, and decoder 2 decodes the ECC words in ECC group_1 based on the ECC error correction code in ECC group_1 and obtains syndrome 2, and determines whether the code elements of ECC group_0 and ECC group_1 are erroneous based on syndromes 1 and 2. If there are errors in the code elements of ECC group_0 and ECC group_1, syndromes Syndrome_1 and Syndrome_2 are directly written into the MCA1 register and the MCA2 register respectively. Afterwards, based on the syndromes Syndrome_1 and Syndrome_2, the erroneous code elements in ECC group_0 and ECC group_1 are corrected to obtain the corrected code elements. Finally, the corrected code elements, syndromes Syndrome_1 and Syndrome_2 can be sent to the software together, so that the software can analyze and count the errors in the storage particles later.

[0060] The inventors of the present disclosure have noticed that compared to Figure 1 The MCA error reporting mechanism shown, although Figure 4The error correction performance of the MCA error reporting mechanism based on the DSC algorithm shown is significantly improved, but under the MCA error reporting mechanism, the error reporting method of directly storing syndromes has some disadvantages. For example, due to the increase of error correction codes and the adoption of an interleaving strategy, two ECC error correction codes work at the same time, and syndromes 1 and 2 respectively decoded by decoders 1 and 2 increase the occupied register space. However, due to the limited resources of the MCA register, the MCA register can usually only store a limited amount of error information. Therefore, when both ECC group_0 and ECC group_1 have errors, the system can only select syndrome 1 or syndrome 2 for storage, and the other syndrome is discarded, resulting in the risk of information loss. At the same time, when multiple correctable errors (CE) occur in a short period of time, the MCA error reporting mechanism can generally only record the syndrome of the first CE, and the syndromes of the remaining CEs will be ignored. In addition, the error reporting method of directly storing syndromes cannot clearly indicate which ECC Group in the interleaving the error belongs to, and the syndromes cannot provide sufficient distinguishing information, resulting in the system being difficult to accurately locate the specific ECC Group where the error occurs.

[0061] One or more embodiments of the present disclosure propose a data processing method and device, an electronic device, and a computer-readable storage medium, which can, for example, report more errors under the premise that the storage resources of the MCA register are limited, improve the utilization rate of storage resources, and the encoded syndrome can directly record the physical location of the error, which facilitates subsequent error analysis and processing.

[0062] The present disclosure is described below through several specific embodiments. In order to keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of known functions and known components may be omitted. When any component of the embodiments of the present disclosure appears in more than one figure, the component is represented by the same or similar reference numeral in each figure.

[0063] Figure 5 A flow chart of a data processing method according to at least one embodiment of the present disclosure is shown. The data processing method may include steps S101 to S102.

[0064] In step S101, decoding operations are performed on M groups of error correction codewords to obtain corresponding M groups of syndromes, where M is an integer greater than or equal to 1.

[0065] In some embodiments of the present disclosure, the error correction codeword (i.e., ECC word) includes data bits (also referred to as "code elements" or "data information") and redundant bits for error detection and correction (also referred to as "check bits" or "ECC error correction codes"). For example, M ECC decoders may respectively perform decoding operations on M groups of error correction codewords, and the decoding operation process may be that the decoder calculates the syndrome based on the polynomial operation defined in the ECC encoding algorithm. For example, assuming that the generating polynomial is g(x), and the data bits in the ECC word are represented by the polynomial m(x), then the syndrome s(x) can be calculated by the following formula: s(x)=m(x)modg(x). The technical solution of the present disclosure may also use other decoding methods, which will not be repeated here.

[0066] In some embodiments of the present disclosure, it can be determined whether there is an error in the codeword in the ECC word based on the obtained syndrome. For example, if all elements in the syndrome are 0, it means that there is no error in the ECC word, or the error in the ECC word is undetectable; if there is any non-zero element in the syndrome, it means that there is at least one error in the corresponding codeword in the ECC word. Different error correction codes have different error correction capabilities. The maximum number of errors that an error correction code can correct depends on the error correction code used and its parameters. For example, a Hamming code can correct a single error at most. For a Reed-Solomon Code, the RS(n,k) code can correct a maximum of errors, where n is the length of the ECC word and k is the length of the code element.

[0067] In step S102, in response to the existence of correctable errors in the M groups of error correction codewords, target information of the M groups of syndromes is encoded to obtain encoded syndromes, wherein the encoded syndromes represent the erroneous physical positions and error degrees of erroneous code elements in the M groups of error correction codewords.

[0068] For example, the error physical position indicates which codeword in which group of error correction codewords the error codeword belongs to, and the error degree of the error codeword depends on the number of errors in the error codeword. The more errors in the error codeword, the higher the error degree of the error codeword.

[0069] For example, if there are error symbols in the M groups of error correction codewords and the number of error symbols is within the error correction capability of the adopted error correction algorithm, then there are correctable errors in the M groups of error correction codewords. For example, taking the M groups of error correction codewords all adopting the DSC algorithm as an example, when the DSC algorithm is adopted, at most 2 error symbols can be corrected at the same time. If there are no more than 2 error symbols in the first group of error correction codewords in the M groups of error correction codewords, then the errors in the first group of error correction codewords are correctable errors. After determining that there are correctable errors, the target information of the first group of syndromes can be encoded to obtain the encoded syndrome, and the encoded syndrome can be written into the corresponding register, such as the MCA register. Here, the target information can include key information such as the error position of each error symbol in the first group of error correction codewords, the number of errors in the error symbol, etc., and the present disclosure does not limit this.

[0070] In some embodiments of the present disclosure, the data processing method may further include step S103: in response to the presence of uncorrectable errors in the first group of error correction codewords, directly storing syndromes corresponding to the first group of error correction codewords.

[0071] For example, taking the DSC algorithm as an example, when the DSC algorithm is used, at most 2 error code elements can be corrected at the same time. If there are 3 or more error code elements in the first group of error correction code words, the errors in the first group of error correction code words are uncorrectable errors. At this time, the errors can be reported by directly storing the syndrome corresponding to the first group of error correction code words. In the case where there are multiple groups of error correction code words in the M groups of error correction code words with uncorrectable errors, for example, the first group, the second group, and the fourth group of error correction code words all have uncorrectable errors, the syndrome corresponding to any one group of error correction code words in the first group, the second group, and the fourth group of error correction code words can be selected for storage and reporting to ensure the efficiency and simplicity of information transmission.

[0072] As described above, in the data processing method provided by the embodiments of the present disclosure, for example, compared with the error reporting method of directly storing the syndrome, the error reporting method of storing the encoded syndrome requires less storage resources, can realize the error reporting of more correctable errors, and overcomes the problem of limited MCA register resources; when transmitting the encoded syndrome, unnecessary data transmission is reduced, and the efficiency of data transmission is improved; and the encoded syndrome directly records the erroneous physical position of the erroneous codeword and the error degree of the erroneous codeword, and the error reporting method is clearer and more intuitive, which is conducive to subsequent error analysis and processing.

[0073] In some embodiments of the present disclosure, M groups of error correction codewords may come from storage particles, which generally refer to basic units or components in computer storage and memory devices. The error physical location characterizes the pin location in the storage particle where the symbol error exists. The error degree characterizes the number of error bits in the symbol error. For example, when it is detected that the symbol symbol_1 is wrong, the symbol symbol_1 corresponds to the pin pin_1, and there is a 3-bit data error in the symbol symbol_1, after encoding the syndrome, the error physical location indicates that the pin location pin_1 is wrong, and the error degree is 3 to indicate that the 3-bit data is wrong.

[0074] In some embodiments of the present disclosure, the M groups of error correction codewords may also come from a communication system, and the error physical position characterizes a channel in the communication system where a transmission error exists, and the error degree characterizes the number of error symbols on the channel where a transmission error exists. For example, when it is detected that a transmission error exists in channel channel_0 of the communication system, that is, among the multiple symbols transmitted on channel channel_0, symbol symbol_0 and symbol symbol_4 are wrong, then after encoding the syndrome, the error physical position indicates that channel channel_0 is wrong, and the error degree is 2 to indicate that 2 symbols on the channel are wrong.

[0075] In some embodiments of the present disclosure, the target information includes an error position of an error symbol and an error value in the error symbol, and for each group of syndromes in the M groups of syndromes, step S102 includes step S1021 and step S1022.

[0076] Step S1021: Encode the error position of the error symbol to obtain the error physical position of the error symbol.

[0077] Step S1022: Count the number of error values ​​in the error code element to obtain the number of errors in the error code element, wherein the number of errors in the error code element represents the error degree of the error code element.

[0078] For example, the encoded syndrome may include the erroneous physical locations of the erroneous symbols in the M sets of error correction codewords and the number of errors in the erroneous symbols.

[0079] In step S1021, the error physical position corresponding to the error position can be determined according to the lookup table. In a specific application scenario, a lookup table can be configured by software or manually, and the lookup table can translate the error positions of all error code elements into actual physical positions. In addition to using a lookup table, the embodiments of the present disclosure can also use other methods to encode the error positions of error code elements to determine their actual physical positions. For example, a specific encoding algorithm can be used to encode the error position into a corresponding error physical position, or a hash function can be used to map the error position to a corresponding error physical position. Mathematical formulas, bit operations, state machines, etc. can also be used, and the present disclosure does not limit this.

[0080] In step S1022, when counting the number of error values ​​in the error symbol to obtain the number of errors in the error symbol, a counter may be used for counting. Taking the counting of the number of error values ​​in the first error symbol as an example, the number of errors in the first error symbol may be increased by 1 each time one error value in the first error symbol is detected; or the number of errors in the first error symbol may be increased by 1 each time two error values ​​in the first error symbol are detected.

[0081] For example, in the case where the first error symbol is an 8-bit symbol, each time an error value (i.e., 1-bit error) is detected in the first error symbol, the counter is incremented by 1, and the encoded syndrome uses a 3-bit length field to reflect the error degree of the error symbol. Specifically, 000 indicates that there is no error in the 8-bit symbol, 001 indicates that there is a 1-bit error, 010 indicates that there is a 2-bit error, 011 indicates that there is a 3-bit error, 100 indicates that there is a 4-bit error, 101 indicates that there is a 5-bit error, 110 indicates that there is a 6-bit error, and 111 indicates that there is a 7-bit or 8-bit error.

[0082] For example, in the case where the first error symbol is a 16-bit symbol, each time two error values ​​(i.e., 2-bit errors) are detected in the first error symbol, the counter is incremented by 1, and the encoded syndrome using a 3-bit length field can also reflect the error degree of the error symbol, thereby saving storage resources. Specifically, 000 indicates that there is no error in the 16-bit symbol, 001 indicates that there is a 2-bit error, 010 indicates that there is a 4-bit error, 011 indicates that there is a 6-bit error, 100 indicates that there is an 8-bit error, 101 indicates that there is a 10-bit error, 110 indicates that there is a 12-bit error, and 111 indicates that there is a 14-bit or 16-bit error.

[0083] For example, the carry rule of the counter can be set according to actual needs, and the present disclosure does not impose any restrictions on this.

[0084] In some embodiments of the present disclosure, M=2, and the M groups of error correction codewords include a first group of error correction codewords and a second group of error correction codewords, the first group of error correction codewords are read from a first group of pins of the storage particles, and the second group of error correction codewords are read from a second group of pins of the storage particles that are different from the first group of pins.

[0085] For example, all pins of the storage particles may be numbered in sequence, the first group of pins including all pins with even numbers, and the second group of pins including all pins with odd numbers. When error correction codewords are read or received from the pins of the storage particles, the error correction codewords read or received may be divided into two groups of error correction codewords, such as a first group of error correction codewords ECC group_0 and a second group of error correction codewords ECC group_1. The two groups of error correction codewords adopt a two-line interleaving strategy.

[0086] For example, in response to the presence of correctable errors in both the first group of error correction codewords ECC group_0 and the second group of error correction codewords ECC group_1, target information of a first group of syndromes corresponding to the first group of error correction codewords ECC group_0 and target information of a second group of syndromes corresponding to the second group of error correction codewords ECC group_1 are encoded respectively to obtain a first encoded syndrome and a second encoded syndrome, wherein the encoded syndromes include the first encoded syndrome and the second encoded syndrome.

[0087] For example, the first group of error correction codewords ECC group_0 and the second group of error correction codewords ECC group_1 may include N error correction codewords respectively, where N is an integer greater than or equal to 1. For each group of error correction codewords: in response to the number of error codewords in the N error correction codewords being less than or equal to a preset number, it may be determined that the N error correction codewords have correctable errors; the error positions of the error codewords in the N error correction codewords are encoded to obtain the error physical positions of the error codewords, and the number of error values ​​in the error codewords is counted to obtain the number of errors in each error codeword; wherein the preset number is the maximum number of error codewords that can be corrected simultaneously in the N error correction codewords.

[0088] For example, the preset number may also be determined according to the ECC algorithm used for the error correction codeword. For example, when the DSC algorithm is used, the DSC algorithm can correct up to 2 erroneous codewords at the same time. In this case, the preset number is 2.

[0089] Figure 6 A structural schematic diagram of an MCA error reporting mechanism using a DSC algorithm and a 2-line interleaving strategy according to at least one embodiment of the present disclosure is shown.

[0090] like Figure 6 As shown, the error correction codeword comes from the storage particle 610 (for example, the memory particle). Due to the two-line interleaving strategy, M=2, two groups of error correction codewords ECC group_0 and ECC group_1 are read from the storage particle 610 to obtain the data information (i.e., code element) and check information (i.e., ECC error correction code) of each group of error correction codewords. The ECC decoding module 620 performs an ECC decoding operation on ECC group_0 to obtain a group of syndromes Syndrome_0, and the ECC decoding module 621 performs an ECC decoding operation on ECC group_1 to obtain another group of syndromes Syndrome_1. In the case that both ECC group_0 and ECC group_1 have correctable errors, the ECC error correction module 630 performs ECC error correction on ECC group_0 based on Syndrome_0, the ECC error correction module 631 performs ECC error correction on ECC group_1 based on Syndrome_1, and the MCA encoding module 640 (i.e., the syndrome encoding module) encodes the target information of Syndrome_0 and Syndrome_1 to obtain the encoded syndrome MCA_SYNC, and then writes the encoded syndrome MCA_SYNC into the MCA memory 650. After the ECC error correction is completed, the error-corrected codewords in ECC group_0 and ECC group_1 and the encoded syndrome MCA_SYNC in the MCA memory 650 are transmitted to the software.

[0091] Figure 7 Shows Figure 6 Schematic diagram of the structure of the MCA encoding module.

[0092] like Figure 7 As shown, the MCA encoding module 640 includes an encoding submodule 6401 and an encoding submodule 6402 for ECC group_0 and ECC group_1, respectively. Since the DSC algorithm is adopted, the DSC algorithm can correct up to 2 error symbols at the same time, and the encoding submodules 6401 and 6402 each include 2 groups of position conversion units and bit accumulation units, for example, the position conversion unit 6601 and the bit accumulation unit 6701 are used for the first error symbol in ECC group_0, the position conversion unit 6602 and the bit accumulation unit 6702 are used for the second error symbol in ECC group_0, the position conversion unit 6603 and the bit accumulation unit 6703 are used for the first error symbol in ECCgroup_1, and the position conversion unit 6604 and the bit accumulation unit 6704 are used for the second error symbol in ECC group_1.

[0093] like Figure 7As shown, the ECC error correction module 630 is coupled to the encoding submodule 6401, and the ECC error correction module 631 is coupled to the encoding submodule 6402. When the ECC error correction module 630 and the ECC error correction module 631 perform ECC error correction on ECC group_0 and ECC group_1 respectively, the target information of Syndrome_0 and Syndrome_1 are output to the encoding submodule 6401 and the encoding submodule 6402 respectively. For example, Figure 7 As shown, the target information of Syndrome_0 may include error position 0 and error position 1 of the error code element in ECC group_0, and error value 0 and error value 1 in the error code element; the target information of Syndrome_1 may include error position 2 and error position 3 of the error code element in ECC group_1, and error value 2 and error value 3 in the error code element.

[0094] like Figure 7 As shown, different control signals are applied to the position conversion units 6601-6604 and the bit accumulation units 6701-6704 to control the operation of the position conversion units 6601-6604 and the bit accumulation units 6701-6704. For example, the control signal config_0 can control the position conversion unit 6601 to convert the error position 0 into the error physical position Pos0 based on a preset lookup table, or control the position conversion unit 6601 to encode the error position 0 into the error physical position pos0 based on a specific encoding algorithm. For example, the control signal config_1 can set the carry rule of the bit accumulation unit 6701, and the carry rule can be that for each error value 0 detected in the error code element, the number of errors in the corresponding error code element is increased by 1, and after counting the error value in the corresponding error code element, the bit accumulation unit 6701 outputs the error number err_bit_ctr0 of the corresponding error code element. The operations of the remaining position conversion units and the bit accumulation unit can refer to the operations of the position conversion unit 6601 and the bit accumulation unit 6701, which will not be repeated here.

[0095] In the above example, the encoded syndrome MCA_SYNC=[err_bit_ctr0, pos0, err_bit_ctr1, pos1, err_bit_ctr2, pos2, err_bit_ctr3, pos3] is finally obtained, and the encoded syndrome MCA_SYNC is written into the MCA register 650.

[0096] In order to more clearly describe the process of encoding the companion target information, the following example is taken where a memory channel of 40-bit DDR5 has a correctable error and the DSC algorithm is used.

[0097] Figure 8A schematic diagram showing the occurrence of 4 error symbols according to at least one embodiment of the present disclosure is shown.

[0098] like Figure 8 As shown, one memory channel of DDR5 corresponds to 8 x4 data memory particles ( Figure 8 The first row of the 8 memory chips numbered 0-7) and 2 x4 check memory chips ( Figure 8 Receive or read eight bursts of data Burst0-Burst7 from the storage channel. The eight bursts of data include 256 bits of data information (data bit_0-bit_255) and 64 bits of check information (ECC bit_0-bit_63), which correspond to bits 0-255 of the eight data memory particles (numbered 0-7) and bits 0-63 of the two check memory particles (numbered 8-9). The 256 bits of data information and the 64 bits of check information form two groups of ECC words, namely ECC group_0 and ECC group_1. ECC group_0 includes 16 8-bit data symbols and 4 8-bit check symbols ( Figure 8 Indicated in white in the figure), ECC group_1 includes 16 8-bit data symbols and 4 8-bit check symbols ( Figure 8 in grey).

[0099] like Figure 8As shown, in ECC group_0, data bit25, data bit82, data bit83 and data bit85 are error values, where data bit25 belongs to the 4th symbol symbol_3 in ECC group_0, and data bit82, data bit83 and data bit85 belong to the 11th symbol symbol_10 in ECC group_0; in ECC group_1, data bit227, data bit228, data bit246 and data bit247 are error values, where data bit227 and data bit228 belong to the 13th symbol symbol_12 in ECCgroup_1, and data bit246 and data bit247 belong to the 15th symbol symbol_14 in ECC group_1. Due to the use of the DSC algorithm for error correction, both ECC group_0 and ECC group_1 have two error symbols, and the errors in ECC group_0 and ECC group_1 do not exceed the error correction capability of the DSC algorithm, so they are correctable errors. After encoding the target information of the syndromes of ECC group_0 and ECC group_1, the obtained encoded syndrome MCA_SYNC=[err_bit_ctr0,pos0,err_bit_ctr1,pos1,err_bit_ctr2,pos2,err_bit_ctr3,pos3] can be expressed as:

[0100] err_bit_ctr0 = 001, pos0 = 00100, indicating that symbol_3 in ECC group_0 is an error symbol, and the error degree is 1, that is, there is a 1-bit error;

[0101] err_bit_ctr1 = 011, pos1 = 01010, indicating that symbol_10 in ECC group_0 is an error symbol, the error degree is 3, and there is a 3-bit error;

[0102] err_bit_ctr2 = 010, pos2 = 01100, indicating that symbol_12 in ECC group_1 is an error symbol, the error degree is 2, and there is a 2-bit error;

[0103] err_bit_ctr3=010, pos3=01110, indicating that symbol_14 in ECC group_1 is an error symbol, the error degree is 2, and there is a 2-bit error.

[0104] In the above example, when the number of error symbols is 4, the 32-bit MCA_SYNC field can describe all the error symbols, occupying only 32-bit storage resources of the MCA register; if an error reporting mechanism that directly stores the syndrome is adopted and the number of error symbols is also 4, at least 64-bit storage resources of the MCA register are required to store the syndrome corresponding to any error symbol, and the syndromes corresponding to the remaining error symbols will be ignored. Therefore, the data processing method provided by the embodiment of the present disclosure improves the utilization rate of the MCA register storage resources, and more correctable errors can be reported when storage resources are limited. In addition, the encoded syndrome MCA_SYNC can directly reflect the physical location and severity of the error symbol. This design not only simplifies the error analysis process, but also facilitates operation and maintenance personnel to directly perform system maintenance.

[0105] It should be noted that the order of the fields in the encoded syndrome MCA_SYNC is preset. For example, for 32-bit MCA_SYNC, the first 16-bit is used to describe the error codeword in ECC group_0, and the last 16-bit is used to describe the error codeword in ECC group_1. If the syndrome corresponding to ECC group_0 is 0, it means that there is no error codeword in ECC group_0. At this time, the syndrome does not need to be encoded. err_bit_ctr0, pos0, err_bit_ctr1 and pos1 are all 0, that is, MCA_SYNC = [000, 00000, 000, 00000, err_bit_ctr2, pos2, err_bit_ctr3, pos3]. If there is 1 error codeword in ECC group_0 and 2 error codewords in ECC group_1, err_bit_ctr1 and pos1 are both 0, that is, MCA_SYNC = [err_bit_ctr0, pos0, 000, 00000, err_bit_ctr2, pos2, err_bit_ctr3, pos3].

[0106] In the embodiments of the present disclosure, the pins of the storage particles may be uniformly numbered. Figure 8As shown, each x4 data memory particle and x4 check memory particle each include 4 pins, and the 10 memory particles numbered 0-9 include a total of 40 pins, pin_0 to pin39. When receiving or reading eight burst data Burst0-Burst7 are organized into two groups of ECC words (error correction code words), the error correction code words received or read from the pins with even pin numbers (i.e., pin_2n, n=0,1,...,19) can be divided into ECC group_0, and the error correction code words received or read from the pins with odd pin numbers (i.e., pin_(2n+1), n=0,1,...,19) can be divided into ECC group_1.

[0107] For example, when determining which error symbol belongs to which error code element in which group of error correction code words according to the encoded syndrome MCA_SYNC, it is also possible to locate which pin of which memory particle has an error. For example, according to err_bit_ctr0=001, pos0=00100 in MCA_SYNC, it can be determined that symbol_3 in ECC group_0 is an error code element with an error degree of 1, and it can also be determined that symbol_3 is received or read from a pin numbered pin_6 (pin_2n=pin_(2*3)=pin_6), that is, the pin with an error is pin_6 and belongs to a data storage particle numbered 1. Therefore, the data processing method provided in the embodiment of the present disclosure can also accurately locate the pin and storage particle with an error, and accurately indicate the number of bits with an error, which provides the system with more comprehensive and accurate error information, and helps to more effectively locate and process errors.

[0108] According to at least one embodiment of the present disclosure, the data processing method (such as Figure 5 Correspondingly, at least one embodiment of the present disclosure further provides a data processing device. For example, the data processing device may be a data sending device.

[0109] Fig. 9 A schematic diagram of a data processing device according to at least one embodiment of the present disclosure is shown.

[0110] like Fig. 9 As shown, the data processing device 900 includes: a decoding module 910, configured to perform a decoding operation on M groups of error correction codewords to obtain corresponding M groups of syndromes, wherein M is an integer greater than or equal to 1; and a syndrome encoding module 920, configured to encode target information of the M groups of syndromes in response to the presence of correctable errors in the M groups of error correction codewords to obtain encoded syndromes, wherein the encoded syndromes represent the erroneous physical position and error degree of each erroneous codeword in the M groups of error correction codewords.

[0111] In a possible embodiment, the syndrome coding module includes M coding submodules, and each coding submodule includes a position conversion unit and a bit accumulation unit. For each syndrome in the M syndrome groups, the position conversion unit in the corresponding coding submodule is configured to encode the error position of each error symbol to obtain the error physical position of each error symbol, and the bit accumulation unit in the corresponding coding submodule is configured to count the number of error values ​​in each error symbol to obtain the number of errors in each error symbol, wherein the number of errors in the error symbol represents the error degree of the error symbol; wherein the encoded syndrome includes the error physical position of each error symbol in the M error correction codewords and the number of errors in each error symbol.

[0112] In a possible embodiment, when encoding the error position of each error symbol to obtain the error physical position of each error symbol, the position conversion unit is configured to determine the error physical position corresponding to the error position according to a lookup table.

[0113] In a possible embodiment, the error code element includes a first error code element, and when the bit accumulation unit counts the number of error values ​​in each error code element to obtain the number of errors in each error code element, the bit accumulation unit is configured as follows: the number of errors in the first error code element is increased by 1 for each error value detected in the first error code element; or, the number of errors in the first error code element is increased by 1 for each two error values ​​detected in the first error code element.

[0114] In a possible embodiment, the M groups of error correction codewords include a first group of error correction codewords, and the data processing device also includes a register, which is configured to: in response to the presence of uncorrectable errors in the first group of error correction codewords, directly store syndromes corresponding to the first group of error correction codewords.

[0115] In a possible embodiment, M groups of error correction codewords come from storage particles, and the error physical location represents the pin location of the storage particle where a symbol error exists, and the error degree represents the number of error bits in the symbol error; or M groups of error correction codewords come from a communication system, and the error physical location represents a channel with transmission errors in the communication system, and the error degree represents the number of error symbols on each channel with transmission errors.

[0116] In a possible embodiment, M=2, the M groups of error correction codewords include a first group of error correction codewords and a second group of error correction codewords, the first group of error correction codewords are read from a first group of pins of the storage particles, and the second group of error correction codewords are read from a second group of pins of the storage particles that are different from the first group of pins.

[0117] In a possible embodiment, all pins of the storage particle are numbered in sequence, the first group of pins includes pins with even numbers, and the second group of pins includes pins with odd numbers.

[0118] In a possible embodiment, the syndrome coding module includes a first coding submodule and a second coding submodule. In response to the presence of a correctable error in the first group of error correction codewords, the first coding submodule is configured to encode target information of a first group of syndromes corresponding to the first group of error correction codewords to obtain a first encoded syndrome; in response to the presence of a correctable error in the second group of error correction codewords, the second coding submodule is configured to encode target information of a second group of syndromes corresponding to the second group of error correction codewords to obtain a second encoded syndrome; wherein the encoded syndrome includes a first encoded syndrome and a second encoded syndrome.

[0119] In a possible embodiment, each group of error correction codewords in the first group of error correction codewords and the second group of error correction codewords includes N error correction codewords, where N is an integer greater than or equal to 1, and the data processing device further includes an error type determination module, wherein for each group of error correction codewords, the error type determination module is configured to: in response to the number of error code elements in the N error correction codewords being less than or equal to a preset number, determine that the N error correction codewords have correctable errors; the syndrome coding module is configured to encode the error positions of the error code elements in the N error correction codewords to obtain the error physical positions of the error code elements, and count the number of error values ​​in the error code elements to obtain the number of errors in the error code elements; wherein the preset number is the maximum number of error code elements in the N error correction codewords that can be corrected simultaneously.

[0120] As described above, according to at least one embodiment of the present disclosure, the data processing device 900 can, for example, report more errors under the premise that the storage resources of the MCA register are limited, thereby improving the utilization rate of storage resources, and the encoded syndrome can directly record the physical location of the error, which facilitates subsequent error analysis and processing.

[0121] The above-mentioned additional aspects of the data processing device 900 according to at least one embodiment of the present disclosure may correspond to the additional aspects of the data processing method according to at least one embodiment of the present disclosure. Therefore, the technical effects of the additional aspects of the data processing method according to at least one embodiment of the present disclosure can also be mapped to the additional aspects of the data processing device 900 according to at least one embodiment of the present disclosure, which will not be repeated here.

[0122] At least one embodiment of the present disclosure further provides an electronic device, which includes at least one processor and at least one memory, wherein the memory stores instructions, wherein when the instructions are executed by the processor, the processor executes the data processing method provided by any of the above embodiments.

[0123] Fig.10 A schematic diagram of an electronic device 1000 according to at least one embodiment of the present disclosure is shown.

[0124] like Fig.10 As shown, the electronic device 1000 includes a processor 1010 and a memory 1020. The memory 1020 includes one or more computer program modules 1021. The one or more computer program modules 1021 are stored in the memory 1020 and are configured to be executed by the processor 1010. The one or more computer program modules 1021 include instructions for executing the data processing method according to at least one embodiment of the present disclosure. When the instructions are executed by the processor 1010, the data processing method according to at least one embodiment of the present disclosure and one or more steps of additional aspects thereof can be executed. The memory 1020 and the processor 1010 can be interconnected through a bus system and / or other forms of connection mechanisms (not shown). For example, the bus can be a peripheral component interconnect standard (PCI) bus or an extended industrial standard architecture (EISA) bus, etc. The communication bus can be divided into an address bus, a data bus, a control bus, etc.

[0125] For example, the processor 1010 may be a central processing unit (CPU), a digital signal processor (DSP), or other forms of processing units with data processing capabilities and / or program execution capabilities, such as a field programmable gate array (FPGA), etc.; for example, the central processing unit (CPU) may be an X86 or ARM architecture, a RISC-V architecture, etc. The processor 1010 may be a general-purpose processor or a dedicated processor, and may control other components in the electronic device 1000 to perform desired functions.

[0126] For example, the memory 1020 may include any combination of one or more computer program products, and the computer program product may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory (cache), etc. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disk read-only memory (CD-ROM), USB memory, flash memory, etc. One or more computer program modules 1021 may be stored on the computer-readable storage medium, and the processor 1010 may run one or more computer program modules 1021 to implement various functions of the electronic device 1000. Various applications and various data, as well as various data used and / or generated by the application, etc. may also be stored in the computer-readable storage medium.

[0127] For example, the electronic device 1000 may also include input devices such as a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; output devices such as a liquid crystal display, a speaker, a vibrator, etc.; storage devices such as a magnetic tape, a hard disk (HDD or SDD), etc.; and communication devices such as a network interface card such as a LAN card, a modem, etc. may also be included. The communication device may allow the electronic device 1000 to communicate with other devices wirelessly or by wire to exchange data, and perform communication processing via a network such as the Internet. The drive is connected to the I / O interface as needed. Removable storage media, such as a disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., are installed on the drive as needed so that the computer program read therefrom is installed into the storage device as needed.

[0128] For example, the electronic device 1000 may further include a peripheral interface (not shown in the figure), etc. The peripheral interface may be various types of interfaces, such as a USB interface, a lightning interface, etc. The communication device may communicate with a network and other devices through wireless communication, such as the Internet, an intranet and / or a wireless network such as a cellular phone network, a wireless local area network (LAN), and / or a metropolitan area network (MAN). Wireless communication may use any of a variety of communication standards, protocols, and technologies, including but not limited to a global system for mobile communications (GSM), an enhanced data GSM environment (EDGE), a wideband code division multiple access (W-CDMA), a code division multiple access (CDMA), a time division multiple access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, and / or IEEE 802.11n standards), a voice transmission over Internet protocol (VoIP), Wi-MAX, protocols for email, instant messaging, and / or short message service (SMS), or any other suitable communication protocol.

[0129] The electronic device 1000 may be, for example, a system on a chip (SOC) or a device including the SOC, for example, a mobile phone, a tablet computer, a laptop computer, an e-book, a game console, a television, a digital photo frame, a navigator, a home appliance, a communication base station, an industrial controller, a server, or any other device, or a combination of any data processing device and hardware, which is not limited by the embodiments of the present disclosure. The specific functions and technical effects of the electronic device 1000 may refer to the description of the data processing method and its additional aspects according to at least one embodiment of the present disclosure, which will not be repeated here.

[0130] At least one embodiment of the present disclosure further provides a computer-readable storage medium having computer-readable instructions stored thereon, wherein when the computer-readable instructions are executed by a processor, the processor executes the data processing method provided by any of the above embodiments.

[0131] Fig.11 A schematic diagram of a non-transitory readable storage medium 1100 according to at least one embodiment of the present disclosure is shown.

[0132] like Fig.11 As shown, a non-transitory readable storage medium 1100 stores computer instructions 1110, and when the computer instructions 1110 are executed by a processor, one or more steps of the data processing method and its additional aspects as described above are performed.

[0133] For example, the non-transitory readable storage medium 1100 may be any combination of one or more computer-readable storage media.

[0134] For example, when the program code is read by a computer, the computer can execute the program code stored in the computer storage medium to perform, for example, one or more steps of the data processing method and additional aspects thereof according to at least one embodiment of the present disclosure.

[0135] For example, the non-transitory readable storage medium may include a memory card of a smart phone, a storage component of a tablet computer, a hard disk of a personal computer, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a portable compact disk read-only memory (CD-ROM), flash memory, and other non-transitory readable storage media or any combination thereof.

[0136] In addition to the above exemplary descriptions, there are a few points that need to be explained:

[0137] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure, and other structures may refer to the general design.

[0138] (2) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to obtain new embodiments.

[0139] The above description is merely an exemplary embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure. The protection scope of the present disclosure is determined by the appended claims.

Claims

1. A data processing method, comprising: Performing a decoding operation on the M groups of error correction codewords to obtain corresponding M groups of syndromes, where M is an integer greater than or equal to 1; and In response to the existence of correctable errors in the M groups of error correction codewords, target information of the M groups of syndromes is encoded to obtain encoded syndromes, wherein the encoded syndromes characterize the erroneous physical positions and error degrees of erroneous codewords in the M groups of error correction codewords.

2. The data processing method according to claim 1, wherein: The target information includes an error position of the error symbol and an error value in the error symbol, and encoding the target information of the M groups of syndromes to obtain the encoded syndromes includes: For each of the M groups of syndromes, encoding the error position of the error symbol to obtain the error physical position of the error symbol, and counting the number of error values ​​in the error symbol to obtain the number of errors in the error symbol, wherein the number of errors in the error symbol represents the error degree of the error symbol; The encoded syndrome includes the erroneous physical position of the erroneous codeword in the M groups of error correction codewords and the number of errors in the erroneous codeword.

3. The data processing method according to claim 2, wherein: The step of encoding the error position of the error symbol to obtain the error physical position of the error symbol comprises: The error physical position corresponding to the error position is determined according to a lookup table.

4. The data processing method according to claim 2, wherein: The error code elements include a first error code element, and counting the number of error values ​​in the error code elements to obtain the number of errors in each of the error code elements includes: Each time one of the error values ​​in the first error codeword is detected, the number of errors in the first error codeword is increased by 1; or, Every time two of the error values ​​in the first error codeword are detected, the number of errors in the first error codeword is increased by 1.

5. The data processing method according to claim 1, wherein: The M groups of error correction codewords include a first group of error correction codewords, and the data processing method further includes: In response to the presence of uncorrectable errors in the first group of error correction codewords, syndromes corresponding to the first group of error correction codewords are directly stored.

6. The data processing method according to claim 1, wherein: The M groups of error correction codewords are from storage particles, and the error physical position represents the pin position where a symbol error exists in the storage particle, and the error degree represents the number of error bits in the symbol error; or The M groups of error correction codewords are from a communication system, and the error physical location represents a channel in the communication system where transmission errors exist, and the error degree represents the number of error symbols on each channel where transmission errors exist.

7. The data processing method according to claim 1, wherein: M=2, the M groups of error correction codewords include a first group of error correction codewords and a second group of error correction codewords, the first group of error correction codewords are read from a first group of pins of a storage particle, and the second group of error correction codewords are read from a second group of pins of the storage particle that is different from the first group of pins.

8. The data processing method according to claim 7, wherein: All pins of the storage particle are numbered in sequence, the first group of pins includes pins with even numbers, and the second group of pins includes pins with odd numbers.

9. The data processing method according to claim 7, wherein: In response to the presence of correctable errors in the M groups of error correction codewords, encoding target information of the M groups of syndromes to obtain encoded syndromes comprises: In response to the correctable errors existing in both the first group of error correction codewords and the second group of error correction codewords, target information of a first group of syndromes corresponding to the first group of error correction codewords and target information of a second group of syndromes corresponding to the second group of error correction codewords are respectively encoded to obtain a first encoded syndrome and a second encoded syndrome, The post-coded syndrome includes the first post-coded syndrome and the second post-coded syndrome.

10. The data processing method according to claim 9, wherein: Each of the first group of error correction codewords and the second group of error correction codewords includes N error correction codewords, where N is an integer greater than or equal to 1. In response to the correctable errors existing in both the first group of error correction codewords and the second group of error correction codewords, encoding target information of a first group of syndromes corresponding to the first group of error correction codewords and target information of a second group of syndromes corresponding to the second group of error correction codewords, respectively; Including, for each set of error correction codewords: In response to the number of error symbols in the N error correction codewords being less than or equal to a preset number, determining that the N error correction codewords have the correctable errors; as well as Encoding the error positions of the error symbols in the N error correction codewords to obtain the error physical positions of the error symbols, and counting the number of error values ​​in the error symbols to obtain the number of errors in the error symbols; The preset number is based on the maximum number of erroneous code elements that can be corrected simultaneously in the N error correction code words.

11. A data processing device, comprising: a decoding module configured to perform a decoding operation on the M groups of error correction codewords to obtain corresponding M groups of syndromes, where M is an integer greater than or equal to 1; and The syndrome encoding module is configured to encode target information of the M groups of syndromes in response to the presence of correctable errors in the M groups of error correction codewords to obtain encoded syndromes, wherein the encoded syndromes represent the erroneous physical positions and error degrees of erroneous code elements in the M groups of error correction codewords.

12. The data processing apparatus according to claim 11, wherein: The syndrome coding module includes M coding submodules, and the coding submodules include a position conversion unit and a bit accumulation unit. For each group of syndromes in the M groups of syndromes, the position conversion unit in the corresponding encoding submodule is configured to encode the error position of the error codeword to obtain the error physical position of the error codeword, and the bit accumulation unit in the corresponding encoding submodule is configured to count the number of error values ​​in the error codeword to obtain the number of errors in the error codeword.

13. The data processing apparatus according to claim 12, wherein: When encoding the error position of the error symbol to obtain the error physical position of the error symbol, the position conversion unit is configured to determine the error physical position corresponding to the error position according to a lookup table.

14. The data processing apparatus according to claim 12, wherein: The error code element comprises a first error code element, and when counting the number of error values ​​in the error code element to obtain the number of errors in the error code element, the bit accumulation unit is configured to: Each time one of the error values ​​in the first error codeword is detected, the number of errors in the first error codeword is increased by 1; or, Whenever two error values ​​in the first error codeword are detected, the error number of the first error codeword is increased by 1.

15. An electronic device, comprising: at least one processor; at least one memory having instructions stored thereon, When the instruction is executed by the at least one processor, the at least one processor executes the data processing method according to any one of claims 1 to 10.

16. A computer-readable storage medium having computer-readable instructions stored thereon, in, When the computer-readable instructions are executed by a processor, the processor is caused to perform the data processing method according to any one of claims 1 to 10.

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