Cache line-based data backup method, device, processor and computing device

Abstract

A cache line-based data backup method, device, processor and computing device belong to the technical field of storage. In the method, in response to a first data write instruction, the data in the first data write instruction is written into a first cache line in the cache, so that the state of the first cache line is modified, and a backup cache line of the first cache line is stored in the cache. In the above method, the modified state indicates that the data in the first cache line is new data, does not exist in other caches, and is inconsistent with the data in the memory. Therefore, storing the backup cache line of the first cache line in the cache can avoid the data inconsistency problem caused by the error of the data in the first cache line.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to a data backup method, apparatus, processor and computing device based on cache lines. Background Technology

[0002] Cache memory (or simply cache) is a high-speed, small-capacity memory located between the central processing unit (CPU) and main memory in a computer's storage system hierarchy. Cache is divided into Level 1 cache (L1 cache), Level 2 cache (L2 cache), and Level 3 cache (L3 cache). The L1, L2, and L3 caches are located further away from the CPU, with increasing capacity and decreasing data retrieval speed in that order. In multi-core processors, each core has its own dedicated L1 and L2 cache, while all cores share the L3 cache. When the CPU writes data, it first writes the data to the cache; when the CPU reads data, it first checks the cache. Only if the required data is not found in the cache is the data read from main memory. The units in the cache that store data are called cache lines.

[0003] In related technologies, when any core in the CPU initiates a write instruction to memory, the operating system first writes the data corresponding to the write instruction into the cache line in the cache corresponding to that core, and marks the state of the cache line based on the cache coherence protocol (modified exclusive shared invalid, MESI). The state of the cache line is used to indicate the consistency status of the data in the caches and memory corresponding to multiple CPU cores. For example, if the cache line is marked as modified (M), it means that the data in the cache line is new data and is inconsistent with the data that does not exist in other caches and is not in memory.

[0004] However, in the above method, since the data in the cache line marked as modified is inconsistent with the data in other caches and memory and is only stored once, the longer the data exists in the cache, the greater the probability of bit flipping will be, leading to errors in the cached data and thus reducing the reliability of the data. Summary of the Invention

[0005] This application provides a data backup method, apparatus, processor, and computing device based on a cache line, which can improve the reliability of the stored data. The technical solution is as follows.

[0006] Firstly, a data backup method based on a cache line is provided, the method comprising:

[0007] In response to a first data write instruction, the data in the data write instruction is written to a first cache line in the cache, such that the state of the first cache line is modified, the modified state indicating that the data in the first cache line is new data and does not exist in the cache and is inconsistent with the data in memory.

[0008] Here, the first data is the data corresponding to the first write instruction, and the state of the first data is modified. The modified state indicates that the first data is valid, exists only in the cache, and is inconsistent with the data in memory. The first data satisfies the write-back condition when the first cache line storing the first data needs to be used to store backup data of other data, that is, the data in the first cache line needs to be replaced.

[0009] In the above method, since the state of the first data is modified, that is, it only exists in the cache and is inconsistent with the data in memory, storing backup data of the first data in the cache can avoid data inconsistency problems caused by errors in the first data. Furthermore, only data in the modified state is stored in the cache as backup data, while data in the exclusive state (which is consistent with the data in memory) and data in the shared state (which also exists in other caches and is consistent with the data in memory) are not stored in the cache as backup data. This can avoid excessive cache occupation by redundant backup data, thereby ensuring cache hit rate while ensuring data reliability.

[0010] Optionally, in response to a first data write instruction, writing the data in the first data write instruction into a first cache line in the cache includes:

[0011] In response to a write instruction to a memory address, the data in the write instruction is written to the first cache line.

[0012] Optionally, in response to a first data write instruction, writing the data in the first data write instruction into a first cache line in the cache includes:

[0013] In response to a write-back instruction to the previous cache level, the data in the write-back instruction is written to the first cache line.

[0014] Optionally, the cache includes multiple groups, each group including multiple cache lines, and a backup cache line of the first cache line is stored in the cache, including:

[0015] The backup cache line of the first cache line is stored in the group where the first cache line is located.

[0016] Optionally, storing backup cache lines of the first cache line in the group containing the first cache line includes:

[0017] Identify at least one second cache line in the group containing the first cache line; copy the first cache line to the at least one second cache line.

[0018] Optionally, the group to which the first cache line belongs includes 2N cache lines, wherein the i-th cache line corresponds to the (N+i)-th cache line, where N is an integer greater than 1 and i is an integer greater than or equal to 0 and less than N;

[0019] Determining at least one second cache line in the group containing the first cache line includes: determining the cache line in the group containing the first cache line that corresponds to the first cache line as the second cache line.

[0020] Optionally, determining at least one second cache line in the group containing the first cache line includes any of the following:

[0021] Based on the Least Recently Used algorithm, at least one second cache line is determined in the group containing the first cache line; based on the First In First Out algorithm, at least one second cache line is determined in the group containing the first cache line; based on the Random Replacement algorithm, at least one second cache line is determined in the group containing the first cache line.

[0022] Among them, the Least Recently Used (LRU) algorithm is used to determine the cache line that has been accessed the least recently as the second cache line; the First In First Out (FIFO) algorithm is used to determine the cache line that has existed the longest as the second cache line; and the Random Replacement (RAND) algorithm is used to determine the cache line determined by a random number as the second cache line.

[0023] Optionally, copying the first cache line to the at least one second cache line includes:

[0024] If the second cache line is in an exclusive, shared, or invalid state, then the first cache line is copied to the second cache line; if the second cache line is in a modified state, then the data in the second cache line is written back to memory, and the first cache line is copied to the second cache line.

[0025] Specifically, the exclusive state indicates that the data in the second cache line does not exist in other caches and is consistent with the data in memory; the shared state indicates that the data in the second cache line also exists in other caches and is consistent with the data in memory; and the invalid state indicates that the data in the second cache line is invalid.

[0026] The second cache line may have stored other data before storing the first data, and the stored data may exist only in that cache, or it may exist in both that cache and memory or other caches. To avoid data loss caused by overwriting the data originally stored in the second cache line when the first data is copied to it, the computing device copies the first data to at least one second cache line based on the state of the data already stored in the second cache line.

[0027] Optionally, the first cache line further includes a memory mirroring marker, which indicates whether there is a backup of the data at the memory address corresponding to the first cache line in that memory. A backup cache line of the first cache line is stored in the cache, including:

[0028] If the memory mirroring mark in the first cache line indicates that the data at the memory address corresponding to the first data write instruction has a backup in memory, then the backup cache line of the first cache line is stored in the cache.

[0029] Optionally, the method further includes:

[0030] In response to a read instruction for the memory address, the backup cache lines of the first and second cache lines in the cache are verified respectively. The first cache line is the cache line corresponding to the memory address. If both the first cache line and its backup cache line are verified successfully, the data in the first cache line is returned. If only one of the first cache line and its backup cache line is verified successfully, the data in the successfully verified cache line is returned, and the cache line that failed to be verified is restored based on the successfully verified cache line.

[0031] Optionally, the cache line includes a label, status information, a memory mirror marker, and data. The label is used to indicate the memory address corresponding to the cache line. The method further includes:

[0032] Error checking and correcting (ECC) is used to protect the tags, status information and memory image markers in the cache lines, while cyclic redundancy check (CRC) is used to protect the data in the cache lines.

[0033] Optionally, the method further includes:

[0034] In response to a second data write instruction, the data in the second data write instruction is written to the first cache line in the cache; the data in the backup cache line of the first cache line is overwritten with the data in the second data write instruction.

[0035] The second data write instruction can be a write instruction to a memory address or a write-back instruction to the previous level cache.

[0036] In a second aspect, a cache-line-based data backup apparatus is provided, the apparatus comprising at least one functional module for performing the cache-line-based data backup method provided by the first aspect or any possible implementation thereof.

[0037] Thirdly, a processor is provided for executing the cache-line-based data backup method provided by the first aspect or any possible implementation thereof.

[0038] Fourthly, a computing device is provided, the computing device including a processor and a memory storing program code, the processor executing the program code, causing the computing device to perform a cache-line-based data backup method as provided in the first aspect or any possible implementation of the first aspect.

[0039] Fifthly, a storage medium is provided for storing at least one piece of program code for executing a cache-line-based data backup method as provided in the first aspect or any possible implementation thereof.

[0040] Based on the implementation methods provided in the above aspects, this application can be further combined to provide more implementation methods. Attached Figure Description

[0041] Figure 1 This is a schematic diagram of the structure of a computing device provided in an embodiment of this application;

[0042] Figure 2 This is a schematic diagram of a cache consistency architecture provided in an embodiment of this application;

[0043] Figure 3 This is a flowchart of a data backup method based on a cache line provided in an embodiment of this application;

[0044] Figure 4 This is a flowchart illustrating a data backup method based on a cache line provided in an embodiment of this application;

[0045] Figure 5 This is a flowchart illustrating the data reading method in a data backup method based on a cache line provided in an embodiment of this application;

[0046] Figure 6 This is a flowchart illustrating the data writing method in a data backup method based on a cache line provided in an embodiment of this application;

[0047] Figure 7 This is a schematic diagram of the structure of a data backup device based on a cache line provided in an embodiment of this application. Detailed Implementation

[0048] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0049] First, the structure of a computing device provided in an embodiment of this application is introduced.

[0050] like Figure 1 As shown, Figure 1 This is a schematic diagram of the structure of a computing device provided in an embodiment of this application. The computing device 100 may be a host, server, or personal computer, etc. The computing device 100 may be implemented using a general bus architecture.

[0051] The computing device 100 includes at least one processor 101, a communication bus 102, a memory 103, and at least one communication interface 104.

[0052] Processor 101 may be, for example, a general-purpose central processing unit (CPU), a network processor (NP), a graphics processing unit (GPU), a neural-network processing unit (NPU), a data processing unit (DPU), a microprocessor, or one or more integrated circuits for implementing the embodiments of this application. For example, processor 101 may include an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. A PLD may be, for example, a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.

[0053] The communication bus 102 is used to transmit information between the aforementioned components. The communication bus 102 can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 1The symbol is represented by only one line, but this does not mean that there is only one bus or one type of bus.

[0054] Memory 103 may be, for example, read-only memory (ROM) or other types of static storage devices capable of storing static information and instructions; random access memory (RAM) or other types of dynamic storage devices capable of storing information and instructions; electrically erasable programmable read-only memory (EEPROM); compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed discs, laser discs, optical discs, digital universal discs, Blu-ray discs, etc.); magnetic disk storage media or other magnetic storage devices; or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer, but not limited thereto. Memory 103 may exist independently and be connected to processor 101 via communication bus 102. Memory 103 may also be integrated with processor 101.

[0055] Communication interface 104 uses any transceiver-like device for communicating with other devices or communication networks. Communication interface 104 includes a wired communication interface and may also include a wireless communication interface. The wired communication interface may be, for example, an Ethernet interface. The Ethernet interface may be an optical interface, an electrical interface, or a combination thereof. The wireless communication interface may be a wireless local area network (WLAN) interface, a cellular network communication interface, or a combination thereof.

[0056] As one embodiment, processor 101 may include one or more CPUs.

[0057] As one embodiment, computing device 100 may include a plurality of processors, each of which may be a single-core processor (single-CPU) or a multi-core processor (multi-CPU). Here, a processor may refer to one or more devices, circuits, and / or processing cores used to process data (such as program code).

[0058] As one embodiment, the computing device 100 may further include an output device and an input device. The output device communicates with the processor 101 and can display information in various ways. For example, the output device may be a liquid crystal display (LCD), a light-emitting diode (LED) display device, a cathode ray tube (CRT) display device, or a projector, etc. The input device communicates with the processor 101 and can receive user input in various ways. For example, the input device may be a mouse, a keyboard, a touchscreen device, or a sensing device, etc.

[0059] In some embodiments, the memory 103 is used to store program code for executing the scheme of this application, and the processor 101 can execute the program code stored in the memory 103. That is, the computing device 100 can implement the cache-line-based data backup method provided in the method embodiment through the processor 101 and the program code in the memory 103.

[0060] This application relates to a cache coherence architecture in computing devices. To facilitate understanding of the embodiments of this application, the following description is provided. Figure 2 This document explains several technical terms related to cache consistency architecture.

[0061] Figure 2 This is a schematic diagram of a cache consistency architecture provided in an embodiment of this application, such as... Figure 2 As shown, the cache coherent architecture includes multiple CPU cores (core1 and core2), a cache memory, and memory.

[0062] The cache, or simply cache, is a high-speed, small-capacity memory located between the CPU and main memory in the computer's storage system hierarchy. When the CPU needs data, it first checks the cache. If the data is not found in the cache, it reads the data from main memory. The cache is divided into Level 1 cache (L1 cache), Level 2 cache (L2 cache), and Level 3 cache (L3 cache). The L1, L2, and L3 caches are located further away from the CPU, with increasing capacity and decreasing speed for data retrieval. When the CPU needs data, it first checks the L1 cache. If the data is not found in the L1 cache, it checks the L2 cache. If the data is not found in the L2 cache, it checks the L3 cache. If the data is not found in the L3 cache either, it checks main memory. In multi-core processors, each core has its own dedicated L1 and L2 caches, while all cores share the L3 cache. Because the data required by the CPU changes over time, some data stored in the cache becomes infrequently accessed by the CPU. This infrequently accessed data is written back to memory level by level to avoid excessive cache usage. Specifically, write-back means that when data in the higher-level cache meets the write-back condition, it is written to the lower-level cache; when data in the lowest-level cache meets the write-back condition, it is written to memory. For example, when data in the first-level cache meets the write-back condition, it is written to the second-level cache; when data in the second-level cache meets the write-back condition, it is written to the third-level cache; and when data in the third-level cache meets the write-back condition, it is written to memory.

[0063] A cache line is a unit of data storage in a cache, and also the smallest unit for data interaction between the cache and main memory. In some embodiments, the capacity of a cache line is limited to the amount of data that can be accessed within one storage cycle of main memory (i.e., main memory).

[0064] Entry: In this application, an entry in the cache refers to an entry containing tag, data, and attribute fields, corresponding to a cache line. The tag indicates a memory address, data stores the data, and the attribute stores the cache line's attribute information. For multi-core CPUs, based on the cache coherency protocol, the MESI status is used to describe the status of the data in the cache line. Correspondingly, the attribute field in the entry stores the cache line's MESI status, which can be described using Table 1 below. For a single-core CPU, the state of the cache line is described by the value of its target bit (dirty valid). For example, a dirty valid value of 00 indicates that the data in the cache line is invalid (corresponding to the I state in MESI), a dirty valid value of 01 indicates that the data in the cache line is valid and has not been modified (corresponding to the E state in MESI), a dirty valid value of 10 indicates that the state is invalid, and a dirty valid value of 11 indicates that the data in the cache line is valid and has been modified (corresponding to the M state in MESI). Correspondingly, the attribute field in the entry stores the dirty valid status of the data. In some embodiments, the attribute field in the entry also stores a memory mirroring flag (MF), which is used to indicate whether there is a backup of the data at the memory address corresponding to the cache line in memory.

[0065] Table 1

[0066]

[0067] Snoop filter (SF): A part of the cache memory, at the same level as the L3 cache, used to solve cache coherency issues. The SF listens for write commands from other cores and invalidates data in its local cache when necessary to ensure the consistency of the same data in the caches of multiple cores (this process is called snooping). The SF records the cache line tag, MESI status, and the core number of the cache line. Snooping refers to a local core sending read / write requests to other specific cores via the bus, allowing the receiving core to respond to the read / write request based on its local conditions.

[0068] Write back: When the CPU initiates a write instruction to memory, it only temporarily writes the data to the cache and marks it with a flag. The data is not written back to memory until it is evicted, flushed, or snooped.

[0069] Based on the cache consistency structure in the aforementioned computing device, this application provides a data backup method based on cache lines. In response to a first data write instruction, the data in the first data write instruction is written to a first cache line in the cache, making the state of the first cache line "modified." A backup cache line of the first cache line is stored in the cache. In this method, the "modified" state indicates that the data in the first cache line is new data, does not exist in other caches, and is inconsistent with the data in memory. Therefore, storing a backup cache line of the first cache line in the cache can avoid data inconsistency problems caused by errors in the data in the first cache line. Furthermore, only cache lines in the "modified" state have their backup cache lines stored in the cache. For cache lines in the exclusive state (data exists only in this cache and is consistent with the data in memory) and shared state (data also exists in other caches and is consistent with the data in memory), their backup cache lines are not stored in the cache. This avoids excessive cache occupation by redundant backups, thereby ensuring both data reliability and cache hit rate.

[0070] The basic process of a data backup method based on a cache line provided by the embodiments of this application has been introduced above. The process of this method will be described in detail below. Figure 3 This is a flowchart of a data backup method based on a cache line provided in an embodiment of this application, such as... Figure 3 As shown, taking the method as an example of being executed by a computing device, the method includes the following steps 301 to 304.

[0071] 301. In response to a first data write instruction, the computing device writes the data in the first data write instruction into a first cache line in the cache, such that the state of the first cache line is modified, and the modified state indicates that the data in the first cache line is new data, does not exist in other caches, and is inconsistent with the data in memory.

[0072] The first data write instruction can be a write instruction to a memory address. Correspondingly, writing the data in the first data write instruction to the first cache line in the cache is equivalent to writing the data in the write instruction to that first cache line. The first data write instruction can also be a write-back instruction to the previous level cache. Correspondingly, writing the data in the first data write instruction to the first cache line in the cache is equivalent to writing the data in the write-back instruction to that first cache line. The cache refers to the cache corresponding to the CPU core that initiated the first data write instruction in the computing device, including the L1, L2, and L3 caches corresponding to that CPU core. Correspondingly, other caches refer to other caches in the computing device besides the cache corresponding to that CPU core. Since multiple CPU cores share the L3 cache, other caches are also the L1 and L2 caches exclusively used by other CPU cores. The cache includes multiple cache lines, each storing a tag, data, and attribute information. The attribute information includes the cache line's status and a memory mirror marker.

[0073] In this process, the computing device responds to the first data write instruction by determining a first cache line in the cache and writing the data in the first data write instruction into the determined first cache line.

[0074] The computing device uses a set-associative mapping method to determine the first cache line in the cache. In this mapping method, the cache includes multiple groups, and each group includes multiple cache lines. The first string in the memory address carried by the first data write instruction is the comparison tag, the second string is the group index, and the third string is the offset. The process by which the computing device determines the first cache line in the cache includes: determining the group corresponding to the group index in the cache based on the group index in the memory address; comparing the comparison tag in the memory address with the tags in the multiple cache lines in the determined group; if the tag of any cache line in the group matches the comparison tag (i.e., a write hit), then the cache line is determined as the first cache line; if the tags of all cache lines in the group do not match the comparison tag, and the cache is full (i.e., a write miss and the cache is full), then a cache line in the cache is determined as the first cache line; if the tags of all cache lines in the group do not match the comparison tag, and the cache is not full (i.e., a write miss and the cache is not full), then any free cache line in the group is determined as the first cache line. In the three cases mentioned above, the process of the computing device writing the data in the first data write instruction to the first cache line is different. The process of writing data to the first cache line in the three cases will be described below.

[0075] The first scenario is a write hit. Based on the state of the first cache line, the computing device writes the data from the first data write instruction into the first cache line. Specifically, if the first cache line was previously in a modified or exclusive state, the computing device directly overwrites the original data stored in the first cache line with the data from the first data write instruction. If the first cache line was previously in a shared state, the computing device will snoop to invalidate the corresponding cache line state of other cores possessing the same data, making the first cache line in this cache exclusive, and then overwrite the original data stored in the first cache line with the data from the first data write instruction. This process can be understood as modifying the state of the first cache line to a modified or exclusive state before writing data.

[0076] The second scenario: Write miss and cache full. The computing device, based on the state of the first cache line, writes the data from the first data write instruction to the first cache line. Specifically, if the first cache line was previously in a modified state, the computing device first writes back the data originally stored in the first cache line, then sets the state of the first cache line to invalid. If the first cache line was previously in an exclusive or shared state, the computing device directly sets the state of the first cache line to invalid and notifies the SF to update the state of the first cache line. For the data originally stored in the first cache line, the computing device first checks the state recorded in the SF. If there is no record in the SF, it checks the L3 cache and memory. If other caches store the same data as the first cache line in this cache, the local core uses snoop to instruct other cores with the same data to set the state of their corresponding cache lines to invalid. The local core then writes the data from the first data write instruction to the first cache line.

[0077] The third scenario: Write miss and cache not full. The calculation first checks the status of the record in the SF. If there is no record in the SF, it checks the L3 cache and memory. If other caches store the same data as the first cache line in this cache, the local core uses snoop to make other cores with the same data invalidate the status of the corresponding cache line. The local core then writes the data in the first data write instruction into the first cache line.

[0078] 302. The computing device determines at least one second cache line in the group to which the first cache line belongs.

[0079] The second cache line serves as a backup cache line for the first cache line. The number of the second cache lines can be set according to actual needs. For example, if the reliability requirement of the data in the first cache line is higher, the number of backup cache lines for the first cache line will be more, which means the number of the second cache lines will be more. If the reliability requirement of the data in the first cache line is lower, the number of backup cache lines for the first cache line will be less, which means the number of the second cache lines will be less. This application does not limit the number of backup cache lines for the first cache line, and therefore does not limit the number of the second cache lines.

[0080] The computing device determines the second cache line within the group containing the first cache line based on either a fixed or non-fixed strategy. The determination of the second cache line under both the fixed and non-fixed strategies are described below.

[0081] Fixed strategy: The position of the backup cache line corresponding to each cache line is fixed. The group containing the first cache line includes 2N cache lines, where the i-th cache line corresponds to the (N+i)-th cache line, where N is an integer greater than 1 and i is an integer greater than or equal to 0 and less than N; the computing device determines the cache line in the group containing the first cache line that corresponds to the first cache line as the second cache line. It should be noted that the above-described cache line correspondence is merely exemplary, and the cache line correspondence can be determined based on the number of backup cache lines. This application embodiment does not limit this.

[0082] Non-fixed strategy: The location of the backup cache line corresponding to each cache line is not fixed. The process by which the computing device determines at least one second cache line in the group containing the first cache line includes any of the following methods: First method: determining at least one second cache line in the group containing the first cache line based on the Least Recently Used (LRU) algorithm; Second method: determining at least one second cache line in the group containing the first cache line based on the First In First Out (FIFO) algorithm; Third method: determining at least one second cache line in the group containing the first cache line based on the Random Replacement (RAND) algorithm. The Least Recently Used (LRU) algorithm is used to determine the cache line that has been accessed least recently as the second cache line; the First In First Out (FIFO) algorithm is used to determine the cache line that has existed the longest as the second cache line; and the Random Replacement (RAND) algorithm is used to determine the cache line determined by a random number as the second cache line. It should be noted that the above three replacement algorithms are merely exemplary and can be set according to actual needs; this application embodiment does not limit this.

[0083] In some embodiments, the attribute information of the first cache line includes a memory mirroring marker. If the memory mirroring marker in the first cache line indicates that the data at the memory address corresponding to the first cache line has a backup in memory, the computing device determines at least one second cache line in the group to which the first cache line belongs, so as to store the backup cache line of the first cache line in the cache. In the above method, the backup of the data is stored on the cache side only when the memory side performs mirror protection for the data at the memory address corresponding to the first data write instruction. That is, mirroring is selectively performed on the cache side, which can avoid the problem that the data protection effect on the cache side is greatly reduced due to mirroring on the cache side but not on the memory side. At the same time, selective mirroring on the cache side can increase the proportion of valid data in the cache while ensuring the reliability of the cache side data, and avoid excessive cache occupation by backup data leading to a decrease in cache hit rate.

[0084] 303. The computing device copies the first cache line to at least one second cache line based on the state of the at least one second cache line, so as to store a backup cache line of the first cache line in the cache.

[0085] The second cache line may have stored other data before storing the data in the first cache line, and the stored data may exist only in this cache, or it may exist in both this cache and memory or other caches.

[0086] Taking the copying of the first cache line to any second cache line as an example, the process of the computing device copying the first cache line to the second cache line based on the state of the second cache line includes: if the state of the second cache line is exclusive, shared, or invalid, then the first cache line is copied to the second cache line; if the state of the second cache line is modified, then the data in the second cache line is written back to memory, and then the first cache line is copied to the second cache line.

[0087] It should be noted that steps 302 and 303 above are one implementation of storing the backup cache line of the first cache line in the cache. In some embodiments, this step is also implemented in other ways, and this application embodiment does not limit this.

[0088] 304. In response to the first cache line meeting the write-back condition, the computing device writes back the data in the first cache line to memory level by level.

[0089] In this context, "the first cache line meeting the write-back condition" means that the first cache line needs to store backup data for other data, i.e., the data in the first cache line needs to be replaced. "Level-by-level write-back" means that when data in a higher-level cache meets the write-back condition, that data is written to a lower-level cache; when data in the lowest-level cache meets the write-back condition, that data is written to memory. For example, when data in a first-level cache meets the write-back condition, it is written to a second-level cache; when data in a second-level cache meets the write-back condition, it is written to a third-level cache; and when data in a third-level cache meets the write-back condition, it is written to memory. After the computing device writes the first data back to memory, it updates the records in the listener filter.

[0090] In some embodiments, in response to the first cache line meeting the write-back condition, the computing device writes the data in the first cache line back to memory level by level, and invalidates the status of all backup cache lines of the first cache line. In the above method, the first cache line meeting the write-back condition indicates that the CPU accesses the data in the first cache line less frequently. Writing back the data in the first cache line while invalidating the backup cache lines of the first cache line can avoid excessive cache occupation and free up space for data that is accessed more frequently by the CPU.

[0091] For computing devices including multi-core CPUs, in some embodiments, if the listener filter detects a read instruction from another core for the first cache line, the current core modifies the state of the first cache line in the cache to a shared state and modifies the state of the backup cache line of the first cache line to an invalid state. In the above method, when other cores need to read the first cache line, setting the first cache line to a shared state allows other caches to synchronize the first cache line, satisfying the possible read needs of other cores for the first cache line. Other CPU cores do not need to read the first cache line from memory, which can improve the read efficiency of the first cache line. At the same time, setting the backup cache line of the first cache line to an invalid state can avoid excessive cache occupation. In other embodiments, if the listener filter detects a write instruction from another core for the memory address or modifies the state of the cache line corresponding to the memory address in the cache to an exclusive state, the current core modifies the state of both the first cache line and the backup cache line of the first cache line in the cache to an invalid state and writes back the data in the first cache line.

[0092] It should be noted that step 304 is an optional step. In some embodiments, step 304 may not be performed. This application does not limit this.

[0093] The following is based on Figure 4 For example, the process shown in step 304 of step 301 above will be illustrated. Figure 4This is a flowchart illustrating a data backup method based on a cache line provided in an embodiment of this application, as shown below. Figure 4 As shown, the memory stores data "Data_x = 3" and data "Data_y = 2". The memory address corresponding to "Data_x = 3" is mapped to the second way cache line of the first group (i.e., the first cache line). The memory address corresponding to "Data_y = 2" is mapped to the fourth way cache line of the first group. If the state of the fourth way cache line of the first group is invalid (I), shared (S), or exclusive (E), the process of the computing device executing the cache line-based data backup method includes: Step ①: In response to the CPU executing a write instruction on the second way cache line of the first group, a request is sent to the listener filter (SF). The status of the second cache line in group 1 is E, SF returns the status as E; modify the data "Data_x=3" in the second cache line of group 1 to "Data_x=5", set its status to modified status (M), and notify SF to update the record; Step ②: Select one cache line to store the backup cache line: taking the LRU algorithm under non-fixed strategy as an example, determine the least recently used cache line in group 1 as the fourth cache line, determine the fourth cache line of group 1 as the second cache line, and the status of the second cache line is I; Step ③: copy "Data_x=5" from the second cache line of group 1 to the fourth cache line of group 1, and set the status of the fourth cache line of group 1 to M. If the state of the fourth cache line of the first group is modified (M), the process is the same as above. The difference is that before copying "Data_x=5" from the second cache line of the first group to the fourth cache line of the first group, the computing device first writes the data in the fourth cache line of the first group back to memory. The similarities will not be repeated here.

[0094] In the above method, the modified state indicates that the data in the first cache line is new data, does not exist in other caches, and is inconsistent with the data in memory. Therefore, storing a backup cache line of the first cache line in the cache can avoid data inconsistency caused by errors in the data in the first cache line. Furthermore, the backup cache line is only stored in the cache for the cache line in the modified state. For cache lines in the exclusive state (data exists only in this cache and is consistent with the data in memory) and the shared state (data also exists in other caches and is consistent with the data in memory), the backup cache line is not stored in the cache. This can avoid excessive cache occupation by redundant backups, thereby ensuring both data reliability and cache hit rate. Furthermore, the backup cache line of the first cache line is only stored on the cache side when the memory side performs mirror protection on the data at the memory address corresponding to the first write instruction. That is, mirroring is selectively performed on the cache side, which can avoid the problem of greatly reduced data protection effect on the cache side due to mirroring on the cache side but not on the memory side. It can also further increase the proportion of effective data in the cache and further avoid excessive cache occupation by backup cache lines, which would lead to a decrease in cache hit rate.

[0095] The above describes the flow of a data backup method based on cache lines provided by embodiments of this application. Based on steps 301 to 303 above, the cache already stores a first cache line and a backup cache line of the first cache line. In some embodiments, the computing device can read data from the first cache line from the cache. This process includes: in response to a read instruction for a memory address, verifying the first cache line and the backup cache line of the second cache line in the cache respectively, wherein the first cache line is the cache line corresponding to the memory address; if both the first cache line and the backup cache line of the first cache line are successfully verified, then the data in the first cache line is returned; if only one of the first cache line and the backup cache line of the first cache line is successfully verified, then the data in the successfully verified cache line is returned, and the cache line that failed to be verified is restored based on the successfully verified cache line.

[0096] As can be seen from step 302 above, if the computing device determines the second cache line within the group containing the first cache line based on a fixed strategy, then the position of the second cache line is fixed, which also means the position of the backup cache line for the first cache line is fixed. If the computing device determines the second cache line within the group containing the first cache line based on a non-fixed strategy, then the position of the second cache line is not fixed, which also means the position of the backup cache line for the first cache line is not fixed. The data reading process under the fixed strategy and the data reading process under the non-fixed strategy will be described below.

[0097] The cache line includes a tag, data, and attribute information. The tag indicates the memory address corresponding to the cache line, and the attribute information indicates the cache line's status (MESI) and memory mirror mark (MF). If the tag is incorrect, the computing device will fail to hit the cache; if the data in the cache line is incorrect, the computing device will read incorrect data; if the attribute information is incorrect, the computing device will obtain an incorrect status or memory mirror mark. Therefore, the computing device verifies the cache line before reading data from the cache. For cache lines with backup cache lines, error checking and correcting (ECC) is used to protect the tag, status (MESI), and memory mirror mark (MF) of the cache line, and cyclic redundancy check (CRC) is used to protect the data in the cache line. For cache lines without backup cache lines, ECC is used to protect the cache line. The computing device verifies the cache lines according to the verification method corresponding to the protection method described above. It should be noted that the above description of the protection and verification methods is merely exemplary. In some embodiments, other methods may be used to protect and verify the cache lines, and this application does not limit this.

[0098] First, we introduce the data reading process under a fixed policy. Using the aforementioned verification method as an example, we will illustrate the data reading process under a fixed policy. Under a fixed policy, in response to a read instruction for a memory address, the computing device first verifies multiple cache lines in the target group in the cache according to the aforementioned verification method, and then reads the data based on the verification results. The target group is the group in the cache corresponding to the memory address. The data reading process under a fixed policy includes the following two cases.

[0099] Scenario 1: All cache lines are successfully verified. If the tag of any of the cache lines matches the memory address in the read instruction, the computing device returns the data in that cache line. If none of the cache line tags match the memory address in the read instruction, the computing device determines a cache line to be replaced based on a replacement strategy. If the replaced cache line has a backup cache line, it is written back to the next level cache or memory. The data corresponding to the memory address is then read from the next level cache or memory, and the read data is written to the replaced cache line. The CPU then reads the data from the cache.

[0100] The second scenario: the first cache line verification succeeds, but the backup cache line verification fails. If the label of the first cache line matches the memory address in the read instruction, the computing device returns the data in the first cache line and copies the first cache line to the backup cache line to restore the backup cache line. If the labels of multiple cache lines do not match the memory address in the read instruction, the computing device determines a cache line to be replaced from the cache based on the replacement strategy. If the replaced cache line has a backup cache line, the cache line is written back to the next level cache or memory. The data corresponding to the memory address is then read from the next level cache or memory and written to the replaced cache line. The CPU then reads the data from the cache. If there are still cache lines that have failed verification, the computing device restores the cache line based on its backup cache line (if the cache line has a backup cache line and the verification is successful). If the backup cache lines of multiple cache lines fail verification, the computing device restores the backup cache lines one by one. The restoration process is the same as the process of restoring the backup cache line of the first cache line based on the first cache line in the second case, and will not be described again.

[0101] The data reading process under a non-fixed strategy is described below. Taking the above verification method as an example, the data reading process under a non-fixed strategy is illustrated below. Under a non-fixed strategy, in response to a read instruction for a memory address, the computing device first verifies multiple cache lines in the target group in the cache according to the above verification method, and reads the data from the cache lines based on the verification results. The target group is the group in the cache corresponding to the memory address. The data reading process under a non-fixed strategy includes the following four cases.

[0102] Scenario 1: All cache lines are successfully verified. If the tag of any of the cache lines matches the memory address in the read instruction, the computing device returns the data in that cache line. If none of the cache line tags match the memory address in the read instruction, the computing device determines a cache line to be replaced based on a replacement strategy. If the replaced cache line has a backup cache line, it is written back to the next level cache or memory. The data corresponding to the memory address is then read from the next level cache or memory, and the read data is written to the replaced cache line. The CPU then reads the data from the cache.

[0103] The second scenario: The first cache line verification succeeds, but the tag verification of another cache line fails, and the computing device cannot find a backup cache line for the first cache line (i.e., the first cache line is not paired). This indicates that the cache line whose tag verification failed is a backup cache line for the first cache line. If the tag of the first cache line matches the memory address in the read instruction, the computing device returns the data from the first cache line and copies the first cache line to the backup cache line to restore the backup cache line. If the tags of multiple cache lines do not match the memory address in the read instruction, the computing device determines a cache line to be replaced based on a replacement strategy. If the replaced cache line has a backup cache line, it is written back to the next level cache or memory. The data corresponding to the memory address is then read from the next level cache or memory and written to the replaced cache line. The CPU then reads the data from the cache. If there are still cache lines that have failed verification at this point, the computing device restores the cache line based on its backup cache line (if the cache line has a backup cache line and the verification succeeds).

[0104] The third scenario: If the first cache line verification succeeds, and there exists a cache line with the same tag as the first cache line but whose data verification fails, then this cache line becomes the backup cache line for the first cache line. If the tag of the first cache line matches the memory address in the read instruction, the computing device returns the data from the first cache line and copies the first cache line to its backup cache line to restore the backup cache line. If the tags of multiple cache lines do not match the memory address in the read instruction, the computing device determines a cache line to be replaced based on a replacement strategy. If the replaced cache line has a backup cache line, it is written back to the next level cache or memory. Then, the data corresponding to the memory address is read from the next level cache or memory, and the read data is written to the replaced cache line. The CPU then reads the data from the cache. If there are still cache lines that have failed verification, the computing device restores the cache line based on its backup cache line (if the cache line has a backup cache line and the verification succeeds).

[0105] The fourth scenario: The first cache line verification succeeds, but multiple cache lines fail to verify their tags or data, and the computing device cannot find a backup cache line for the first cache line (i.e., the first cache line is not paired). If the tag of the first cache line matches the memory address in the read instruction, the computing device returns the data from the first cache line. The computing device arbitrarily selects one of the cache lines that failed verification as the backup cache line for the first cache line and copies the first cache line to the selected backup cache line to restore the backup cache line of the first cache line. If the tags of multiple cache lines do not match the memory address in the read instruction, the computing device determines a cache line to be replaced from the cache based on a replacement strategy. If the replaced cache line has a backup cache line, the cache line is written back to the next level cache or memory. Then, the data corresponding to the memory address is read from the next level cache or memory, and the read data is written to the replaced cache line. The CPU then reads the data from the cache. If there are still cache lines that failed verification at this time, the computing device restores the cache line based on its backup cache line (if the cache line has a backup cache line and the verification is successful). If there are multiple unpaired cache lines that originally had backup cache lines, the computing device restores their backup cache lines in the same way as the first cache line, which will not be described in detail here.

[0106] The following is based on Figure 5 For example, the above data reading process will be illustrated. Figure 5 This is a schematic diagram of a data reading method in a data backup method based on a cache line provided in an embodiment of this application, as shown below. Figure 5 As shown, the memory stores the data "Data_x = 3". The memory address corresponding to "Data_x = 3" is mapped to cache line 2 of group 1 (which stores the data "Data_x = 5", i.e., the first cache line) and cache line 4 of group 1 (which stores the data "Data_x = 5", i.e., the backup cache line of the first cache line). The states of cache line 2 of group 1 and cache line 4 of group 1 are both M. In response to a read instruction on the memory address, the computing device performs ECC verification on multiple cache lines. If the ECC verification of cache line 2 of group 1 succeeds, but the ECC verification of cache line 4 of group 1 fails, the computing device copies cache line 4 of group 1 to cache line 2 of group 1 for cache line restoration. When the tag in cache line 2 of group 1 matches the memory address, the computing device returns the data in cache line 2 of group 1. When the tag in cache line 2 of group 1 does not match the memory address, the computing device reads the data corresponding to the memory address from the next level cache or memory.

[0107] In the above method, since a backup cache line of the first cache line is stored in the cache, if the backup cache line of the first cache line fails the verification when reading data from the first cache line in the cache, the data in the first cache line can be read, and the backup cache line can be restored based on the first cache line. Similarly, the first cache line can be restored based on the backup cache line, which improves the reliability of the data.

[0108] The above describes the process of reading data from the first cache line in the cache. In some embodiments, the computing device can also modify the data in the first cache line, that is, write new data into the first cache line. This process includes: responding to a second data write instruction, writing the data in the second data write instruction into the first cache line in the cache; and overwriting the data in the backup cache line of the first cache line with the data in the second data write instruction. Before writing data into the cache, the computing device first verifies the cache line. For cache lines with backup cache lines, ECC is used to verify the tag, status (MESI), and memory mirror mark (MF) of the cache line, and CRC is used to verify the data in the cache line. For cache lines without backup cache lines, ECC is used to verify the cache line. It should be noted that the above description of the verification method is only exemplary. In some embodiments, other methods can be used to verify the cache line, and this application embodiment does not limit this.

[0109] As can be seen from step 302 above, if the computing device determines the second cache line within the group containing the first cache line based on a fixed strategy, then the position of the second cache line is fixed, which also means the position of the backup cache line for the first cache line is fixed. If the computing device determines the second cache line within the group containing the first cache line based on a non-fixed strategy, then the position of the second cache line is not fixed, which also means the position of the backup cache line for the first cache line is not fixed. The data writing process under the fixed strategy and the data writing process under the non-fixed strategy will be described below.

[0110] First, we will introduce the data writing process under the fixed policy. Taking the above verification method as an example, we will illustrate the data writing process under the fixed policy. Under the fixed policy, in response to the second data write instruction, the computing device first verifies multiple cache lines in the target group in the cache according to the above verification method, and writes data based on the verification results. The target group is the group in the cache corresponding to the memory address. The data writing process under the fixed policy includes the following two cases.

[0111] Scenario 1: All cache lines are successfully verified. If the label of the first cache line matches the memory address in the second data write instruction, the computing device writes the data in the second data write instruction to the first cache line, overwriting the data in the backup cache line of the first cache line with the data in the second data write instruction. If the labels of multiple cache lines do not match the memory address in the second data write instruction, the computing device determines a cache line to be replaced from the cache based on the replacement strategy. If the replaced cache line has a backup cache line, the cache line is written back to the next level cache or memory, and then the data in the second data write instruction is written to the determined cache line.

[0112] The second scenario: The first cache line verification succeeds, but the backup cache line verification fails. If the tag of the first cache line matches the memory address in the second data write instruction, the computing device writes the data in the second data write instruction to the first cache line, overwriting the data in the backup cache line with the data in the second data write instruction. If there are still cache lines that have failed verification, the computing device restores the cache line based on its backup cache line (if the cache line has a backup cache line and the verification succeeds). If the tags of multiple cache lines do not match the memory address in the second data write instruction, the computing device determines a cache line to be replaced from the cache based on a replacement strategy. If the replaced cache line has a backup cache line, the cache line is written back to the next level cache or memory. Then, the data in the second data write instruction is written to the determined cache line. If there are still cache lines that have failed verification, the computing device restores the cache line based on its backup cache line (if the cache line has a backup cache line and the verification succeeds). If the backup cache line verification fails for multiple cache lines, the computing device will restore the backup cache lines respectively. The restoration process is the same as the process of restoring the backup cache line of the first cache line based on the first cache line in the second case, and will not be described again.

[0113] It should be noted that if the cache line hit by the memory address in the second data write instruction does not have a backup cache line (that is, the cache line is not in a modified state or MF indicates that it does not have a backup cache line), then the process by which the computing device writes the data in the second data write instruction into the cache is the same as described above. Figure 3 The illustrated embodiment is similar and will not be described again here. The process by which the computing device writes the data in the second data write instruction to the cache line is also the same as described above. Figure 3 The embodiments shown are similar and will not be described again here.

[0114] The data writing process under a non-fixed strategy is described below. Taking the above verification method as an example, the data writing process under a non-fixed strategy will be illustrated. Under a non-fixed strategy, in response to the second data write instruction, the computing device first verifies multiple cache lines in the target group in the cache according to the above verification method, and writes data based on the verification results. The target group is the group in the cache corresponding to the memory address. Among them, for a cache line with a modified state and a backup cache line in the cache (that is, the first cache line mentioned above), the process of the computing device writing data to the first cache line based on the verification results includes the following four cases.

[0115] Scenario 1: All cache lines are successfully verified. If the label of the first cache line matches the memory address in the second data write instruction, the computing device writes the data in the second data write instruction to the first cache line, overwriting the data in the backup cache line of the first cache line with the data in the second data write instruction. If the labels of all cache lines do not match the memory address in the second data write instruction, the computing device determines a cache line to be replaced from the cache based on the replacement strategy. If the replaced cache line has a backup cache line, the cache line is written back to the next level cache or memory, and then the data in the second data write instruction is written to the determined cache line.

[0116] The second scenario: The first cache line verification is successful, but the tag verification of another cache line fails, and the computing device cannot find the backup cache line of the first cache line (that is, the first cache line is not paired). This indicates that the cache line whose tag verification failed is the backup cache line of the first cache line. If the label of the first cache line matches the memory address in the second data write instruction, the computing device writes the data in the second data write instruction to the first cache line, overwriting the data in the backup cache line of the first cache line with the data in the second data write instruction. If there are still cache lines that fail verification at this time, the computing device restores the cache line based on its backup cache line (if the cache line has a backup cache line and the verification is successful). If the labels of multiple cache lines do not match the memory address in the second data write instruction, the computing device determines a cache line to be replaced from the cache based on the replacement strategy. If the replaced cache line has a backup cache line, the cache line is written back to the next level cache or memory, and the data in the second data write instruction is written to the determined cache line. If there are still cache lines that fail verification at this time, the computing device restores the cache line based on its backup cache line (if the cache line has a backup cache line and the verification is successful).

[0117] The third scenario: The first cache line verification succeeds, but there exists a cache line with the same tag as the first cache line that fails data verification. If the tag of the first cache line matches the memory address in the second data write instruction, the computing device writes the data in the second data write instruction to the first cache line, overwriting the data in the backup cache line of the first cache line with the data in the second data write instruction. If there are still cache lines that have failed verification at this point, the computing device restores the cache line based on its backup cache line (if the cache line has a backup cache line and the verification succeeds). If the tags of multiple cache lines do not match the memory address in the second data write instruction, the computing device determines a cache line to be replaced from the cache based on a replacement strategy. If the replaced cache line has a backup cache line, the cache line is written back to the next level cache or memory, and then the data in the second data write instruction is written to the determined cache line. If there are still cache lines that have failed verification at this point, the computing device restores the cache line based on its backup cache line (if the cache line has a backup cache line and the verification succeeds).

[0118] The fourth scenario: The first cache line verification is successful, but the tag or data verification of multiple cache lines fails, and the computing device cannot find the backup cache line of the first cache line (that is, the first cache line is not paired). If the label of the first cache line matches the memory address in the second data write instruction, the computing device writes the data in the second data write instruction to the first cache line. The computing device arbitrarily selects one cache line from multiple cache lines that failed verification as the backup cache line of the first cache line, and overwrites the data in the backup cache line of the first cache line with the data in the second data write instruction. If there are still cache lines that failed verification at this time, the computing device restores the cache line based on its backup cache line (if the cache line has a backup cache line and the verification is successful). If the labels of multiple cache lines do not match the memory address in the second data write instruction, the computing device selects a cache line to be replaced from the cache based on the replacement strategy. If the replaced cache line has a backup cache line, the cache line is written back to the next level cache or memory. The data in the second data write instruction is then written to the selected cache line. If there are still cache lines that failed verification at this time, the computing device restores the cache line based on its backup cache line (if the cache line has a backup cache line and the verification is successful). If there are multiple unpaired cache lines that originally had backup cache lines, the computing device restores their backup cache lines in the same way as the first cache line, which will not be described in detail here.

[0119] It should be noted that if the cache line hit by the memory address in the second data write instruction does not have a backup cache line (that is, the cache line is not in a modified state or MF indicates that it does not have a backup cache line), then the process by which the computing device writes the data in the second data write instruction into the cache is the same as described above. Figure 3 The illustrated embodiment is similar and will not be described again here. The process by which the computing device writes the data in the second data write instruction to the cache line is also the same as described above. Figure 3 The embodiments shown are similar and will not be described again here.

[0120] The following is based on Figure 6 For example, the above data writing process will be illustrated. Figure 6 This is a flowchart illustrating the data writing method in a data backup method based on a cache line provided in an embodiment of this application. Figure 6 As shown, the memory stores the data "Data_x = 3". The memory address corresponding to "Data_x = 3" is mapped to cache line 2 of group 1 (also known as the first cache line, which stores the data "Data_x = 5") and cache line 4 of group 1 (also known as the backup cache line of the first cache line, which stores the data "Data_x = 5"). The states of cache line 2 of group 1 and cache line 4 of group 1 are both M. The process of writing data to the computing device includes: Step ①: In response to the CPU executing the second data write instruction (write) on cache line 2 of group 1, the data in cache line 2 of group 1 is modified from "Data_x = 5" to "Data_x = 6"; Step ②: The data "Data_x = 6" in cache line 2 of group 1 is copied to cache line 4 of group 1 to achieve backup data synchronization.

[0121] Figure 7 This is a schematic diagram of a data backup device based on a cache line provided in an embodiment of this application. The device includes a writing module 701 and a storage module 702.

[0122] The write module 701 is used to respond to a first data write instruction and write the data in the first data write instruction into a first cache line in the cache, such that the state of the first cache line is a modified state, and the modified state indicates that the data in the first cache line is new data, does not exist in other caches and is inconsistent with the data in memory.

[0123] The storage module 702 is used to store a backup cache line of the first cache line in the cache.

[0124] Optionally, the write module 701 is used for:

[0125] In response to a write instruction to a memory address, the data in the write instruction is written to the first cache line.

[0126] Optionally, the write module 701 is used to include:

[0127] In response to a write-back instruction to the previous cache level, the data in the write-back instruction is written to the first cache line.

[0128] Optionally, the cache includes multiple groups, each group including multiple cache lines, and the storage module 702 includes storage units:

[0129] The backup cache line of the first cache line is stored in the group where the first cache line is located.

[0130] Optionally, the storage unit is used for:

[0131] Identify at least one second cache line in the group containing the first cache line; copy the first cache line to the at least one second cache line.

[0132] Optionally, the group to which the first cache line belongs includes 2N cache lines, wherein the i-th cache line corresponds to the (N+i)-th cache line, where N is an integer greater than 1 and i is an integer greater than or equal to 0 and less than N;

[0133] This storage unit is used to: identify the cache line in the group containing the first cache line that corresponds to the first cache line as the second cache line.

[0134] Optionally, the storage unit is used for any of the following:

[0135] Based on the Least Recently Used algorithm, at least one second cache line is determined in the group containing the first cache line; based on the First In First Out algorithm, at least one second cache line is determined in the group containing the first cache line; based on the Random Replacement algorithm, at least one second cache line is determined in the group containing the first cache line.

[0136] Optionally, the storage module 702 is used for:

[0137] If the second cache line is in an exclusive, shared, or invalid state, then the first cache line is copied to the second cache line; if the second cache line is in a modified state, then the data in the second cache line is written back to memory, and the first cache line is copied to the second cache line.

[0138] Optionally, the first cache line further includes a memory mirroring marker, which is used to indicate whether the data at the memory address corresponding to the first cache line has a backup in that memory. The storage module 702 is used for:

[0139] If the memory mirroring mark in the first cache line indicates that the data at the memory address corresponding to the first data write instruction has a backup in memory, then the backup cache line of the first cache line is stored in the cache.

[0140] Optionally, the device further includes a reading module, comprising:

[0141] The verification unit is used to verify the backup cache lines of the first cache line and the second cache line in the cache in response to the read instruction of the memory address. The first cache line is the cache line corresponding to the memory address.

[0142] The return unit is used to return the data in the first cache line if both the first cache line and its backup cache line are successfully verified, and to return the data in the successfully verified cache line if only one of the first cache line and its backup cache line is successfully verified. The cache line that failed to be verified is then restored based on the successfully verified cache line.

[0143] Optionally, the cache line includes a label, status information, a memory mirror marker, and data. The label is used to indicate the memory address corresponding to the cache line. The method further includes:

[0144] The protection module is used to protect the tags, status information and memory image markers in the cache line using error checking and correction (ECC) respectively, and to protect the data in the cache line using cyclic redundancy check (CRC).

[0145] Optionally, the write module 701 is also used for:

[0146] In response to a second data write instruction, the data in the second data write instruction is written to the first cache line in the cache; the data in the backup cache line of the first cache line is overwritten with the data in the second data write instruction.

[0147] Both the write module 701 and the storage module 702 can be implemented in software or in hardware. For example, the implementation of the write module 701 will be described below. Similarly, the implementation of the storage module 702 can be referenced from the implementation of the write module 701.

[0148] As an example of a software functional unit, the write module 701 may include code running on a computing instance. The computing instance may include at least one of a physical host (computing device), a virtual machine, or a container. Further, the aforementioned computing instance may be one or more. For example, the write module 701 may include code running on multiple hosts / virtual machines / containers. It should be noted that the multiple hosts / virtual machines / containers used to run the code may be distributed within the same region or in different regions. Further, the multiple hosts / virtual machines / containers used to run the code may be distributed within the same availability zone (AZ) or in different AZs, each AZ including one or more geographically proximate data centers. Typically, a region may include multiple AZs.

[0149] Similarly, multiple hosts / virtual machines / containers used to run this code can be distributed within the same Virtual Private Cloud (VPC) or across multiple VPCs. Typically, a VPC is set up within a region. Communication between two VPCs within the same region, as well as between VPCs in different regions, requires a communication gateway to be set up within each VPC to enable interconnection between VPCs.

[0150] As an example of a hardware functional unit, the write module 701 may include at least one computing device, such as a server. Alternatively, the write module 701 may also be a device implemented using an application-specific integrated circuit (ASIC) or a programmable logic device (PLD). The PLD may be implemented using a complex programmable logical device (CPLD), a field-programmable gate array (FPGA), generic array logic (GAL), or any combination thereof.

[0151] The multiple computing devices included in the write module 701 can be distributed in the same region or in different regions. Similarly, the multiple computing devices included in the write module 701 can be distributed in the same Availability Zone (AZ) or in different AZs. Likewise, the multiple computing devices included in the write module 701 can be distributed in the same Virtual Private Cloud (VPC) or in multiple VPCs. These multiple computing devices can be any combination of computing devices such as servers, ASICs, PLDs, CPLDs, FPGAs, and GALs.

[0152] It should be noted that in other embodiments, the steps implemented by the above modules can be specified as needed. The above modules can respectively implement different steps in the cache-line-based data backup method to achieve all the functions of the above device. That is, the cache-line-based data backup device provided in the above embodiments is only illustrated by the division of the above functional modules when implementing the cache-line-based data backup method. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. Furthermore, the device provided in the above embodiments and the corresponding method embodiments belong to the same concept, and their specific implementation process is detailed in the method embodiments, which will not be repeated here.

[0153] This application provides a processor for executing a cache-line-based data backup method as provided in the foregoing method embodiments or any possible implementation thereof.

[0154] This application provides a storage medium for storing at least one piece of program code for executing a cache-line-based data backup method as provided in the foregoing method embodiments or any possible implementation thereof.

[0155] It should be noted that all information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, stored data, displayed data, etc.), and signals involved in this application have been authorized by the user or fully authorized by all parties, and the collection, use, and processing of related data must comply with the relevant laws, regulations, and standards of the relevant countries and regions. For example, the data involved in this application was obtained with full authorization.

[0156] Those skilled in the art will recognize that the method steps and units described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the steps and components of each embodiment have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0157] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be found in the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0158] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the couplings or direct couplings or communication connections shown or discussed may be indirect couplings or communication connections through some interfaces, apparatuses, or units, or they may be electrical, mechanical, or other forms of connection.

[0159] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of the embodiments of this application, depending on actual needs.

[0160] Furthermore, the units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or software.

[0161] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computing device (which may be a personal computer, server, or computing device, etc.) to execute all or part of the steps of the methods in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0162] In this application, the terms "first," "second," etc., are used to distinguish identical or similar items that have substantially the same function and purpose. It should be understood that there is no logical or temporal dependency between "first," "second," and "nth," nor does it limit the quantity or execution order. It should also be understood that although the following description uses the terms "first," "second," etc., to describe various elements, these elements should not be limited by the terms. These terms are merely used to distinguish one element from another. For example, without departing from the scope of various examples, a first data write instruction can be referred to as a second data write instruction, and similarly, a second data write instruction can be referred to as a first data write instruction. Both the first and second data write instructions can be write instructions, and in some cases, they can be separate and different data write instructions.

[0163] In this application, the term "at least one" means one or more, and the term "multiple" means two or more; for example, multiple buffer lines refer to two or more buffer lines. The terms "system" and "network" are often used interchangeably in this document.

[0164] It should also be understood that the term "if" can be interpreted as meaning "when" or "upon" or "in response to determination" or "in response to detection." Similarly, depending on the context, the phrases "if determination..." or "if detection [the stated condition or event]" can be interpreted as meaning "when determination..." or "in response to determination..." or "when detection [the stated condition or event]" or "in response to detection [the stated condition or event]."

[0165] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0166] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product. This computer program product includes one or more computer program instructions. When these computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device.

[0167] The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer program instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired or wireless means. The computer-readable storage medium can be any available medium that a computer can access, or a data storage device such as a server or data center that integrates one or more available media. The available medium can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., digital video discs (DVDs), or semiconductor media (e.g., solid-state drives)).

[0168] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0169] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit it. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A data backup method based on a cache line, characterized in that, The method includes: In response to a first data write instruction, the data in the first data write instruction is written to a first cache line in the cache, such that the state of the first cache line is modified. The modified state indicates that the data in the first cache line is new data, does not exist in other caches, and is inconsistent with the data in memory. The cache refers to the cache corresponding to the CPU core of the central processing unit that initiated the first data write instruction in the computing device. The other caches refer to the L1 cache and L2 cache exclusively occupied by other CPU cores in the computing device besides the CPU core. The cache line of the first cache line is stored in the cache.

2. The method according to claim 1, characterized in that, The step of responding to a first data write instruction by writing the data in the first data write instruction into the first cache line in the cache includes: In response to a write instruction to a memory address, the data in the write instruction is written to the first cache line.

3. The method according to claim 1, characterized in that, The step of responding to a first data write instruction by writing the data in the first data write instruction into the first cache line in the cache includes: In response to a write-back instruction to the previous cache level, the data in the write-back instruction is written to the first cache line.

4. The method according to any one of claims 1 to 3, characterized in that, The cache includes multiple groups, each group including multiple cache lines, and stores backup cache lines of the first cache line in the cache, including: Store backup cache lines of the first cache line in the group containing the first cache line.

5. The method according to claim 4, characterized in that, The step of storing a backup cache line of the first cache line in the group containing the first cache line includes: Determine at least one second cache line in the group containing the first cache line; The first cache line is copied to the at least one second cache line.

6. The method according to claim 5, characterized in that, The group containing the first cache line includes 2N cache lines, where the i-th cache line corresponds to the (N+i)-th cache line, where N is an integer greater than 1 and i is an integer greater than or equal to 0 and less than N; Determining at least one second cache line in the group containing the first cache line includes: The cache line in the group containing the first cache line that corresponds to the first cache line is identified as the second cache line.

7. The method according to claim 5, characterized in that, Determining at least one second cache line in the group containing the first cache line includes any of the following: Based on the Least Recently Used algorithm, at least one second cache line is determined in the group containing the first cache line; Based on the first-in-first-out algorithm, at least one second cache line is determined in the group containing the first cache line; Based on a random replacement algorithm, at least one second cache line is determined in the group containing the first cache line.

8. The method according to claim 5, characterized in that, The step of copying the first cache line to the at least one second cache line includes: If the state of the second cache line is exclusive, shared, or invalid, then the first cache line is copied to the second cache line. The exclusive state indicates that the data in the second cache line does not exist in other caches and is consistent with the data in the memory. The shared state indicates that the data in the second cache line also exists in other caches and is consistent with the data in the memory. The invalid state indicates that the data in the second cache line is invalid. If the second cache line is in a modified state, the data in the second cache line is written back to the memory, and the first cache line is copied to the second cache line.

9. The method according to any one of claims 1 to 3, characterized in that, The first cache line further includes a memory mirroring marker, which indicates whether the data at the memory address corresponding to the first cache line is backed up in memory. The step of storing a backup cache line of the first cache line in the cache includes: If the memory mirroring marker in the first cache line indicates that the data at the memory address corresponding to the first data write instruction has a backup in the memory, then the backup cache line of the first cache line is stored in the cache.

10. The method according to claim 1, characterized in that, The method further includes: In response to a read instruction on a memory address, the first cache line and the backup cache line of the first cache line in the cache are verified respectively, wherein the first cache line is the cache line corresponding to the memory address; If both the first cache line and the backup cache line of the first cache line are successfully verified, the data in the first cache line is returned. If only one of the first cache line and its backup cache line is successfully verified, the data from the successfully verified cache line is returned, and the cache line that failed to be verified is restored based on the successfully verified cache line.

11. The method according to claim 1, characterized in that, The cache line includes a label, status information, a memory mirror marker, and data. The label is used to indicate the memory address corresponding to the cache line. The method further includes: Error checking and correction (ECC) are used to protect the tags, status information and memory image markers in the cache line, respectively, and cyclic redundancy check (CRC) is used to protect the data in the cache line.

12. The method according to claim 1, characterized in that, The method further includes: In response to a second data write instruction, the data in the second data write instruction is written into the first cache line in the cache; The data in the second data write instruction overwrites the data in the backup cache line of the first cache line.

13. A data backup device based on a cache line, characterized in that, The device includes: The write module is used to respond to a first data write instruction by writing the data in the first data write instruction into a first cache line in the cache, such that the state of the first cache line is modified. The modified state indicates that the data in the first cache line is new data, does not exist in other caches, and is inconsistent with the data in memory. The cache refers to the cache corresponding to the CPU core of the central processing unit that initiated the first data write instruction in the computing device. The other caches refer to the L1 cache and L2 cache exclusively occupied by other CPU cores in the computing device besides the CPU core. A storage module is used to store a backup cache line of the first cache line in the cache.

14. A processor, characterized in that, The processor is used to execute the data backup method based on cache lines as described in any one of claims 1 to 12.

15. A computing device, characterized in that, The computing device includes a processor and a memory, the memory storing program code, and the processor executing the program code to cause the computing device to perform the cache-line-based data backup method as described in any one of claims 1 to 12.

16. A storage medium, characterized in that, The storage medium is used to store at least one piece of program code, which is used to execute the data backup method based on cache lines as described in any one of claims 1 to 12.

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