Testing device and method for field programmable gate array system

Abstract

The invention relates to the technical field of field-programmable gate array systems, and discloses a test device and method for a field-programmable gate array system, the test device comprises a built-in self-test state machine and a plurality of built-in self-test circuits, and the built-in self-test circuits are configured on corresponding function modules; the built-in self-test state machine is used for receiving bit stream data; the built-in self-test state machine is also used for determining a first test route based on the bit stream data, and is used for controlling the built-in self-test circuit to generate a test excitation signal; the built-in self-test state machine is also used for controlling the built-in self-test circuit to send a test excitation signal to the corresponding function module to be tested; the built-in self-test state machine is further used for receiving the test result output by the at least one to-be-tested function module and determining whether the corresponding to-be-tested function module is normal or not based on the test result. According to the invention, only the function module required by the specific application which needs to be completed by the field programmable gate array system can be tested, so that the test time is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of field programmable gate array systems, and in particular to a testing device and method for a field programmable gate array system. Background Art

[0002] Field Programmable Gate Array (FPGA) is a programmable integrated circuit chip that can flexibly change its internal logic functions and circuit connections through programming to adapt to different application requirements. It is widely used in communications, automotive electronics, industrial control, aerospace, data centers and other fields. During the production and configuration process of the FPGA system, the FPGA system needs to be tested to ensure the reliability and stability of the functional modules in the FPGA system.

[0003] At present, the test method of FPGA system is generally to complete the configuration of FPGA system and generate bit stream data through hardware description language code, then transmit the bit stream data to FPGA system, and then use automatic test equipment to program and test all components in the order of bit stream data transmission to determine whether each component is normal. If the area of ​​FPGA system is large, it will take a long time to complete the test of all logic resources of FPGA system, and the cost is high. Summary of the invention

[0004] In view of this, the present invention provides a testing device and method for a field programmable gate array system to solve the problems of long testing time and high testing cost of the FPGA system.

[0005] In a first aspect, the present invention provides a testing device for a field programmable gate array system, the testing device comprising a built-in self-test state machine and a plurality of built-in self-test circuits, the field programmable gate array system comprising a plurality of functional modules, the plurality of functional modules corresponding to the plurality of built-in self-test circuits one-to-one, the built-in self-test circuits being configured on the corresponding functional modules; the built-in self-test state machine is used to receive bit stream data, the bit stream data being used to indicate a connection relationship between at least one functional module required for a target application and at least one functional module; the built-in self-test state machine is also used to determine a first test route based on the bit stream data, and to control the built-in self-test circuit to generate a test excitation signal, the first test route being used to indicate a test sequence of at least one functional module to be tested, the functional module to be tested being a functional module required for the target application; the built-in self-test state machine is also used to control the built-in self-test circuit to send a test excitation signal to the corresponding functional module to be tested based on the first test route; the built-in self-test state machine is also used to receive a test result output by at least one functional module to be tested collected by the built-in self-test circuit, and to determine whether the corresponding functional module to be tested is normal based on the test result.

[0006] The test device for the FPGA system provided in this embodiment can test only the functional modules required for the specific application that the FPGA system needs to complete through the cooperation of the built-in self-test state machine and the built-in self-test circuit, thereby reducing the test time and saving the test cost. Moreover, through the cooperation of the built-in self-test state machine and the built-in self-test circuit, the test mode can be dynamically adjusted to test whether the corresponding functional modules of the FPGA system are normal in different application scenarios, thereby improving the flexibility of the test.

[0007] In an optional embodiment, the built-in self-test state machine is also used to re-determine a second test route based on the bit stream data to update the first test route when the functional module to be tested is abnormal, and the second test route is used to represent the test order of the normal functional module to be tested and the first functional module, and the first functional module is a functional module of the same type as the abnormal functional module to be tested.

[0008] In this embodiment, when the functional module to be tested is abnormal, the built-in self-test state machine can reselect the test route to skip the functional module with the abnormality, and use a functional module with the same function (the first functional module) to replace the faulty functional module, thereby improving the yield of the FPGA system.

[0009] In an optional implementation, the functional module includes a wiring switch box, and the built-in self-test state machine adjusts the first test route to the second test route through the wiring switch box.

[0010] In an optional implementation, the test stimulus signal is used to trigger the corresponding functional module to be tested to perform fixed-point multiplication processing.

[0011] In an optional implementation, the built-in self-test state machine is used to determine that the corresponding to-be-tested functional module is normal when the test result is the same as the preset result.

[0012] In an optional implementation, the built-in self-test state machine is further configured to determine a clock signal generated by an internal oscillator as a reference clock.

[0013] In this embodiment, the internal oscillator set in the FPGA system itself is used as a reference clock and a BIST flag, which can simplify the test device and save costs.

[0014] In an optional implementation, the plurality of functional modules include at least one of a digital signal processor, a programmable logic group, and a memory.

[0015] In a second aspect, the present invention provides a testing method for a field programmable gate array system, the testing method being applied to a built-in self-test state machine in a testing device of the first aspect or any corresponding embodiment thereof, the testing method comprising: receiving bit stream data, the bit stream data being used to indicate at least one functional module required for a target application and a connection relationship between at least one functional module; determining a first test route based on the bit stream data, the first test route being used to indicate a test order of at least one functional module to be tested, the functional module to be tested being a functional module required for the target application; controlling a built-in self-test circuit to generate a test excitation signal; based on the first test route, controlling the built-in self-test circuit to send a test excitation signal to a corresponding functional module to be tested; receiving a test result output by at least one functional module to be tested collected by the built-in self-test circuit; and determining whether the corresponding functional module to be tested is normal based on the test result.

[0016] The test method of the FPGA system provided in the present embodiment determines a first test route based on the bit stream data after receiving the bit stream data, and controls the built-in self-test circuit to generate a test stimulus signal, and then controls the built-in self-test circuit to send the test stimulus signal to the corresponding functional module to be tested based on the first test route, and after receiving the test result output by at least one functional module to be tested collected by the built-in self-test circuit, determines whether the corresponding functional module to be tested is normal based on the test result, and can test only the functional modules required for the specific application that the FPGA system needs to complete, thereby reducing the test time and saving the test cost.

[0017] In an optional embodiment, the testing method also includes: when the functional module to be tested is abnormal, re-determining a second test route based on the bit stream data to update the first test route, the second test route is used to represent the test order of the normal functional module to be tested and the first functional module, and the first functional module is a functional module of the same type as the abnormal functional module to be tested.

[0018] In an optional implementation, determining whether the corresponding functional module to be tested is normal based on the test result includes: when the test result is the same as the preset result, determining that the corresponding functional module to be tested is normal. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the related technologies, the drawings required for use in the specific embodiments or the related technical descriptions will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0020] Figure 1is a schematic diagram of a testing device for an FPGA system according to an embodiment of the present invention;

[0021] Figure 2 is a schematic diagram of a first test route according to an embodiment of the present invention;

[0022] Figure 3 is a schematic diagram of a second test route according to an embodiment of the present invention;

[0023] Figure 4 is a flow chart of a method for testing an FPGA system according to an embodiment of the present invention;

[0024] Figure 5 It is a flowchart of another FPGA system testing method according to an embodiment of the present invention.

[0025] Figure numerals: 100, field programmable gate array system; 110, intellectual property core; 120, block random access memory; 130, programmable logic block; 140, wiring switch box; 150, digital signal processor; 160, input / output module; 210, built-in self-test state machine; 220, built-in self-test circuit. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0027] After receiving the bitstream data, the automatic test equipment of the FPGA system transmits the bitstream data to the FPGA system. The bitstream flows in a preset order to program and test all components of the FPGA system. Although this test method has a high coverage rate, since each compiled bit is tested, if the FPGA system area is large, it may lead to a long test time and high cost.

[0028] In view of this, the present invention provides a testing device for a field programmable gate array system, which, through a built-in self-test state machine, can only test the functional modules required for a specific application that the field programmable gate array system needs to complete, thereby reducing testing time and saving testing costs.

[0029] In conjunction with the accompanying drawings, the structure of the test device for the field programmable gate array (FPGA) system provided by the present invention is first described in detail below.

[0030] like Figure 1As shown, the test device of the FPGA system includes a built-in self-test (BIST) state machine (Finite State Machine, FSM) 210 and multiple built-in self-test (BIST) circuits 220. Specifically, the field programmable gate array (FPGA) system 100 includes multiple functional modules, and the multiple functional modules correspond to the multiple built-in self-test circuits 220 one by one, and the built-in self-test circuits 220 are configured on the corresponding functional modules.

[0031] Exemplarily, the functional module may be a digital signal processor (DSP), a configurable logic cell (CLC), a memory (Mem), or a switch box (SWH).

[0032] in, Figure 1 Taking multiple functional modules including an intellectual property (IP) core 110, a block random-access memory (BRAM) 120, a configurable logic block (CLB) 130, a wiring switch box (SWH) 140, a digital signal processor (DSP) 150 and an input / output (IO) module 160 as an example, but not limited to this.

[0033] Specifically, the IP core 110 is a pre-designed, reusable functional module. For example, the IP core 110 can be a processor core, a communication protocol core, etc. The block random access memory 120 is a large-capacity storage module that can be used to store data, program code, etc. The programmable logic block 130 can implement various logic functions through programming, such as combinational logic (AND, OR, NOT, etc.) and sequential logic (flip-flops, counters, etc.). The wiring switch box 140 can flexibly change the connection relationship between various functional modules according to the configuration information in the bit stream data to implement different circuit functions. The digital signal processor 150 is used to process data signals, such as filtering, transformation, etc. The input / output module 160 is an interface for the FPGA system to interact with external devices. Through the IO module 160, the FPGA system can receive external data and send processed data to external devices.

[0034] It should be understood that the FPGA system 100 can be divided into multiple regions, each of which can include multiple functional modules, and multiple regions can be independently tested and configured. Figure 1Two regions (Region_1 and Region_2) are taken as an example, but are not limited thereto.

[0035] Specifically, the BIST FSM 210 is used to receive bit stream data, determine a first test route based on the bit stream data, and control the BIST circuit 220 to generate a test stimulus signal. The BIST FSM 210 is also used to control the BIST circuit 220 to send a test stimulus signal to the functional module to be tested based on the first test route, and to control the BIST circuit 220 to collect a test result output by at least one functional module to be tested, and receive the test result. The BIST FSM 210 is also used to determine whether the corresponding functional module to be tested is normal based on the test result.

[0036] The bitstream data is used to indicate at least one functional module and the connection relationship of at least one functional module required by the target application. Specifically, the bitstream data can be generated by an FPGA programming tool and can include configuration information of multiple functional modules, so that the FPGA system can implement the corresponding functions (i.e., the target application) according to the design requirements. When the bitstream data is loaded into the FPGA system, the logical functions and connection relationships within the FPGA system are determined.

[0037] The first test route is used to represent the test order of at least one functional module to be tested, where the functional module to be tested is a functional module required by the target application. For example, if the target application needs Figure 1 In this case, the functional modules to be tested can be all the functional modules in Region_1 and Region_2, and the first test route can be Figure 2 The path is shown by the dashed line.

[0038] Specifically, FPGA has a wide variety of application scenarios, and different applications correspond to different bitstream data, which will cause the functional modules inside the FPGA system to present different functions and connection relationships. BIST FSM210 can dynamically adjust the test route according to the bitstream data of different applications currently loaded.

[0039] The test excitation signal is used to instruct the functional module to be tested to perform a specific operation in order to verify whether the function of the functional module to be tested is normal. For example, the test excitation signal can be used to trigger the corresponding functional module to be tested (such as DSP) to perform fixed-point multiplication processing. The test excitation signal can be a high-level signal or a low-level signal. The built-in self-test state machine 210 can control the built-in self-test circuit 220 to generate the test excitation signal according to the pre-defined test strategy and the characteristics of the functional module to be tested. After generating the test excitation signal, the built-in self-test state machine 210 controls the BIST circuit 220 to transmit the test excitation signal to the corresponding functional module to be tested in the order set by the first test route.

[0040] For example, a register transfer level (RTL) design netlist can be input into a software synthesizer, and the software synthesizer performs logic synthesis operations based on the RTL design netlist to obtain bitstream data. The RTL design netlist can be written by a designer using a hardware description language (such as Verilog or VHDL), and the RTL design netlist mainly includes registers, combinational logic units (such as logic circuits composed of logic gates such as AND gates, OR gates, and NOT gates), and the connection relationship between various modules.

[0041] Specifically, the software synthesizer can convert the relatively abstract register transfer level logic into a specific gate-level circuit representation composed of various basic logic elements based on the logic description in the RTL design netlist and some pre-set constraints (such as clock frequency requirements, resource usage restrictions, etc.), and then go through a series of back-end processing to generate bitstream data that can be loaded into the FPGA system.

[0042] When the test device of the FPGA system provided by the present embodiment tests the functional modules of the FPGA system, after receiving the bit stream data, the BISTFSM 210 first enters the initialization state, in which the BIST FSM 210 initializes some registers, counters and other resources related to the BIST circuit 220, such as clearing the counters, setting the initial test mode flags, etc., to prepare for the subsequent formal testing. At the same time, the functional modules to be tested (such as CLB, DSP or BRAM, etc.) inside the FPGA system can also be reset to ensure that the functional modules are in a known initial state, so as to facilitate the subsequent accurate judgment of the test results.

[0043] Then, the BIST FSM 210 enters a test stimulus generation state, in which the BIST FSM 210 can determine a first test route based on the bit stream data, and control the BIST circuit 220 to generate a corresponding test stimulus signal according to a predefined test strategy and the functions of each functional module to be tested, and control the BIST circuit 220 to send a test stimulus signal to the corresponding functional module to be tested based on the first test route.

[0044] After the test stimulus signal is sent to the corresponding functional modules to be tested in sequence, the BIST FSM 210 enters a test execution state, in which each functional module to be tested receives the test stimulus signal and starts to execute a corresponding operation, and the BIST FSM 210 waits for each functional module to be tested to output a test result.

[0045] After each functional module to be tested performs the corresponding operation, the BIST FSM 210 enters the result detection state. In this state, the BIST FSM 210 controls the BIST circuit 220 to collect the test results output by each functional module to be tested. After receiving the test results, the BIST FSM 210 determines whether the corresponding functional module to be tested is normal based on the test results.

[0046] The test device for the FPGA system provided in this embodiment can test only the functional modules required for the specific application to be completed by the FPGA system through the cooperation between the BIST FSM 210 and the BIST circuit 220, thereby reducing the test time and saving the test cost. Moreover, through the cooperation between the BIST FSM 210 and the BIST circuit 220, the test mode can be dynamically adjusted to test whether the corresponding functional modules of the FPGA system are normal in different application scenarios, thereby improving the flexibility of the test.

[0047] In one example, the BIST FSM 210 is used to determine that the corresponding function module to be tested is normal when the test result is the same as the preset result. That is, if the test result is the same as the preset result, the corresponding function module to be tested is normal; if the test result is different from the preset result, the corresponding function module to be tested is abnormal.

[0048] When an abnormality occurs in the functional module to be tested, the BIST FSM 210 may enter a fault handling state, in which the BIST FSM 210 may store information such as the location of the faulty functional module, the fault type (such as a logic function error, a timing error, or other types) in a specific register, and may also issue a fault prompt signal to inform the designer that an abnormality occurs in the functional module to be tested.

[0049] Further, in some embodiments, the BIST FSM 210 is also used to re-determine a second test route based on the bit stream data when the function module to be tested is abnormal, and the second test route is used to represent the test order of the normal function module to be tested and the first function module, and the first function module is a function module of the same type as the abnormal function module to be tested. That is, when the function module to be tested is abnormal, the BIST FSM 210 can re-select the test route to skip the function module with the abnormality, and use a function module with the same function (the first function module) to replace the faulty function module, thereby improving the yield of the FPGA system.

[0050] Exemplarily, the functional module includes a wiring switch box (SWH), and the BIST FSM 210 adjusts the first test route to the second test route through the wiring switch box. That is, when the functional module to be tested is abnormal, the first test route can be changed to the second test route by reprogramming the SWH to bypass the abnormal functional module.

[0051] In some embodiments, the second test route may also be the first test route that bypasses the abnormal functional module. For example, if it is determined that Figure 1 There is an abnormality in the BRAM on Region_2. At this time, the second test route can be as follows Figure 3 The path is shown by the dashed line.

[0052] In some optional embodiments, the built-in self-test state machine 210 is also used to determine the clock signal generated by the internal oscillator (Internal Oscillator, OSC) as the reference clock (Closk, CLK), and the internal oscillator can also be output as a BIST flag. The BIST flag is used to characterize the state of the BIST FSM 210, such as the initialization state, test stimulus generation state, test execution state, result inspection state or fault handling state.

[0053] In this embodiment, the internal oscillator set in the FPGA system itself is used as a reference clock and a BIST flag, which can simplify the test device and save costs.

[0054] In this embodiment, a test method for an FPGA system is also provided, which can be used for the above-mentioned built-in self-test state machine 210. Figure 4 FIG. 1 is a flow chart of a method for testing an FPGA system according to an embodiment of the present invention. Figure 4 As shown, the method comprises the following steps:

[0055] Step S401, receiving bit stream data.

[0056] The bitstream data is used to indicate at least one functional module required by the target application and a connection relationship between at least one functional module.

[0057] Specifically, the bitstream data may be generated by an FPGA programming tool, and may include configuration information of multiple functional modules, so that the FPGA system can implement corresponding functions (ie, target applications) according to design requirements.

[0058] Step S402: determine a first test route based on the bit stream data.

[0059] The first test route is used to represent the test order of at least one functional module to be tested, and the functional module to be tested is a functional module required by the target application.

[0060] Exemplarily, the first test route may be Figure 2 The path is shown by the dashed line.

[0061] Step S403, controlling the built-in self-test circuit to generate a test stimulus signal.

[0062] Specifically, the test stimulus signal is used to instruct the functional module to perform a specific operation to verify whether the function of the functional module to be tested is normal. For example, the test stimulus signal can be used to trigger the corresponding functional module to be tested (such as DSP) to perform fixed-point multiplication processing.

[0063] Step S404: Based on the first test route, control the built-in self-test circuit to send a test stimulus signal to the corresponding functional module to be tested.

[0064] Step S405 , receiving a test result output by at least one functional module to be tested collected by a built-in self-test circuit.

[0065] Step S406: determine whether the corresponding function module to be tested is normal based on the test result.

[0066] Exemplarily, when the test result is the same as the preset result, it is determined that the corresponding function module to be tested is normal; when the test result is different from the preset result, it is determined that the corresponding function module to be tested is abnormal.

[0067] In some optional implementations, whether the corresponding functional module to be tested is normal can also be determined by whether the test result is detected. Specifically, if the built-in self-test circuit does not collect the test result, the functional module to be tested corresponding to the built-in self-test circuit is abnormal; if the built-in self-test circuit collects the test result, the functional module to be tested corresponding to the built-in self-test circuit is normal.

[0068] The test method of the FPGA system provided in the present embodiment determines a first test route based on the bit stream data after receiving the bit stream data, and controls the built-in self-test circuit to generate a test stimulus signal, and then controls the built-in self-test circuit to send the test stimulus signal to the corresponding functional module to be tested based on the first test route, and after receiving the test result output by at least one functional module to be tested collected by the built-in self-test circuit, determines whether the corresponding functional module to be tested is normal based on the test result, and can test only the functional modules required for the specific application that the FPGA system needs to complete, thereby reducing the test time and saving the test cost.

[0069] Optionally, when the functional module to be tested is abnormal, the built-in self-test state machine 210 re-determines the second test route based on the bit stream data to update the first test route, and the second test route is used to represent the test order of the normal functional module to be tested and the first functional module, and the first functional module is a functional module of the same type as the abnormal functional module to be tested.

[0070] Specifically, Figure 5 As shown, after the built-in self-test state machine 210 executes steps S401 to S406, when there is an abnormality in the functional module to be tested, step S501 is executed, and the built-in self-test state machine 210 re-determines the second test route based on the bit stream data to update the first test route (the second test route is the new first test route), and then returns to step S403 until all the functional modules to be tested have no abnormalities; when there is no abnormality in the functional module to be tested, step S502 is executed to end the test.

[0071] The built-in self-test state machine 210 in this embodiment is presented in the form of a functional unit, which refers to an application specific integrated circuit (ASIC), a processor and memory that executes one or more software or fixed programs, and / or other devices that can provide the above functions.

[0072] Exemplary, the built-in self-test state machine may include: one or more processors, memory, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components are connected to each other using different buses for communication, and can be installed on a common mainboard or installed in other ways as required. The processor can process instructions executed in the computer device, including instructions stored in or on the memory to display the graphical information of the GUI on an external input / output device (such as, a display device coupled to the interface).

[0073] In some optional embodiments, if desired, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides part of the necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system).

[0074] The processor may be a central processing unit, a network processor or a combination thereof. The processor may further include a hardware chip. The hardware chip may be a dedicated integrated circuit, a programmable logic device or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic or any combination thereof.

[0075] The memory stores instructions executable by at least one processor, so that the at least one processor executes the method shown in the above embodiment.

[0076] The memory may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created according to the use of the computer device, etc. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory may optionally include a memory remotely arranged relative to the processor, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0077] The memory may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk or solid state drive; the memory may also include a combination of the above types of memory.

[0078] The built-in self-test state machine also includes a communication interface, which is used for the built-in self-test state machine to communicate with other devices or a communication network.

[0079] It should be understood that the various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, a plurality of steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0080] In the description of this specification, the description with reference to the terms "this embodiment", "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, unless they are contradictory.

[0081] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0082] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the present invention.

Claims

1. A test device for a field programmable gate array system, characterized in that: The test device includes a built-in self-test state machine and a plurality of built-in self-test circuits, the field programmable gate array system includes a plurality of functional modules, the plurality of functional modules correspond to the plurality of built-in self-test circuits one by one, and the built-in self-test circuits are configured on the corresponding functional modules; The built-in self-test state machine is used to receive bit stream data, and the bit stream data is used to indicate at least one of the functional modules required by the target application and a connection relationship between at least one of the functional modules; The built-in self-test state machine is further used to determine a first test route based on the bit stream data, and to control the built-in self-test circuit to generate a test stimulus signal, wherein the first test route is used to indicate a test order of at least one functional module to be tested, and the functional module to be tested is the functional module required by the target application; The built-in self-test state machine is further used to control the built-in self-test circuit to send the test stimulus signal to the corresponding functional module to be tested based on the first test route; The built-in self-test state machine is further used to receive a test result output by at least one of the functional modules to be tested and collected by the built-in self-test circuit, and to determine whether the corresponding functional module to be tested is normal based on the test result.

2. The testing device according to claim 1, characterized in that: The built-in self-test state machine is also used to re-determine a second test route based on the bit stream data to update the first test route when the functional module to be tested is abnormal, and the second test route is used to represent the test order of the normal functional module to be tested and the first functional module, and the first functional module is a functional module of the same type as the abnormal functional module to be tested.

3. The testing device according to claim 2, characterized in that: The functional module includes a wiring switch box, and the built-in self-test state machine adjusts the first test route to the second test route through the wiring switch box.

4. The testing device according to any one of claims 1 to 3, characterized in that: The test excitation signal is used to trigger the corresponding function module to be tested to perform fixed-point multiplication processing.

5. The testing device according to any one of claims 1 to 3, characterized in that: The built-in self-test state machine is used to determine that the corresponding to-be-tested functional module is normal when the test result is the same as the preset result.

6. The testing device according to any one of claims 1 to 3, characterized in that: The built-in self-test state machine is further configured to determine a clock signal generated by an internal oscillator as a reference clock.

7. The testing device according to any one of claims 1 to 3, characterized in that: The plurality of functional modules include at least one of a digital signal processor, a programmable logic group and a memory.

8. A method for testing a field programmable gate array system, characterized in that: The test method is applied to a built-in self-test state machine in a test device according to any one of claims 1 to 7, and the test method comprises: Receiving bit stream data, wherein the bit stream data is used to indicate at least one functional module required by a target application and a connection relationship between at least one of the functional modules; Determine a first test route based on the bit stream data, where the first test route is used to represent a test order of at least one functional module to be tested, where the functional module to be tested is the functional module required by the target application; Control the built-in self-test circuit to generate a test stimulus signal; Based on the first test route, controlling the built-in self-test circuit to send the test stimulus signal to the corresponding functional module to be tested; Receiving a test result output by at least one of the functional modules to be tested collected by the built-in self-test circuit; Based on the test result, it is determined whether the corresponding functional module to be tested is normal.

9. The testing method according to claim 8, characterized in that: The test method also includes: When the functional module to be tested is abnormal, a second test route is re-determined based on the bit stream data to update the first test route, wherein the second test route is used to represent the test sequence of the normal functional module to be tested and the first functional module, and the first functional module is a functional module of the same type as the abnormal functional module to be tested.

10. The testing method according to claim 8, characterized in that: The determining whether the corresponding function module to be tested is normal based on the test result includes: When the test result is the same as the preset result, it is determined that the corresponding function module to be tested is normal.

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