SFP and RJ45 data interaction device based on FPGA

Abstract

According to the FPGA-based SFP and RJ45 data interaction device, an FPGA chip is connected to an SFP interface through a multi-path optical port and is connected to an RJ45 interface through a multi-path PHY chip on an FMC daughter board, and the FPGA chip and the RJ45 interface are used for data interaction; the FMC daughter board is connected with the FPGA development board through a multi-pin IO expansion port, and the FPGA chip processes the received data; data flow control, data protocol conversion and data synchronization control are realized through logic design in the FPGA chip, so that data received by the SFP interface and data received by the RJ45 interface can be normally transmitted to a transmitting end of an opposite side, and data interconnection between the two interfaces is met. The equipment connected with the two interfaces can carry out real-time communication at a gigabit rate through the Ethernet; and the working state of the system can be indicated by controlling the LED indicating lamp. The data interaction device can realize data interaction between the SFP interface and the RJ45 interface in a hardware programmable mode, and has remarkable advantages in the aspects of practicability, real-time performance and flexibility.

Description

Technical Field

[0001] The invention relates to the field of high-speed communication, and in particular to an SFP and RJ45 data interaction device based on FPGA. Background Art

[0002] Nowadays, Ethernet is widely used, and there are a lot of Ethernet data communications in various production and life scenarios. Most Ethernet devices use RJ45 interfaces through twisted pair cables for data exchange; and with the development of optical communication, more and more systems use SFP interfaces through optical fibers for Ethernet data transmission. For the two different interfaces, they use different data transmission protocols, different data formats, and different numbers of interface signals, making it impossible for the two to communicate directly.

[0003] At present, in order to solve this problem, the method of setting both RJ45 interface and SFP interface on the communication equipment is usually used to achieve the purpose of communicating with different interface devices. However, this method increases the number of IO interfaces, increases the complexity and redundancy of the system, and the increase in the types and number of interfaces greatly increases the cost and difficulty of system construction, and also increases the size and occupied area of ​​the equipment.

[0004] Secondly, it is not guaranteed that all communication devices have these two interfaces. Especially for Ethernet communication devices produced earlier, most of them do not have SFP interfaces, which makes it impossible for them to perform normal Ethernet communication with SFP interface devices.

[0005] In addition, although the communication equipment with two interfaces can perform Ethernet communication through the twisted pair RJ45 interface and the optical fiber SFP interface, there is a situation where one communication interface is not effectively connected during Ethernet communication. The idle communication interface may cause some unexpected faults, thereby affecting the operation of the entire communication system.

[0006] Therefore, there is an urgent need for a hardware device and logic design for data interaction between SFP and RJ45 that is flexible and easy to use. Summary of the invention

[0007] The invention provides an SFP and RJ45 data interaction device based on FPGA to solve the problems of different interfaces unable to communicate normally and interface redundancy in the prior art.

[0008] To achieve the above object, the present invention adopts the following technical solutions:

[0009] An SFP and RJ45 data interaction device based on FPGA includes an FMC daughter board with an RJ45 interface, and an FPGA development board with an FPGA chip and an SFP interface; wherein the FPGA chip is connected to the SFP interface through a multi-channel optical port, and is connected to the RJ45 interface through a multi-channel physical layer chip PHY on the FMC daughter board for data interaction; the FMC daughter board is connected to the FPGA development board through a multi-pin IO expansion port, and the FPGA chip processes the received data;

[0010] Among them, data flow control, data protocol conversion and data synchronization control are realized through the logic design inside the FPGA chip; wherein, through the data flow control, data from different interfaces can reach another interface in an orderly manner for data transmission; through the data protocol conversion, the data to be transmitted in a format different from that of the interface to be transmitted is converted into a data format supported by the interface for interface matching; through the data synchronization control, data from different interfaces can be synchronized for effective transmission.

[0011] Furthermore, it also includes an LED indication module for indicating whether the logic circuit is working normally and for fault indication.

[0012] Furthermore, the RJ45 interface and the SFP interface are both 4-way interfaces, and each interface performs data exchange in a one-to-one correspondence.

[0013] Furthermore, the data flow control specifically includes: controlling the flow direction of the internal data flow of the FPGA development board so that the received data from the SFP interface on the FPGA development board is transmitted to the transmitting end of the corresponding RJ45 interface on the FPGA development board; and transmitting the received data from the RJ45 interface on the FMC daughter board to the transmitting end of the corresponding SFP interface on the FPGA development board.

[0014] Furthermore, the logic design includes RGMII and GMII modules, and GMII and GTX modules; the RGMII and GMII modules perform conversion between RGMII format data and GMII format data through data single and double edge sampling, and transmit the processed data signals to respective locations for the next step of circuit processing; the GMII and GTX modules perform conversion between GMII format data and GTX format data through high-speed parallel-to-serial / serial-to-parallel conversion and 4B / 5B encoding and decoding, and transmit the processed data signals to respective locations for the next step of circuit processing.

[0015] Furthermore, the logic design includes a clock module, and the clock module is used to generate a system reference clock.

[0016] Furthermore, the logic design includes a FIFO module; the FIFO module performs clock synchronization of two interfaces through read and write operations of a foreign clock, thereby ensuring synchronization of data to be transmitted and transmission clocks at the two interfaces.

[0017] Furthermore, the data protocol conversion specifically includes: converting the RGMII format data from the RJ45 interface into GMII format data by double-edge sampling to single-edge sampling, and then converting the obtained GMII format data into GTX format data by parallel-to-serial conversion and 8B / 10B encoding, so that the SFP interface on the FPGA development board can transmit the data; converting the GTX format data from the SFP interface into GMII format data by serial-to-parallel conversion and 10B / 8B decoding, and then converting the obtained GMII format data into RGMII format data by single-edge sampling to double-edge sampling, so that the RJ45 interface on the FPGA development board can transmit the data.

[0018] Furthermore, the data synchronization control specifically includes: synchronizing asynchronous data from the SFP interface and the RJ45 interface respectively. For the data to be sent by the RJ45 interface on the FMC daughter board, the data source is the SFP receiving interface on the FPGA development board, so the SFP synchronization clock is used to send data to achieve data synchronization of the RJ45 interface; for the data to be sent by the SFP interface of the FPGA development board, the data source is the RJ45 receiving interface on the FMC daughter board, the SFP uses a channel binding clock, uses a FIFO read-write module, uses the RJ45 interface synchronization clock to read in, and the SFP channel binding clock synchronization clock to write out data for data clock synchronization, and uses the SFP channel binding clock to send and write data at the SFP sending interface of the FPGA development board to achieve data synchronization of the SFP interface.

[0019] A data interaction method using the FPGA-based SFP and RJ45 data interaction device comprises: utilizing the internal logic design of an FPGA chip to realize data flow control, transferring data from an SFP interface to a corresponding RJ45 interface, and transferring data from an RJ45 interface to a corresponding SFP interface; utilizing the internal logic design of an FPGA chip to realize data protocol conversion, converting data to be transmitted in different formats from an application interface to a data format supported by the interface for interface matching; and utilizing the internal logic design of an FPGA chip to realize data synchronization control, synchronizing data from different interface sources for effective transmission.

[0020] In some embodiments, the present invention provides an FPGA-based SFP and RJ45 data interaction hardware device, including an FMC daughterboard including a 4-way PHY chip, a 4-way SFP interface, and an FPGA development board. The FMC daughterboard is connected to the FPGA development board through the 40-pin IO expansion port on the FPGA development board. There are 4-way RJ45 interfaces at the other end of the PHY chip for connecting an Ethernet device with an RJ45 interface; the SFP interface is provided by the FPGA development board and is used to connect an Ethernet device with an SFP interface. On this hardware basis, the SFP interface device and the RJ45 interface device are hardware-connected through the FPGA development board.

[0021] Optionally, the FPGA development board model is KINTEX-7AX7325B, which is used to provide a 40-pin IO expansion port, a 4-way SFP interface and 4 LED indicator lights.

[0022] Optionally, the PHY chip model is FL9031, which is used to provide 4-way PHY chips and 4-way RJ45 interfaces.

[0023] In some embodiments, the FPGA-based SFP and RJ45 data interaction logic design includes a data flow control module, a data protocol conversion module, a clock synchronization module, and an LED indication module.

[0024] The data flow control module is used to control the flow direction of the internal data flow of the FPGA development board, so that the received data from the SFP interface on the FPGA development board is transmitted to the transmitting end of the corresponding RJ45 interface on the FPGA development board; and the received data from the RJ45 interface on the FMC daughter board is transmitted to the transmitting end of the corresponding SFP interface on the FPGA development board.

[0025] The data protocol conversion module is used to perform protocol conversion on data from different interface types. The logical process is: convert the RGMII format data from the RJ45 interface into GMII format data through double-edge sampling to single-edge sampling, and then convert the obtained GMII format data into GTX format data through parallel-to-serial conversion and 8B / 10B encoding, so that the SFP interface on the FPGA development board can transmit the data; convert the GTX format data from the SFP interface into GMII format data through serial-to-parallel conversion and 10B / 8B decoding, and then convert the obtained GMII format data into RGMII format data through single-edge sampling to double-edge sampling, so that the RJ45 interface on the FPGA development board can transmit the data.

[0026] The clock synchronization module is used to synchronize asynchronous data from the SFP interface and the RJ45 interface respectively. For the data to be sent from the RJ45 interface on the FMC daughter board, the data source is the SFP receiving interface on the FPGA development board, so the SFP synchronization clock is used to send data to achieve data synchronization of the RJ45 interface; for the data to be sent from the SFP interface of the FPGA development board, the data source is the RJ45 receiving interface on the FMC daughter board. Since the SFP uses a channel binding clock, a FIFO read-write module is used to read in the RJ45 interface synchronization clock and write out the data using the SFP channel binding clock synchronization clock to perform data clock synchronization. The SFP channel binding clock is used to send and write data at the SFP sending interface of the FPGA development board to achieve data synchronization of the SFP interface.

[0027] The LED indicator module is used to indicate whether the current pair of RJ45 interfaces and SFP interfaces on the FPGA development board are working properly. If the current pair of RJ45 interfaces and SFP interfaces can normally perform Gigabit Ethernet communication, and the data flow control module, data protocol conversion module, and clock synchronization module can operate normally, the current LED lights up.

[0028] In some embodiments, a method for using an FPGA-based SFP and RJ45 data interaction device is also provided, which includes the following steps:

[0029] Step 1, connect the communication device with RJ45 interface to the RJ45 interface on the FMC daughter board through a twisted pair cable; Step 2, connect the communication device with SFP interface to the corresponding SFP interface on the FPGA development board through optical fiber; Step 3, the device receives signals from the two interfaces, transmits and sends to each other, and indicates whether the system is working normally through the corresponding LED.

[0030] The present invention has the following beneficial effects:

[0031] The present invention provides an SFP and RJ45 data interaction device based on FPGA, which enables the data received by the SFP interface and the data received by the RJ45 interface to be normally transmitted to the other sending end, so as to meet the data interconnection between the two interfaces, and enables the devices connected by the two interfaces to perform real-time communication at a gigabit rate through Ethernet. The device can realize the data interaction between the SFP interface and the RJ45 interface in a hardware programmable manner, and has advantages in practicality, real-time performance, and flexibility.

[0032] The present invention realizes the data interaction and conversion function between the RJ45 interface and the SFP interface, so that communication devices with two different interfaces can be interconnected through the present invention, thereby reducing device costs, improving system flexibility, and increasing the available devices in the Ethernet, so that more devices can be interconnected.

[0033] Compared with the prior art, the significant advantage of the present invention is that it can enable any two data with SFP interfaces or RJ45 interfaces to communicate over Gigabit Ethernet. It can not only connect older Ethernet devices with only RJ45 interfaces to the fiber optic network, but also transmit the information transmitted in the optical fiber through the RJ45 interface in the Ethernet RGMII format, so that more devices can be used in fiber optic networks and Ethernet.

[0034] The advantages of the embodiments of the present invention also lie in:

[0035] 1. The present invention includes 4 pairs of SFP interfaces and RJ45 interfaces, which can simultaneously perform 4-way data conversion and transmission, and support normal data exchange operation of four groups of different interface devices;

[0036] 2. The present invention provides FPGA processing logic, which ensures the normal transmission of data flow, correct conversion of data format and correct clock synchronization. Due to its programmability and high efficiency of data processing, the flexibility and reliability of the entire system are increased.

[0037] 3. The present invention greatly saves IO interface resources of the communication device and saves the data input and output paths in the PCB board of the communication device.

[0038] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0040] Figure 1 This is a hardware structure diagram of an FPGA-based SFP and RJ45 data interaction device of the present invention;

[0041] Figure 2 This is a schematic diagram of the internal logic interface of an FPGA-based SFP and RJ45 data interaction device of the present invention;

[0042] Figure 3 A schematic diagram of the structure of an FPGA-based SFP and RJ45 data interaction device provided in Embodiment 1 of the present invention;

[0043] Figure 4A flowchart of the steps provided in Embodiment 1 of the present invention;

[0044] Figure 5 A schematic diagram of the structure of an FPGA-based SFP and RJ45 data interaction device provided in Embodiment 2 of the present invention;

[0045] Figure 6 This is a flowchart of the steps provided in Embodiment 2 of the present invention. DETAILED DESCRIPTION

[0046] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0047] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0048] The invention provides an SFP and RJ45 data interaction device based on FPGA, comprising an FMC daughter board with an RJ45 interface, an FPGA development board with an FPGA chip and an SFP interface; wherein the FPGA chip is connected to the SFP interface through a multi-channel optical port, and is connected to the RJ45 interface through a multi-channel PHY chip on the FMC daughter board for data interaction; the FMC daughter board is connected to the FPGA development board through a multi-pin IO expansion port, and the FPGA chip processes the received data; wherein data flow control, data protocol conversion and data synchronization control are realized through the logic design inside the FPGA chip; wherein the data flow control enables data from different interfaces to reach another interface in an orderly manner for data transmission; the data protocol conversion enables data to be transmitted in different formats between the application and the interface to be transmitted to be converted into a data format supported by the interface for interface matching; and the data synchronization control enables data from different interfaces to be synchronized for effective transmission.

[0049] The FPGA-based SFP and RJ45 data interaction device of the present invention realizes data communication between the SFP optical interface and the RJ45 electrical interface, effectively solves the compatibility problem between two different interface devices, and improves the flexibility and reliability of data communication. Based on the hardware design, data flow control, protocol conversion and clock synchronization are realized through the internal logic design of FPGA to ensure accurate data transmission. Compared with the prior art, the data interaction device of the present invention can enable any two devices with SFP or RJ45 interfaces to communicate over Gigabit Ethernet, support multi-channel data conversion and transmission, save IO interface resources, and improve system flexibility and reliability.

[0050] In a preferred embodiment, the data flow control specifically includes: controlling the flow direction of the internal data flow of the FPGA development board so that the received data from the SFP interface on the FPGA development board is transmitted to the transmitting end of the corresponding RJ45 interface on the FPGA development board; and transmitting the received data from the RJ45 interface on the FMC daughter board to the transmitting end of the corresponding SFP interface on the FPGA development board.

[0051] In a preferred embodiment, the logic design includes RGMII and GMII modules, and GMII and GTX modules; the RGMII and GMII modules perform conversion between RGMII format data and GMII format data through data single and double edge sampling, and transmit the processed data signals to respective locations for the next step of circuit processing; the GMII and GTX modules perform conversion between GMII format data and GTX format data through high-speed parallel-serial / serial-parallel conversion and 4B / 5B encoding and decoding, and transmit the processed data signals to respective locations for the next step of circuit processing. The logic design also includes a clock module and a FIFO module. The clock module is used to generate a system reference clock. The FIFO module performs clock synchronization of the two interfaces through the read and write operations of the foreign clock, ensuring the synchronization of the data to be transmitted and the transmission clock at the two interfaces.

[0052] In a preferred embodiment, the data protocol conversion specifically includes: converting the RGMII format data from the RJ45 interface into GMII format data through double-edge sampling to single-edge sampling, and then converting the obtained GMII format data into GTX format data through parallel-to-serial conversion and 8B / 10B encoding, so that the SFP interface on the FPGA development board can transmit the data; converting the GTX format data from the SFP interface into GMII format data through serial-to-parallel conversion and 10B / 8B decoding, and then converting the obtained GMII format data into RGMII format data through single-edge sampling to double-edge sampling, so that the RJ45 interface on the FPGA development board can transmit the data. This data protocol conversion scheme can efficiently and accurately convert the data formats of different interfaces, ensuring the compatibility and correct transmission of data between the SFP and RJ45 interfaces.

[0053] In a preferred embodiment, the data synchronization control specifically includes: synchronizing the asynchronous data from the SFP interface and the RJ45 interface respectively, for the data to be sent from the RJ45 interface on the FMC daughter board, the data source is the SFP receiving interface on the FPGA development board, so the SFP synchronization clock is used to send data to achieve data synchronization of the RJ45 interface; for the data to be sent from the SFP interface of the FPGA development board, the data source is the RJ45 receiving interface on the FMC daughter board, the SFP uses a channel binding clock, uses a FIFO read-write module, uses the RJ45 interface synchronization clock to read in, and the SFP channel binding clock synchronization clock writes out data for data clock synchronization, and uses the SFP channel binding clock to send and write data at the SFP sending interface of the FPGA development board to achieve data synchronization of the SFP interface. The data synchronization control scheme can accurately process asynchronous data from different interfaces, ensure the timing consistency and synchronization of data during high-speed transmission, and thus improve the reliability of communication.

[0054] In the embodiment of the present invention, the FPGA chip realizes logical functions such as data flow control from different sources, conversion between GTX protocol and RGMII protocol, and clock synchronization management through hardware description language, so that the data received by the SFP interface and the data received by the RJ45 interface can be normally transmitted to the other sending end to meet the data interconnection between the two interfaces, so that the devices connected by the two interfaces can communicate in real time at a gigabit rate through Ethernet; and the system working status can also be indicated by controlling the LED indicator. The device proposed by the present invention can realize data interaction between the SFP interface and the RJ45 interface in a hardware programmable manner, and has advantages in practicality, real-time performance, and flexibility.

[0055] The specific embodiments of the present invention are further described below.

[0056] An SFP and RJ45 data interaction device based on FPGA includes an FPGA chip, 4-way SFP interfaces and 4-way RJ45 interfaces, wherein the 4-way SFP interfaces correspond to the 4-way RJ45 interfaces one by one. The FPGA chip is connected to the four-way Gigabit Ethernet interface RJ45 through a PHY chip, and is connected to the 4-way SFP interface through an optical port.

[0057] Figure 1 The hardware structure diagram of the SFP and RJ45 data interaction device based on FPGA of the present invention is as follows: Figure 1 As shown, an embodiment of the present invention proposes an interface conversion device for 4 pairs of SFP interfaces and RJ45 interfaces, including an FPGA development board and an FMC daughter board. The logic circuit arranged on the FPGA development board is used to realize data flow control and protocol conversion; the RJ45 interface on the FMC daughter board is used to connect an Ethernet device with an RJ45 interface. When the present invention is working, the information sent by the connected Ethernet device with an RJ45 interface will be output from the SFP interface on the corresponding FPGA development board; the SFP interface on the FPGA development board is used to connect an Ethernet device with an SFP interface. When the present invention is working, the information sent by the connected Ethernet device with an SFP interface will be output from the SFP interface on the corresponding FPGA development board.

[0058] In this way, the present invention realizes the data interaction and conversion function between the RJ45 interface and the SFP interface, so that communication devices with two different interfaces can be interconnected through the present invention, reducing equipment costs, improving system flexibility, and increasing the available devices in the Ethernet, allowing more devices to be interconnected.

[0059] Optionally, each pair of RJ46 interfaces and SFP interfaces corresponds to an LED indicator on the FPGA development board. When the two ends of the system are communicating with Gigabit Ethernet normally and the FPGA development board can work normally, the LED indicator lights up. Therefore, people skilled in the art can judge whether the device is working normally according to the state of the LED indicator, which is convenient for the work of the technicians.

[0060] Figure 2 The figure is a schematic diagram of the internal logic interface of an FPGA-based SFP and RJ45 data interaction device of the present invention. Figure 2 As shown, the logic design of the present invention can obtain the sending data of different interfaces of the opposite end through two data protocol conversions, internal interface links, and FIFO buffering, thereby realizing the control of the overall data flow, protocol conversion, and clock synchronization by the FPGA development board.

[0061] Optionally, the RGMII and GMII modules are used to receive the RGMII signal output from the RJ45 interface, and transform the RGMII signal from double-edge sampling to single-edge sampling to obtain the GMII signal for subsequent processing; at the same time, the module can also transform the GMII data from single-edge sampling to double-edge sampling to obtain RGMII data, which is the data to be transmitted by the RJ45 interface.

[0062] It is understandable that the FPGA development board cannot directly process the RGMII signal with double-edge sampling, so the conversion between RGMII format data and GMII format data is necessary so that the FPGA development board can further process the data.

[0063] Optionally, the GMII and GTX modules are used to convert the data format of the converted GMII data to obtain the GTX data to be transmitted by the SFP interface. Specifically, the GMII data is first converted from serial to parallel to obtain a high-speed serial data stream, and then the high-speed data stream is encoded with 4B / 5B data to prevent the occurrence of long continuous 0 or long continuous 1, so that the data can be easily transmitted using optical fiber. At the same time, the module will also perform 4B / 5B data decoding and serial-to-parallel conversion on the data received from the SFP interface to obtain GMII data for subsequent processing.

[0064] Optionally, the FIFO module is used to synchronously process the two asynchronous data from the RJ45 interface and the SFP interface. The converted GMII data to be transmitted from the RJ45 interface is synchronized with the RJ45 interface clock. Through the FIFO read and write operations and the reset logic, the GMII data to be transmitted that is synchronized with the SFP interface reference clock is obtained, so that the system works normally in the synchronous timing.

[0065] In addition, for the converted GMII data to be transmitted from the SFP interface, the RGMII and GMII modules directly use the SFP reference clock for conversion and transmission, thereby achieving clock synchronization.

[0066] A method for using an SFP and RJ45 data interaction device based on FPGA, comprising the following steps:

[0067] Step 1, connect the communication device with RJ45 interface to the RJ45 interface on the FMC daughter board through a twisted pair cable; Step 2, connect the communication device with SFP interface to the corresponding SFP interface on the FPGA development board through optical fiber; Step 3, the device receives signals from the two interfaces, transmits and sends to each other, and indicates whether the system is working normally through the corresponding LED.

[0068] Embodiment 1

[0069] Figure 3 A schematic diagram of the structure of an FPGA-based SFP and RJ45 data interaction device provided in Embodiment 1 of the present invention is shown in FIG. Figure 3 As shown, the Ethernet device with an RJ45 interface is connected to the FPGA development board with an FMC daughter board through a twisted pair cable, and the corresponding SFP interface on the FPGA development board is connected to other devices.

[0070] Figure 4 The flowchart of the steps provided in the first embodiment of the present invention is as follows. Specifically, the information sent by the Ethernet device with an RJ45 interface is transmitted to the RJ45 interface on the FMC daughter board through a twisted pair cable, that is, the RGMII data to be transmitted on the RJ45 interface, and the data format to be transmitted is converted into GTX data through the logic circuit arranged on the FPGA development board, and transferred to the corresponding SFP interface on the FPGA development board, becoming the data to be transmitted on the SFP interface.

[0071] The SFP interface on the FPGA development board sends the data to be transmitted in the format of high-speed serial data and exchanges data with the device connected to the SFP interface.

[0072] The FPGA-based SFP and RJ45 data interaction device provided in the embodiment of the present invention includes an Ethernet device with an RJ45 interface as an RJ45 interface source, an FMC daughter board providing a PHY chip, and an FPGA development board as a means of data processing and providing an SFP interface connected to other devices. The FPGA-based SFP and RJ45 data interaction device provided in the embodiment of the present invention achieves the effect of interface conversion through data format conversion and data flow control, does not require complex circuit design and has programmability, can reduce overall costs, improve system flexibility, and is convenient for large-scale use.

[0073] Embodiment 2

[0074] Figure 5 A schematic diagram of the structure of an FPGA-based SFP and RJ45 data interaction device provided in Embodiment 2 of the present invention is shown in FIG. Figure 4 As shown, the Ethernet device with an SFP interface is connected to the SFP interface on the FPGA development board through a twisted pair cable, and the corresponding RJ45 interface on the FMC daughter board is connected to other devices.

[0075] Figure 6The flowchart of the steps provided in the second embodiment of the present invention. Specifically, the information sent by the Ethernet device with an SFP interface is transmitted to the SFP interface on the FPGA development board through an optical fiber, that is, the GTX data to be transmitted on the SFP interface, and the data format to be transmitted is converted into RGMII data through the logic circuit arranged on the FPGA development board, and transferred to the corresponding RJ45 interface on the FMC daughter board, becoming the data to be transmitted on the RJ45 interface.

[0076] The RJ45 interface on the FMC daughter board sends the data to be transmitted in the format of multi-channel parallel data, and exchanges data with the device connected to the RJ45 interface.

[0077] The FPGA-based SFP and RJ45 data interaction device provided in an embodiment of the present invention includes an Ethernet device with an SFP interface as an SFP interface information source, an FPGA development board as a means of data processing and providing an SFP interface connected to other devices, and an FMC daughter board providing a PHY chip and an RJ45 interface for transmitting the data to be transmitted obtained by the converted SFP interface.

[0078] The four male pairs of RJ45 and SFP interfaces involved in the present invention can simultaneously provide connection communications for four pairs of communication devices of different interface types.

[0079] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0080] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. An SFP and RJ45 data interaction device based on FPGA, characterized in that: It includes an FMC daughter board with an RJ45 interface, and an FPGA development board with an FPGA chip and an SFP interface; wherein the FPGA chip is connected to the SFP interface through a multi-channel optical port, and is connected to the RJ45 interface through a multi-channel physical layer chip PHY on the FMC daughter board for data interaction; the FMC daughter board is connected to the FPGA development board through a multi-pin IO expansion port, and the FPGA chip processes the data received; Among them, data flow control, data protocol conversion and data synchronization control are realized through the logic design inside the FPGA chip; wherein, through the data flow control, data from different interfaces can reach another interface in an orderly manner for data transmission; through the data protocol conversion, the data to be transmitted in a format different from that of the interface to be transmitted is converted into a data format supported by the interface for interface matching; through the data synchronization control, data from different interfaces can be synchronized for effective transmission.

2. The FPGA-based SFP and RJ45 data interaction device according to claim 1, characterized in that: It also includes an LED indication module for indicating whether the logic circuit is working normally and for fault indication.

3. The FPGA-based SFP and RJ45 data interaction device according to claim 1 or 2, characterized in that: The RJ45 interface and the SFP interface are both 4-way interfaces, and each interface performs data exchange in a one-to-one correspondence.

4. The FPGA-based SFP and RJ45 data interaction device according to any one of claims 1 to 3, characterized in that: The data flow control specifically includes: controlling the flow direction of the internal data flow of the FPGA development board so that the received data from the SFP interface on the FPGA development board is transmitted to the transmitting end of the corresponding RJ45 interface on the FPGA development board; and transmitting the received data from the RJ45 interface on the FMC daughter board to the transmitting end of the corresponding SFP interface on the FPGA development board.

5. The FPGA-based SFP and RJ45 data interaction device according to any one of claims 1 to 4, characterized in that: The logic design includes RGMII and GMII modules, and GMII and GTX modules; the RGMII and GMII modules perform conversion between RGMII format data and GMII format data through data single and double edge sampling, and transmit the processed data signals to respective positions for the next step of circuit processing; the GMII and GTX modules perform conversion between GMII format data and GTX format data through high-speed parallel-serial / serial-parallel conversion and 4B / 5B encoding and decoding, and transmit the processed data signals to respective positions for the next step of circuit processing.

6. The FPGA-based SFP and RJ45 data interaction device according to any one of claims 1 to 5, characterized in that: The logic design includes a clock module, and the clock module is used to generate a system reference clock.

7. The FPGA-based SFP and RJ45 data interaction device according to any one of claims 1 to 6, characterized in that: The logic design includes a FIFO module; the FIFO module performs clock synchronization of two interfaces through read and write operations of a foreign clock, thereby ensuring synchronization of data to be transmitted and transmission clocks at the two interfaces.

8. The FPGA-based SFP and RJ45 data interaction device according to claim 5, characterized in that: The data protocol conversion specifically includes: converting the RGMII format data from the RJ45 interface into GMII format data by double-edge sampling to single-edge sampling, and then converting the obtained GMII format data into GTX format data by parallel-to-serial conversion and 8B / 10B encoding, so that the SFP interface on the FPGA development board can transmit the data; converting the GTX format data from the SFP interface into GMII format data by serial-to-parallel conversion and 10B / 8B decoding, and then converting the obtained GMII format data into RGMII format data by single-edge sampling to double-edge sampling, so that the RJ45 interface on the FPGA development board can transmit the data.

9. The FPGA-based SFP and RJ45 data interaction device according to claim 5, characterized in that: The data synchronization control specifically includes: synchronizing asynchronous data from the SFP interface and the RJ45 interface respectively. For the data to be sent from the RJ45 interface on the FMC daughter board, the data source is the SFP receiving interface on the FPGA development board, so the SFP synchronization clock is used to send data to achieve data synchronization of the RJ45 interface; for the data to be sent from the SFP interface of the FPGA development board, the data source is the RJ45 receiving interface on the FMC daughter board, the SFP uses a channel binding clock, uses a FIFO read-write module, uses the RJ45 interface synchronization clock to read in, and the SFP channel binding clock synchronization clock to write out data for data clock synchronization, and uses the SFP channel binding clock to send and write data at the SFP sending interface of the FPGA development board to achieve data synchronization of the SFP interface.

10. A data interaction method using the FPGA-based SFP and RJ45 data interaction device according to any one of claims 1 to 9, characterized in that: include: The internal logic design of the FPGA chip is used to implement data flow control, and the data from the SFP interface is transferred to the corresponding RJ45 interface, and the data from the RJ45 interface is transferred to the corresponding SFP interface; the internal logic design of the FPGA chip is used to implement data protocol conversion, so that the data to be transmitted in different formats from the application and the interface to be transmitted is converted into a data format supported by the interface for interface matching; and the internal logic design of the FPGA chip is used to implement data synchronization control, so that data from different interface sources are synchronized for effective transmission.

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