Cache security defense method and system based on RISC-V

Abstract

The invention discloses a cache security defense method and system based on RI SC-V. The method comprises the steps that when an RI SC-V processor executes a target data loading instruction of a target request component, a target physical address in the target data loading instruction is extracted; encrypting the target physical address through a physical address encryption module to obtain a target encrypted address; and accessing a security data cache in the security cache module according to the target encrypted address, and if a target cache line corresponding to the target encrypted address exists in the security data cache, outputting the target cache line to the target request component, so that the target request component executes a target data operation on the target cache line. According to the method and the device, the channel attack on the cache side can be effectively resisted, the performance of the cache in the RI SC-V processor is improved, the information security guarantee level is improved, the potential information leakage risk is reduced, and the method and the device can be widely applied to the technical field of data security.

Description

Technical Field

[0001] The present application relates to the field of data security technology, and in particular to a cache security defense method and system based on RISC-V. Background Art

[0002] At present, the design goal of RISC-V is to provide a flexible, scalable, high-performance, and low-power processor architecture that can be used in various fields, such as embedded systems, servers, and high-performance computing. Microarchitectural side-channel attacks are a way of using the microarchitectural state of the processor to carry out side-channel attacks. Among them, cache-based side-channel attacks are a way of microarchitectural side-channel attacks, which use the widely existing cache structure in the processor to obtain sensitive information in the target system. In this attack, the attacker infers the execution of the target program by observing the target program's access pattern and access time to the cache, thereby obtaining sensitive information, which poses a high threat to system security and also poses a threat to user privacy security.

[0003] In summary, the technical problems existing in the relevant technologies need to be improved. Summary of the invention

[0004] The embodiments of the present application aim to solve at least one of the technical problems in the related art to a certain extent. To this end, the main purpose of the embodiments of the present application is to propose a cache security defense method and system based on RISC-V, which can effectively resist cache side channel attacks, improve the performance of the cache in the RISC-V processor, and at the same time improve the level of information security protection and reduce the potential risk of information leakage.

[0005] To achieve the above-mentioned purpose, an embodiment of the present application proposes a RISC-V-based cache security defense method, which is applied to a security cache module in a RISC-V processor, wherein the functional modules in the security cache module include a physical address encryption module, and the method includes the following steps:

[0006] When the RISC-V processor executes a target data load instruction of a target request component, extracting a target physical address in the target data load instruction;

[0007] Encrypting the target physical address by the physical address encryption module to obtain a target encrypted address;

[0008] The secure data cache in the secure cache module is accessed according to the target encrypted address, and if a target cache line corresponding to the target encrypted address exists in the secure data cache, the target cache line is output to the target request component so that the target request component performs a target data operation on the target cache line.

[0009] In some embodiments, the method further comprises:

[0010] Accessing the secure data cache in the secure cache module according to the target encrypted address, and if the target cache line corresponding to the target encrypted address does not exist in the secure data cache, extracting the target memory line from the memory module in the RISC-V processor according to the target physical address;

[0011] The target memory line is stored in the secure data cache in the secure cache module.

[0012] In some embodiments, the functional module in the security cache module further includes an encrypted address decryption module, and the method further includes:

[0013] Accessing the secure data cache in the secure cache module according to the target encrypted address, if the target cache line corresponding to the target encrypted address does not exist in the secure data cache, and a dirty line exists in the secure data cache, extracting the dirty line encrypted address corresponding to the dirty line;

[0014] Decrypting the dirty row encrypted address by the encrypted address decryption module to obtain a dirty row physical address;

[0015] Writing the dirty line into a memory module in the RISC-V processor according to the dirty line physical address.

[0016] In some embodiments, the functional module in the security cache module further includes a record table buffer module, the security cache module is provided with a reordering buffer, and the method further includes:

[0017] When the RISC-V processor executes the target data loading instruction of the target request component, if the target data loading instruction modifies the target cache line to obtain a target modified cache line, the target data loading instruction and the target modified cache line are stored in a record table in the record table buffer module;

[0018] Monitoring the instruction state of the target data load instruction through the reorder buffer, and if the instruction state of the target data load instruction is a non-retired state, updating the data state of the target modified cache line to a non-secure state to prohibit non-target data load instructions from modifying the target modified cache line;

[0019] If the instruction state of the target data load instruction is a retired state, the data state of the target modified cache line is updated to a secure state, and the target modified cache line is stored in the secure data cache in the secure cache module.

[0020] In some embodiments, the method further comprises:

[0021] When the space occupied by the data in the record table is greater than or equal to the record storage space of the record table, a first-in-first-out replacement algorithm is used to replace the target data entry in the record table.

[0022] In some embodiments, the method further comprises:

[0023] Get the attack test program;

[0024] The attack test program is stored in the memory module of the RISC-V processor, and the attack test program is executed by the RISC-V processor to obtain a simulation test result;

[0025] The defense level of the security cache module is evaluated according to the simulation test results.

[0026] In some embodiments, encrypting the target physical address by the physical address encryption module to obtain the target encrypted address includes:

[0027] The target physical address is encrypted by the physical address encryption module using a low-latency block cipher to obtain the target encrypted address.

[0028] To achieve the above purpose, another aspect of the embodiment of the present application proposes a cache security defense system based on RISC-V, which is applied to a security cache module in a RISC-V processor. The functional modules in the security cache module include a physical address encryption module. The system includes the following modules:

[0029] A physical address extraction module, configured to extract a target physical address in a target data loading instruction when the RISC-V processor executes a target data loading instruction of a target request component;

[0030] A physical address encryption module, used to encrypt the target physical address through the physical address encryption module to obtain a target encrypted address;

[0031] An encrypted address access module is used to access the secure data cache in the secure cache module according to the target encrypted address. If there is a target cache line corresponding to the target encrypted address in the secure data cache, the target cache line is output to the target request component so that the target request component performs a target data operation on the target cache line.

[0032] To achieve the above-mentioned purpose, another aspect of an embodiment of the present application provides an electronic device, the electronic device comprising a memory and a processor, the memory storing a computer program, and the processor implementing the above-mentioned method when executing the computer program.

[0033] To achieve the above objective, another aspect of an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method described above is implemented.

[0034] The embodiments of the present application include at least the following beneficial effects: the present application provides a cache security defense method and system based on RI SC-V, which is applied to a secure cache module in a RI SC-V processor, and the functional modules in the secure cache module include a physical address encryption module. When the RI SC-V processor executes a target data loading instruction of a target request component, the scheme extracts the target physical address in the target data loading instruction; encrypts the target physical address through the physical address encryption module to obtain a target encrypted address; accesses the secure data cache in the secure cache module according to the target encrypted address, and if a target cache line corresponding to the target encrypted address exists in the secure data cache, the target cache line is output to the target request component, so that the target request component performs a target data operation on the target cache line. The embodiment of the present application encrypts the target physical address carried in the target data loading instruction through the physical address encryption module in the security cache module to obtain the target encrypted address, and the avalanche effect of the encryption will cause the rows with spatial correlation in the physical address space to be scattered in the entire space of the encrypted address, and the encrypted cache address is invisible to the attacker, which can protect the system from malicious attacks and achieve effective defense against cache side-channel attacks. That is, the embodiment of the present application can effectively complete the random mapping of memory rows to cache locations by operating the cache in the encrypted address space instead of the physical address space, and by randomizing the fixed mapping relationship between memory rows and cache rows, it is impossible for the attacker to determine the cache set of the target address, thereby protecting the system from malicious attacks and achieving effective defense against cache side-channel attacks, thereby improving the performance of the cache in the RISC-V processor, while improving the level of information security protection and reducing potential information leakage risks. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 It is a flowchart of the steps of the cache security defense method based on RISC-V provided in an embodiment of the present application;

[0036] Figure 2 It is a schematic diagram of a secure cache design architecture for a RISC-V processor provided in an embodiment of the present application;

[0037] Figure 3 It is a schematic diagram of the record table structure of the record table buffer module provided in an embodiment of the present application;

[0038] Figure 4 It is a schematic diagram of the compilation process of the attack simulation program provided in the embodiment of the present application;

[0039] Figure 5 It is a flow chart of a cache security defense method based on RISC-V provided in an embodiment of the present application;

[0040] Figure 6 It is a structural diagram of a cache security defense system based on RISC-V provided in an embodiment of the present application;

[0041] Figure 7 It is a schematic diagram of the hardware structure of the electronic device provided in the embodiment of the present application. DETAILED DESCRIPTION

[0042] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below in conjunction with the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the embodiments of the present application. They are only examples of systems and methods consistent with some aspects of the embodiments of the present application as detailed in the attached claims.

[0043] It is understood that the terms "first", "second", etc. used in this application can be used to describe various concepts in this article, but unless otherwise specified, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another concept. For example, without departing from the scope of the embodiment of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the words "if" and "if" as used herein can be interpreted as "at the time of" or "when" or "in response to determination".

[0044] The terms "at least one", "multiple", "each", "any", etc. used in this application, at least one includes one, two or more, multiple includes two or more, each refers to each of the corresponding multiple, and any refers to any one of the multiple.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0046] At present, in the field of chip instruction set architecture, with the promotion of open source code and the continuous development of the RISC-V ecosystem, RISC-V has received widespread attention. RISC-V is an open source instruction set architecture (ISA) based on the reduced instruction set (RISC). The design goal of RISC-V is to provide a flexible, scalable, high-performance, and low-power processor architecture that can be used in various fields, such as embedded systems, servers, and high-performance computing. However, RISC-V may be subject to microarchitectural side channel attacks. Microarchitectural side channel attacks are a way of conducting side channel attacks using the microarchitectural state of the processor, which breaks the isolation means provided by the operating system and other software layers, and seriously threatens the information security of users. Unlike other traditional side channel attacks, microarchitectural side channel attacks do not require the attacker to have physical contact with the attacked object, nor do they require complex analysis equipment. The attack can be completed by simply being able to execute code in the same environment as the attacked object. Among them, cache-based side channel attack is a microarchitecture side channel attack method that uses the cache structure widely present in the processor to obtain sensitive information in the target system. In this attack, the attacker infers the execution of the target program by observing the access pattern and access time of the target program to the cache, thereby obtaining sensitive information. As an example, the processor cache has three characteristics: first, there is a cache structure in most processors; second, the cache can have a system-wide fine-grained data access and instruction execution status information; third, when the cache status is different, the execution results of the program are the same, but the external characteristics such as running time will have large differences. However, attackers can build side channels through these characteristics. Cache-based side channel attacks can be used to obtain encryption keys of encryption algorithms such as AES (Advanced Encryption Standard), DES (Data Encryption Standard), and RSA (Rivest-Shamir-Adleman), and can also be used to steal users' privacy information, posing a high threat to system security. In the related technologies, most of the current research on microarchitectural side-channel attacks focuses on the processor architecture of Intel or ARM (Advanced RISC Machines), and there are fewer studies on microarchitectural side-channel attacks on the RISC-V architecture.

[0047] In view of this, a RISC-V-based cache security defense method and system are provided in an embodiment of the present application, which is applied to a secure cache module in a RISC-V processor. The functional modules in the secure cache module include a physical address encryption module. When the RISC-V processor executes a target data loading instruction of a target request component, the target physical address in the target data loading instruction is extracted; the target physical address is encrypted by the physical address encryption module to obtain a target encrypted address; the secure data cache in the secure cache module is accessed according to the target encrypted address, and if a target cache line corresponding to the target encrypted address exists in the secure data cache, the target cache line is output to the target request component, so that the target request component performs a target data operation on the target cache line. In the embodiment of the present application, the physical address encryption module in the security cache module encrypts the target physical address carried in the target data loading instruction to obtain the target encrypted address, and the avalanche effect of the encryption will cause the rows with spatial correlation in the physical address space to be scattered in the entire space of the encrypted address, and the encrypted cache address is invisible to the attacker, which can protect the system from malicious attacks and achieve effective defense against cache side-channel attacks. That is, the embodiment of the present application can effectively complete the random mapping of memory rows to cache locations by operating the cache in the encrypted address space instead of the physical address space. By randomizing the fixed mapping relationship between memory rows and cache rows, the attacker cannot determine the cache set of the target address, thereby protecting the system from malicious attacks and achieving effective defense against cache side-channel attacks, thereby improving the performance of the cache in the RISC-V processor, while improving the level of information security protection and reducing potential information leakage risks.

[0048] The cache security defense method based on RISC-V provided in the embodiment of the present application relates to the field of data security technology. The cache security defense method based on RISC-V provided in the embodiment of the present application can be applied to a terminal, can also be applied to a server, and can also be software running in a terminal or a server. In some embodiments, the terminal can be a smart phone, a tablet computer, a laptop, a desktop computer, a smart speaker, a smart watch, and a car terminal, etc., but is not limited to this; the server side can be configured as an independent physical server, or it can be configured as a server cluster or a distributed system composed of multiple physical servers, and can also be configured to provide cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, CDN (Content Delivery Network, content distribution network) and cloud servers for basic cloud computing services such as big data and artificial intelligence platforms, and the server can also be a node server in a blockchain network; the software can be an application that implements a cache security defense method based on RISC-V, etc., but is not limited to the above forms.

[0049] The present application can be used in many general or special computer system environments or configurations. For example: personal computers, server computers, handheld devices or portable devices, tablet devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronic devices, network PCs (Personal Computers, personal computers), minicomputers, mainframe computers, distributed computing environments including any of the above systems or devices, etc. The present application can be described in the general context of computer executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform specific tasks or implement specific abstract data types. The present application can also be practiced in distributed computing environments, in which tasks are performed by remote processing devices connected through a communication network. In a distributed computing environment, program modules can be located in local and remote computer storage media including storage devices.

[0050] See also Figure 1 , Figure 1 It is an optional step flow chart of the RISC-V-based cache security defense method provided in an embodiment of the present application, which is applied to the security cache module in the RISC-V processor, and the functional modules in the security cache module include a physical address encryption module, Figure 1 The method may include but is not limited to steps S101 to S103.

[0051] Step S101, when the RISC-V processor executes a target data loading instruction of a target request component, extracting a target physical address in the target data loading instruction;

[0052] Among them, RISC-V is an open source instruction set architecture based on a reduced instruction set. The design goal of RISC-V is to provide a flexible, scalable, high-performance, low-power processor architecture that can be used in various fields, such as embedded systems, servers, high-performance computing, etc. The RISC-V processor is a processor based on the RISC-V instruction set architecture.

[0053] In the embodiment of the present application, the focus is on designing the cache part in the RISC-V processor, namely the secure cache module. Among them, the secure cache module is an important component in the RISC-V processor, which is used to store and process data to improve the data access speed. The defense scheme of the secure cache in the embodiment of the present application is divided into two parts. The first part is to randomize the address mapping to the cache set, and through the fixed mapping relationship between the randomized memory line and the cache line, the attacker cannot determine the cache set of the target address; the second part is to temporarily store the cache line that needs to be modified by the load instruction in the record table buffer module, until the load instruction retires and then fills the corresponding cache line into the cache, so that the attacker cannot observe the unsafe cache line.

[0054] In the embodiment of the present application, the functional modules in the security cache module include not only a physical address encryption module, but also an encrypted address decryption module and a record table buffer module. The physical address encryption module is used to encrypt the physical address corresponding to the data loading instruction to obtain the encrypted address, so that the cache can be accessed through the encrypted address; the encrypted address decryption module is used to convert the encrypted address of the fetched row in the cache into the physical address corresponding to the fetched row, so that the decrypted physical address can be used to perform write-back; the record table buffer module is used to store the loading instruction and the modified cache line, wherein the record table in the record table buffer module retains the records of the affected cache lines, such as the records of the modified cache lines.

[0055] See also Figure 2 , Figure 2 Schematic diagram of a secure cache design architecture for a RISC-V processor provided in an embodiment of the present application; Figure 2As shown, a security cache is provided in the RISC-V processor core, and the security cache includes a physical address encryption module, an encrypted address decryption module and a record table buffer module. The hardware part includes a SoC (System on Chip) system built according to the RISC-V processor core. The RISC-V processor core is connected to the peripherals through an AXI (Advanced eXtensible Interface) bus. The peripherals include a UART (Universal Asynchronous Receiver / Transmitter) serial port and a memory. The software program (i.e., the attack program used to evaluate the security cache module in the embodiment of the present application) is stored in the memory, and the UART serial port is used to output the program running results. In a specific implementation, the same attack program can be placed in the original SoC system in the related art and the SoC system in which the security cache designed in the embodiment of the present application is replaced for comparison. Specifically, the attack program is placed in the memory. After the RISC-V processor starts running, the program is read from the memory to the RISC-V processor core through the AXI bus for execution. The running result is output through the AXI bus via the UART serial port. After the running is completed, the original SoC system will be successfully attacked by the attack program, while the SoC system in which the security cache designed in the embodiment of the present application is replaced will fail to be attacked, thereby verifying the defense function of the security cache designed in the embodiment of the present application against attacks.

[0056] The target request component may be a hardware component or a software module that issues a data load request (i.e., a target data load instruction) to the RISC-V processor. For each load instruction that attempts to modify the cache, the cache is accessed using a physical address.

[0057] Optionally, the target physical address is a memory address specified in a target data load instruction for locating data to be loaded.

[0058] Step S102, encrypting the target physical address by the physical address encryption module to obtain a target encrypted address;

[0059] In some embodiments, step S102 may include: encrypting the target physical address using a low-latency block cipher through a physical address encryption module to obtain a target encrypted address.

[0060] In the embodiment of the present application, a low latency block cipher (LLBC) is used as the address encryption method, and the low latency block cipher is also used for decryption in the subsequent address decryption part. It should be noted that the encryption and decryption methods can also adopt an XOR method, which is not limited in the embodiment of the present application.

[0061] The target encrypted address is the target physical address in the target data load instruction encrypted by the physical address encryption module using a low-latency block cipher. The encrypted address is only visible in the cache, while the rest of the memory system operations remain unchanged and continue to be executed using the physical address.

[0062] In the specific implementation, by operating the cache on the encrypted address space instead of the physical address space, the random mapping of memory lines to cache locations can be effectively completed. Among them, the avalanche effect of encryption will cause lines with spatial correlation in the physical address space (such as lines mapped to the same set of caches) to be scattered throughout the encrypted address space. This dispersion will occur in an unpredictable manner and is determined by the encryption key. Since the attacker has no direct visibility into the ciphertext, the attacker cannot remember the plaintext-ciphertext pair, that is, the encrypted cache address is invisible to the attacker, so there is no need for memory-based attacks, thereby protecting the system from various malicious attacks and achieving effective defense against multiple cache side-channel attacks.

[0063] Step S103, accessing the secure data cache in the secure cache module according to the target encryption address, and if there is a target cache line corresponding to the target encryption address in the secure data cache, outputting the target cache line to the target request component so that the target request component performs a target data operation on the target cache line.

[0064] For the secure data cache, it is a storage mechanism in the secure cache module for storing data. The secure data cache is designed to protect the data from unauthorized access or leakage to ensure the security and privacy of the data. In the embodiment of the present application, the access to the secure data cache requires the use of an encrypted address. The physical address cannot directly access the secure data cache. By operating the cache on the encrypted address space instead of the physical address space, the random mapping of memory rows to cache locations can be effectively completed. The encrypted cache address is invisible to attackers, thereby protecting the system from various malicious attacks and achieving effective defense against multiple cache side-channel attacks.

[0065] The target cache line refers to the data block located by a specific request (specified by the target physical address corresponding to the target encrypted address) in the secure data cache. In a specific implementation, when a component (such as a processor, input / output device, etc.) requests access to data corresponding to a certain address, the secure cache module will check whether there is a line matching the address. If so, the corresponding line is considered to be the target cache line. The target cache line contains the requested data and can be output to the component requesting the data.

[0066] Optionally, the target data operation refers to a series of data processing actions performed on the target cache line retrieved from the secure data cache, and the target data operation may include but is not limited to reading data, writing data, updating data, deleting data, etc. The specific type of the target data operation depends on the actual application requirements of the requesting component and the purpose of the data.

[0067] In some embodiments, it may also include: accessing the secure data cache in the secure cache module according to the target encryption address; if the target cache line corresponding to the target encryption address does not exist in the secure data cache, extracting the target memory line from the memory module in the RISC-V processor according to the target physical address; and storing the target memory line in the secure data cache in the secure cache module.

[0068] The memory module is a physical device used to store data and programs in a computer system. In the RICS-V processor architecture, the memory module is part of the main memory (such as DRAM) and is used to store data and instructions required by the processor to execute programs.

[0069] The target memory row refers to the data block located by a specific request (specified by the target physical address) in the memory module. In the specific implementation, when there is no target cache row corresponding to the target encrypted address in the secure data cache, the system will extract the corresponding data block from the memory module according to the target physical address corresponding to the target encrypted address. This data block is called the target memory row. The target memory row contains the requested data and will then be stored in the secure data cache for subsequent secure access.

[0070] In a specific implementation, when the execution unit of the processor executes program instructions, it will encounter a load instruction that needs to read data from the memory. The load instruction will contain the memory address of the data to be read. The processor first checks whether the cache has the corresponding data. If the cache hits (the cache uses the tag part of the address to determine whether it hits), the data will be read directly from the cache, which is much faster than reading from the main memory; if it does not hit, the processor will load the data from the main memory and may write the data to the cache for future use.

[0071] In some embodiments, it may also include: accessing the secure data cache in the secure cache module according to the target encrypted address, if the target cache line corresponding to the target encrypted address does not exist in the secure data cache, and there is a dirty line in the secure data cache, extracting the dirty line encrypted address corresponding to the dirty line; decrypting the dirty line encrypted address through the encrypted address decryption module to obtain the dirty line physical address; writing the dirty line into the memory module in the RISC-V processor according to the dirty line physical address.

[0072] In a specific implementation, when a cache miss occurs (i.e., the target cache line corresponding to the target encrypted address does not exist in the secure data cache), if space is to be made in the cache to store new data, a cache line needs to be selected for replacement. Specifically, when there is a dirty cache line in the cache, the dirty cache line needs to be written back to the main memory first, and then the dirty cache line corresponding to the original cache line in the cache is replaced. Since the required data will be saved to the missed line when the cache misses, the data originally existing in this line position will be written back, and there is no dirty line in the cache when the cache hits; in addition, when there is a clean cache line in the cache, the clean cache line can be directly replaced without writing the cache line back to the main memory, wherein a clean cache line is a cache line whose data is consistent with the data in the main memory and has not been modified, or any modification has been written back to the main memory.

[0073] Optionally, the functional modules in the security cache module also include an encrypted address decryption module. The encrypted address decryption module uses the same password as the physical address encryption module, and both can be encrypted or decrypted using a low latency block cipher (LLBC). For the selection of the password, an XOR method can also be selected. Among them, the encrypted address decryption module is used to convert the encrypted address of the fetched row in the cache into a physical address corresponding to the fetched row, so that the decrypted physical address can be used to perform write back. Exemplarily, when it is necessary to "evict" the dirty row in the security data cache, the dirty row is first taken out of the security data cache. Since the tag information in the security data cache is based on the encrypted address, the encrypted address decryption module must first be used to decrypt the encrypted address corresponding to the dirty row into the original physical address, and then the original physical address is used to perform write back, that is, the dirty row is written back to the memory.

[0074] A dirty line refers to a row of data in the secure data cache whose content has been modified in the secure data cache but has not yet been synchronously written back to the main memory (i.e., the storage module). In a specific implementation, after the data is loaded into the secure data cache, the processor may modify the data. If the modified data has not yet been written back to the main memory, the row of modified data is marked as "dirty", i.e., a dirty line, indicating that its content is different from the original data in the main memory; when the cache is replaced, the modified data in the row originally stored in the cache must be written back to the main memory to ensure that the data in the main memory remains consistent.

[0075] For the dirty line encrypted address, it is the encrypted address corresponding to the dirty line in the secure data cache, the dirty line physical address is the original address corresponding to the dirty line, the dirty line physical address can be obtained after being encrypted by the physical address encryption module, and the dirty line encrypted address can be obtained after being decrypted by the encrypted address decryption module.

[0076] In a specific implementation, a low latency block cipher (LLBC) can be used to convert a physical address into an encrypted address, and the encrypted address is used to access the cache. If the cache line corresponding to the accessed encrypted address (i.e., the cache line corresponding to the physical address) exists in the cache, the cache indicates a hit and provides data to the component that makes a load instruction request; if the cache line corresponding to the accessed encrypted address (i.e., the cache line corresponding to the physical address) is not in the cache, i.e., a miss, the cache may evict a dirty line, i.e., when there is a dirty line in the cache, the dirty line must be written back to the memory. Since the tag information in the cache is based on the encrypted address, the encrypted address of the fetched line (such as the encrypted address of the dirty line) must first be converted to the original physical address. Since the evicted line now has the original physical address, the fetched line can be written back to the memory according to the original physical address. Among them, the encrypted address is only visible in the cache, and the memory does not need to obtain the encrypted address, i.e., the rest of the operations of the memory system remain unchanged and continue to be executed using the physical address. It is worth mentioning that the cache organization and hit / miss detection remain the same, it’s just that instead of accesses to physical addresses (which might be mapped to some set X), the cache receives accesses to encrypted addresses (which might be mapped to a different set Y).

[0077] In an embodiment of the present application, by operating the cache on an encrypted address space instead of a physical address space, random mapping of memory rows to cache locations can be effectively completed. The avalanche effect of encryption will cause rows with spatial correlation in the physical address space (for example, rows mapped to the same set of caches) to be scattered throughout the entire space of the encrypted address. This dispersion will occur in an unpredictable manner and is determined by the encryption key. Since the attacker has no direct visibility of the ciphertext, the attacker cannot remember the plaintext-ciphertext pairs. The encrypted cache address is invisible to the attacker, so no memory-based attack is required, thereby protecting the system from various malicious attacks and achieving effective defense against multiple cache side-channel attacks, thereby ensuring user data privacy and security and improving the security of the system.

[0078] In some embodiments, it may also include: when the RI SC-V processor executes the target data loading instruction of the target request component, if the target data loading instruction modifies the target cache line to obtain the target modified cache line, the target data loading instruction and the target modified cache line are stored in the record table in the record table buffer module; the instruction state of the target data loading instruction is monitored through the reorder buffer, if the instruction state of the target data loading instruction is a non-retired state, the data state of the target modified cache line is updated to a non-secure state to prohibit non-target data loading instructions from modifying the target modified cache line; if the instruction state of the target data loading instruction is a retired state, the data state of the target modified cache line is updated to a secure state, and the target modified cache line is stored in the secure data cache in the secure cache module.

[0079] In some embodiments, the method may further include: when the space occupied by the data in the record table is greater than or equal to the record storage space of the record table, a first-in-first-out replacement algorithm is used to replace the target data entry in the record table.

[0080] The security cache module is provided with a re-order buffer, namely ROB (Re-order Buffer).

[0081] The target modified cache line is a data line obtained by modifying the target cache line corresponding to the load instruction through the load instruction, that is, the cache line affected by the load instruction.

[0082] The instruction state of the target data load instruction can be divided into a non-retired state and a retired state. When the instruction state of the target data load instruction is the non-retired state, the data state of the target modified cache line is considered to be in an unsafe state; when the instruction state of the target data load instruction is the retired state, the corresponding line of the target data load instruction stored in the record table is stored in the corresponding line in the cache, and the data state of the target modified cache line is modified to a safe state.

[0083] As for the data occupied space, it is the data usage space of the record table in the record table buffer module; the record storage space is the maximum storage space of the record table in the record table buffer module.

[0084] Optionally, the functional module in the security cache module also includes a record table buffer module. For any load instruction, it will be recorded in the record table buffer module. The record table buffer module contains a record table. Figure 3 , Figure 3 is a schematic diagram of the record table structure of the record table buffer module provided in the embodiment of the present application, such as Figure 3 As shown, the specific record table structure and its execution process are as follows: the record table contains n items, each of which has an IID field and an index field ( Figure 3The address field in the table). The IID field contains the IID of the load instruction, which is used to compare with the IID of the ROB unit; the index field records the address of the cache line affected by the load instruction. In order to minimize the delay caused by querying the record table, the embodiment of the present application uses a multi-channel comparator. The multi-channel comparator circuit can be completed within one clock cycle, so that the IID of the ROB unit can be compared with the IID of each item in the record table at the same time. If the requested memory address hits the record table (that is, the same IID appears in the ROB unit and the record table), the address information of the cache line corresponding to the same IID as this item is output from the record table.

[0085] In the specific implementation, once the load instruction modifies the cache line corresponding to the load instruction, the load instruction and the modified cache line will be saved in the record table of the record table buffer module. At this time, the modified cache line becomes invisible and is no longer accessed by other subsequent instructions. Specifically, when the load instruction enters the execution stage, the security status of the load instruction is still unknown. However, when the load instruction retires, by monitoring the header of the ROB, if the load instruction is recorded in the record table buffer module, the modified cache line corresponding to the load instruction is updated to a secure state. At this time, the modified cache line becomes visible and can be accessed by other subsequent instructions.

[0086] It is easy to understand that after the load instruction reaches the head of the ROB, the state of the load instruction is converted to a safe instruction. Therefore, an important sign of the safe transition of the instruction is that the instruction reaches the head of the ROB. Specifically, the arrival of the instruction at the head of the ROB is a processing mechanism of the processor, that is, the submission (commit) of the instruction means that the current instruction is already in the retirement window of the head of the ROB, and all instructions before this instruction have been retired or are retiring normally, that is, the submission of an instruction means that the instruction is safe (it will definitely be executed). Among them, the retirement (retire) of the instruction is the process of removing the instruction from the ROB after the instruction is executed and it can be determined that it has an impact on the processor. However, the malicious instructions used in the attack cannot reach the head of the ROB; once the instruction reaches the head of the ROB, the instruction will retire. Therefore, monitoring the head of the ROB to understand whether the instruction is retired is an important means to check the security of the instruction.

[0087] Among them, the execution phase refers to the phase in which the processor actually executes instructions, such as completing calculations, memory reading, writing, and other operations. In this phase, the execution effect of the instruction has occurred, but its status (such as security) has not been fully determined. In particular, for load instructions, although the load instruction obtains data in the execution phase, this data may be loaded under the wrong branch prediction path or potential mis-speculation, so its status is still unknown. Specifically, in the initial execution phase: when the instruction is issued to the execution unit (such as ALU (Arithmetic Logic Unit, arithmetic logic unit), load / store unit), the execution phase of the instruction begins. In this phase, the load instruction may obtain data from the cache or memory, and the arithmetic instruction performs calculations; in the end of the execution phase: the end of the execution phase occurs after the instruction completes its operation and generates a result, and the result is usually written back to the register file or cache. At this time, although the load instruction has completed the calculation or data acquisition, it has not completely exited the processor's pipeline and is still waiting for retirement in the instruction reorder buffer (ROB).

[0088] In practical applications, cache side-channel attacks may exploit all non-retired load instructions. Therefore, if a load instruction is executed but not retired, the load instruction is considered unsafe and cache modifications need to be prohibited. If a load instruction is executed and retired, the load instruction can be considered safe, and the cache line status can then be updated to a safe state, and all modifications can be queried by subsequent instructions.

[0089] Among them, the load instruction replaces the oldest entry in the record table according to the first-in-first-out (FIFO) replacement algorithm for the record of the record table. In a specific implementation, since the record may exceed the maximum capacity of the record table, once the space in the record table is filled, the record table needs to discard some items, so the record table of the embodiment of the present application replaces the oldest entry according to the first-in-first-out (FIFO) replacement algorithm. It is worth mentioning that some instructions in the record table may be discarded in a non-updated state. Since the record table is large enough, unless it is an unsafe instruction, the load instruction cannot remain in a non-retired state for a long time until the record table expels it. Therefore, the record table retains the records of the affected cache lines and can prevent subsequent other instructions from accessing the records of the affected cache lines. After the load instruction corresponding to the record of the affected cache line retires, the cache line affected by the load instruction will be released and returned to a visible state, and all modifications can be queried or accessed by subsequent instructions.

[0090] In some embodiments, it may also include: obtaining an attack test program; storing the attack test program in a memory module of a RISC-V processor, executing the attack test program through the RISC-V processor to obtain a simulation test result; and evaluating the defense level of the security cache module based on the simulation test result.

[0091] As for the attack test program, it is a program used to test the defense level of the security cache module designed in the embodiment of the present application. In the specific implementation, the program of the software part (such as the attack test program) is converted into an executable file through the compilation tool chain, and the executable file is then converted into a binary file through the tool chain and stored in the memory, wherein the binary file is a piece of software attack code, which is placed in the memory of the SoC system and executed after power-on. The tool chain used in the embodiment of the present application is the standard tool chain of the RISC-V architecture. Please refer to Figure 4 , Figure 4 : is a schematic diagram of the compilation process of the attack simulation program provided in the embodiment of the present application; Figure 4 As shown in Figure 1, the structure of the standard tool chain based on the RISC-V architecture usually includes a compiler, an assembler, a linker, etc., and all these components work together to implement the translation process from C / C++ source code to executable files. Figure 4 As shown, the compilation process of the attack simulation program is: input the source code into the preprocessor. When the input source code does not conform to the C / C++ language standard or the GNU extended syntax specification (the language standard selected by the compilation file -std=gnu89 or -std=gnu++99), the compiler will generate corresponding diagnostic information to prompt the program developer that the corresponding source code file has syntax or semantic errors. The final work of the compiler is to generate assembly code for a specific target machine, and then the assembler assembles the assembly code generated by the compiler into target code; then the linker links multiple target files and several static libraries and dynamic shared libraries into a complete executable file. For the structure of the standard tool chain based on the RICS-V architecture and its compilation process, the specific implementation principles in the relevant technology can be referred to, and the embodiments of this application will not be repeated here.

[0092] In a specific implementation, a simulated attack is conducted on the security cache designed for a high-performance RISC-V processor according to an embodiment of the present application, and the defense effect is observed, so as to verify the correctness of the system constructed according to the embodiment of the present application.

[0093] Specifically, the same attack program can be placed in the original SoC system in the related technology and the SoC system in which the security cache designed in the embodiment of the present application is replaced for comparison. Specifically, the attack program is placed in the memory. After the RI SC-V processor starts running, the program is read from the memory to the RI SC-V processor core through the AXI bus for execution. The running results are output through the AXI bus via the UART serial port. After the running is completed, the original SoC system will be successfully attacked by the attack program, while the SoC system in which the security cache designed in the embodiment of the present application is replaced will fail to be attacked, thereby verifying the defense function of the security cache designed in the embodiment of the present application against attacks.

[0094] In steps S101 to S103 shown in the embodiment of the present application, when the RI SC-V processor executes the target data loading instruction of the target request component, the target physical address in the target data loading instruction is extracted; the target physical address is encrypted by the physical address encryption module to obtain the target encrypted address; the secure data cache in the secure cache module is accessed according to the target encrypted address, and if there is a target cache line corresponding to the target encrypted address in the secure data cache, the target cache line is output to the target request component, so that the target request component performs a target data operation on the target cache line. The embodiment of the present application encrypts the target physical address carried in the target data loading instruction through the physical address encryption module in the security cache module to obtain the target encrypted address, and the avalanche effect of the encryption will cause the rows with spatial correlation in the physical address space to be scattered in the entire space of the encrypted address, and the encrypted cache address is invisible to the attacker, which can protect the system from malicious attacks and achieve effective defense against cache side-channel attacks. That is, the embodiment of the present application can effectively complete the random mapping of memory rows to cache locations by operating the cache in the encrypted address space instead of the physical address space, and by randomizing the fixed mapping relationship between memory rows and cache rows, it is impossible for the attacker to determine the cache set of the target address, thereby protecting the system from malicious attacks and achieving effective defense against cache side-channel attacks, thereby improving the performance of the cache in the RISC-V processor, while improving the level of information security protection and reducing potential information leakage risks.

[0095] In order to explain the principle of the technical solution of the present invention in detail, the overall process of the present invention is described below in combination with some specific embodiments. It is easy to understand that the following is an explanation of the technical principle of the present invention and cannot be regarded as a limitation of the present invention.

[0096] In the embodiment of the present application, by integrating the randomization scheme and the record table scheme, a secure cache design of the embodiment of the present application can be constructed. Among them, the randomization scheme can be effectively completed by using an encrypted address to access the cache. Specifically, the physical address of the cache receiving access is encrypted or decrypted through a low latency block cipher (LLBC), that is, by randomizing the address mapping to the cache set, and by randomizing the fixed mapping relationship between the memory line and the cache line, the attacker cannot determine the cache set of the target address; the defense method of the record table scheme temporarily stores the cache line that needs to be modified by the load instruction in the record table in the record table buffer module until the load instruction retires and then fills the corresponding modified cache line into the secure data cache, so that the attacker cannot observe the unsafe cache line.

[0097] See also Figure 5 , Figure 5 is a flow chart of a cache security defense method based on RISC-V provided in an embodiment of the present application; Figure 5 As shown in FIG. 1 , the process of the cache security defense method based on RISC-V is as follows: for each load instruction that attempts to modify the cache (i.e., access the cache using a physical address), first, the physical address corresponding to the load instruction is encrypted using a low latency block cipher (LLBC) through a physical address encryption module to obtain an encrypted address; then, the cache is accessed using the encrypted address ( Figure 5 DCache in the cache), and set the flag bit S in the cache line corresponding to the encrypted address to 0 (meaning that any subsequent access to this cache line is a miss), and at the same time, record the encrypted address and the ID (IID: Instruction ID) of the load instruction into the record table in the record table buffer module; then, if the cache line corresponding to the accessed encrypted address (i.e., the cache line corresponding to the physical address) exists in the cache, the cache indicates a hit and provides data to the component that proposes the load instruction; if the cache line corresponding to the accessed encrypted address (i.e., the cache line corresponding to the physical address) does not exist in the cache, that is, a miss, the cache may evict the dirty line, and the dirty line must be written back to the memory; further, when the line in the cache needs to be written back to the memory, the encrypted address decryption module is used to use a low latency block cipher (LLBC) to decrypt the line that needs to be written back (such as the dirty line), that is, the encrypted address of the line to be taken out is converted into a physical address, and finally the physical address is used to perform a memory write back operation, wherein the low latency block cipher (LLBC) uses the same key for encryption and decryption operations. In addition, during the randomization mapping process, when the load instruction retires, the header of the ROB can be monitored. If the load instruction is recorded in the record table buffer module (that is, the ID in the ROB is the same as the ID saved in the record table), the modified cache line of the encrypted address corresponding to the load instruction is updated to a secure state (S is set to 1), so that other subsequent instructions can access the modified cache line.

[0098] It should be pointed out that this embodiment only provides a brief schematic description of the general process of the cache security defense method based on RISC-V. The detailed description of each step can refer to the relevant content in the aforementioned embodiment and will not be repeated here. It can be understood that the present invention is not limited to this.

[0099] The embodiments of the present application provide a RISC-V-based cache security defense method and system, which are applied to a secure cache module in a RISC-V processor. The functional modules in the secure cache module include a physical address encryption module. When the RISC-V processor executes a target data loading instruction of a target request component, the target physical address in the target data loading instruction is extracted; the target physical address is encrypted by the physical address encryption module to obtain a target encrypted address; the secure data cache in the secure cache module is accessed according to the target encrypted address, and if a target cache line corresponding to the target encrypted address exists in the secure data cache, the target cache line is output to the target request component, so that the target request component performs a target data operation on the target cache line. In the embodiment of the present application, the physical address encryption module in the security cache module encrypts the target physical address carried in the target data loading instruction to obtain the target encrypted address, and the avalanche effect of the encryption will cause the rows with spatial correlation in the physical address space to be scattered in the entire space of the encrypted address, and the encrypted cache address is invisible to the attacker, which can protect the system from malicious attacks and achieve effective defense against cache side-channel attacks. That is, the embodiment of the present application can effectively complete the random mapping of memory rows to cache locations by operating the cache in the encrypted address space instead of the physical address space. By randomizing the fixed mapping relationship between memory rows and cache rows, the attacker cannot determine the cache set of the target address, thereby protecting the system from malicious attacks and achieving effective defense against cache side-channel attacks, thereby improving the performance of the cache in the RISC-V processor, while improving the level of information security protection and reducing potential information leakage risks.

[0100] In summary, in order to solve the problem that traditional cache cannot provide sufficient security protection and is vulnerable to malicious attacks. The embodiment of the present application provides a secure cache design for high-performance RISC-V processors, which not only provides the functions and performance of traditional caches, but also can protect the system from various malicious attacks, and effectively resist a variety of cache side-channel attacks. It not only targets specific attack methods, but also has a wider range of applicability and defense capabilities. The secure cache design for high-performance RISC-V processors not only provides a highly customizable hardware platform, but also provides users with a secure and reliable computing environment.

[0101] See also Figure 6The embodiment of the present application also provides a RISC-V-based cache security defense system 600, which is applied to a secure cache module in a RISC-V processor. The functional modules in the secure cache module include a physical address encryption module, which can implement the above-mentioned RISC-V-based cache security defense method. The system includes the following modules:

[0102] A physical address extraction module 601 is used to extract a target physical address in the target data loading instruction when the RISC-V processor executes the target data loading instruction of the target request component;

[0103] A physical address encryption module 602, configured to encrypt the target physical address through the physical address encryption module to obtain a target encrypted address;

[0104] The encrypted address access module 603 is used to access the secure data cache in the secure cache module according to the target encrypted address. If there is a target cache line corresponding to the target encrypted address in the secure data cache, the target cache line is output to the target request component so that the target request component performs a target data operation on the target cache line.

[0105] It can be understood that the contents of the above method embodiments are all applicable to the present system embodiments, the functions specifically implemented by the present system embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0106] The embodiment of the present application also provides an electronic device, the electronic device includes a memory and a processor, the memory stores a computer program, and the processor implements the above-mentioned RISC-V-based cache security defense method when executing the computer program. The electronic device can be any intelligent terminal including a tablet computer, a car computer, etc.

[0107] It can be understood that the contents of the above method embodiments are all applicable to the present device embodiments, the functions specifically implemented by the present device embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0108] See also Figure 7 , Figure 7 The hardware structure of an electronic device of another embodiment is illustrated, and the electronic device includes:

[0109] The processor 701 may be implemented by a general-purpose CPU (Central Processing Unit), a microprocessor, an application-specific integrated circuit (Application Specific Integrated Circuit, ASIC for short), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of the present application;

[0110] The memory 702 can be implemented in the form of a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 702 can store an operating system and other applications. When the technical solution provided in the embodiment of this specification is implemented by software or firmware, the relevant program code is stored in the memory 702, and the processor 701 calls and executes the cache security defense method based on RISC-V in the embodiment of this application;

[0111] Input / output interface 703, used to implement information input and output;

[0112] Communication interface 704, used to realize communication interaction between the device and other devices, which can be realized through wired mode (such as USB, network cable, etc.) or wireless mode (such as mobile network, WIFI, Bluetooth, etc.);

[0113] A bus 705 that transmits information between the various components of the device (e.g., the processor 701, the memory 702, the input / output interface 703, and the communication interface 704);

[0114] The processor 701 , the memory 702 , the input / output interface 703 and the communication interface 704 are connected to each other in communication within the device via a bus 705 .

[0115] An embodiment of the present application also provides a computer-readable storage medium, which stores a computer program, and when the computer program is executed by a processor, the above-mentioned RISC-V-based cache security defense method is implemented.

[0116] It can be understood that the contents of the above method embodiments are all applicable to the present storage medium embodiments, the functions specifically implemented by the present storage medium embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0117] The memory, as a non-transient computer-readable storage medium, can be used to store non-transient software programs and non-transient computer executable programs. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some embodiments, the memory may optionally include a memory remotely disposed relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0118] The RISC-V-based cache security defense method and the RISC-V-based cache security defense system provided in the embodiments of the present application, when the RISC-V processor executes the target data loading instruction of the target request component, extracts the target physical address in the target data loading instruction; encrypts the target physical address through the physical address encryption module to obtain the target encrypted address; accesses the secure data cache in the secure cache module according to the target encrypted address, and if there is a target cache line corresponding to the target encrypted address in the secure data cache, outputs the target cache line to the target request component, so that the target request component performs the target data operation on the target cache line. The embodiment of the present application encrypts the target physical address carried in the target data loading instruction through the physical address encryption module in the security cache module to obtain the target encrypted address, and the avalanche effect of the encryption will cause the rows with spatial correlation in the physical address space to be scattered in the entire space of the encrypted address, and the encrypted cache address is invisible to the attacker, which can protect the system from malicious attacks and achieve effective defense against cache side-channel attacks. That is, the embodiment of the present application can effectively complete the random mapping of memory rows to cache locations by operating the cache in the encrypted address space instead of the physical address space, and by randomizing the fixed mapping relationship between memory rows and cache rows, it is impossible for the attacker to determine the cache set of the target address, thereby protecting the system from malicious attacks and achieving effective defense against cache side-channel attacks, thereby improving the performance of the cache in the RISC-V processor, while improving the level of information security protection and reducing potential information leakage risks.

[0119] The embodiments described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Those skilled in the art will appreciate that with the evolution of technology and the emergence of new application scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0120] Those skilled in the art will appreciate that the technical solutions shown in the figures do not constitute a limitation on the embodiments of the present application, and may include more or fewer steps than shown in the figures, or a combination of certain steps, or different steps.

[0121] The system embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separated, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment.

[0122] Those skilled in the art will appreciate that all or some of the steps in the methods disclosed above, and the functional modules / units in the systems and devices may be implemented as software, firmware, hardware, or a suitable combination thereof.

[0123] The terms "first", "second", "third", "fourth", etc. (if any) in the specification of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0124] It should be understood that in the present application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0125] In the several embodiments provided in the present application, it should be understood that the disclosed systems and methods can be implemented in other ways. For example, the system embodiments described above are only schematic. For example, the division of the above units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of systems or units, which can be electrical, mechanical or other forms.

[0126] The units described above as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0127] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0128] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including multiple instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, referred to as ROM), random access memory (Random Access Memory, referred to as RAM), disk or optical disk and other media that can store programs.

[0129] The preferred embodiments of the present invention are described above with reference to the accompanying drawings, but the scope of the rights of the present invention is not limited thereto. Any modification, equivalent substitution and improvement made by a person skilled in the art without departing from the scope and essence of the present invention should be within the scope of the rights of the present invention.

Claims

1. A cache security defense method based on RISC-V, characterized in that: A security cache module applied to a RISC-V processor, wherein the functional modules in the security cache module include a physical address encryption module, and the method includes the following steps: When the RISC-V processor executes a target data load instruction of a target request component, extracting a target physical address in the target data load instruction; Encrypting the target physical address by the physical address encryption module to obtain a target encrypted address; The secure data cache in the secure cache module is accessed according to the target encrypted address, and if a target cache line corresponding to the target encrypted address exists in the secure data cache, the target cache line is output to the target request component so that the target request component performs a target data operation on the target cache line.

2. The method according to claim 1, characterized in that The method further comprises: Accessing the secure data cache in the secure cache module according to the target encrypted address, and if the target cache line corresponding to the target encrypted address does not exist in the secure data cache, extracting the target memory line from the memory module in the RISC-V processor according to the target physical address; The target memory line is stored in the secure data cache in the secure cache module.

3. The method according to claim 1, characterized in that The functional module in the security cache module further includes an encrypted address decryption module, and the method further includes: Accessing the secure data cache in the secure cache module according to the target encrypted address, if the target cache line corresponding to the target encrypted address does not exist in the secure data cache, and a dirty line exists in the secure data cache, extracting the dirty line encrypted address corresponding to the dirty line; Decrypting the dirty row encrypted address by the encrypted address decryption module to obtain a dirty row physical address; Writing the dirty line into a memory module in the RISC-V processor according to the dirty line physical address.

4. The method according to claim 1, characterized in that: The functional module in the security cache module further includes a record table buffer module, the security cache module is provided with a reordering buffer, and the method further includes: When the RISC-V processor executes the target data loading instruction of the target request component, if the target data loading instruction modifies the target cache line to obtain a target modified cache line, the target data loading instruction and the target modified cache line are stored in a record table in the record table buffer module; Monitoring the instruction state of the target data load instruction through the reorder buffer, and if the instruction state of the target data load instruction is a non-retired state, updating the data state of the target modified cache line to a non-secure state to prohibit non-target data load instructions from modifying the target modified cache line; If the instruction state of the target data load instruction is a retired state, the data state of the target modified cache line is updated to a secure state, and the target modified cache line is stored in the secure data cache in the secure cache module.

5. The method according to claim 4, characterized in that The method further comprises: When the space occupied by the data in the record table is greater than or equal to the record storage space of the record table, a first-in-first-out replacement algorithm is used to replace the target data entry in the record table.

6. The method according to claim 1, characterized in that The method further comprises: Get the attack test program; The attack test program is stored in the memory module of the RISC-V processor, and the attack test program is executed by the RISC-V processor to obtain a simulation test result; The defense level of the security cache module is evaluated according to the simulation test results.

7. The method according to claim 1, characterized in that The step of encrypting the target physical address by the physical address encryption module to obtain a target encrypted address includes: The target physical address is encrypted by the physical address encryption module using a low-latency block cipher to obtain the target encrypted address.

8. A cache security defense system based on RISC-V, characterized in that: A secure cache module applied to a RISC-V processor, wherein the functional modules in the secure cache module include a physical address encryption module, and the system includes the following modules: A physical address extraction module, used for extracting a target physical address in the target data loading instruction when the RISC-V processor executes the target data loading instruction of the target request component; A physical address encryption module, used to encrypt the target physical address through the physical address encryption module to obtain a target encrypted address; An encrypted address access module is used to access the secure data cache in the secure cache module according to the target encrypted address. If there is a target cache line corresponding to the target encrypted address in the secure data cache, the target cache line is output to the target request component so that the target request component performs a target data operation on the target cache line.

9. An electronic device, characterized in that: The electronic device comprises a memory and a processor, the memory stores a computer program, and the processor implements the method according to any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 7 is implemented.

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