Core particle type selection method

Abstract

The invention provides a core particle type selection method, which comprises the following steps: S1, acquiring a core particle library in a data form constructed according to a specified core particle library specification, the core particle library containing a plurality of core particles and description files thereof; s2, obtaining a to-be-accelerated application, obtaining the application, and converting the application into a task data flow diagram by using a semantic matching rule, the task data flow diagram comprising operators and dependency relationships thereof; s3, according to the core particle library and the task data flow diagram, performing multiple times of grouping mapping for each core particle combination based on the multiple core particle combinations, calculating performance indexes of each task grouping mapping scheme, and determining an optimal core particle combination according to the performance indexes of the task grouping mapping schemes, the task grouping mapping scheme comprises a plurality of mapping relations, and each mapping relation comprises an operator in an application, a grouping serial number of the operator and an operation core grain distributed for the operator. According to the method, the model selection efficiency and quality of the core particle integration system can be improved, and the time overhead and cost of manual model selection are reduced.

Description

Technical Field

[0001] The present invention relates to the field of electronic automation design, in particular to the field of core particle design technology, and more particularly to a core particle selection method. Background Art

[0002] In the post-Moore era, chiplet technology, as an innovative chip design and integration method, has indeed played an important role in improving chip manufacturing yield, shortening R&D cycle and reducing costs. Chiplet technology breaks down a large chip into multiple small chips (chiplets) with predetermined functions, and then uses advanced packaging technology to integrate these chiplets into a complete system chip (also known as chiplet integrated system, chiplet system). This technology not only improves production yield, but also allows the mixed integration of chiplets of different process nodes and different materials, thereby improving R&D efficiency and reducing non-repetitive engineering costs.

[0003] The existing technology has the following difficulties in the design process from application to core particle system adapted to the application:

[0004] First, the information about the relevant core particles can only be obtained in a scattered manner from the providers of each core particle (such as sales, manufacturers, etc.), and this information is often incomplete and difficult to be directly used in the design of the core particle system;

[0005] Second, even if the information of the chiplets provided by various providers is known, it is still difficult for the user to efficiently design and determine the optimal chiplet system for adapting the application.

[0006] It should be noted that this background technology is only used to introduce the relevant information of the present invention to help understand the technical solution of the present invention, but it does not mean that the relevant information is necessarily the prior art. The relevant information is submitted and disclosed together with the present invention solution. If there is no evidence that the relevant information has been disclosed before the application date of the present invention, the relevant information shall not be regarded as the prior art. Summary of the invention

[0007] Therefore, the purpose of the present invention is to overcome the defects of the prior art and provide a core particle selection method.

[0008] The objective of the present invention is achieved through the following technical solutions:

[0009] According to a first aspect of the present invention, a coregrain selection method is provided, comprising the steps of: S1, obtaining a coregrain library in data form constructed according to a specified coregrain library specification, which contains a plurality of coregrains and their description files; S2, obtaining an application to be accelerated, obtaining the application to be accelerated, and converting the application into a task data flow graph including operators and their dependencies using preset semantic matching rules; S3, performing multiple group mappings for the application based on each coregrain combination in a plurality of coregrain combinations according to the coregrain library and the task data flow graph, and calculating the performance index of each task group mapping scheme, and determining the optimal coregrain combination according to the performance index of the task group mapping scheme, wherein the task group mapping scheme includes a plurality of mapping relationships, and each mapping relationship includes an operator in the application, a group sequence number of the operator, and an operation coregrain allocated to the operator. The scheme can at least achieve the following beneficial technical effects: the coregrain library of the scheme is constructed in accordance with a coregrain library specification (standard), and can serve as a bridge between the coregrain integration design and the real coregrain. Based on the primitives supported by the coregrain provided by the coregrain library, the application to be accelerated can be converted into a task data flow graph. Subsequently, based on the various coregrains provided by the coregrain library and their description files, a variety of coregrain combinations can be efficiently generated and the optimal coregrain combination can be selected from them, and a set of task grouping mapping schemes with the best comprehensive performance can be determined from the optimal coregrain combination, thereby improving the selection efficiency and effect of the coregrain integration system and reducing the time overhead and cost of manual selection.

[0010] Optionally, step S3 includes using multiple genetic algorithms to optimize from the level of core particle combination and the level of task grouping mapping scheme, including: S31, at the core particle combination level, using a first genetic algorithm to iteratively optimize the core particle combination; S32, at the task grouping mapping scheme level, using a second genetic algorithm to iteratively optimize the task grouping mapping scheme according to the core particle combination obtained by the first genetic algorithm, including: optimizing the grouping of each operator and the assigned core particles.

[0011] Optionally, the first genetic algorithm includes: S311, based on the coreparticle types contained in the coreparticle library, randomly generate a set of multiple initialized coreparticle combinations that meet the area constraint, and calculate the fitness of each initialized coreparticle combination, wherein the coreparticle combination includes the number of various coreparticles, and the fitness refers to the performance index corresponding to the coreparticle combination; S312, according to the current set of coreparticle combinations and the fitness corresponding to each coreparticle combination therein, select multiple coreparticle combinations in order of fitness from small to large to form a first parent generation set, randomly select multiple pairs of parents from the first parent generation set for crossover, and obtain multiple initial first offspring; S313, perform a first mutation operation on the multiple initial first offspring at a preset mutation rate to obtain multiple second offspring after the mutation operation; S314, respectively input the coreparticle combinations corresponding to the multiple second offspring into the second genetic algorithm to calculate the fitness corresponding to the coreparticle combination, and repeat steps S312-S314 until the preset requirements are met. This scheme can at least achieve the following beneficial technical effects: this scheme performs multiple iterative optimizations on the initialized multiple coreparticle combinations at the coreparticle combination level, so as to better combine the characteristics of excellent parents to screen out high-quality coreparticle combinations from the coreparticle types provided by the coreparticle library, and combines mutation operations to explore other possible coreparticle combinations beyond the information contained in the better parents, thereby improving the quality of the screened coreparticle combinations from two aspects.

[0012] Optionally, the first mutation operation contains one or more mutation modes, wherein the mutation modes contained in the first mutation operation include: changing the quantity of a certain coregrain in the coregrain combination at a preset first mutation rate; and / or exchanging the quantity of two coregrains in the coregrain combination at a preset second mutation rate.

[0013] Optionally, the second genetic algorithm includes performing the following operations for each core particle combination obtained: S321, randomly generating multiple initialized task grouping mapping schemes that meet preset constraints based on the task data flow diagram and the core particle combination, and calculating the fitness of each scheme; S322, selecting multiple task grouping mapping schemes in order of the fitness of the scheme from small to large to form a second parent generation set, randomly selecting multiple pairs of parents from the second parent generation set, performing a crossover operation on each pair of parents to obtain an initial third offspring, and obtaining multiple initial third offspring after aggregation; S323, performing a second mutation operation on the multiple initial third offspring at a predetermined mutation rate to obtain multiple fourth offspring that have undergone the mutation operation; S324, calculating the fitness of the task grouping mapping scheme corresponding to each fourth offspring, and determining the fitness corresponding to the core particle combination based on the fitness corresponding to the multiple fourth offspring.

[0014] Optionally, the process of performing a crossover operation on each pair of parent generations to obtain an initial third offspring generation includes: extracting existing subgraphs as genetic fragments from the task grouping mapping scheme of the pair of parent generations to form a genetic fragment set, each genetic fragment including at least one operator; setting each operator in the task data flow graph as an undetermined operator to form an undetermined operator set; based on the genetic fragment set, the undetermined operator set and the task data flow graph, using the genetic fragments in the genetic fragment set to generate the initial third offspring generation, including: selecting a current operator from the undetermined operator set in turn according to the execution order of the operator in the task data flow graph; for the current operator, randomly copying a genetic fragment containing the current operator from the genetic fragment set to implement the operator, and removing all operators included in the selected genetic fragment from the undetermined operator set and setting them as determined operators, wherein, if the currently copied genetic fragment includes a determined operator, the undetermined operator in the currently copied genetic fragment is split out to form a new genetic fragment; when the undetermined operator set is an empty set, combining the genetic fragments where the determined operators are located to obtain the initial third offspring generation. This solution can at least achieve the following beneficial technical effects: the core particle combination can be continuously optimized by combining the genetic fragments of the two parents, thereby improving the performance of the final required core particle combination.

[0015] Optionally, the second mutation operation includes: mutation mode 1: changing the grouping of a certain operator; mutation mode 2: splitting a subgraph into two subgraphs; mutation mode 3: merging two subgraphs into one subgraph; mutation mode 4: mapping a subgraph to another core particle for operation; and mutation mode 5: exchanging the operation core particles of the two subgraphs; or a combination of the above mutation modes. The scheme can at least achieve the following beneficial technical effects: the scheme uses multiple mutation modes to find a high-quality task grouping mapping scheme in the search space of the task grouping mapping scheme.

[0016] Optionally, the fitness of the task grouping mapping scheme is a weighted sum of total delay, power consumption, area and cost corresponding to the scheme.

[0017] According to a second aspect of the present invention, there is provided a computer program product, comprising a computer program / instruction, which implements the steps of the method described in the first aspect when executed by a processor.

[0018] According to a third aspect of the present invention, there is provided an electronic device (such as a server or a server cluster), comprising: one or more processors; and a memory, wherein the memory is used to store executable instructions; the one or more processors are configured to implement the steps of the method described in the first aspect by executing the executable instructions. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The embodiments of the present invention are further described below with reference to the accompanying drawings, in which:

[0020] Figure 1 A schematic diagram of a process of a core particle selection method according to an embodiment of the present invention;

[0021] Figure 2 is a schematic diagram of a flow chart of a second genetic algorithm according to an embodiment of the present invention;

[0022] Figure 3 A schematic diagram of group mapping according to an embodiment of the present invention;

[0023] Figure 4 A schematic diagram of a crossover operation performed by a parent generation in a second genetic algorithm according to an embodiment of the present invention;

[0024] Figure 5 A schematic diagram of a mutation operation in a second genetic algorithm according to an embodiment of the present invention;

[0025] Figure 6 is a schematic diagram of a core particle assembly according to an embodiment of the present invention;

[0026] Figure 7 Schematic diagram of the application of the core particle selection method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below through specific embodiments in conjunction with the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0028] As mentioned in the background technology section, the prior art has the following difficulties in the design process from application to chiplet system adapted to the application: first, the information about the relevant chiplets can only be obtained in a scattered manner from the providers of each chiplet (such as sales, manufacturers, etc.), and this information is often incomplete and difficult to be directly used in the design of the chiplet system; second, even if the information about the chiplets provided by each provider is known, it is still difficult for the user to efficiently and high-quality design and determine the optimal chiplet system adapted to the application. In this regard, the inventors believe, after research, that the first problem can be solved by constructing a coregrain library in data form according to the specified coregrain library specifications, so that various coregrains and their description files can be stored in the coregrain library for design calls; for the second problem, semantic matching can be used to match languages ​​written in different code habits to recognizable languages, and then the application can be converted into a task data flow graph, and then based on the coregrain library and the task data flow graph, a group of optimal coregrain combinations can be selected from a variety of coregrain combinations for the application, and a group of task grouping mapping schemes with the best (global) performance indicators can be determined based on the optimal coregrain combination, and hierarchical optimization can be performed from the coregrain combination layer and the task grouping mapping scheme level under the coregrain combination to improve the efficiency and quality of coregrain selection.

[0029] According to one embodiment of the present invention, see Figure 1 , a core particle selection method is provided, comprising steps S1, S2, S3, S4 or a combination thereof. In order to better understand the present invention, each step is described in detail below in conjunction with specific embodiments.

[0030] Step S1: Obtain a coregear library in data form constructed according to a specified coregear library specification, which contains a variety of coregears and their description files.

[0031] According to an embodiment of the present invention, the implementer can construct the core particle library specification in advance, and the specification needs to specify the rules / standards for warehousing. In this regard, when each core particle provider needs to put its core particle product into the warehouse, it needs to provide the relevant core particles (models) and their description files according to the specification.

[0032] According to another embodiment of the present invention, the implementer may also use the designated "Coregrain Library Standard" (if any) as the coregrain library specification.

[0033] According to an embodiment of the present invention, the coregrain library specification specifies the deliverables of the coregrain library, and these deliverables constitute the description file of the coregrain. The description file includes: a physical model, a behavioral model and / or a performance model. Among them:

[0034] Optionally, the physical model includes the length, width, area, and manufacturing cost of the core particle. Of course, the physical model can also include other sub-items, such as the definition of IO information. With this information, the user can complete the selection of the core particle based on the occupied area and manufacturing cost, and the layout on the reconfigurable silicon substrate based on the length, width, and IO information.

[0035] Optionally, the behavior model includes the definition of the core particle's internal architecture, mapping space constraints, and semantic matching rules. The core particle's internal architecture includes a multi-level storage structure and a PE array structure. When mapping tasks, subgraph storage constraints are made according to the multi-level storage structure, and data flow scheduling is made according to the PE array structure. Mapping space constraints refer to some constraints that hardware has to impose on software scheduling due to the hardware's own structure. They can also be some mapping constraints that are artificially suggested to achieve better performance software scheduling. Of course, the behavior model can also include other sub-items, such as a D2D (Die to Die) interface. The D2D interface can be a unified UCIE standard interface. In order to achieve the interconnection of any two core particles, this also requires the core particle provider to provide a D2D interface that complies with the UCIE standard into the library.

[0036] Optionally, the performance model includes a core-grain functional model and / or a performance lookup table, which includes the operators supported by the core-grain and the delay and power consumption corresponding to the operation on the core-grain. If the core-grain provider can provide a core-grain functional model written in a language such as SystemC, then the performance of the core-grain can be easily modeled; if the core-grain provider does not provide it, but only provides a black box core-grain, then the core-grain provider is required to attach a performance lookup table as a performance model.

[0037] Constructing the performance model of the core library is a big challenge. Because without the functional model written in SystemC, it is difficult for the core provider to accurately provide the performance lookup table required for different tasks. For a black box NPU core, necessary information such as whether it is a single core with a single accelerator or a single core with multiple accelerators and the basic architecture must be provided. In this case, the NPU core can be packaged, and then test cases can be generated. Running multiple cases can obtain the fitted delay and power consumption model, which is relatively inaccurate.

[0038] Schematically, the NPU chip performance model is constructed in advance based on the hardware structure. It is a single accelerator based on the NVDLA architecture (or EYERISS architecture, ShiDianNao architecture) on a single chip. The Timeloop simulator (or SCALE-Sim simulator) is used to accurately model the delay and power consumption of a single operator on the chip.

[0039] Schematically, the CGRA chiplet performance model is constructed in advance based on the hardware structure. It is a single accelerator based on the HyCUBE architecture (or Stdnoc architecture) on a single chiplet. The Morpher simulator (or CGRAME simulator) is used to accurately model the latency and power consumption of a single operator on the chiplet.

[0040] Schematically, the CPU chip performance model is constructed in advance based on the hardware structure. It is a processor based on the RISC-V architecture (or ARM architecture) with a vector operation unit. The GEM5 simulator is used to accurately model the delay and power consumption of a single operator on the chip.

[0041] Of course, implementers may also add other types of core particles, such as: GPU core particles, systolic array core particles, storage core particles and / or IO core particles, etc.

[0042] Optionally, the coregrain library specification also requires that each coregrain provider must fill in the semantic matching sub-rule corresponding to the coregrain when entering the coregrain library. The collection of semantic matching sub-rules of all coregrains in the coregrain library is the semantic matching rule. In addition, in order to ensure the competitiveness of coregrains, the coregrain provider will continue to update the library of semantic matching rules. In this way, even if new applications appear, as long as the semantic matching rules are updated, the problems of new applications can be solved.

[0043] In addition, the coregrain library specification in this embodiment only lists the abstract model for selecting coregrains. In real scenarios, in order to guide coregrain users to integrate coregrains into systems, more detailed coregrain deliverables may also be provided, for example, including the following deliverables or a combination thereof:

[0044] 1) Thermal model, guiding chiplet users to perform hot spot analysis on chiplets;

[0045] 2) Library Exchange Format (LEF file), which defines the two-dimensional physical size, layer and electrical network name of each chip bump pin;

[0046] 3) Hardware description language (e.g. Verilog or SystemVerilog) to physical pin mapping file, mapping the chiplet functional pins to physical pins;

[0047] 4) Power and ground, description of the chip power and ground connections;

[0048] 5) Peripheral interconnect model, which specifies the interconnect resistance and capacitance used when the physical I / O port of the chiplet is connected to its internal gate circuit;

[0049] 6) Signal integrity model, used for board-level signal integrity analysis, to help analyze high-speed D2D interfaces (Die-to-DIe);

[0050] 7) Eye diagram specifications, including: eye width and eye height;

[0051] 8) Chip boundary scan test model for low-speed IO and interconnect testing inside and outside the package at system and board levels;

[0052] 9) Chiplet ATPG vectors, generated by DFT test tools, test the internal logic of the chiplet through the chiplet IO pins; chiplet ATPG vectors refer to test vectors used for automatic test pattern generation (ATPG) in chiplet design. These vectors are used to verify the functional correctness of the chiplets and detect manufacturing defects. DFT test tools are a type of electronic design automation (EDA) tool specifically designed to support design testability (DFT). These tools help generate, execute, and analyze test patterns by inserting test logic during the design phase, ultimately improving the test efficiency of the chip during manufacturing and use.

[0053] 10) Chiplet MBIST vectors, generated by the DFT test tool, test the internal memory of the chiplet through the chiplet IO pins; the chiplet MBIST vector refers to a set of test vectors used for memory built-in self-test (MBIST), which are used to test the memory module in the chiplet design to ensure its correct function and detect possible manufacturing defects.

[0054] 11) Packaging deliverables, providing information to describe the packaging technology for integrating the chip into the system and documenting the chip-compatible packaging assembly suppliers / processes.

[0055] Therefore, the coreparticle provider (or coreparticle library builder) can store various coreparticles (it should be understood that they are actually coreparticle models corresponding to coreparticles (products)) according to the coreparticle library specifications, and the construction of the coreparticle library is completed.

[0056] Step S2: Obtain the application to be accelerated, and use the preset semantic matching rules to convert the application into a task data flow graph, which includes operators and their dependencies.

[0057] According to an embodiment of the present invention, the application refers to a software program, including source code of the application. Preferably, the source code of the application includes multiple layers of nested loops and control logic.

[0058] According to one embodiment of the present invention, the semantic matching rule includes a rule for converting each sub-code in the source code into a unified code block (intermediate code block). Thus, the source code of the application is converted into a unified code block. In addition, the semantic matching rule also includes a rule for converting the unified code block (intermediate code block) into the running code (primitive) supported by the core grain; so as to facilitate matching when using the real core grain product to process the application later. Thus, efficient conversion between the application and the primitives supported by the core grain can be achieved. Schematically, the semantic matching is completed during the code compilation process, and the source code described in programming languages ​​such as C / C++ or Fortran is converted to the corresponding dialect under the MLIR framework, and then the dialect is downgraded and optimized, detected and extracted, and finally a code block that meets the core grain semantic matching rule is generated. With the help of the semantic matching rule, the conversion process in step 2 refers to splitting the task application into several operators, for example, a convolution layer is an operator, a matrix multiplication represents an operator, a reduction operation represents an operator, etc. Nodes can be used to represent operators, and edges can be used to represent the dependencies between operators, that is, the application is converted into a task data flow graph. Therefore, if the coregrain user wants to complete the hardware design adapted to the real application, he only needs to input the real application source code written in any language, automatically complete the semantic matching of the source code, convert it into a unified code block that conforms to the coregrain semantic matching rules in the coregrain library, and construct the task data flow graph.

[0059] According to an example of the present invention, the real application can be set according to the needs of the implementer. For example, in this example, it can be a robot grasping program, involving subtasks such as collision detection and motion planning. In this example, for the NPU core, the supported code is generally a loop nested code structure of a convolutional layer, such as the convolutional layer and the fully connected layer in the SSD512 algorithm used for target detection in the robot grasping task. In the semantic matching process, it will be converted into the code format specified by the semantic matching rule of the NPU core, and in the subsequent task group scheduling, this code can be mapped to the NPU core. However, if it is a code that is not supported by the NPU core in the robot grasping task, such as a loop nested code with control flow, it is impossible to perform semantic matching of the NPU core, and in the subsequent task group scheduling, this code cannot be mapped to the NPU core. In this example, the semantic matching principle for the CRGA core and the CPU core is the same as that for the NPU core. The task data flow graph finally obtained is a directed acyclic graph, including multiple nodes and edges.

[0060] Step S3: According to the core-grain library and the task data flow diagram, multiple group mappings are performed for each core-grain combination in the multiple core-grain combinations for the application, and the performance indicators of each task group mapping scheme are calculated, and the optimal core-grain combination is determined according to the performance indicators of the task group mapping scheme, wherein the task group mapping scheme includes multiple mapping relationships, each mapping relationship includes an operator in the application, the group serial number of the operator, and the operation core-grain assigned to the operator.

[0061] Step S3 includes using multiple genetic algorithms to optimize from the level of core particle combination and the level of task grouping mapping scheme, including: S31, at the core particle combination level, using a first genetic algorithm to iteratively optimize the core particle combination; S32, at the task grouping mapping scheme, using a second genetic algorithm to iteratively optimize the task grouping mapping scheme based on the core particle combination obtained by the first genetic algorithm, including: optimizing the grouping of each operator and the assigned core particles.

[0062] According to one embodiment of the present invention, the first genetic algorithm optimizes the core particle combination, and adjusts the type and quantity of core particles in the core particle combination according to the indicators returned by the second genetic algorithm. The core particle combination is encoded as [m1, m2, m3...mN], where 1-N corresponds to the 1st to Nth core particles, and m1, m2, m3...mN represents the number of 1, 2, 3...N core particles. It should be understood that when the number of a certain core particle in m1, m2, m3...mN is 0, it is equivalent to not using this type of core particle, so that the type and quantity of core particles are optimized by optimizing the core particle combination. Preferably, the first genetic algorithm includes: S311, based on the coreparticle types contained in the coreparticle library, randomly generate a set of multiple initialized coreparticle combinations that meet the area constraint, and calculate the fitness of each initialized coreparticle combination, wherein the coreparticle combination includes the number of various coreparticles, and the fitness refers to the performance index corresponding to the coreparticle combination; S312, according to the current set of coreparticle combinations and the fitness corresponding to each coreparticle combination therein, select multiple coreparticle combinations in order of fitness from small to large to form a first parent generation set, randomly select multiple pairs of parents from the first parent generation set for crossover, and obtain multiple initial first offspring; S313, perform a first mutation operation on the multiple initial first offspring at a preset mutation rate to obtain multiple second offspring subjected to the mutation operation; S314, respectively input the coreparticle combinations corresponding to the multiple second offspring into the second genetic algorithm to calculate the fitness corresponding to the coreparticle combination, and repeat steps S312-S314 until the preset requirements are met. Preferably, the first mutation operation contains one or more mutation modes, wherein the mutation modes contained in the first mutation operation include: changing the number of a certain coregrain in the coregrain combination at a preset first mutation rate; and / or exchanging the number of two coregrains in the coregrain combination at a preset second mutation rate.

[0063] According to an example of the present invention, there are three types of core particles in the core particle library, namely, NPU core particles, CGRA core particles and CPU core particles. In this example, the core particle combination is encoded as [m1, m2, m3], where m1 / 2 / 3 represent the number of NPU core particles, CGRA core particles and CPU core particles respectively. The schematic process is as follows:

[0064] 1) First, 10 initial core particle combinations are randomly generated to check whether the area constraint is satisfied; if not, the fitness is set to infinity; if satisfied, the second genetic algorithm is used to calculate the initial fitness.

[0065] 2) Select the top 1 / 2 (or a preset number) of core particle combinations with small fitness as the parent generation, and cross any two parent generations. For example, cross [m1, m2, m3] and [n1, n2, n3] to get two offsprings [m1, n2, m3] and [n1, m2, n3]. Repeat 5 times to generate 10 core particle combinations as offspring.

[0066] 3) Perform mutation operations on the offspring at a certain mutation rate. There are two types of mutation operations: a) mutating the number of a certain core particle, for example, [m1, n2, m3] may mutate to [m1, n2, p3]; b) exchanging the number of two core particles, for example, [m1, n2, m3] may mutate to [m1, m3, n3].

[0067] 4) Enter the second genetic algorithm to calculate the fitness of the 10 core particle combinations respectively, select the core particle combination with the smallest fitness, and determine whether to iterate 10 times. If so, the optimization ends and the core particle combination with the smallest fitness is output; if not, the core particle combination with the first 1 / 2 of the smallest fitness is selected again to repeat the above steps 2) to 4). It should be understood that in addition to the number of iterations, other requirements can also be used as the preset requirements, such as whether the change range of fitness is less than a preset threshold for a preset number of consecutive times.

[0068] According to an embodiment of the present invention, the second genetic algorithm performs task group mapping on a universal core particle combination. That is, at the task group mapping scheme level, the second genetic algorithm is used to iteratively optimize the task group mapping scheme according to the core particle combination obtained by the first genetic algorithm, including: optimizing the grouping of each operator and the assigned core particles.

[0069] According to an optional embodiment of the present invention, the second genetic algorithm includes performing the following operations for each core-grain combination obtained: S321', randomly generating X initialized task grouping mapping schemes that meet preset constraints according to the task data flow graph and the core-grain combination, and calculating the fitness of each scheme; S322', selecting a predetermined proportion (such as the first 1 / 2 or the first 1 / 3, etc.) of the task grouping mapping schemes in order of the fitness of the scheme from small to large to form a second parent generation set, randomly selecting X pairs of parents from the second parent generation set, performing a crossover operation on each pair of parents to obtain an initial third offspring, and summarizing to obtain X initial third offspring; S323', performing a second mutation operation on the X initial third offspring at a predetermined mutation rate to obtain X fourth offspring after the mutation operation; S324', calculating the fitness of the task grouping mapping scheme corresponding to each fourth offspring, and taking the minimum fitness among the X fourth offspring as the fitness corresponding to the core-grain combination.

[0070] According to another optional embodiment of the present invention, the second genetic algorithm includes performing the following operations for each core particle combination obtained: S321", randomly generating X initialized task grouping mapping schemes that meet the preset constraints according to the task data flow graph and the core particle combination, and calculating the fitness of each scheme; S322", selecting a predetermined number (such as Xa or more) in the order of the fitness of the scheme from small to large wait, The task grouping mapping schemes (denoted as rounded down) are used to form a second parent generation set, N pairs of parents (N≠X and N>X) are randomly selected from the second parent generation set, and a crossover operation is performed on each pair of parents to obtain an initial third offspring, and N initial third offspring are obtained after aggregation; S323", a second mutation operation is performed on the N initial third offspring at a predetermined mutation rate to obtain N fourth offspring after the mutation operation; S324", the fitness of each fourth offspring corresponding to the task grouping mapping scheme is calculated, and the minimum fitness among the N fourth offspring is taken as the fitness corresponding to the core particle combination.

[0071] Preferably, the preset constraints in the second genetic algorithm include: the subgraph dependency relationship cannot form a loop, and the subgraph size cannot exceed the cache of the core particle.

[0072] Optionally, the fitness is the weighted sum of total delay, power consumption, area, and cost. Alternatively, the fitness is the weighted sum of total delay, power consumption, and area. The total delay consists of two parts: the computation time of the subgraph on the core particle and the time to transfer data between core particles.

[0073] It should be understood that the fitness corresponding to the core particle combination can also be obtained in other ways, for example, it can also be: the average fitness of the fitness of multiple fourth-generation corresponding task grouping mapping schemes, or the average value without the highest fitness and the lowest fitness. The implementer can also adopt a customized method, and the present invention does not impose any limitation on this.

[0074] Preferably, the process of performing a crossover operation on each pair of parent generations to obtain an initial third offspring generation includes: extracting existing subgraphs as genetic fragments from the task grouping mapping scheme of the pair of parent generations to form a genetic fragment set, each genetic fragment including at least one operator; setting each operator in the task data flow graph as an undetermined operator to form an undetermined operator set; based on the genetic fragment set, the undetermined operator set and the task data flow graph, using the genetic fragments in the genetic fragment set to generate the initial third offspring generation, including: selecting a current operator from the undetermined operator set in turn according to the execution order of the operator in the task data flow graph; for the current operator, randomly copying a genetic fragment containing the current operator from the genetic fragment set to implement the operator, and removing all operators included in the selected genetic fragment from the undetermined operator set and setting them as determined operators, wherein, if the currently copied genetic fragment includes a determined operator, the undetermined operator in the currently copied genetic fragment is split out to form a new genetic fragment; when the undetermined operator set is an empty set, combining the genetic fragments where the determined operators are located to obtain the initial third offspring generation.

[0075] According to one embodiment of the present invention, see Figure 2 , the execution process of the second genetic algorithm includes:

[0076] a) Obtain the task data flow graph and a set of core particle combinations, and randomly generate an initial population, for example, generate n sets of triples (v, gid, cid) for grouping and assigning core particles to each operator, where n is the population size.

[0077] b) Determine whether all preset constraints are met. If not, the fitness is set to infinity.

[0078] c) Calculate the fitness of n populations respectively, and select the first 1 / 2 individuals with the smallest fitness as parents.

[0079] d) Repeat n times to generate offspring by crossover from the parent generation, for example, each time randomly select two individuals from the parent generation to generate offspring by crossover.

[0080] e) Perform mutation operations at a certain mutation rate, for example: perform five mutation operations at five mutation rates on the generated n offspring, recalculate the fitness, and select the individual with the smallest fitness.

[0081] f) Determine whether the maximum number of iterations has been reached. If so, repeat the be operation until the number of iterations reaches m. A new population can be generated through the above operation, where m is the maximum number of iterations.

[0082] According to an example of the present invention, this example takes NPU core particles, CGRA core particles and CPU core particles as examples, combined with Figure 2-4 An exemplary implementation of the second genetic algorithm is described. The purpose of the method of the present invention is to hide the underlying implementation details as much as possible from the designer of the chiplet integration system (chiplet user), and to perform task group mapping for various chiplets in a universal manner. This requires that the semantic matching in the aforementioned process can identify the code blocks that can be executed by the NPU chiplet, CGRA chiplet and CPU chiplet, and then obtain the operators that support the operation of each. Under this premise, the performance optimization of task group mapping is performed.

[0083] Combination Figure 3 The left part of the diagram shows that Figure 3 The circled numbers 1-7 represent the node numbers corresponding to the operators, each dotted circle represents a subgraph, and A, B, and C represent the codes of the three computing core particles. The principle of task group mapping for performance optimization is that when operators 1 and 3 are divided into the same group and mapped to the same core particle, the output of operator 1 can be directly used for the calculation of operator 3. Compared with operators 1 and 3 being divided into different groups or different core particles, the two parts of delay overhead and power consumption overhead of storing the output result of operator 1 and loading the output of operator 1 to the input of operator 3 are omitted.

[0084] In addition, when the operator increases, the core cache will also be required to increase. There is a trade-off between computing resources and storage resources on the core. If the operator is particularly large, it is necessary to consider splitting the operator.

[0085] For the second-order genetic algorithm, in this example, the operator, group, and core are encoded as a set of triples (v, gid, cid), where v represents the node number, gid represents the group number, and cid represents the core code of the operation core. Figure 3 As shown in the right part of , the first row indicates that task operator 1 is divided into group 1 and mapped to core particle A operation, where the number of groups cannot be greater than the number of core particles. The schematic process is as follows:

[0086] 1) First, input the task data flow graph obtained by S2 and a set of core particle combinations obtained by the first genetic algorithm, randomly generate 10 initial task grouping mapping schemes, and determine whether the two preset constraints are satisfied. If not, the fitness is set to infinity; if satisfied, the fitness is calculated according to the aforementioned fitness calculation function. The two preset constraints are:

[0087] a) Determine whether the dependency relationship between the divided subgraphs forms a loop. If a loop is formed, the two subgraphs will wait endlessly for each other to complete during task execution, thus forming a deadlock;

[0088] b) Determine whether the sub-graph size exceeds the cache of the chip. If so, the sub-graph needs to be split. Figure 3 In the left part of FIG, core A is an NPU core, and operators 1 and 3 are convolution layers. For example, the core global cache needs to store the input feature map, convolution kernel weight, and output feature map of operator 1 and the input feature map and convolution kernel weight of operator 3. The reason why the output feature map of operator 3 does not need to be stored here is that the output feature map of operator 3 can be directly transmitted to core C or written back to DRAM.

[0089] In addition, since the performance model in the chiplet library only includes the delay and power consumption of a chiplet completing an operator operation, when evaluating the total delay and power consumption in fitness, the transmission time of the operator output data across groups also needs to be considered. If it crosses groups but not across chiplets, the transmission time is the memory access time between the chiplet and the DRAM; if it crosses groups and across chiplets, the transmission time is the communication time between the two chiplets.

[0090] 2) Select the first 1 / 2 task grouping mapping schemes with small fitness as the parents, and select any two parents to cross. The crossover rule is: randomly select a parent class for each undecided operator to reproduce the corresponding subgraph. If the copied subgraph contains determined operators, a new subgraph that does not contain these operators is split out. For example, in Figure 4 In the example, the determined operator 5 first selects the genetic fragment of parent 1, and the undecided operator 6 selects the genetic fragment of parent 2. Then the offspring will split the subgraph of parent 2 excluding operator 5 to form a new subgraph. The cycle is repeated 10 times to generate 10 task grouping mapping schemes as offspring.

[0091] 3) Perform mutation operations on the offspring at a certain mutation rate;

[0092] 4) According to the fitness calculation function: the weighted sum of total delay, power consumption, area and cost, recalculate the fitness of the 10 task grouping mapping schemes under the current core particle combination, select the task grouping mapping scheme with the smallest fitness, and determine whether to iterate 10 times. If so, the optimization ends, outputs the task grouping mapping scheme with the smallest fitness and the fitness at this time as the fitness corresponding to the core particle combination; if not, repeat steps 2) to 4).

[0093] According to one embodiment of the present invention, the second mutation operation includes: mutation mode 1: changing the grouping of a certain operator; mutation mode 2: splitting a subgraph into two subgraphs; mutation mode 3: merging two subgraphs into one subgraph; mutation mode 4: mapping a subgraph to another core particle for operation; and mutation mode 5: exchanging the operation core particles of two subgraphs; or a combination of the above mutation modes. A subgraph refers to a set of operators assigned to an operation core particle, that is, a set of operators with the same grouping id. In addition, each mutation mode can independently set a corresponding mutation rate. The mutation rate of a mutation mode refers to the probability of the occurrence of the mutation mode. For example, the mutation rate of a mutation mode can be set to 0.01, and each time the corresponding probability function is used to determine whether the mutation occurs.

[0094] According to an example of the present invention, the following Figure 5 , the mutation method in the second mutation operation is schematically illustrated:

[0095] Figure 5 The circled numbers 1-7 represent the node numbers corresponding to the operators, each dotted circle represents a subgraph, and A, B, C, and D represent the codes of the four operation core particles; Figure 5 The z in the figure represents a schematic offspring, which will be used as the basis for the subsequent description of the variation.

[0096] For variant 1, see Figure 5 a in the example, operator 4 is classified as group 4 and mapped to core particle D to which group 4 belongs;

[0097] For variant 2, see Figure 5 For example, if we split the subgraph {2,4,5} into subgraph {2,5} and subgraph {4}, they belong to two different groups, and the mapped core particle remains unchanged, which is still the B core particle.

[0098] For variant 3, see Figure 5 In c, for example, the subgraph {1,3} and the subgraph {2,4,5} are merged into the subgraph {1,2,3,4,5}, which belong to the same group, and the mapped core particles are randomly selected from core particles A and B;

[0099] For variant 4, see Figure 5 For example, the subgraph {2, 4, 5} is mapped from core particle B to core particle C, and the grouping remains unchanged.

[0100] For variant 5, see Figure 5 For example, if we swap the operation core particles B and C of the subgraph {2,4,5} and the subgraph {6}, the grouping remains unchanged.

[0101] Optionally, according to the needs of the implementer, the specific mutation mode of the second mutation operation can be adjusted. For example, the second mutation operation includes the above mutation modes 1-5 or a combination thereof and mutation mode 6: splitting an operator into two operators.

[0102] According to an embodiment of the present invention, the fitness of the task group mapping scheme is the weighted sum of the total delay, power consumption, area and cost corresponding to the scheme. The fitness corresponding to the core particle combination is the minimum fitness among the fitness of each task group mapping scheme obtained according to the core particle combination.

[0103] S4. Output the optimal core particle combination and its performance indicators.

[0104] According to one embodiment of the present invention, the optimal core-grain combination is the core-grain combination on which the optimal task grouping mapping scheme depends, that is, the core-grain combination on which the task grouping mapping scheme with the minimum fitness depends. The performance index of the optimal core-grain combination is the performance index of the optimal task grouping mapping scheme, that is, the optimal performance index. Finally, multiple sub-indicators can also be output, such as: total delay, power consumption, area and cost and their combinations. The optimal performance index refers to the minimum fitness, such as the minimum value of the weighted sum of total delay, power consumption, area and cost. In addition, step S4 can also output the optimal core-grain combination, the optimal task grouping mapping scheme and its performance index. Alternatively, as other alternative embodiments, S4 can also output the optimal core-grain combination and / or the optimal task grouping mapping scheme, but does not output the performance index of the optimal task grouping mapping scheme.

[0105] Indicatively, after completing the double genetic algorithm optimization in S3, the optimal combination of core particles for the real application input by the core particle user is obtained, which in this embodiment is: m NPU core particles, n CGRA core particles and p CPU core particles. Moreover, from the optimal combination of core particles, based on the existing core particle layout algorithm, the heterogeneous core particles can be reasonably laid out on the reconfigurable silicon substrate, and the area of ​​the entire core particle integration system can be optimized, and finally a hardware design scheme based on the core particle library for real applications is obtained, that is, a core particle integration system. The core particle integration system includes the type and number of core particles, the topology of interconnection between core particles, and the layout of core particles on the reconfigurable silicon substrate. The reconfigurable silicon substrate refers to pre-manufacturing micro-bumps on the silicon substrate to provide power supply, clock, IO signals, etc. for the core particles, and the core particles can be arbitrarily arranged on the silicon substrate.

[0106] In addition, the hardware design based on the core particle library in this embodiment is completed in the pre-silicon customization stage. The original ASIC-based method is very slow and requires chip design and tape-out. The emergence of core particles has accelerated this process, but there is a problem: the design of integrated chips based on core particles takes time, which can of course be solved by automatic selection, automatic layout and other means. At this time, the bottleneck becomes the software adaptation process. Therefore, based on the semantic matching method in this embodiment, the core particle user's code does not need to be modified in any way, and it can identify the code snippets in the application that can be accelerated by the core particle, and then automatically insert the code called by the accelerator, realizing the entire tool chain from software application to integrated core particles.

[0107] In addition, in the task group mapping of this embodiment, the optimization effect of spatially parallel operation of multiple operators on delay and power consumption is also considered. Figure 6 As shown in the figure, operator 4 and operator 5 are operated in parallel on core B. This spatial parallel operation can further explore the optimization space of the spatiotemporal graph and pipeline on a single core with multiple accelerators, reduce the waiting time caused by task dependency, and significantly improve performance.

[0108] Finally, an illustrative embodiment is provided to illustrate the application of the method of the present invention.

[0109] According to one embodiment of the present invention, see Figure 7 , providing a core particle selection method, comprising:

[0110] Input the real application source code, perform semantic matching, and obtain the task data flow graph;

[0111] Obtain a coreparticle library constructed according to preset coreparticle library standards, including physical models, behavioral models, and performance models;

[0112] Task grouping mapping is performed according to the task data flow diagram and the core-grain library to obtain the core-grain integrated system and its optimal performance parameters (optimal performance indicators).

[0113] In general, according to the method of the above embodiment, the chip provider delivers its own chip information and completes the construction of its own chip information in the real chip library. The designer of the chip integration system uses the method of the present invention and then combines semantic matching and task group mapping based on the abstract model in the above chip library to complete the selection of chip with optimal performance. For the designer, he is only responsible for inputting the real application source code, and does not need to pay attention to the details of the chip library or application code. He only needs to put forward the real application requirements to obtain the chip combination and optimal performance parameters that achieve the best application performance. The whole process is completed automatically, which improves the efficiency and quality of the selection of chip and the design of the chip integration system. Compared with the conventional coreparticle selection method, the method proposed by the inventor is based on the coreparticle model of the coreparticle library, which can complete the hardware design based on the coreparticle library for real applications, and has a high feasibility. At the same time, when the shipment volume is certain, the total cost and shipment time are greatly compressed; it can also optimize delay and power consumption through task grouping mapping, optimize area and share one-time costs through reasonable coreparticle layout and reusable silicon substrate, and ultimately achieve a significant reduction in the total delay, power consumption, area and cost of the coreparticle integrated system.

[0114] It should be noted that although the above describes the various steps in a specific order, it does not mean that the various steps must be executed in the above specific order. In fact, some of these steps can be executed concurrently or even in a different order as long as the required functions can be achieved.

[0115] The present invention may be a system, a method and / or a computer program product. The computer program product may include a computer-readable storage medium carrying computer-readable program instructions for causing a processor to implement various aspects of the present invention.

[0116] Computer readable storage medium can be a tangible device that holds and stores instructions used by an instruction execution device. Computer readable storage medium can include, for example, but is not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. More specific examples (non-exhaustive list) of computer readable storage medium include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disk read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device, for example, a punch card or a protruding structure in a groove on which instructions are stored, and any suitable combination thereof.

[0117] The embodiments of the present invention have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or technical improvements in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A core particle selection method, characterized in that: Includes steps: S1, obtaining a coreparticle library in data form constructed according to a specified coreparticle library specification, which contains a plurality of coreparticles and description files thereof; S2. Obtain the application to be accelerated, and convert the application into a task data flow graph including operators and their dependencies using a preset semantic matching rule; S3. According to the core-particle library and the task data flow diagram, multiple group mappings are performed for each core-particle combination in the multiple core-particle combinations for the application, and the performance indicators of each task group mapping scheme are calculated. The optimal core-particle combination is determined according to the performance indicators of the task group mapping scheme, wherein the task group mapping scheme includes multiple mapping relationships, each mapping relationship includes an operator in the application, the group serial number of the operator, and the operation core-particle assigned to the operator.

2. The method according to claim 1, characterized in that Step S3 includes using multiple genetic algorithms to optimize from the level of core particle combination and the level of task group mapping scheme, including: S31. At the core-particle combination level, the core-particle combination is iteratively optimized using the first genetic algorithm; S32. At the task grouping mapping scheme level, the task grouping mapping scheme is iteratively optimized using a second genetic algorithm based on the core particle combination obtained by the first genetic algorithm, including: optimizing the grouping of each operator and the assigned operation core particles.

3. The method according to claim 2, characterized in that The first genetic algorithm includes: S311, based on the types of core particles contained in the core particle library, randomly generate a set of multiple initialized core particle combinations that meet the area constraint, and calculate the fitness of each initialized core particle combination, wherein the core particle combination includes the number of various core particles, and the fitness refers to the performance index corresponding to the core particle combination; S312, according to the current set of core particle combinations and the fitness corresponding to each core particle combination, multiple core particle combinations are selected in order of fitness from small to large to form a first parent generation set, and multiple pairs of parents are randomly selected from the first parent generation set for crossover to obtain multiple initial first child generations; S313, performing a first mutation operation on the multiple initial first offspring at a preset mutation rate to obtain multiple second offspring that have undergone the mutation operation; S314, input the core particle combinations corresponding to the multiple second offspring into the second genetic algorithm to calculate the fitness corresponding to the core particle combination, and repeat steps S312-S314 until the preset requirements are met.

4. The method according to claim 3, characterized in that: The first mutation operation includes one or more mutation modes, wherein the mutation modes included in the first mutation operation include: Changing the quantity of a certain coreparticle in the coreparticle combination; and / or The number of two core particles in the exchange core particle combination.

5. The method according to claim 3 or 4, characterized in that: The second genetic algorithm includes performing the following operations for each core particle combination obtained: S321, randomly generate multiple initialized task grouping mapping schemes that meet preset constraints according to the task data flow graph and the core particle combination, and calculate the fitness of each scheme; S322, selecting multiple task grouping mapping schemes in order of fitness from small to large to form a second parent generation set, randomly selecting multiple pairs of parents from the second parent generation set, performing a crossover operation on each pair of parents to obtain an initial third child generation, and obtaining multiple initial third children generations after aggregation; S323, performing a second mutation operation on the multiple initial third offspring at a predetermined mutation rate to obtain multiple fourth offspring that have undergone the mutation operation; S324, calculating the fitness of each task grouping mapping scheme corresponding to the fourth child generation, and determining the fitness corresponding to the core particle combination based on the fitness corresponding to multiple fourth child generations.

6. The method according to claim 5, characterized in that The process of performing a crossover operation on each pair of parent generations to obtain an initial third child generation includes: Extracting existing subgraphs from the task grouping mapping scheme of the pair of parents as genetic fragments to form a set of genetic fragments, each of which includes at least one operator; Set each operator in the task data flow graph as an undetermined operator to form an undetermined operator set; Based on the genetic fragment set, the undetermined operator set and the task data flow graph, the genetic fragments in the genetic fragment set are used to generate the initial third offspring, including: According to the execution order of operators in the task data flow graph, a current operator is selected from the undecided operator set in turn; For the current operator, a genetic segment containing the current operator is randomly copied from the genetic segment set to implement the operator, and all operators included in the selected genetic segment are removed from the undetermined operator set and set as determined operators, wherein if the currently copied genetic segment includes a determined operator, the undetermined operators in the currently copied genetic segment are split out to form a new genetic segment; When the set of undetermined operators is an empty set, the genetic fragments where the determined operators are located are combined to obtain the initial third offspring.

7. The method according to claim 5, characterized in that The second mutation operation includes: Mutation method 1: Change the grouping of a certain operator; Variation 2: Split a subgraph into two subgraphs; Variation 3: Merge two subgraphs into one subgraph; Variation 4: Map a subgraph to another core particle for operation; and Variation 5: Exchange the computational cores of the two subgraphs; Or a combination of the above variations.

8. The method according to claim 5, characterized in that The fitness of the task grouping mapping scheme is the weighted sum of the total delay, power consumption, area and cost corresponding to the scheme.

9. A computer program product, comprising a computer program / instruction, which, when executed by a processor, implements the steps of the method according to any one of claims 1 to 8.

10. An electronic device, characterized in that: include: one or more processors; as well as A memory, wherein the memory is used to store executable instructions; The one or more processors are configured to implement the steps of the method of any one of claims 1-8 by executing the executable instructions.

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