FPGA design method based on EDA software system and EDA software system

Abstract

The invention relates to the technical field of FPGA design, in particular to an FPGA design method based on an EDA software system and the EDA software system.The method comprises the steps that the EDA software system is started, a project path is set, a user source code is created, a comprehensive process module is started, a comprehensive netlist is obtained, a layout and wiring process module is started, layout and wiring operation is executed on the comprehensive netlist, and a layout and wiring netlist is obtained; the method comprises the following steps: acquiring a design bit stream file, acquiring a target FPGA chip and information of the target FPGA chip, querying a compatible result of the information of the target FPGA chip and the design bit stream file in a database, and if the compatible result of the information of the target FPGA chip and the design bit stream file is confirmed to be compatible, downloading the design bit stream file to the target FPGA chip. The method comprises the steps of obtaining adaptive FPGA equipment and downloading operation process information, storing the downloading operation process information to obtain a downloading operation log, and completing FPGA design based on an EDA software system based on the adaptive FPGA equipment and the downloading operation log. The design efficiency can be improved, and the design process can be optimized.

Description

Technical Field

[0001] The present invention relates to the field of FPGA design technology, and in particular to an FPGA design method based on an EDA software system and an EDA software system. Background Art

[0002] EDA software system refers to a system that optimizes the design process and improves design efficiency through innovative algorithms and modern user interfaces. FPGA is a flexible and powerful digital circuit that is widely used in many fields such as communication, data processing, image and signal processing. Its main advantage is that it can program logical functions at the hardware level, thereby providing high-performance customized hardware solutions for specific applications.

[0003] With the advancement of technology and changes in market demand, traditional EDA tools can no longer fully meet the needs of modern FPGA design. Especially in the process of program writing, synthesis, layout and routing, and downloading programs to FPGA chips, designers face many challenges, such as design optimization, timing analysis, resource management, and power consumption control. These challenges require EDA tools to not only provide an efficient design process, but also be highly user-friendly and flexible to support rapid design iterations and complexity management. Summary of the invention

[0004] The present invention provides an FPGA design method based on an EDA software system and an EDA software system, the main purpose of which is to improve design efficiency and optimize the design process.

[0005] To achieve the above object, the present invention provides an FPGA design method based on an EDA software system, comprising: Receive FPGA design instructions, start a pre-built EDA software system according to the FPGA design instructions, set a project path according to the started EDA software system, and create user source code according to the project path, wherein the EDA software system includes: intelligent parser, download process management, database, comprehensive process module and layout and routing process module; Start the integrated flow module, and obtain the integrated netlist based on the started integrated flow module and the user source code; Starting the layout and routing process module, and using the started layout and routing process module to perform layout and routing operations on the integrated netlist to obtain a layout and routing netlist, wherein the layout and routing process module includes: an advanced layout algorithm and a path planning algorithm; Obtaining a design bitstream file according to the layout and routing netlist, wherein the design bitstream file is a binary file, and the design bitstream file includes: all information required to configure the FPGA; Obtaining information of a target FPGA chip and a target FPGA chip, querying the database for a compatibility result between the information of the target FPGA chip and the design bitstream file, wherein the compatibility result includes: compatible and incompatible; If it is confirmed that the information of the target FPGA chip is compatible with the compatibility result of the design bitstream file, the design bitstream file is downloaded to the target FPGA chip to obtain the adapted FPGA device and the download operation process information, wherein the download operation process information includes: time, date, device information and download result; The pre-built log file is used to save the download operation process information to obtain the download operation log. Based on the adapted FPGA device and the download operation log, the FPGA design based on the EDA software system is completed.

[0006] Optionally, the step of obtaining a comprehensive netlist based on the started comprehensive flow module and the user source code includes: Reading the user source code based on the started comprehensive flow module, and parsing the read user source code using the intelligent parser to obtain source code data, wherein the intelligent parser includes: Verilog and SystemVerilog; Performing syntax check on the source code data to obtain verification source code data, and performing data initialization on the verification source code data to obtain initialization source code data; Performing a technology mapping operation on the initialization source code data and standardizing the structure of the mapped initialization source code data to obtain a standard structure source code, wherein the technology mapping operation includes: DSP, storage mapping, register mapping, LUT mapping and other device mappings; Using a pre-built optimization algorithm to perform optimization operations on the standard structure source code to obtain an initial optimized circuit, wherein the optimization operations include: circuit optimization and clock optimization, wherein the optimization algorithm includes: constant propagation, dead code elimination, logic simplification, and area and speed trade-off optimization; Performing a final inspection operation on the initial optimized circuit to obtain a final inspection result, and when the final inspection result of the initial optimized circuit is a preset passing result, confirming the initial optimized circuit as an optimized circuit, wherein the final inspection operation includes: circuit connection inspection, drive unit inspection, hierarchy inspection, and timing inspection; Generate a synthetic netlist based on the optimized circuit.

[0007] Optionally, the using the started layout and routing process module to perform layout and routing operations on the integrated netlist to obtain the layout and routing netlist includes: The integrated netlist is read and parsed using the started placement and routing flow module to obtain a logic unit set; Performing a physical mapping phase on the logical unit set to obtain a physical device set with a determined connection relationship, wherein the physical mapping phase includes: device mapping and local connection; Performing layout phase operations on the physical device set, determining the spatial position of each physical device in the physical device set, obtaining an optimal layout set, and performing device position check on each optimal layout set in the optimal layout set to obtain a standard optimal layout set; Get the standard thermal distribution map of the FPGA design chip; Performing routing phase operations on the standard optimal layout set according to the standard heat distribution map to obtain the optimal layout and routing set, wherein the routing phase operations include: initializing the model, forward routing path finding, reverse routing check, netlist connection check and timing analysis; Generate a place-and-route netlist based on the optimal place-and-route set.

[0008] Optionally, performing a physical mapping phase on the logical unit set to obtain a physical device set with a determined connection relationship includes: Obtain the physical location set of the target FPGA chip, and perform the following operations on each logic unit in the logic unit set: Mapping the logical unit to a target physical location in the physical location set, wherein the logical unit corresponds to the physical location one by one; The target physical locations are summarized to obtain a set of physical devices with a determined connection relationship corresponding to the logical unit set.

[0009] Optionally, performing a layout phase operation on the physical device set to determine a spatial position of each physical device in the physical device set to obtain an optimal layout set includes: Constructing a layout equation according to the physical device set, obtaining a clock constraint, and grouping the logic unit set according to the clock constraint to obtain a plurality of logic unit groups; Extract one logical unit group from multiple logical unit groups in turn, and perform the following operations on each of the extracted logical unit groups: Utilizing the layout equation, advanced layout algorithm and path planning algorithm to perform layout analysis on the logic unit group to obtain a suboptimal layout, wherein the advanced layout algorithm includes: simulated annealing, genetic algorithm and particle swarm optimization; According to the preset key component positions, the suboptimal layout is constrained to obtain the optimal layout; The optimal layout is summarized and the spatial position of each physical device in the physical device set is determined to obtain the optimal layout set corresponding to the multiple logic unit groups.

[0010] Optionally, obtaining a standard thermal distribution map of the FPGA design chip includes: Use the EDA software system to simulate the initial thermal distribution map of the FPGA design chip, and compare the effects of the initial thermal distribution map with the preset thermal distribution map; If the initial thermal distribution map does not meet the preset thermal distribution map effect, the hot spot area is obtained according to the initial thermal distribution map, and the layout and wiring of the hot spot area are adjusted until the initial thermal distribution map meets the preset thermal distribution map effect to obtain a standard thermal distribution map.

[0011] Optionally, downloading the design bitstream file to a target FPGA chip to obtain information about an adapted FPGA device and a download operation process includes: Obtain multiple program download interfaces, including JTAG, USB and Ethernet; Extracting a target download interface from multiple program download interfaces and setting a custom download configuration, wherein the custom download configuration includes: download speed, selecting a target device and setting specific download parameters; Obtain the development environment according to the target FPGA chip, the target download interface and the custom download configuration, and start the download process management, wherein the download process management includes the process management mechanism; Use the process management mechanism to monitor the download process in real time and provide real-time feedback information, including download progress, error detection and problem diagnosis; Get advanced encryption, authentication, and download options, including automated and batch downloads; According to the development environment, download function options, advanced encryption and verification mechanisms, the design bitstream file is downloaded to the target FPGA chip to obtain an adapted FPGA device, and download operation process information is generated according to real-time feedback information.

[0012] Optionally, before downloading the design bitstream file to the target FPGA chip according to the development environment, download function options, advanced encryption and verification mechanism, the method further includes: If it is confirmed that error detection or difficult problem diagnosis appears in the real-time feedback information, the EDA software system is used to provide a solution, and the error detection or difficult problem diagnosis is solved according to the solution until the error detection or difficult problem diagnosis does not appear in the real-time feedback information.

[0013] To achieve the above object, the present invention further provides an EDA software system, comprising: A user source code creation module is used to receive FPGA design instructions, start the pre-built EDA software system according to the FPGA design instructions, set the project path according to the started EDA software system, and create user source code according to the project path, wherein the EDA software system includes: intelligent parser, download process management, database, comprehensive process module and layout and routing process module; A comprehensive process startup module is used to start the comprehensive process module and obtain a comprehensive netlist based on the started comprehensive process module and user source code; A layout and routing startup module is used to start the layout and routing process module, and use the started layout and routing process module to perform layout and routing operations on the integrated netlist to obtain a layout and routing netlist, wherein the layout and routing process module includes: an advanced layout algorithm and a path planning algorithm, and obtains a design bitstream file according to the layout and routing netlist, wherein the design bitstream file is a binary file, and the design bitstream file includes: all information required to configure the FPGA, obtains information of the target FPGA chip and the target FPGA chip, and queries the target FPGA chip information in the database for a compatibility result with the design bitstream file, wherein the compatibility result includes: compatible and incompatible; The design file download module is used to download the design bitstream file to the target FPGA chip if it is confirmed that the information of the target FPGA chip is compatible with the compatibility result of the design bitstream file, and obtain the adapted FPGA device and the download operation process information, wherein the download operation process information includes: time, date, device information and download results, and use a pre-built log file to save the download operation process information to obtain the download operation log, and complete the FPGA design based on the EDA software system based on the adapted FPGA device and the download operation log.

[0014] In order to solve the above problem, the present invention further provides an electronic device, the electronic device comprising: A memory storing at least one instruction; The processor executes the instructions stored in the memory to implement the above-mentioned FPGA design method based on the EDA software system.

[0015] In order to solve the above problem, the present invention also provides a computer-readable storage medium, in which at least one instruction is stored. The at least one instruction is executed by a processor in an electronic device to implement the above-mentioned FPGA design method based on the EDA software system.

[0016] The present invention is to solve the problem described in the background technology. The present invention receives FPGA design instructions, starts a pre-built EDA software system according to the FPGA design instructions, sets a project path according to the started EDA software system, and creates user source code according to the project path. The EDA software system includes: an intelligent parser, a download process management, a database, a comprehensive flow module, and a layout and wiring flow module. The EDA software system of the present invention integrates multiple functional modules such as an intelligent parser, a download process management, a database, a comprehensive flow module, and a layout and wiring flow module, and provides a comprehensive design platform, which is convenient for designers to perform various subsequent design operations and improve design efficiency and quality. User source code is the basis of FPGA design, and designers can Write code according to specific design requirements to achieve specific functions, provide original design data for subsequent synthesis and layout and routing, start the synthesis process module, and obtain the synthesis netlist based on the started synthesis process module and user source code. The synthesis process module of the present invention is a process that can convert high-level hardware description language code into gate-level logic that can be implemented on FPGA, convert abstract design description into specific hardware circuit representation, and provide an operable circuit model for subsequent layout and routing. The synthesis netlist is a hardware-level abstract representation of the design function, which contains the connection relationship and logical function between each logic unit in the design, provides accurate circuit information for layout and routing, and helps to optimize the performance and resource utilization of the design. Start the layout and routing process The layout and routing module is used to perform layout and routing operations on the integrated netlist by using the layout and routing process module after startup to obtain the layout and routing netlist, wherein the layout and routing process module includes: advanced layout algorithm and path planning algorithm. The layout and routing process module of the present invention adopts advanced layout algorithm and path planning algorithm, can physically implement the integrated netlist, reasonably place the logic circuit on the physical resources of the target FPGA chip, and plan the routing path of the signal to ensure that the design can work normally on the actual FPGA chip, obtain the design bitstream file according to the layout and routing netlist, wherein the design bitstream file is a binary file, and the design bitstream file includes: all information required to configure the FPGA. The present invention configures the FPGA to realize the functions expected by the designer. , is the key conversion of FPGA design from software description to hardware implementation, obtains the target FPGA chip and the target FPGA chip information, queries the target FPGA chip information and the design bitstream file compatibility result in the database, wherein the compatibility result includes: compatible and incompatible, the present invention can find out in advance whether the design bitstream file is compatible with the target FPGA chip by querying the database, avoids chip damage or program errors caused by incompatibility during the download process, and improves the reliability and stability of the design, if it is confirmed that the target FPGA chip information and the design bitstream file compatibility result are compatible, then the design bitstream file is downloaded to the target FPGA chip, and the adapted FPGA device and download operation process information are obtained, wherein,The download operation process information includes: time, date, device information and download results. The present invention ensures that the design can be correctly implemented on the target FPGA chip by determining the compatibility of the target FPGA chip information with the design bitstream file, converts the software design into actual hardware functions, and completes the ultimate goal of FPGA design. The download operation process information is saved using a pre-built log file to obtain a download operation log. Based on the adapted FPGA device and the download operation log, the FPGA design based on the EDA software system is completed. The present invention records the detailed information of each download operation through a log file, which is convenient for designers to track problems and analyze problems in the design process, while also meeting the requirements of auditing and quality control. Therefore, the present invention can improve design efficiency and optimize the design process. , BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A flowchart of an FPGA design method based on an EDA software system provided by an embodiment of the present invention; Figure 2 A module diagram of an EDA software system provided by an embodiment of the present invention; Figure 3 A schematic diagram of the structure of an electronic device for implementing the FPGA design method based on the EDA software system provided by an embodiment of the present invention.

[0018] Description of reference numerals: 1. Electronic device; 10. Processor; 11. Memory; 12. Bus; 100. EDA software system; 101. User source code creation module; 102. Comprehensive process start module; 103. Layout and routing start module; 104. Design file download module.

[0019] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0020] It should be understood that the specific embodiments described herein are only used to explain the present invention, and are not used to limit the present invention.

[0021] The embodiment of the present application provides an FPGA design method based on an EDA software system. The execution subject of the FPGA design method based on the EDA software system includes but is not limited to at least one of the electronic devices such as a server and a terminal that can be configured to execute the method provided in the embodiment of the present application. In other words, the FPGA design method based on the EDA software system can be executed by software or hardware installed on a terminal device or a server device, and the software can be a blockchain platform. The server includes but is not limited to: a single server, a server cluster, a cloud server or a cloud server cluster, etc.

[0022] Reference Figure 1 FIG. 1 is a flow chart of an FPGA design method based on an EDA software system provided in one embodiment of the present invention. In this embodiment, the FPGA design method based on the EDA software system includes: S1. Receive FPGA design instructions, start the pre-built EDA software system according to the FPGA design instructions, set the project path according to the started EDA software system, and create user source code according to the project path.

[0023] Specifically, the EDA software system includes: intelligent parser, download process management, database, comprehensive process module and layout and routing process module.

[0024] It should be explained that FPGA design instructions are signal instructions issued manually to trigger the start of the FPGA design process. EDA software system refers to a set of tool software specifically used to assist in electronic circuit design. The EDA software system described in the embodiment of the present invention integrates a variety of functional modules, which can help designers efficiently complete the entire process from FPGA design to implementation, and it has a deep understanding of Verilog and SystemVerilog, including all the grammatical structures and semantic rules of Verilog and SystemVerilog, and can parse complex data structures, coding styles and design patterns, thereby providing designers with a flexible programming environment system.

[0025] Importantly, the steps of setting the project path according to the EDA software system after startup and creating user source code according to the project path are as follows: select the path where the project is placed in the file manager of the EDA software system after startup to obtain the project path, and use the file editing function to create the source code file according to the project path: the user first clicks the file button in the new source file page, then selects Sources in the pop-up options, and clicks Create to enter the source code file creation interface. After the user enters the module name, the EDA software system will create the corresponding source code file for the user.

[0026] S2. Start the integrated process module, and obtain the integrated netlist based on the started integrated process module and the user source code.

[0027] In detail, the step of obtaining a comprehensive netlist based on the started comprehensive flow module and user source code includes: Reading the user source code based on the started comprehensive flow module, and parsing the read user source code using the intelligent parser to obtain source code data, wherein the intelligent parser includes: Verilog and SystemVerilog; Performing syntax check on the source code data to obtain verification source code data, and performing data initialization on the verification source code data to obtain initialization source code data; Performing a technology mapping operation on the initialization source code data and standardizing the structure of the mapped initialization source code data to obtain a standard structure source code, wherein the technology mapping operation includes: DSP, storage mapping, register mapping, LUT mapping and other device mappings; Using a pre-built optimization algorithm to perform optimization operations on the standard structure source code to obtain an initial optimized circuit, wherein the optimization operations include: circuit optimization and clock optimization, wherein the optimization algorithm includes: constant propagation, dead code elimination, logic simplification, and area and speed trade-off optimization; Performing a final inspection operation on the initial optimized circuit to obtain a final inspection result, and when the final inspection result of the initial optimized circuit is a preset passing result, confirming the initial optimized circuit as an optimized circuit, wherein the final inspection operation includes: circuit connection inspection, drive unit inspection, hierarchy inspection, and timing inspection; Generate a synthetic netlist based on the optimized circuit.

[0028] It should be explained that the comprehensive process module is a module that converts high-level hardware description language code into a module that can implement gate-level logic processes on FPGA. The comprehensive process module described in the embodiment of the present invention is specially designed to optimize this conversion process to ensure that the designer's Verilog or SystemVerilog code can be efficiently and accurately mapped to the FPGA hardware. The comprehensive process module includes: a comprehensive tool, an intelligent optimization function, a design rule checking function, a timing analysis function, and a resource estimation function. The timing analysis function includes: a timing analyzer, which can predict the timing performance of the design in the actual hardware in advance in the comprehensive process module, and by analyzing the data path delay and clock domain, the comprehensive tool can point out potential timing problems and automatically adjust in some cases to meet the timing requirements. In this way, the designer can iteratively optimize the design before layout and routing, saving valuable development time.

[0029] Importantly, in the synthesis flow module, the synthesis tool provides a rough estimate of the required FPGA resources, including lookup tables (LUTs), registers, input / output blocks (IOBs) and other dedicated hardware resources (such as DSP blocks and memory), allowing designers to have a reasonable expectation of the scale and complexity of the design in the early stage and make corresponding design adjustments. In order to support the development of complex projects and the collaboration of large teams, the synthesis tool provides powerful scripting and automation capabilities. The design team can use scripts to arrange the synthesis process, automatically execute optimization strategies, and integrate custom design checks and rules. These automation functions greatly improve development efficiency and reduce the possibility of human errors. Considering that multiple design solutions may need to be tested during the design process of the synthesis flow module, the synthesis tool supports multi-version synthesis and can compare different synthesis results, allowing designers to explore different design options, compare their performance and resource consumption, and finally select the best solution.

[0030] Understandably, Verilog and SystemVerilog refer to the two most widely used hardware description languages. An intelligent parser refers to a device that is able to recognize and optimize high-level language constructs, such as parameterized modules, make statements, and complex control flow structures.

[0031] It should be explained that user source code refers to the code written by FPGA designers using hardware description language according to specific design requirements. Source code data refers to the data obtained after the integrated process module uses the intelligent parser to parse the read user source code. Verification source code data refers to the data obtained after syntax checking of source code data. Initialization source code data refers to the data obtained after data initialization operation is performed on the verification source code data based on the verification source code data. Technology mapping operation refers to the operation of mapping the logic description in the initialization source code data to the hardware resources supported by the target FPGA chip.

[0032] It is understood that an optimization algorithm refers to an algorithm that can reduce the number of logic units required and optimize timing to achieve a higher operating frequency. The initial optimized circuit refers to the circuit model obtained after performing an optimization operation on the standard structure source code using an optimization algorithm. The final inspection result refers to the result obtained after performing the final inspection operation on the initial optimized circuit, including pass and fail. The optimized circuit refers to the final circuit formed after parsing, checking, technology mapping and various optimization steps starting from the source code written by the user. The comprehensive netlist includes: resource usage distribution, timing performance analysis and indication of potential problems.

[0033] S3. Start the layout and routing process module, and use the started layout and routing process module to perform layout and routing operations on the integrated netlist to obtain a layout and routing netlist.

[0034] Specifically, the layout and routing process module includes: an advanced layout algorithm and a path planning algorithm, and the path planning algorithm includes: a Lee algorithm and a Hadlock algorithm.

[0035] It should be explained that the path planning algorithm is used to handle complex routing challenges. It can intelligently optimize the path length and crossing of signals, reduce signal delays and routing congestion, and improve the performance and reliability of the design.

[0036] In detail, the activated layout and routing process module is used to perform layout and routing operations on the integrated netlist to obtain the layout and routing netlist, including: The integrated netlist is read and parsed using the started placement and routing flow module to obtain a logic unit set; Performing a physical mapping phase on the logical unit set to obtain a physical device set with a determined connection relationship, wherein the physical mapping phase includes: device mapping and local connection; Performing layout phase operations on the physical device set, determining the spatial position of each physical device in the physical device set, obtaining an optimal layout set, and performing device position check on each optimal layout set in the optimal layout set to obtain a standard optimal layout set; Get the standard thermal distribution map of the FPGA design chip; Performing routing phase operations on the standard optimal layout set according to the standard heat distribution map to obtain the optimal layout and routing set, wherein the routing phase operations include: initializing the model, forward routing path finding, reverse routing check, netlist connection check and timing analysis; Generate a place-and-route netlist based on the optimal place-and-route set.

[0037] It should be explained that the layout and routing process module refers to the module of the process of mapping the synthesized logic to the target FPGA chip, including: spatial positioning of components and path planning of connections between different components. The logic unit set refers to the set of logic units obtained after the layout and routing process module reads and parses the synthesized netlist. The physical device set refers to the set of physical devices obtained after the physical mapping stage is performed on the logic unit set. The layout stage operation is the operation of the process of automatically allocating logic units to physical locations on the FPGA design chip. This process is driven by advanced layout algorithms and takes into account key factors such as the interconnection strength, timing requirements, and thermal distribution between logic units.

[0038] It should be explained that the optimal layout set refers to the set obtained after performing layout stage operations on the physical device set and determining the spatial position of each physical device in the physical device set. The standard optimal layout set refers to the set of standard optimal layouts obtained after checking the device position of each optimal layout in the optimal layout set. FPGA design chip refers to a chip that configures the FPGA chip by programming. The optimal layout and routing set is a set of the final optimization results of the layout and routing operations, which describes in detail the location of the physical devices on the chip and how they are connected.

[0039] In detail, the physical mapping stage is performed on the logical unit set to obtain a physical device set with a determined connection relationship, including: Obtain the physical location set of the target FPGA chip, and perform the following operations on each logic unit in the logic unit set: Mapping the logical unit to a target physical location in the physical location set, wherein the logical unit corresponds to the physical location one by one; The target physical locations are summarized to obtain a set of physical devices with a determined connection relationship corresponding to the logical unit set.

[0040] It should be explained that the physical location set refers to the set of all available physical location information on the target FPGA chip. The target physical location refers to the specific physical location corresponding to each logical unit in the logical unit set selected from the physical location set during the physical mapping phase of the logical unit set.

[0041] In detail, performing the layout phase operation on the physical device set, determining the spatial position of each physical device in the physical device set, and obtaining the optimal layout set includes: Constructing a layout equation according to the physical device set, obtaining a clock constraint, and grouping the logic unit set according to the clock constraint to obtain a plurality of logic unit groups; Extract one logical unit group from multiple logical unit groups in turn, and perform the following operations on each of the extracted logical unit groups: Utilizing the layout equation, advanced layout algorithm and path planning algorithm to perform layout analysis on the logic unit group to obtain a suboptimal layout, wherein the advanced layout algorithm includes: simulated annealing, genetic algorithm and particle swarm optimization; According to the preset key component positions, the suboptimal layout is constrained to obtain the optimal layout; The optimal layout is summarized and the spatial position of each physical device in the physical device set is determined to obtain the optimal layout set corresponding to the multiple logic unit groups.

[0042] It should be explained that the step of grouping the logic unit set according to the clock constraint to obtain multiple logic unit groups is: grouping the logic units affected by the same clock constraint together to obtain logic unit groups, and aggregating the logic unit groups to obtain multiple logic unit groups. The suboptimal layout refers to the layout obtained in the process of performing layout analysis on the logic unit group. The key component position is a pre-specified position.

[0043] Furthermore, the step of obtaining a standard thermal distribution diagram of the FPGA design chip includes: Use the EDA software system to simulate the initial thermal distribution map of the FPGA design chip, and compare the effects of the initial thermal distribution map with the preset thermal distribution map; If the initial thermal distribution map does not meet the preset thermal distribution map effect, the hot spot area is obtained according to the initial thermal distribution map, and the layout and wiring of the hot spot area are adjusted until the initial thermal distribution map meets the preset thermal distribution map effect to obtain a standard thermal distribution map.

[0044] It should be explained that the initial thermal distribution map refers to the temperature distribution graph of the FPGA design chip obtained by simulating the FPGA design chip using the EDA software system. The thermal distribution map refers to a pre-set graph used to avoid performance degradation and reliability problems caused by overheating of the FPGA design chip. The standard thermal distribution map refers to a graph that adjusts the hot spot area of ​​the FPGA design chip until the initial thermal distribution map meets the preset thermal distribution map effect.

[0045] S4. Obtain a design bitstream file according to the layout and routing netlist, wherein the design bitstream file is a binary file and includes: all information required to configure the FPGA.

[0046] It should be explained that the layout and routing netlist refers to a file generated based on the optimal layout and routing set, which records the specific locations of physical devices on the FPGA chip and the connection relationships between them.

[0047] S5. Obtain the target FPGA chip and the target FPGA chip information, and query the target FPGA chip information and the compatibility result of the design bitstream file in the database, wherein the compatibility result includes: compatible and incompatible.

[0048] It should be explained that the database includes: multiple FPGA models and configuration specifications, which can ensure that the design bitstream file is compatible with the target FPGA chip to avoid equipment damage or program errors. The step of querying the target FPGA chip information and the compatibility result of the design bitstream file in the database is: querying the FPGA model and configuration specifications of the target FPGA chip in the database, and determining whether the FPGA model and configuration specifications of the target FPGA chip obtained by the query are compatible with the FPGA chip designed in the design bitstream file.

[0049] S6. If it is confirmed that the information of the target FPGA chip is compatible with the compatibility result of the design bitstream file, the design bitstream file is downloaded to the target FPGA chip to obtain the adapted FPGA device and the download operation process information, wherein the download operation process information includes: time, date, device information and download result.

[0050] In detail, downloading the design bitstream file to the target FPGA chip to obtain the adapted FPGA device and download operation process information includes: Obtain multiple program download interfaces, including JTAG, USB and Ethernet; Extracting a target download interface from multiple program download interfaces and setting a custom download configuration, wherein the custom download configuration includes: download speed, selecting a target device and setting specific download parameters; Obtain the development environment according to the target FPGA chip, the target download interface and the custom download configuration, and start the download process management, wherein the download process management includes the process management mechanism; Use the process management mechanism to monitor the download process in real time and provide real-time feedback information, including download progress, error detection and problem diagnosis; Get advanced encryption, authentication, and download options, including automated and batch downloads; According to the development environment, download function options, advanced encryption and verification mechanisms, the design bitstream file is downloaded to the target FPGA chip to obtain an adapted FPGA device, and download operation process information is generated according to real-time feedback information.

[0051] It should be explained that the target download interface refers to a specific interface extracted from a variety of program download interfaces, which is used to download the design bitstream file to the target FPGA chip. The purpose of setting the custom download configuration in the embodiment of the present invention is to provide flexibility so that the user can adjust the download process according to specific design requirements and resource conditions. The purpose of automated download is to allow users to preset download tasks and automatically execute the download when the conditions are met. Batch download refers to the ability to download programs to multiple FPGA devices at the same time, which is especially useful for large-scale production and testing. Download process management is responsible for the management of safely and accurately transferring the user-designed, synthesized and layout-processed FPGA configuration bitstream to the target FPGA chip.

[0052] It should be explained that the purpose of the advanced encryption and verification mechanism is to ensure the security of the design bitstream file during the download process. The FPGA adaptation device refers to a device that enables the target FPGA chip to work normally according to the design requirements after the design bitstream file is successfully downloaded to the target FPGA chip. The purpose of the multiple program download interfaces described in the embodiment of the present invention is to adapt to different user needs and hardware configurations. Users can choose the most appropriate download method according to actual hardware settings and personal preferences.

[0053] Importantly, the process management mechanism described in the embodiment of the present invention is used to prompt the user and provide possible solutions so as to correct the error in time and ensure the smooth completion of the download process.

[0054] In detail, before downloading the design bitstream file to the target FPGA chip according to the development environment, download function options, advanced encryption and verification mechanism, the method also includes: If it is confirmed that error detection or difficult problem diagnosis appears in the real-time feedback information, the EDA software system is used to provide a solution, and the error detection or difficult problem diagnosis is solved according to the solution until the error detection or difficult problem diagnosis does not appear in the real-time feedback information.

[0055] S7. Use the pre-built log file to save the download operation process information to obtain the download operation log.

[0056] It should be explained that the log file in the embodiment of the present invention is very important for tracking problems, improving design processes and meeting audit requirements. The download operation log refers to a file used to record detailed information about the operation process of downloading the design bitstream file to the target FPGA chip.

[0057] S8. Complete the FPGA design based on the EDA software system based on the adapted FPGA device and downloaded operation log.

[0058] It should be explained that the EDA software system provides a comprehensive, efficient and secure program download solution, which can not only adapt to a variety of FPGA devices and different download interfaces, but also effectively manage and monitor the entire download process to ensure the correctness and integrity of the design. In addition, functions such as user-defined settings and batch downloads make the EDA software system suitable not only for R&D and testing environments, but also for large-scale production environments. Through extra attention to security and reliability, as well as powerful logging functions, traceability and reliability are ensured when transforming designs from concept to actual deployment.

[0059] The present invention is to solve the problem described in the background technology. The present invention receives FPGA design instructions, starts a pre-built EDA software system according to the FPGA design instructions, sets a project path according to the started EDA software system, and creates user source code according to the project path. The EDA software system includes: an intelligent parser, a download process management, a database, a comprehensive flow module, and a layout and wiring flow module. The EDA software system of the present invention integrates multiple functional modules such as an intelligent parser, a download process management, a database, a comprehensive flow module, and a layout and wiring flow module, and provides a comprehensive design platform, which is convenient for designers to perform various subsequent design operations and improve design efficiency and quality. User source code is the basis of FPGA design, and designers can Write code according to specific design requirements to achieve specific functions, provide original design data for subsequent synthesis and layout and routing, start the synthesis process module, and obtain the synthesis netlist based on the started synthesis process module and user source code. The synthesis process module of the present invention is a process that can convert high-level hardware description language code into gate-level logic that can be implemented on FPGA, convert abstract design description into specific hardware circuit representation, and provide an operable circuit model for subsequent layout and routing. The synthesis netlist is a hardware-level abstract representation of the design function, which contains the connection relationship and logical function between each logic unit in the design, provides accurate circuit information for layout and routing, and helps to optimize the performance and resource utilization of the design. Start the layout and routing process The layout and routing module is used to perform layout and routing operations on the integrated netlist by using the layout and routing process module after startup to obtain the layout and routing netlist, wherein the layout and routing process module includes: advanced layout algorithm and path planning algorithm. The layout and routing process module of the present invention adopts advanced layout algorithm and path planning algorithm, can physically implement the integrated netlist, reasonably place the logic circuit on the physical resources of the target FPGA chip, and plan the routing path of the signal to ensure that the design can work normally on the actual FPGA chip, obtain the design bitstream file according to the layout and routing netlist, wherein the design bitstream file is a binary file, and the design bitstream file includes: all information required to configure the FPGA. The present invention configures the FPGA to realize the functions expected by the designer. , is the key conversion of FPGA design from software description to hardware implementation, obtains the target FPGA chip and the target FPGA chip information, queries the target FPGA chip information and the design bitstream file compatibility result in the database, wherein the compatibility result includes: compatible and incompatible, the present invention can find out in advance whether the design bitstream file is compatible with the target FPGA chip by querying the database, avoids chip damage or program errors caused by incompatibility during the download process, and improves the reliability and stability of the design, if it is confirmed that the target FPGA chip information and the design bitstream file compatibility result are compatible, then the design bitstream file is downloaded to the target FPGA chip, and the adapted FPGA device and download operation process information are obtained, wherein,The download operation process information includes: time, date, device information and download results. The present invention ensures that the design can be correctly implemented on the target FPGA chip by determining the compatibility of the target FPGA chip information with the design bitstream file, converts the software design into actual hardware functions, and completes the ultimate goal of FPGA design. The download operation process information is saved using a pre-built log file to obtain a download operation log. Based on the adapted FPGA device and the download operation log, the FPGA design based on the EDA software system is completed. The present invention records the detailed information of each download operation through a log file, which is convenient for designers to track problems and analyze problems in the design process, while also meeting the requirements of auditing and quality control. Therefore, the present invention can improve design efficiency and optimize the design process. ,

[0060] like Figure 2 FIG. 1 is a block diagram of an EDA software system provided by an embodiment of the present invention.

[0061] The EDA software system 100 of the present invention can be installed in an electronic device. According to the functions to be implemented, the EDA software system 100 may include a user source code creation module 101, a comprehensive process startup module 102, a layout and routing startup module 103, and a design file download module 104. The module of the present invention may also be referred to as a unit, which refers to a series of computer program segments that can be executed by an electronic device processor and can complete fixed functions, which are stored in the memory of the electronic device; The user source code creation module 101 is used to receive FPGA design instructions, start the pre-built EDA software system according to the FPGA design instructions, set the project path according to the started EDA software system, and create the user source code according to the project path, wherein the EDA software system includes: intelligent parser, download process management, database, comprehensive process module and layout and routing process module; The integrated process startup module 102 is used to start the integrated process module and obtain the integrated netlist based on the started integrated process module and the user source code; The layout and routing start module 103 is used to start the layout and routing process module, and use the started layout and routing process module to perform layout and routing operations on the integrated netlist to obtain a layout and routing netlist, wherein the layout and routing process module includes: an advanced layout algorithm and a path planning algorithm, and obtains a design bitstream file according to the layout and routing netlist, wherein the design bitstream file is a binary file, and the design bitstream file includes: all information required to configure the FPGA, obtain information of the target FPGA chip and the target FPGA chip, and query the target FPGA chip information in the database for a compatibility result with the design bitstream file, wherein the compatibility result includes: compatible and incompatible; The design file download module 104 is used to download the design bitstream file to the target FPGA chip if it is confirmed that the information of the target FPGA chip is compatible with the compatibility result of the design bitstream file, and obtain the adapted FPGA device and the download operation process information, wherein the download operation process information includes: time, date, device information and download results, and use a pre-built log file to save the download operation process information to obtain the download operation log, and complete the FPGA design based on the EDA software system based on the adapted FPGA device and the download operation log.

[0062] In detail, each module in the EDA software system 100 in the embodiment of the present invention is used in the same manner as described above. Figure 1 The FPGA design method based on EDA software system described in the previous section has the same technical means and can produce the same technical effects, so I will not go into details here.

[0063] like Figure 3 FIG. 1 is a schematic diagram of the structure of an electronic device for implementing an FPGA design method based on an EDA software system provided by an embodiment of the present invention.

[0064] The electronic device 1 may include a processor 10, a memory 11 and a bus 12, and may also include a computer program stored in the memory 11 and executable on the processor 10, such as an FPGA design method program based on an EDA software system.

[0065] Among them, the memory 11 includes at least one type of readable storage medium, and the readable storage medium includes flash memory, mobile hard disk, multimedia card, card-type memory (for example: SD or DX memory, etc.), magnetic memory, disk, optical disk, etc. In some embodiments, the memory 11 can be an internal storage unit of the electronic device 1, such as a mobile hard disk of the electronic device 1. In other embodiments, the memory 11 can also be an external storage device of the electronic device 1, such as a plug-in mobile hard disk, a smart memory card (Smart Media Card, SMC), a secure digital (SecureDigital, SD) card, a flash card (Flash Card), etc. equipped on the electronic device 1. Further, the memory 11 also includes an internal storage unit of the electronic device 1 and an external storage device. The memory 11 can not only be used to store application software and various types of data installed in the electronic device 1, such as the code of the FPGA design method program based on the EDA software system, but also can be used to temporarily store data that has been output or is to be output.

[0066] The processor 10 may be composed of an integrated circuit in some embodiments, for example, a single packaged integrated circuit, or a plurality of packaged integrated circuits with the same or different functions, including one or more central processing units (CPUs), microprocessors, digital processing chips, graphics processors, and combinations of various control chips, etc. The processor 10 is the control core (Control Unit) of the electronic device, and uses various interfaces and lines to connect various components of the entire electronic device, and executes or executes programs or modules (such as FPGA design method programs based on EDA software systems, etc.) stored in the memory 11, and calls data stored in the memory 11 to execute various functions of the electronic device 1 and process data.

[0067] The bus 12 may be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The bus 12 may be divided into an address bus, a data bus, a control bus, etc. The bus 12 is configured to realize connection and communication between the memory 11 and at least one processor 10, etc.

[0068] Figure 3 Only an electronic device with components is shown, and those skilled in the art will understand that Figure 3 The structure shown does not constitute a limitation on the electronic device 1, and may include fewer or more components than shown in the figure, or combine certain components, or arrange the components differently.

[0069] For example, although not shown, the electronic device 1 may also include a power source (such as a battery) for supplying power to various components. Preferably, the power source may be logically connected to the at least one processor 10 through a power management device, so that the power management device can realize functions such as charging management, discharging management, and power consumption management. The power source may also include one or more DC or AC power sources, recharging devices, power failure detection circuits, power converters or inverters, power status indicators, and other arbitrary components. The electronic device 1 may also include a variety of sensors, Bluetooth modules, Wi-Fi modules, etc., which will not be repeated here.

[0070] Furthermore, the electronic device 1 may also include a network interface. Optionally, the network interface may include a wired interface and / or a wireless interface (such as a WI-FI interface, a Bluetooth interface, etc.), which is generally used to establish a communication connection between the electronic device 1 and other electronic devices.

[0071] Optionally, the electronic device 1 may further include a user interface, which may be a display, an input unit (such as a keyboard), or a standard wired interface or a wireless interface. Optionally, in some embodiments, the display may be an LED display, a liquid crystal display, a touch-sensitive liquid crystal display, and an OLED (Organic Light-Emitting Diode) touch device. The display may also be appropriately referred to as a display screen or a display unit, which is used to display information processed in the electronic device 1 and to display a visual user interface.

[0072] The FPGA design method program based on the EDA software system stored in the memory 11 of the electronic device 1 is a combination of multiple instructions. When running in the processor 10, it can achieve: Receive FPGA design instructions, start a pre-built EDA software system according to the FPGA design instructions, set a project path according to the started EDA software system, and create user source code according to the project path, wherein the EDA software system includes: intelligent parser, download process management, database, comprehensive process module and layout and routing process module; Start the integrated flow module, and obtain the integrated netlist based on the started integrated flow module and the user source code; Starting the layout and routing process module, and using the started layout and routing process module to perform layout and routing operations on the integrated netlist to obtain a layout and routing netlist, wherein the layout and routing process module includes: an advanced layout algorithm and a path planning algorithm; Obtaining a design bitstream file according to the layout and routing netlist, wherein the design bitstream file is a binary file, and the design bitstream file includes: all information required to configure the FPGA; Obtaining information of a target FPGA chip and a target FPGA chip, querying the database for a compatibility result between the information of the target FPGA chip and the design bitstream file, wherein the compatibility result includes: compatible and incompatible; If it is confirmed that the information of the target FPGA chip is compatible with the compatibility result of the design bitstream file, the design bitstream file is downloaded to the target FPGA chip to obtain the adapted FPGA device and the download operation process information, wherein the download operation process information includes: time, date, device information and download result; The pre-built log file is used to save the download operation process information to obtain the download operation log. Based on the adapted FPGA device and the download operation log, the FPGA design based on the EDA software system is completed.

[0073] Specifically, the specific implementation method of the processor 10 for the above instructions can refer to Figures 1 to 3 The description of the relevant steps in the corresponding embodiments will not be repeated here.

[0074] Furthermore, if the module / unit integrated in the electronic device 1 is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. The computer-readable storage medium can be volatile or non-volatile. For example, the computer-readable medium can include: any entity or device capable of carrying the computer program code, a recording medium, a USB flash drive, a mobile hard disk, a magnetic disk, an optical disk, a computer memory, and a read-only memory (ROM).

[0075] The present invention further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor of an electronic device, the computer program can implement: Receive FPGA design instructions, start a pre-built EDA software system according to the FPGA design instructions, set a project path according to the started EDA software system, and create user source code according to the project path, wherein the EDA software system includes: intelligent parser, download process management, database, comprehensive process module and layout and routing process module; Start the integrated flow module, and obtain the integrated netlist based on the started integrated flow module and the user source code; Starting the layout and routing process module, and using the started layout and routing process module to perform layout and routing operations on the integrated netlist to obtain a layout and routing netlist, wherein the layout and routing process module includes: an advanced layout algorithm and a path planning algorithm; Obtaining a design bitstream file according to the layout and routing netlist, wherein the design bitstream file is a binary file, and the design bitstream file includes: all information required to configure the FPGA; Obtaining information of a target FPGA chip and a target FPGA chip, querying the database for a compatibility result between the information of the target FPGA chip and the design bitstream file, wherein the compatibility result includes: compatible and incompatible; If it is confirmed that the information of the target FPGA chip is compatible with the compatibility result of the design bitstream file, the design bitstream file is downloaded to the target FPGA chip to obtain the adapted FPGA device and the download operation process information, wherein the download operation process information includes: time, date, device information and download result; The pre-built log file is used to save the download operation process information to obtain the download operation log. Based on the adapted FPGA device and the download operation log, the FPGA design based on the EDA software system is completed.

[0076] In the several embodiments provided by the present invention, it should be understood that the disclosed devices, systems and methods can be implemented in other ways. For example, the system embodiments described above are only illustrative, and actual implementation may have other division methods.

[0077] The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0078] In addition, each functional module in each embodiment of the present invention may be integrated into one processing unit, each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of hardware plus software functional modules.

[0079] It is obvious to those skilled in the art that the present invention is not limited to the details of the above exemplary embodiments, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0080] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the spirit and scope of the technical solution of the present invention.

Claims

1. An FPGA design method based on an EDA software system, characterized in that: The method comprises: Receive FPGA design instructions, start a pre-built EDA software system according to the FPGA design instructions, set a project path according to the started EDA software system, and create user source code according to the project path, wherein the EDA software system includes: intelligent parser, download process management, database, comprehensive process module and layout and routing process module; Start the integrated flow module, and obtain the integrated netlist based on the started integrated flow module and the user source code; Starting the layout and routing process module, and using the started layout and routing process module to perform layout and routing operations on the integrated netlist to obtain a layout and routing netlist, wherein the layout and routing process module includes: an advanced layout algorithm and a path planning algorithm; Obtaining a design bitstream file according to the layout and routing netlist, wherein the design bitstream file is a binary file, and the design bitstream file includes: all information required to configure the FPGA; Obtaining information of a target FPGA chip and a target FPGA chip, querying the database for a compatibility result between the information of the target FPGA chip and the design bitstream file, wherein the compatibility result includes: compatible and incompatible; If it is confirmed that the information of the target FPGA chip is compatible with the compatibility result of the design bitstream file, the design bitstream file is downloaded to the target FPGA chip to obtain the adapted FPGA device and the download operation process information, wherein the download operation process information includes: time, date, device information and download result; The pre-built log file is used to save the download operation process information to obtain the download operation log. Based on the adapted FPGA device and the download operation log, the FPGA design based on the EDA software system is completed.

2. The FPGA design method based on the EDA software system according to claim 1, characterized in that: The step of obtaining a comprehensive netlist based on the started comprehensive flow module and user source code includes: Reading the user source code based on the started comprehensive flow module, and parsing the read user source code using the intelligent parser to obtain source code data, wherein the intelligent parser includes: Verilog and SystemVerilog; Performing syntax check on the source code data to obtain verification source code data, and performing data initialization on the verification source code data to obtain initialization source code data; Performing a technology mapping operation on the initialization source code data and standardizing the structure of the mapped initialization source code data to obtain a standard structure source code, wherein the technology mapping operation includes: DSP, storage mapping, register mapping, LUT mapping and other device mappings; Using a pre-built optimization algorithm to perform optimization operations on the standard structure source code to obtain an initial optimized circuit, wherein the optimization operations include: circuit optimization and clock optimization, wherein the optimization algorithm includes: constant propagation, dead code elimination, logic simplification, and area and speed trade-off optimization; Performing a final inspection operation on the initial optimized circuit to obtain a final inspection result, and when the final inspection result of the initial optimized circuit is a preset passing result, confirming the initial optimized circuit as an optimized circuit, wherein the final inspection operation includes: circuit connection inspection, drive unit inspection, hierarchy inspection, and timing inspection; Generate a synthetic netlist based on the optimized circuit.

3. The FPGA design method based on the EDA software system according to claim 1, characterized in that: The method of using the activated layout and routing process module to perform layout and routing operations on the integrated netlist to obtain a layout and routing netlist includes: The integrated netlist is read and parsed using the started placement and routing flow module to obtain a logic unit set; Performing a physical mapping phase on the logical unit set to obtain a physical device set with a determined connection relationship, wherein the physical mapping phase includes: device mapping and local connection; Performing layout phase operations on the physical device set, determining the spatial position of each physical device in the physical device set, obtaining an optimal layout set, and performing device position check on each optimal layout set in the optimal layout set to obtain a standard optimal layout set; Get the standard thermal distribution map of the FPGA design chip; Performing routing phase operations on the standard optimal layout set according to the standard heat distribution map to obtain the optimal layout and routing set, wherein the routing phase operations include: initializing the model, forward routing path finding, reverse routing check, netlist connection check and timing analysis; Generate a place-and-route netlist based on the optimal place-and-route set.

4. The FPGA design method based on the EDA software system as claimed in claim 3, characterized in that: The physical mapping stage is performed on the logical unit set to obtain a physical device set with a determined connection relationship, including: Obtain the physical location set of the target FPGA chip, and perform the following operations on each logic unit in the logic unit set: Mapping the logical unit to a target physical location in the physical location set, wherein the logical unit corresponds to the physical location one by one; The target physical locations are summarized to obtain a set of physical devices with a determined connection relationship corresponding to the logical unit set.

5. The FPGA design method based on the EDA software system as claimed in claim 3, characterized in that: The performing of the layout phase operation on the physical device set, determining the spatial position of each physical device in the physical device set, and obtaining the optimal layout set includes: Constructing a layout equation according to the physical device set, obtaining a clock constraint, and grouping the logic unit set according to the clock constraint to obtain a plurality of logic unit groups; Extract one logical unit group from multiple logical unit groups in turn, and perform the following operations on each of the extracted logical unit groups: Utilizing the layout equation, advanced layout algorithm and path planning algorithm to perform layout analysis on the logic unit group to obtain a suboptimal layout, wherein the advanced layout algorithm includes: simulated annealing, genetic algorithm and particle swarm optimization; According to the preset key component positions, the suboptimal layout is constrained to obtain the optimal layout; The optimal layout is summarized and the spatial position of each physical device in the physical device set is determined to obtain the optimal layout set corresponding to the multiple logic unit groups.

6. The FPGA design method based on the EDA software system as claimed in claim 3, characterized in that: The step of obtaining a standard thermal distribution diagram of the FPGA design chip includes: Use the EDA software system to simulate the initial thermal distribution map of the FPGA design chip, and compare the effects of the initial thermal distribution map with the preset thermal distribution map; If the initial thermal distribution map does not meet the preset thermal distribution map effect, the hot spot area is obtained according to the initial thermal distribution map, and the layout and wiring of the hot spot area are adjusted until the initial thermal distribution map meets the preset thermal distribution map effect to obtain a standard thermal distribution map.

7. The FPGA design method based on the EDA software system according to claim 1, characterized in that: The step of downloading the design bitstream file to the target FPGA chip to obtain the adapted FPGA device and download operation process information includes: Obtain multiple program download interfaces, including JTAG, USB and Ethernet; Extracting a target download interface from multiple program download interfaces and setting a custom download configuration, wherein the custom download configuration includes: download speed, selecting a target device and setting specific download parameters; Obtain the development environment according to the target FPGA chip, the target download interface and the custom download configuration, and start the download process management, wherein the download process management includes the process management mechanism; Use the process management mechanism to monitor the download process in real time and provide real-time feedback information, including download progress, error detection and troubleshooting; Get advanced encryption, authentication mechanisms and download options, including automated and batch downloads; According to the development environment, download function options, advanced encryption and verification mechanisms, the design bitstream file is downloaded to the target FPGA chip to obtain an adapted FPGA device, and download operation process information is generated according to real-time feedback information.

8. The FPGA design method based on the EDA software system as claimed in claim 7, characterized in that: Before downloading the design bitstream file to the target FPGA chip according to the development environment, download function options, advanced encryption and verification mechanism, the method further includes: If it is confirmed that error detection or difficult problem diagnosis appears in the real-time feedback information, the EDA software system is used to provide a solution, and the error detection or difficult problem diagnosis is solved according to the solution until the error detection or difficult problem diagnosis does not appear in the real-time feedback information.

9. An EDA software system, characterized in that: The system comprises: A user source code creation module is used to receive FPGA design instructions, start the pre-built EDA software system according to the FPGA design instructions, set the project path according to the started EDA software system, and create user source code according to the project path, wherein the EDA software system includes: intelligent parser, download process management, database, comprehensive process module and layout and routing process module; A comprehensive process startup module is used to start the comprehensive process module and obtain a comprehensive netlist based on the started comprehensive process module and user source code; A layout and routing startup module is used to start the layout and routing process module, and use the started layout and routing process module to perform layout and routing operations on the integrated netlist to obtain a layout and routing netlist, wherein the layout and routing process module includes: an advanced layout algorithm and a path planning algorithm, and obtains a design bitstream file according to the layout and routing netlist, wherein the design bitstream file is a binary file, and the design bitstream file includes: all information required to configure the FPGA, obtain information of the target FPGA chip and the target FPGA chip, and query the target FPGA chip information in the database for a compatibility result with the design bitstream file, wherein the compatibility result includes: compatible and incompatible; The design file download module is used to download the design bitstream file to the target FPGA chip if it is confirmed that the information of the target FPGA chip is compatible with the compatibility result of the design bitstream file, and obtain the adapted FPGA device and the download operation process information, wherein the download operation process information includes: time, date, device information and download results, and use a pre-built log file to save the download operation process information to obtain the download operation log, and complete the FPGA design based on the EDA software system based on the adapted FPGA device and the download operation log.

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