Wafer defect detection method and device, electronic equipment and storage medium
By obtaining initial defect information and determining the new defect information of large-size defects in traditional wafer defect detection methods, the problem of high missed detection and error detection rates in traditional methods is solved, and higher detection accuracy and reliability are achieved.
Patent Information
- Application Number
- CN202411842543.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-13
- Publication Date
- 2025-03-28
AI Technical Summary
When there are large-size defects in the wafer defect map in the traditional method, the error detection rate of wafer defect detection is high and the missed detection problem of large-size defects occurs.
By obtaining the initial defect information, the new defect information corresponding to the large-sized defect in the wafer defect diagram is determined, and added to the initial defect information, the target defect information is obtained, and sent to the defect re-checking device for detection.
It effectively reduces the missed detection rate and missed detection rate of wafer defect detection, increases the reliability and accuracy of wafer detection results, and avoids missed detection problems of large-size defects.
Smart Images
Figure CN119722636A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a wafer defect detection method, device, electronic equipment and storage medium. Background Art
[0002] In the field of semiconductor wafer manufacturing, wafer defect information is generally determined by performing grayscale comparison on a wafer defect map through a wafer defect scanning device. The wafer defect information can be understood as the defect coordinates and lens length information corresponding to the defective area in the wafer defect map. The wafer defect information is then sent to a defect review device through a wafer defect scanning device, and the defect review device is controlled to adaptively adjust the lens length according to the lens length information, and then the adjusted lens is used to shoot the wafer defect map corresponding to the defect coordinates to obtain the detection result.
[0003] However, if there are large-size defects in the wafer defect map, the determined wafer defect information will appear to be non-wafer defect information. The non-wafer defect information can be understood as the coordinates and lens length information corresponding to the area without defects in the wafer defect map. The defect review equipment is controlled to perform wafer defect detection on the non-wafer defect information, and the detection result obtained is that the wafer is defect-free. The defect review equipment is not controlled to perform wafer defect detection based on the area where the actual large-size defects exist, resulting in the problem of missed detection of large-size defects, increasing the false detection rate of wafer defect detection, that is, the traditional method of determining wafer defect information has a large false detection rate of wafer defect detection when large-size defects exist in the wafer defect map.
[0004] How to reduce the false detection rate of wafer defect detection is an urgent problem to be solved. Summary of the invention
[0005] The present invention provides a wafer defect detection method, device, electronic equipment and storage medium, which can solve the problem of a large false detection rate of wafer defect detection when there are large-sized defects in a wafer defect map in a traditional method of determining wafer defect information.
[0006] According to a first aspect of the present invention, a wafer defect detection method is provided, the method comprising:
[0007] Obtain initial defect information;
[0008] Determine, based on the initial defect information, newly added defect information corresponding to the large-size defect in the wafer defect map;
[0009] Adding the newly added defect information to the initial defect information to obtain target defect information;
[0010] Sending the target defect information to a defect review device;
[0011] The defect review equipment is controlled to perform defect detection on the wafer defect map according to the target defect information.
[0012] According to a second aspect of the present invention, there is provided a wafer defect detection device, the device comprising:
[0013] An information acquisition module, used to obtain initial defect information;
[0014] An information determination module, configured to determine, based on the initial defect information, newly added defect information corresponding to the large-size defect in the wafer defect map;
[0015] An information adding module, used for adding the newly added defect information to the initial defect information to obtain target defect information;
[0016] An information sending module, used for sending the target defect information to a defect review device;
[0017] The defect detection module is used to control the defect review equipment to perform defect detection on the wafer defect map according to the target defect information.
[0018] According to a third aspect of the present invention, there is provided an electronic device, comprising a processor and a memory.
[0019] The memory is used to store codes and related data;
[0020] The processor is used to execute the code in the memory to implement the wafer defect detection method as described in any one of the embodiments of the present invention.
[0021] According to a fourth aspect of the present invention, there is provided a storage medium having a computer program stored thereon, which, when executed by a processor, implements a wafer defect detection method as described in any one of the embodiments of the present invention.
[0022] In an embodiment of the present invention, initial defect information is obtained, and newly added defect information corresponding to large-size defects in a wafer defect map is determined according to the initial defect information, and the newly added defect information is added to the initial defect information to obtain target defect information, and the target defect information is sent to a defect re-inspection device, and the defect re-inspection device is controlled to perform defect detection on the wafer defect map according to the target defect information. Since newly added defect information corresponding to large-size defects in the wafer defect map is determined according to the initial defect information, and the newly added defect information is added to the initial defect information to obtain the target defect information, it is equivalent to adding newly added defect information corresponding to large-size defects in the wafer defect map to the target defect information, and the target defect information includes the initial defect information and the newly added defect information corresponding to the large-size defects, and then when the defect re-inspection device is controlled to perform defect detection on the wafer defect map according to the target defect information, both wafer defect detection can be performed on the wafer defect map corresponding to the initial defect information, and wafer defect detection can be performed on the wafer defect map corresponding to the newly added defect information corresponding to the large-size defects, thereby avoiding the problem of missed detection of large-size defects, effectively reducing the missed detection rate of wafer defect detection, thereby reducing the false detection rate of wafer defect detection, and increasing the reliability and accuracy of the wafer detection results. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0024] Figure 1 It is a flow chart of a wafer defect detection method provided by an embodiment of the present invention;
[0025] Figure 2 is another flow chart of the wafer defect detection method provided by an embodiment of the present invention;
[0026] Figure 3 is a schematic diagram of an extended area provided by an embodiment of the present invention;
[0027] Figure 4 is another schematic diagram of an extended area provided by an embodiment of the present invention;
[0028] Figure 5 is a structural schematic diagram of a wafer defect detection device provided by an embodiment of the present invention;
[0029] Figure 6 It is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION
[0030] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0031] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.
[0032] The technical solution of the present invention is described in detail with specific embodiments below. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.
[0033] Figure 1 The present invention provides a flow chart of a wafer defect detection method. The method can be performed by a wafer defect detection device, which can be implemented in software and / or hardware. In a specific embodiment, the device can be integrated into an electronic device, such as a computer, a server, etc. The following embodiments will be described by taking the device integrated into an electronic device as an example. Figure 1 , the method may specifically include the following steps:
[0034] Step 101, obtaining initial defect information.
[0035] The initial defect information can be understood as the wafer defect information determined by the wafer defect image scanning device performing grayscale comparison on the wafer defect image. The initial defect information may include multiple initial defect coordinates, and the defect coordinates can be understood as the position of the wafer defect image that needs to be captured by the control defect review device, and the initial defect coordinates are the defect coordinates determined in the initial defect information.
[0036] In this embodiment, a wafer defect map scanning device may be used to perform grayscale comparison on the wafer defect map to be inspected, so as to obtain initial defect information corresponding to the wafer defect map to be inspected.
[0037] Step 102, determining new defect information corresponding to large-size defects in the wafer defect map based on the initial defect information.
[0038] Among them, the wafer defect map to be detected includes large-size defects and small-size defects. It can be understood that large-size defects occupy a larger graphic area in the wafer defect map, and when the wafer defect map scanning device performs grayscale comparison on the wafer defect map, it will not be determined as a wafer defect. Small-size defects occupy a smaller graphic area in the wafer defect map, and when the wafer defect map scanning device performs grayscale comparison on the wafer defect map, it will be determined as a wafer defect.
[0039] In this embodiment, the newly added defect information can be understood as information required to control a defect review device to capture a defect image of a wafer with large-size defects.
[0040] In this embodiment, there are multiple initial defect coordinates near the area where the large-size defect is located, and the actual distance between every two initial defect coordinates is less than the preset distance.
[0041] In an optional embodiment, a plurality of intermediate defect coordinates can be determined based on the actual distance between each two initial defect coordinates in the plurality of initial defect coordinates, and based on the actual distance and the preset distance; and then, based on the plurality of intermediate defect coordinates, additional defect information corresponding to large-size defects in the wafer defect map can be further determined.
[0042] The preset distance can be understood as a preset distance threshold, and the intermediate defect coordinate can be understood as an initial defect coordinate whose actual distance is less than the preset distance.
[0043] Specifically, when the actual distance is less than the preset distance, two initial defect coordinates whose actual distance is less than the preset distance are determined as intermediate defect coordinates, so that multiple intermediate defect coordinates near the area where large-size defects exist can be determined from multiple initial defect coordinates.
[0044] In this embodiment, the intermediate defect coordinates near the area where the large-size defect is located can be expanded in a preset area according to a preset expansion method to obtain an extended area, and connecting multiple intermediate defect coordinates belonging to the extended area can form a closed figure. Therefore, the extended area can be obtained by performing area expansion according to the multiple intermediate defect coordinates and the preset expansion method; then, it is determined whether the multiple intermediate defect coordinates belonging to the extended area can form a closed figure. When the multiple intermediate defect coordinates in the extended area can form a closed figure, the newly added defect information corresponding to the large-size defect is determined according to the multiple intermediate defect coordinates.
[0045] Step 103: Add the newly added defect information to the initial defect information to obtain target defect information.
[0046] In this embodiment, the newly added defect information corresponding to the large-size defects in the wafer defect map can be added to the acquired initial defect information to obtain the target defect information containing the large-size defects in the wafer defect map.
[0047] Step 104: Send the target defect information to a defect review device.
[0048] In this embodiment, the target defect information including the large-size defects may be sent together with the wafer defect map to a defect review device for subsequent review.
[0049] Step 105 , controlling the defect review equipment to perform defect detection on the wafer defect map according to the target defect information.
[0050] In this embodiment, the defect review device performs defect detection on the wafer defect map according to the provided target defect information, so as to determine all defects existing in the wafer defect map.
[0051] In one embodiment, the initial defect information may further include initial lens length information corresponding to the initial defect coordinates, and the newly added defect information may include newly added defect coordinates and newly added lens length information.
[0052] Among them, the lens length information can be understood as the lens short axis length and the lens long axis length when controlling the defect review equipment to capture the wafer defect image corresponding to the defect coordinates.
[0053] In this embodiment, the defect review equipment can be controlled to adaptively adjust the lens length according to the initial lens length information and use the adjusted lens to shoot the wafer defect map corresponding to the initial defect coordinates to obtain a first captured image; then the defect review equipment can be controlled to adaptively adjust the lens length according to the newly added lens length information and use the adjusted lens to shoot the wafer defect map corresponding to the newly added defect coordinates to obtain a second captured image; finally, determine whether there are defects in the first captured image and the second captured image to complete the wafer defect detection.
[0054] In an embodiment of the present invention, initial defect information is obtained, and newly added defect information corresponding to large-size defects in a wafer defect map is determined according to the initial defect information, and the newly added defect information is added to the initial defect information to obtain target defect information, and the target defect information is sent to a defect re-inspection device, and the defect re-inspection device is controlled to perform defect detection on the wafer defect map according to the target defect information. Since newly added defect information corresponding to large-size defects in the wafer defect map is determined according to the initial defect information, and the newly added defect information is added to the initial defect information to obtain the target defect information, it is equivalent to adding newly added defect information corresponding to large-size defects in the wafer defect map to the target defect information, and the target defect information includes the initial defect information and the newly added defect information corresponding to large-size defects, and then when the defect re-inspection device is controlled to perform defect detection on the wafer defect map according to the target defect information, both wafer defect detection can be performed on the wafer defect map corresponding to the initial defect information, and wafer defect detection can be performed on the wafer defect map corresponding to the large-size defects, thereby avoiding the problem of missed detection of large-size defects, effectively reducing the missed detection rate of wafer defect detection, thereby reducing the false detection rate of wafer defect detection, and increasing the reliability and accuracy of the wafer detection results.
[0055] The wafer defect detection method provided by the embodiment of the present invention is further described below. Figure 2 As shown, Figure 2 FIG. 4 is another flow chart of the wafer defect detection method provided by an embodiment of the present invention, which may specifically include the following steps:
[0056] Step 201, obtaining initial defect information.
[0057] Step 202: determining the actual distance between every two initial defect coordinates among a plurality of initial defect coordinates.
[0058] Step 203, determine whether the actual distance is less than the preset distance, if so, execute step 204; if not, return to execute step 202.
[0059] Step 204: determine two initial defect coordinates whose actual distance is smaller than the preset distance as intermediate defect coordinates.
[0060] Step 205 , determining new defect information corresponding to the large-size defects in the wafer defect map according to the multiple intermediate defect coordinates.
[0061] In an optional embodiment, in step 205, determining the newly added defect information corresponding to the large-size defect in the wafer defect map according to the multiple intermediate defect coordinates may include: determining any one of the multiple intermediate defect coordinates as an extension point; taking the extension point as the center, extending the preset length in all directions to obtain an extension area; determining whether the extended area includes the intermediate defect coordinates; when the extended area includes the intermediate defect coordinates, updating the extended area according to the edge of the extended area; when the updated extended area includes the intermediate defect coordinates, continuing to update the extended area according to the edge of the extended area until the updated extended area does not include the intermediate defect coordinates; when the updated extended area does not include the intermediate defect coordinates, connecting the multiple intermediate defect coordinates in the extended area to obtain a connection graph; determining whether the connection graph is a closed graph; when the connection graph is a closed graph, determining the newly added defect information corresponding to the large-size defect in the wafer defect map according to the multiple intermediate defect coordinates on the connection graph. Among them, the preset length can be understood as a preset extension length.
[0062] Specifically, the edge of the extension area may be used as an extension side and extended to all sides by a preset length, so as to achieve the purpose of updating the extension area.
[0063] In this embodiment, determining the newly added defect information corresponding to the large-size defects in the wafer defect map according to the multiple intermediate defect coordinates on the connection graph may include: determining the newly added defect coordinates according to the multiple intermediate defect coordinates on the connection graph; and determining the newly added defect coordinates as the newly added defect information corresponding to the large-size defects in the wafer defect map.
[0064] Among them, the newly added defect coordinates can be understood as controlling the position of the wafer defect map where the defect review equipment captures the large-size defect. Furthermore, each intermediate defect coordinate on the connection graph includes a ordinate and a horizontal coordinate respectively; the newly added defect ordinate can be determined according to the maximum ordinate and the minimum ordinate among the multiple intermediate defect coordinates on the connection graph, and the newly added defect horizontal coordinate can be determined according to the maximum horizontal coordinate and the minimum horizontal coordinate among the multiple intermediate defect coordinates on the connection graph; the newly added defect ordinate and the newly added defect horizontal coordinate are determined as the newly added defect coordinates, so that the determined newly added defect coordinates can be closer to the actual location of the large defect.
[0065] In this embodiment, the newly added defect information may also include newly added lens length information. The newly added lens length information may be understood as the lens short axis length and lens long axis length when controlling the defect review device to capture the wafer defect image corresponding to the newly added defect coordinates.
[0066] In this embodiment, the length of the short axis of the newly added lens can be determined according to the maximum vertical coordinate and the minimum vertical coordinate of the multiple intermediate defect coordinates on the connection graph, and the length of the long axis of the newly added lens can be determined according to the maximum horizontal coordinate and the minimum horizontal coordinate of the multiple intermediate defect coordinates on the connection graph; the length of the short axis of the newly added lens and the length of the long axis of the newly added lens are determined as the length information of the newly added lens, so that the appropriate length of the short axis of the lens can be determined according to the maximum vertical coordinate and the minimum vertical coordinate in the Y-axis direction, and the appropriate length of the long axis of the lens can be determined according to the maximum horizontal coordinate and the minimum horizontal coordinate in the X-axis direction, and then a field of view (FOV) lens with appropriate lens length is used to capture the wafer defect image of the area where the large-size defects are located, so as to avoid missing the wafer defect image of the area where the large-size defects are located, avoid the problem of missed detection of large-size defects, and effectively reduce the missed detection rate of wafer defect detection.
[0067] Specifically, a first mean of the maximum ordinate and the minimum ordinate among multiple intermediate defect coordinates on the connection graph can be determined, and the first mean can be determined as the newly added defect ordinate; a second mean of the maximum abscissa and the minimum abscissa among multiple intermediate defect coordinates on the connection graph can be determined, and the second mean can be determined as the newly added defect abscissa; the newly added defect ordinate and the newly added defect abscissa can be determined as the newly added defect coordinates, so that the determined newly added defect coordinates can be closer to the location where the actual large defect exists; then a first difference between the maximum ordinate and the minimum ordinate among multiple intermediate defect coordinates on the connection graph can be determined; a second difference between the maximum abscissa and the minimum abscissa among multiple intermediate defect coordinates on the connection graph can be determined, and the first difference and The larger difference in the second difference is determined as the length of the new lens major axis, and the smaller difference in the first difference and the second difference is determined as the length of the new lens minor axis; the length of the new lens minor axis and the length of the new lens major axis are determined as the length information of the new lens, so that the appropriate lens minor axis length can be determined according to the maximum vertical coordinate and the minimum vertical coordinate in the Y-axis direction, and the appropriate lens major axis length can be determined according to the maximum horizontal coordinate and the minimum horizontal coordinate in the X-axis direction, and then a FOV lens with appropriate lens length is used to capture a wafer defect image of an area where large-size defects are located, so as to avoid missing a wafer defect image of an area where large-size defects are located, thereby avoiding the problem of missed detection of large-size defects, effectively reducing the missed detection rate of wafer defect detection, and thereby reducing the false detection rate of wafer defect detection.
[0068] For example, Figure 3As shown, the coordinate H among the multiple intermediate defect coordinates is determined as the extension point; the extension point is used as the center to extend the preset length L in all directions to obtain the extension area S1; it is determined that the intermediate defect coordinate I is included in the extension area; when the intermediate defect coordinate I is included in the extension area S1, the edge of the extension area S1 is used as the extension edge to extend the preset length L in all directions to obtain the extension area S2, and it is determined that the extension area S2 includes the intermediate defect coordinates J, K, M, and N; when the intermediate defect coordinates J, K, M, and N are included in the extension area S2, the edge of the extension area S2 is used as the extension edge to extend the preset length L in all directions, and it is determined that the intermediate defect coordinate is not included in the extension area S3, and the multiple intermediate defect coordinates (H, I, J, K, M, and N) in the extension area S3 are connected to obtain a connection graph, which is obtained by Figure 3 It can be seen that the multiple intermediate defect coordinates are not connected end to end, so the connection figure obtained by connecting the multiple intermediate defect coordinates is not a closed figure, which triggers the step of obtaining the initial defect information.
[0069] In this embodiment, if the connection graph is a closed graph, such as Figure 4 As shown in the figure, the maximum ordinate among the multiple intermediate defect coordinates on the connection graph in the extended area is the ordinate Y of point A. a , the minimum ordinate is the ordinate Y of point C c , the maximum horizontal coordinate is the horizontal coordinate X of point B b And the minimum horizontal coordinate is the horizontal coordinate X of point D d , the first mean of the maximum ordinate and the minimum ordinate among the multiple intermediate defect coordinates on the connection graph can be determined (the first mean = (Y a –Y c ) / 2), determine the first mean as the ordinate of the newly added defect; determine the second mean of the maximum abscissa and the minimum abscissa among the multiple intermediate defect coordinates on the connection graph (the second mean = (X d –X b ) / 2), determine the second mean as the abscissa of the newly added defect; determine the ordinate of the newly added defect and the abscissa of the newly added defect as the coordinates of the newly added defect.
[0070] Then, the first difference between the maximum ordinate and the minimum ordinate among the plurality of intermediate defect coordinates on the connection graph can be determined (the first difference = Y a –Y c ); determine the second difference between the maximum horizontal coordinate and the minimum horizontal coordinate among the plurality of intermediate defect coordinates on the connection graph (the second difference = X d –X b ), assuming that the first difference is less than the second difference, the first difference can be determined as the length of the minor axis of the newly added lens, and the second difference can be determined as the length of the major axis of the newly added lens; the length of the minor axis of the newly added lens and the length of the major axis of the newly added lens are determined as the length information of the newly added lens.
[0071] Step 206: Add the newly added defect information to the initial defect information to obtain target defect information.
[0072] Step 207: Send the target defect information to a defect review device.
[0073] Step 208: Control the defect review equipment to perform defect detection on the wafer defect map according to the target defect information.
[0074] Continuing with the above example, in this embodiment, controlling the defect re-inspection device to perform defect detection on the wafer defect map according to the target defect information may include: controlling the defect re-inspection device to adaptively adjust the lens major axis length and the lens minor axis length according to the initial lens length information; controlling the defect re-inspection device to shoot the wafer defect map corresponding to the initial defect coordinates using the adjusted lens to obtain a first shot image; and then controlling the defect re-inspection device to adaptively adjust the lens major axis length to the second difference value (X) according to the newly added lens length information. d –X b ), the minor axis length is the first difference (Y a –Y c ), and then control the defect re-inspection equipment to use the adjusted lens to add the defect coordinates ((X d –X b ) / 2,(Y a –Y c ) / 2) to capture the corresponding wafer defect image to obtain a second captured image; finally, determine whether there are defects in the first captured image and the second captured image to complete the wafer defect detection.
[0075] In an embodiment of the present invention, initial defect information is obtained, and newly added defect information corresponding to large-size defects in a wafer defect map is determined according to the initial defect information, and the newly added defect information is added to the initial defect information to obtain target defect information, and the target defect information is sent to a defect re-inspection device, and the defect re-inspection device is controlled to perform defect detection on the wafer defect map according to the target defect information. Since newly added defect information corresponding to large-size defects in the wafer defect map is determined according to the initial defect information, and the newly added defect information is added to the initial defect information to obtain the target defect information, it is equivalent to adding newly added defect information corresponding to large-size defects in the wafer defect map to the target defect information, and the target defect information includes the initial defect information and the newly added defect information corresponding to large-size defects, and then when the defect re-inspection device is controlled to perform defect detection on the wafer defect map according to the target defect information, both wafer defect detection can be performed on the wafer defect map corresponding to the initial defect information, and wafer defect detection can be performed on the wafer defect map corresponding to the large-size defects, thereby avoiding the problem of missed detection of large-size defects, effectively reducing the missed detection rate of wafer defect detection, thereby reducing the false detection rate of wafer defect detection, and increasing the reliability and accuracy of the wafer detection results.
[0076] Figure 5 Schematic diagram of a structure of a wafer defect detection device provided by an embodiment of the present invention, which is suitable for executing a wafer defect detection method provided by an embodiment of the present invention. Figure 5 As shown, the device may specifically include:
[0077] Information acquisition module 301, used to acquire initial defect information;
[0078] An information determination module 302 is used to determine, based on the initial defect information, newly added defect information corresponding to the large-size defect in the wafer defect map;
[0079] An information adding module 303 is used to add the newly added defect information to the initial defect information to obtain target defect information;
[0080] An information sending module 304 is used to send the target defect information to a defect re-inspection device;
[0081] The defect detection module 305 is used to control the defect review device to perform defect detection on the wafer defect map according to the target defect information.
[0082] Optionally, the initial defect information includes a plurality of initial defect coordinates, and the information determination module 302 is specifically used to:
[0083] Determining an actual distance between every two initial defect coordinates of the plurality of initial defect coordinates;
[0084] Determining a plurality of intermediate defect coordinates according to the actual distance and the preset distance;
[0085] According to the multiple intermediate defect coordinates, newly added defect information corresponding to the large-size defects in the wafer defect map is determined.
[0086] Optionally, the information determination module 302 determines a plurality of intermediate defect coordinates according to the actual distance and the preset distance, including:
[0087] When the actual distance is smaller than the preset distance, the initial defect coordinates where the actual distance is smaller than the preset distance are determined as the intermediate defect coordinates.
[0088] Optionally, the information determination module 302 determines the newly added defect information corresponding to the large-size defect in the wafer defect map according to the multiple intermediate defect coordinates, including:
[0089] Determine any one of the plurality of intermediate defect coordinates as an expansion point;
[0090] Taking the extension point as the center, the preset length is extended in all directions to obtain an extension area;
[0091] Determining whether the extended area includes intermediate defect coordinates;
[0092] When the intermediate defect coordinates are included in the extended area, updating the extended area according to the edge of the extended area;
[0093] When the intermediate defect coordinates are included in the updated extended area, continue to update the extended area according to the edge of the extended area until the updated extended area does not include the intermediate defect coordinates;
[0094] When the updated extended area does not include the intermediate defect coordinates, connecting a plurality of intermediate defect coordinates in the extended area to obtain a connection graph;
[0095] Determining whether the connection graph is a closed graph;
[0096] When the connection graph is a closed graph, newly added defect information corresponding to the large-size defects in the wafer defect map is determined according to a plurality of intermediate defect coordinates on the connection graph.
[0097] Optionally, the information determination module 302 determines the newly added defect information corresponding to the large-size defect in the wafer defect map according to the coordinates of the multiple intermediate defects on the connection graph, including:
[0098] Determining the coordinates of the newly added defects according to the multiple intermediate defect coordinates on the connection graph;
[0099] The newly added defect coordinates are determined as the newly added defect information corresponding to the large-size defect in the wafer defect map.
[0100] Optionally, each intermediate defect coordinate on the connection graph includes a ordinate and a abscissa, and the information determination module 302 determines the newly added defect coordinate according to the plurality of intermediate defect coordinates on the connection graph, including:
[0101] Determine a first average value of the maximum ordinate and the minimum ordinate among a plurality of intermediate defect coordinates on the connection graph;
[0102] Determine the first mean as the ordinate of the newly added defect;
[0103] Determine a second mean of the maximum horizontal coordinate and the minimum horizontal coordinate among a plurality of intermediate defect coordinates on the connection pattern;
[0104] Determine the second mean as the newly added defect abscissa;
[0105] The newly added defect ordinate and the newly added defect abscissa are determined as the newly added defect coordinates.
[0106] Optionally, the newly added defect information also includes newly added lens length information. The information determination module 302 determines the newly added defect information corresponding to the large-size defect in the wafer defect map according to the coordinates of the multiple intermediate defects on the connection graph, and further includes:
[0107] Determine a first difference between a maximum ordinate and a minimum ordinate among a plurality of intermediate defect coordinates on the connection pattern;
[0108] Determine a second difference between a maximum horizontal coordinate and a minimum horizontal coordinate among a plurality of intermediate defect coordinates on the connection pattern;
[0109] Determine a larger difference between the first difference and the second difference as the length of the major axis of the newly added lens;
[0110] Determine the smaller difference between the first difference and the second difference as the minor axis length of the newly added lens;
[0111] The length of the minor axis of the newly added lens and the length of the major axis of the newly added lens are determined as the length information of the newly added lens.
[0112] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional modules is used as an example for illustration. In actual applications, the above-mentioned functions can be assigned to different functional modules as needed, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. The specific working process of the functional modules described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.
[0113] The wafer defect detection device provided in the embodiment of the present invention can obtain initial defect information, determine new defect information corresponding to large-size defects in the wafer defect map based on the initial defect information, add the new defect information to the initial defect information, obtain target defect information, send the target defect information to the defect review equipment, and control the defect review equipment to perform defect detection on the wafer defect map according to the target defect information. Since the newly added defect information corresponding to the large-size defects in the wafer defect map is determined according to the initial defect information, and the newly added defect information is added to the initial defect information to obtain the target defect information, it is equivalent to adding the newly added defect information corresponding to the large-size defects in the wafer defect map to the target defect information. The target defect information includes the initial defect information and the newly added defect information corresponding to the large-size defects. Then, when the defect review equipment is controlled to perform defect detection on the wafer defect map according to the target defect information, wafer defect detection can be performed on the wafer defect map corresponding to the initial defect information, and wafer defect detection can also be performed on the wafer defect map corresponding to the large-size defects, thereby avoiding the problem of missed detection of large-size defects, effectively reducing the missed detection rate of wafer defect detection, thereby reducing the false detection rate of wafer defect detection, and increasing the reliability and accuracy of the wafer detection results.
[0114] In one embodiment, an electronic device is provided, which may be a server. Figure 6 It is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention.
[0115] Please refer to Figure 6 , an electronic device 50 is provided, comprising:
[0116] a processor 51; and
[0117] A memory 52, used to store executable instructions of the processor;
[0118] The processor 51 is configured to execute the above-mentioned method by executing the executable instructions.
[0119] The processor 51 can communicate with the memory 52 via a bus 53 .
[0120] The processor of the electronic device is used to provide computing and control capabilities. The memory of the electronic device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a program and a database. The internal memory provides an environment for the operation of the operating system and the program in the non-volatile storage medium. The database of the electronic device is used to store data such as initial defect information, suspected defect information and target defect information. When the program is executed by the processor, the above-mentioned wafer defect detection method is implemented.
[0121] An embodiment of the present invention further provides a computer-readable storage medium on which a computer program is stored. When the program is executed by a processor, the above-mentioned method is implemented.
[0122] Those of ordinary skill in the art can understand that the implementation of all or part of the processes in the above-mentioned embodiment method can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application may include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.
[0123] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A wafer defect detection method, characterized in that: The method comprises: Get initial defect information; Determine, based on the initial defect information, newly added defect information corresponding to the large-size defect in the wafer defect map; Adding the newly added defect information to the initial defect information to obtain target defect information; Sending the target defect information to a defect review device; The defect review equipment is controlled to perform defect detection on the wafer defect map according to the target defect information.
2. The method according to claim 1, characterized in that The initial defect information includes a plurality of initial defect coordinates, and determining the newly added defect information corresponding to the large-size defect in the wafer defect map according to the initial defect information includes: Determining an actual distance between every two initial defect coordinates of the plurality of initial defect coordinates; Determining a plurality of intermediate defect coordinates according to the actual distance and the preset distance; According to the multiple intermediate defect coordinates, newly added defect information corresponding to the large-size defects in the wafer defect map is determined.
3. The method according to claim 2, characterized in that The step of determining a plurality of intermediate defect coordinates according to the actual distance and the preset distance includes: When the actual distance is smaller than the preset distance, the initial defect coordinates where the actual distance is smaller than the preset distance are determined as the intermediate defect coordinates.
4. The method according to claim 2, characterized in that: Determining the newly added defect information corresponding to the large-size defect in the wafer defect map according to the multiple intermediate defect coordinates includes: Determine any one of the plurality of intermediate defect coordinates as an expansion point; Taking the extension point as the center, the preset length is extended in all directions to obtain an extension area; Determining whether the extended area includes intermediate defect coordinates; When the intermediate defect coordinates are included in the extended area, updating the extended area according to the edge of the extended area; When the intermediate defect coordinates are included in the updated extended area, continue to update the extended area according to the edge of the extended area until the updated extended area does not include the intermediate defect coordinates; When the updated extended area does not include the intermediate defect coordinates, connecting a plurality of intermediate defect coordinates in the extended area to obtain a connection graph; Determining whether the connection graph is a closed graph; When the connection graph is a closed graph, newly added defect information corresponding to the large-size defects in the wafer defect map is determined according to a plurality of intermediate defect coordinates on the connection graph.
5. The method according to claim 4, characterized in that Determining the newly added defect information corresponding to the large-size defect in the wafer defect map according to the multiple intermediate defect coordinates on the connection pattern includes: Determining the coordinates of the newly added defects according to the multiple intermediate defect coordinates on the connection graph; The newly added defect coordinates are determined as the newly added defect information corresponding to the large-size defect in the wafer defect map.
6. The method according to claim 5, characterized in that Each intermediate defect coordinate on the connection graph includes a ordinate and a abscissa, and the determining of the newly added defect coordinate according to the plurality of intermediate defect coordinates on the connection graph includes: Determine a first average value of the maximum ordinate and the minimum ordinate among a plurality of intermediate defect coordinates on the connection graph; Determine the first mean as the ordinate of the newly added defect; Determine a second mean of the maximum horizontal coordinate and the minimum horizontal coordinate among a plurality of intermediate defect coordinates on the connection pattern; Determine the second mean as the newly added defect abscissa; The newly added defect ordinate and the newly added defect abscissa are determined as the newly added defect coordinates.
7. The method according to claim 5, characterized in that The newly added defect information also includes newly added lens length information, and the method further includes: Determine a first difference between a maximum ordinate and a minimum ordinate among a plurality of intermediate defect coordinates on the connection pattern; Determine a second difference between a maximum horizontal coordinate and a minimum horizontal coordinate among a plurality of intermediate defect coordinates on the connection pattern; Determine a larger difference between the first difference and the second difference as the length of the major axis of the newly added lens; Determine the smaller difference between the first difference and the second difference as the minor axis length of the newly added lens; The length of the minor axis of the newly added lens and the length of the major axis of the newly added lens are determined as the length information of the newly added lens.
8. A wafer defect detection device, characterized in that: The device comprises: An information acquisition module, used to obtain initial defect information; An information determination module, configured to determine, based on the initial defect information, newly added defect information corresponding to the large-size defect in the wafer defect map; An information adding module, used for adding the newly added defect information to the initial defect information to obtain target defect information; An information sending module, used for sending the target defect information to a defect review device; The defect detection module is used to control the defect review equipment to perform defect detection on the wafer defect map according to the target defect information.
9. An electronic device, characterized in that: Including processor and memory, The memory is used to store codes and related data; The processor is used to execute the code in the memory to implement the wafer defect detection method according to any one of claims 1 to 7.
10. A storage medium having a computer program stored thereon, wherein when the program is executed by a processor, the wafer defect detection method according to any one of claims 1 to 7 is implemented.