Selecting position of object in image

Abstract

The invention discloses selecting a position of an object in an image. Apparatuses, systems, and methods for causing identification of one or more positions of one or more objects in one or more images based at least in part on one or more positions of one or more objects in one or more previous images are disclosed.

Description

Technical Field

[0001] Devices, systems and methods for enabling identification of one or more locations of one or more objects in one or more images based at least in part on one or more locations of the one or more objects in one or more previous images. For example, a processor including one or more circuits is used to generate a region of interest (ROI) based on a combination of one or more locations. Background Art

[0002] Performing object detection in one or more images requires a lot of resources because every part of each frame needs to be evaluated to locate the object, even if many sections of the frame do not contain any objects. This resource usage is particularly evident when performing object detection on many consecutive frames. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Figure 1 An exemplary system for performing object detection using one or more neural networks in accordance with at least one embodiment is shown;

[0004] Figure 2 An example illustrating selecting a region of interest (ROI) is shown in accordance with at least one embodiment;

[0005] Figure 3 illustrates a region of interest selection process according to at least one embodiment;

[0006] Figure 4 Additional exemplary embodiments of a region of interest selection process according to at least one embodiment are shown;

[0007] Figure 5 An exemplary process for adjusting a previously selected region of interest in accordance with at least one embodiment is shown;

[0008] Figure 6 An exemplary system for performing region of interest selection according to at least one embodiment is shown;

[0009] Figure 7 A video analytics architecture using a region of interest process according to at least one embodiment is shown;

[0010] Figure 8 is a block diagram illustrating a driver and / or runtime including one or more libraries for providing one or more application programming interfaces according to at least one embodiment;

[0011] Fig. 9A illustrates logic according to at least one embodiment;

[0012] Fig. 9B illustrates logic according to at least one embodiment;

[0013] Fig.10 illustrates the training and deployment of a neural network according to at least one embodiment;

[0014] Fig.11 An example data center system is shown in accordance with at least one embodiment;

[0015] Fig. 12A An example of an autonomous vehicle is shown in accordance with at least one embodiment;

[0016] Fig. 12B According to at least one embodiment, Fig. 12A Examples of camera positions and fields of view for autonomous vehicles;

[0017] Fig. 12C is an illustration according to at least one embodiment Fig. 12A A block diagram of an example system architecture for an autonomous vehicle;

[0018] Fig.12D is a diagram illustrating a method for one or more cloud-based servers and Fig. 12A A diagram of a system for communicating between autonomous vehicles;

[0019] Fig.13 is a block diagram illustrating a computer system according to at least one embodiment;

[0020] Fig.14 is a block diagram illustrating a computer system according to at least one embodiment;

[0021] Fig.15 A computer system according to at least one embodiment is shown;

[0022] Fig.16 A computer system according to at least one embodiment is shown;

[0023] Fig.17A A computer system according to at least one embodiment is shown;

[0024] Fig. 17B A computer system according to at least one embodiment is shown;

[0025] Fig. 17C A computer system according to at least one embodiment is shown;

[0026] Fig.17D A computer system according to at least one embodiment is shown;

[0027] Fig.17E and Fig.17Fillustrates a shared programming model according to at least one embodiment;

[0028] Fig.18 An exemplary integrated circuit and associated graphics processor are shown in accordance with at least one embodiment;

[0029] Fig.19A and Fig.19B An exemplary integrated circuit and associated graphics processor are shown in accordance with at least one embodiment;

[0030] Fig. 20A and Fig. 20B Additional exemplary graphics processor logic is shown in accordance with at least one embodiment;

[0031] Fig.21 A computer system according to at least one embodiment is shown;

[0032] Fig.22A illustrates a parallel processor according to at least one embodiment;

[0033] Fig. 22B shows a partition unit according to at least one embodiment;

[0034] Fig. 22C illustrates a processing cluster according to at least one embodiment;

[0035] Fig.22D A graphics multiprocessor is shown in accordance with at least one embodiment;

[0036] Fig.23 A multi-graphics processing unit (GPU) system is shown in accordance with at least one embodiment;

[0037] Fig.24 A graphics processor according to at least one embodiment is shown;

[0038] Fig.25 is a block diagram illustrating a processor microarchitecture for a processor according to at least one embodiment;

[0039] Fig.26 A deep learning application processor according to at least one embodiment is shown;

[0040] Fig. 27 is a block diagram illustrating an example neuromorphic processor in accordance with at least one embodiment;

[0041] Fig.28 illustrates at least a portion of a graphics processor according to one or more embodiments;

[0042] Fig.29 illustrates at least a portion of a graphics processor according to one or more embodiments;

[0043] Fig.30 illustrates at least a portion of a graphics processor according to one or more embodiments;

[0044] Fig.31 is a block diagram of a graphics processing engine of a graphics processor according to at least one embodiment;

[0045] Fig.32 is a block diagram of at least a portion of a graphics processor core according to at least one embodiment;

[0046] Fig.33A and Fig.33B Thread execution logic is shown that includes an array of processing elements of a graphics processor core in accordance with at least one embodiment.

[0047] Fig.34 illustrates a parallel processing unit ("PPU") in accordance with at least one embodiment;

[0048] Fig.35 illustrates a general processing cluster ("GPC") in accordance with at least one embodiment;

[0049] Fig.36 illustrates a memory partitioning unit of a parallel processing unit ("PPU") according to at least one embodiment;

[0050] Fig.37 A streaming multiprocessor is shown according to at least one embodiment;

[0051] Fig.38 is an example data flow diagram of a high-level computing pipeline according to at least one embodiment;

[0052] Fig.39 is a system diagram of an example system for training, adapting, instantiating, and deploying machine learning models in an advanced computing pipeline in accordance with at least one embodiment;

[0053] Fig.40 includes an example illustration of a high-level computational pipeline for processing imaging data according to at least one embodiment;

[0054] Fig.41A An example data flow diagram including a virtual instrument supporting an ultrasound device according to at least one embodiment;

[0055] Fig.41B An example data flow diagram including a virtual instrument supporting a CT scanner according to at least one embodiment;

[0056] Fig.42A A data flow diagram illustrating a process for training a machine learning model according to at least one embodiment; and

[0057] Fig.42B is an example illustration of a client-server architecture for enhancing an annotation tool using a pre-trained annotation model in accordance with at least one embodiment. DETAILED DESCRIPTION

[0058] In at least one embodiment, a system, apparatus and / or technique is used to identify one or more locations of one or more objects in one or more images based at least in part on one or more locations of the one or more objects in one or more previous images and / or otherwise perform the operations discussed herein.

[0059] In at least one embodiment, one or more portions of a video frame are selected and a neural network is used to perform inference for the one or more portions of the video frame based on locations where objects appeared in previous video frames. When using a neural network to perform object detection, a significant amount of resources can be wasted in determining whether image regions contain objects when in fact these regions do not contain any objects for which detection is to be performed. For example, for road images, resources are wasted in determining whether image regions contain cars when in fact many regions of the image do not contain cars and are unlikely to contain cars. This use of resources is particularly noticeable when performing object detection in a video when a neural network is used for many frames.

[0060] In at least one embodiment, one or more neural networks perform object detection (also referred to herein as an object detection neural network) in one or more frames of a live video feed. In at least one embodiment, the one or more neural networks perform object detection only within a selected region of interest (ROI). In at least one embodiment, one or more neural networks identify a ROI (also referred to herein as a region of interest neural network) and adjust (e.g., modify) the ROI for use with the object detection neural network. In at least one embodiment, the region of interest neural network divides an input frame of a video feed into a plurality of segments according to a segmentation ratio. In at least one embodiment, the region of interest neural network performs reasoning on each of the plurality of segments of the input frame to identify reasoning activity within the segment (e.g., where one or more objects are detected). In at least one embodiment, the region of interest neural network identifies (e.g., selects) a region of interest of the video feed as a combination of one or more segments identified as having reasoning activity. In at least one embodiment, a region of interest neural network is not required to identify a ROI, as one or more computing systems may execute software to identify the ROI using one or more images.

[0061] In at least one embodiment, one or more neural networks perform object detection on frames of a video. In at least one embodiment, the system or device divides the field of view of the camera into a grid and calculates statistics indicating how often objects appear in each segment of the grid (e.g., the number of times or frequency that a car appears in each segment of the grid). In at least one embodiment, after collecting the statistics, the one or more neural networks perform object detection to generate output only for segments of the grid where the statistics indicate that objects appear frequently (e.g., the amount of time between the frames exceeds a predetermined threshold).

[0062] In at least one embodiment, a system or device having the object detection neural network performs object detection on a selected ROI in real time (or near real time) on a live video feed. In at least one embodiment, the region of interest neural network further dynamically adjusts (e.g., modifies, shrinks, enlarges, etc.) the ROI so that the ROI only contains image segments relevant to object detection without requiring additional user input. In at least one embodiment, the region of interest neural network infers that the ROI does not need to be adjusted based on image segments relevant to object detection (e.g., when there is no inference activity in one or more additional segments in the image). In at least one embodiment, the ROI can be determined using software to be executed by one or more processors without using a neural network.

[0063] In at least one embodiment, a system or device using one or more neural networks described herein is part of a DeepStream architecture pipeline for machine vision or intelligent video analysis (IVA) operations. In at least one embodiment, a system or device using one or more neural networks described herein reduces the required power requirements, bandwidth, or other processing computing resources by limiting object detection to only a portion of the frames within a selected ROI. In at least one embodiment, a system or device using one or more neural networks described herein adjusts the selected ROI without further human intervention.

[0064] In the foregoing and following descriptions, various techniques are described. For the purpose of explanation, specific configurations and details are set forth in order to provide a thorough understanding of possible ways to implement the techniques. However, it will also be apparent that the techniques described below can be practiced in different configurations without the specific details. In addition, well-known features may be omitted or simplified to avoid obscuring the described techniques.

[0065] Figure 1 An exemplary system 100 for performing object detection using a neural network (e.g., object detection neural network 112) is shown in accordance with at least one embodiment. In at least one embodiment, system 100 has a processor ( Figure 1Not depicted, but will be referenced Figure 6 ), the processor causes one or more locations of one or more objects in one or more images to be identified based at least in part on one or more locations of one or more objects in one or more previous images. In at least one embodiment, the camera 102 ( Figure 1 Only one camera is depicted, but more than one camera is also reasonable) to capture a video feed including multiple image frames. In at least one embodiment, these image frames are input as input images 104 through network 106 to a processor including a region of interest neural network 108.

[0066] In at least one embodiment, the processor uses the region of interest neural network 108 to determine a region of interest (ROI) 110 in which to perform object detection. In at least one embodiment, the region of interest neural network 108 divides the input image 104 into a plurality of segments according to a given segmentation ratio. In at least one embodiment, the segmentation ratio is based on the resolution of the input image 104 (e.g., dividing a 4K image into segments of 192x108 pixels each), based on a preset number of segments (e.g., dividing the input image into 50 segments), or other similar techniques. In at least one embodiment, the segmentation ratio is based on various factors, including: the resolution of one or more images, the resolution required to use one or more neural networks, the number of objects detected in previous or concurrent inference rounds, and / or other user-defined parameters. In at least one embodiment, by segmenting the input image 104 into a plurality of segments, this will reduce the frame size and can also reduce processing time.

[0067] In at least one embodiment, the region of interest neural network 108 divides the input image 104 into a plurality of segments, wherein the resolution of at least one of the plurality of segments is varied. In at least one embodiment, the processor forms a batch of segments based at least in part on the segments from the image. In at least one embodiment, all segments in a batch have the same resolution.

[0068] In at least one embodiment, the region of interest neural network 108 performs inference on each segment of the input image 104. In at least one embodiment, the inference is object detection, motion detection, and / or any other activity that the neural network is to detect. In at least one embodiment, the region of interest neural network 108 groups and combines each segment identified as having inference activity into a ROI 110. In at least one embodiment, the region of interest neural network 108 creates a visual overlay of the ROI 110 for output to a display ( Figure 1 not shown).

[0069] In at least one embodiment, an input image 104 having a ROI 110 is input to an object detection neural network 112. In at least one embodiment, the object detection neural network 112 detects and counts one or more objects within the ROI 110 in the video feed. In at least one embodiment, the one or more objects are predetermined by a user for a particular task (e.g., detecting and counting cars using a traffic camera, detecting and counting animals using a wildlife camera, etc.). In at least one embodiment, an object detection output 114 including detected objects and object counts is output to a user, another system, a storage device, and / or a subsequent portion in an imaging pipeline.

[0070] In at least one embodiment, the processor uses the object detection neural network 112 to perform reasoning on the input image 104 for output. In at least one embodiment, the processor uses the region of interest neural network 108 to perform preliminary reasoning to determine the region of interest. In at least one embodiment, the processor first receives the input image 104 using the object detection neural network 112 to perform preliminary reasoning and outputs information to the region of interest neural network 108 to select the region of interest.

[0071] In at least one embodiment, one or more neural networks (e.g., the region of interest neural network 108 or the object detection neural network 112) receive a batch of one or more portions of one or more images for inference. In at least one embodiment, the one or more neural networks receive and use one or more portions or segments for inference. In at least one embodiment, the size of at least one object in each segment in one image is larger than one or more objects in a segment of another image. In at least one embodiment, the one or more neural networks are used to detect objects within a certain size range. In at least one embodiment, the one or more neural networks are trained to detect one or more objects of similar size to one or more objects in each portion, but are not trained to detect one or more objects of similar size to one or more objects in the image. In at least one embodiment, the one or more neural networks are used to detect objects in a certain view or perspective. In at least one embodiment, the one or more neural networks are trained to detect one or more objects displayed in a view or perspective similar to one or more objects in each portion, but are not trained to detect one or more objects displayed in a view or perspective similar to one or more objects in the image. In at least one embodiment, the number of objects detected in all portions using the one or more neural networks is greater than the number of objects detected in the image using the one or more neural networks.

[0072] In at least one embodiment, one or more neural networks (e.g., region of interest neural network 108 or object detection neural network 112) identify all detected objects in all parts and return an inference result. In at least one embodiment, one or more neural networks combine all parts into a combined image and then return an inference result. In at least one embodiment, one or more neural networks change the resolution of at least one of the plurality of parts before combining all parts. In at least one embodiment, one or more neural networks locate one or more parts and then combine all parts.

[0073] In at least one embodiment, the processor uses one or more neural networks (e.g., region of interest neural network 108 or object detection neural network 112) to identify one or more objects in one or more images regardless of the size or view of the one or more objects used to train the one or more neural networks. In at least one embodiment, the one or more neural networks can use one or more untrained neural networks to detect the one or more objects with different sizes or views of the one or more objects by segmenting the one or more images into multiple parts. In at least one embodiment, the system can improve inference accuracy by allowing one or more neural networks to detect many objects with smaller sizes without using one or more neural networks that are specifically trained / retrained to detect only small objects.

[0074] In at least one embodiment, the system 100 is a collection of one or more hardware and / or software computing resources having instructions that, when executed, perform one or more communication processes, such as the communication processes described herein. In at least one embodiment, the system 100 is a software program executed on computer hardware, an application program executed on computer hardware, and / or a variant thereof. In at least one embodiment, one or more processes of the system 100 are executed in any suitable manner by any suitable processing system or unit (e.g., a graphics processing unit (GPU), a general purpose GPU (GPGPU), a parallel processing unit (PPU), a central processing unit (CPU)), a data processing unit (DPU) (described below), including sequentially, in parallel, and / or variants thereof. In at least one embodiment, the system 100 uses a machine learning training framework (e.g., PyTorch, TensorFlow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j) and / or other training frameworks to implement and perform the operations described herein to generate one or more portions of an image based at least in part on less than the entire portion of one or more portions using one or more neural networks. In at least one embodiment, as an example, training the neural network model includes using a server (e.g., an NVIDIA DGX server) that also includes at least a GPU (e.g., 8 A100 40GB GPUs, AMD MI200, Vegal10, Vego20, and Arcturus), an optimizer (e.g., Adam Optimizer), or a discriminator architecture (e.g., a discriminator architecture from face-vid2vid for training using a GAN loss).

[0075] In at least one embodiment, the system 100 includes one or more modules or units. In at least one embodiment, the system 100 includes one or more modules and / or units, such as Figure 6 One or more modules described in Figure 6Elements 606-612 of ), such that the system causes one or more locations of one or more objects in one or more images to be identified based at least in part on one or more locations of one or more objects in one or more previous images. In at least one embodiment, the module or unit includes any combination of any type of logic (e.g., software, hardware, firmware) and / or circuits configured to perform the functions. In at least one embodiment, the module or unit includes one or more circuits that form part of a larger system (e.g., an integrated circuit (IC), a system on a chip (SoC), a central processing unit (CPU), a graphics processing unit (GPU), a data processing unit (DPU), etc.). In at least one embodiment, the controller includes any type of logic (e.g., software, hardware, firmware) and / or circuits configured to perform the functions. In at least one embodiment, the software includes a software package, a code, a programming language, a driver, an instruction, an instruction set, or some combination thereof. In at least one embodiment, the hardware includes a hardwired circuit, a programmable circuit, a state machine circuit, a fixed function circuit, an execution unit circuit, a firmware storing instructions executed by a programmable circuit, or some combination of the above. In at least one embodiment, system 100 performs one or more processes, such as in conjunction with Figures 2 to 8 The processes described.

[0076] In at least one embodiment, the system 100 includes one or more modules, which include one or more logic units. In at least one embodiment, the system 100 includes an image segmentation module 606, a reasoning module 608, a ROI selection module 610 and / or a memory 612, such as Figure 6 As shown. In at least one embodiment, the logic unit includes firmware logic, hardware logic, or some combination thereof configured to provide any functionality further described herein. In at least one embodiment, the logic unit includes circuitry that forms part of a larger system (e.g., IC, SoC, CPU, GPU, DPU). In at least one embodiment, the logic unit includes logic circuitry for implementing firmware and / or hardware to identify one or more locations of one or more objects in one or more images based at least in part on one or more locations of one or more objects in one or more previous images and / or otherwise perform the operations discussed herein.

[0077] In at least one embodiment, the system 100 includes one or more engines including modules and / or logic units as described above and further described herein. In at least one embodiment, the components include modules and / or logic units further described herein. In at least one embodiment, the engine includes software logic, firmware logic, hardware logic, or some combination thereof configured to provide any functions further described herein. In at least one embodiment, the components include software logic, firmware logic, hardware logic, or some combination thereof configured to provide any functions further described herein. In at least one embodiment, the operations performed by hardware and / or firmware may be implemented alternatively by software modules, which may be embodied as software packages, codes, and / or instruction sets. In at least one embodiment, the logic units may also utilize a portion of software to implement their functions. In at least one embodiment, the system 100 includes a machine-readable medium having a set of instructions stored thereon, which, if executed by one or more processors, causes one or more processors to identify one or more positions of one or more objects in one or more images based at least in part on one or more positions of one or more objects in one or more previous images and / or otherwise perform the operations described herein.

[0078] In at least one embodiment, the system 100 performs image processing, or otherwise referred to as processing of an image (e.g., input image 104), which includes analysis or manipulation of a digitized image. In at least one embodiment, the processor uses one or more neural networks trained in conjunction with the system 100 to perform image enhancement, segmentation, reconstruction, anomaly detection, object detection, feature detection, treatment planning, dosimetry, beam planning (or other radiation therapy procedures), and / or other analysis, image processing, or reasoning tasks. In at least one embodiment, the image (e.g., one or more input images 104) includes a digital image, medical imaging, a photograph, a training image, a synthetic image, a video frame, a video game frame, or a set of frames of a video or video game. In at least one embodiment, the image (e.g., input image 104) includes one or more pixels, features, data, tensors, and / or other representations of an image. In at least one embodiment, a pixel is a point on an image that exhibits shading, opacity, or color. In at least one embodiment, a pixel is represented in the form of data (e.g., grayscale, RGB, RGBA, or other variants). In at least one embodiment, a processor (e.g., Figure 6104) performs image processing to analyze or manipulate the input image 104. In at least one embodiment, the processor uses a neural network to perform image processing on the input image 104. In at least one embodiment, examples of image processing include scaling, distortion, cropping, visualization, recognition, sharpening, restoration, pattern recognition, and / or retrieval of an image.

[0079] In at least one embodiment, the input image 104 is obtained using one or more cameras 102, an imaging device, and / or by another system ( Figure 1 In at least one embodiment, the input image 104 includes synthetic data, medical images, and / or video data. In at least one embodiment, the input image 104 includes images of objects to be detected and counted in a given scene predetermined by a user, such as cars on a road. In at least one embodiment, the input image 104 is obtained from an autonomous vehicle (e.g., a reference vehicle) in a driving environment. Figures 12A-12D described) or medical imaging equipment (e.g., reference Figure 38-41B The image obtained by the driving environment includes one or more roads, cars, trucks, trees and / or objects commonly found in a driving environment.

[0080] In at least one embodiment, input image 104 is transmitted through network 106 to region of interest neural network 108 or object detection neural network 112 (or Figure 1 108 and another neural network not depicted in the figure). In at least one embodiment, network 106 represents any suitable communication path between region of interest neural network 108 and one or more other systems. In at least one embodiment, network 106 includes one or more networks, such as the Internet, a local area network, a wide area network, and / or variations thereof. In at least one embodiment, input image 104 includes image data and / or one or more labels (e.g., annotations) determined using various systems, including but not limited to NLP-based annotation tools associated with text data.

[0081] Figure 2 An example 200 is shown showing a region of interest selection of an image 202 in accordance with at least one embodiment. In at least one embodiment, images 202-208 show results from a process in which one or more circuits cause one or more locations of one or more objects in one or more images to be identified based at least in part on one or more locations of one or more objects in one or more previous images. In at least one embodiment, camera 102 (e.g., Figure 1In at least one embodiment, image 202 is a frame of the video that shows a car on a road surrounded by trees, road signs, and buildings, for example, where a user may wish to track traffic patterns on the road. In at least one embodiment, the user specifies that the system 100 recognize cars and trains any or all of the system's neural networks (e.g., region of interest neural network 108, object detection neural network 112, or Figure 1 In at least one embodiment, the image 202 is acquired with respect to a statically mounted camera. In at least one embodiment, the image 202 is acquired using an autonomous vehicle (e.g., a reference Figures 12A-12D The camera in the above) is used to assist in controlling the vehicle.

[0082] In at least one embodiment, there are occasions where it is not preferred to perform object detection on the entire image 202. In at least one embodiment, the image 204 shows a portion 210 of the image (indicated by the parallel lines at the top of the image 204) where cars are not expected to be located, so performing object detection on these areas has little benefit in tracking traffic patterns. In at least one embodiment, specific ROIs in which to perform object detection can be defined to reduce bandwidth, power consumption, or other processing computing resources required for analysis.

[0083] In at least one embodiment, image 206 shows that input image 202 is divided into segments 212 (indicated by the grid in image 206). In at least one embodiment, the processor divides image 206 into segments 212 and identifies the segments in which reasoning activity occurs (indicated by white check marks 214 in image 206). In at least one embodiment, reasoning activity is any activity or target that is recognized or reasoned in a neural network imaging task, such as an object in an object detection task, a movement in a motion detection task, a face in a face detection task, a person in a surveillance task, or other targets in other similar tasks. In at least one embodiment, a positive determination of reasoning activity is based on a threshold, such as an object count, reasoning duration, reasoning confidence score, and / or other metrics that measure the reasoning or recognition. In at least one embodiment, when the task is to recognize a car, if a car is recognized in more than 1 frame within segment 212, the processor executing the neural network will determine that segment 212 has reasoning activity.

[0084] In at least one embodiment, although ROI 216 is Figure 2 216 is shown as a generally rectangular shape, but the ROI 216 is a combination of the segments 212 and can therefore be any shape including the segments. In at least one embodiment, the combination of the segments 212 is a square, a circle, a triangle, or any polygonal shape.

[0085] In at least one embodiment, the camera capturing the input image 202 is a traffic camera. In at least one embodiment, the one or more neural networks will detect that cars are present in the segments of the grid corresponding to roads, but not in the segments of the grid corresponding to off-road areas (e.g., trees, sky, etc.). In at least one embodiment, the one or more neural networks define a ROI that contains only road areas based on the segments of the grid corresponding to the roads.

[0086] Figure 3 A region of interest selection process 300 is shown according to at least one embodiment. In at least one embodiment, by performing Figure 3 The process 300 includes a processor of one or more circuits for causing one or more locations of one or more objects in one or more images to be identified based at least in part on one or more locations of one or more objects in one or more previous images. In at least one embodiment, for example, with reference to Figure 3 As discussed, these one or more locations are combined to generate segments of a region of interest in which object detection is performed. In at least one embodiment, the neural network will perform inference on segments of a video frame based on locations where objects appeared in previous video frames.

[0087] In at least one embodiment, at step 302, a processor (e.g., Figure 6 The processor 604 of the embodiment receives an image captured by a camera (e.g., camera 102) or otherwise generated using another technique (e.g., Figure 1 In at least one embodiment, the image is a still image. In at least one embodiment, the image is a frame of a moving image or video. In at least one embodiment, the image is a current frame following an earlier frame of the moving image or video.

[0088] In at least one embodiment, at step 304, the processor divides the image into segments (e.g., Figure 2 In at least one embodiment, the division into segments is based on a given segmentation ratio. In at least one embodiment, the segmentation ratio is based on the resolution of the input image 104 (e.g., dividing a 4K image into segments of 192x108 pixels each), a preset number of segments (e.g., dividing the input image into 50 segments), or other similar techniques.

[0089] In at least one embodiment, at step 306, a neural network (e.g., Figure 1The processor of the region of interest neural network 108 identifies the segment or location where the object exists. In at least one embodiment, the processor performs an initial object detection operation to identify the segment or location where the current object is detected.

[0090] In at least one embodiment, the processor receives a new image, such as a new frame of input video, at step 308. In at least one embodiment, the processor performs additional object detection operations to identify whether the segment previously identified as having an object at step 306 still contains one or more objects.

[0091] In at least one embodiment, at step 310, if a segment in the image received in step 302 and a corresponding segment in the image received in step 308 both contain an object, the processor determines that the segment meets the threshold and determines that the segment will be part of the region of interest. In at least one embodiment, if a segment in the image received in step 302 and a corresponding segment in the image received in step 308 do not both contain an object, the segment will not be part of the region of interest.

[0092] In at least one embodiment, a processor including one or more circuits is configured to combine all segments designated as being part of the region of interest into a selected region of interest at step 312. In at least one embodiment, a processor including one or more circuits is configured to use one or more neural networks (e.g., Figure 1 The object detection neural network 112) is configured to perform object detection only within the selected region of interest.

[0093] In at least one embodiment, by performing part or all of process 300, a processor including one or more circuits is configured to use one or more neural networks to indicate that one or more regions of one or more first images are to be used to perform object detection based at least in part on one or more locations of one or more objects in one or more second images. In at least one embodiment, a processor including one or more circuits is configured to determine a selected ROI for a current frame by maintaining or adjusting a previously selected ROI from an earlier frame. In at least one embodiment, the previously selected ROI is determined by combining regions in the earlier frame (e.g., with respect to the selected ROI). Figure 3 The area described in steps 304-312) is selected.

[0094] In at least one embodiment, processor 604 uses Figure 6One or more modules described in the process 300 are used to perform one or more steps in the process 300. In at least one embodiment, one or more steps in the process 300 are combined in other ways, performed in series and / or performed in parallel. In at least one embodiment, part or all of the process 300 (or any other process described herein, or a variant and / or combination thereof) is executed under the control of one or more computer systems configured with computer executable instructions, and is implemented as a code (e.g., computer executable instructions, one or more computer programs, or one or more applications) jointly executed by hardware, software, or a combination thereof on one or more processors. In at least one embodiment, the code is stored on a computer-readable storage medium in the form of a computer program, which includes a plurality of computer-readable instructions that can be executed by one or more processors. In at least one embodiment, the computer-readable storage medium is a non-transitory computer-readable medium. In at least one embodiment, at least some of the computer-readable instructions that can be used to perform the process 300 are not stored using only transient signals (e.g., propagated transient electrical or electromagnetic transmissions). In at least one embodiment, the non-transitory computer-readable medium does not necessarily include non-transitory data storage circuits (e.g., buffers, caches, and queues) within the transient signal transceiver. In at least one embodiment, process 300 is performed at least in part on a computer system (e.g., a computer system described elsewhere in this disclosure). In at least one embodiment, logic (e.g., hardware, software, or a combination of hardware and software) performs process 300.

[0095] Figure 4 An additional exemplary embodiment of a region of interest selection process 400 is shown. In at least one embodiment, by performing Figure 4 The process 400 includes a processor of one or more circuits that causes one or more locations of one or more objects in one or more images to be identified based at least in part on one or more locations of one or more objects in one or more previous images. In at least one embodiment, for example, with reference to Figure 4 As discussed, these one or more locations are segments that are combined to generate a region of interest (ROI) in which object detection is performed. In at least one embodiment, the ROI includes only one of the one or more locations. In at least one embodiment, a processor including a neural network (e.g., region of interest neural network 108) performs process 400 in its entirety. In at least one embodiment, multiple processors with multiple neural networks perform the steps or functions of process 400.

[0096] In at least one embodiment, at step 402, a processor (e.g., Figure 6The processor 604 of the embodiment receives an input video frame (e.g., a frame captured by a camera (e.g., camera 102) or otherwise generated using another technique (e.g., Figure 1 In at least one embodiment, the video frame is a single frame from a moving image or video.

[0097] In at least one embodiment, at step 404, the processor divides the input frame into divided segments (eg, Figure 2 In at least one embodiment, the split ratio is based on the resolution of the input image 104 (e.g., dividing a 4K image into segments of 192x108 pixels each), a preset number of segments (e.g., dividing the input image into 50 segments), or other similar techniques.

[0098] In at least one embodiment, at step 406, the processor determines whether any inference activity occurs within each of the segmented segments. In at least one embodiment, the inference activity is any activity or target identified or inferred in a neural network imaging task, such as an object in an object detection task, a movement in a motion detection task, a face in a facial detection task, a person in a surveillance task, or other targets in other similar tasks. In at least one embodiment, the relative coordinates of the identified inference activities are stored in a memory along with accompanying metadata. In at least one embodiment, the neural network is used to perform inference on segments of a video frame based on locations where objects appeared in previous video frames.

[0099] In at least one embodiment, at step 408, the processor determines whether the segmented segment evaluated at step 406 is the last segmented segment to be processed. In at least one embodiment, if the last segmented segment has not been processed (no at step 408), the process 400 returns to step 406. In at least one embodiment, if the last segmented segment has been processed (yes at step 408), the process 400 continues to step 410.

[0100] In at least one embodiment, at step 410, the processor combines and locates the inference activity outputs for each individual segmented segment with the accompanying metadata. In at least one embodiment, the combined inference outputs define a region of interest (ROI) where a predetermined object or activity is expected to occur. In at least one embodiment, the ROI is smaller than the entire input video frame. In at least one embodiment, the ROI is designated as the area to which inference (e.g., object detection) for future video frames will be confined.

[0101] In at least one embodiment, by performing part or all of process 300, the processor uses one or more neural networks to indicate one or more regions of one or more first images to be used to perform object detection based at least in part on one or more locations of one or more objects in one or more second images. In at least one embodiment, the processor determines the selected ROI for the current frame by maintaining or adjusting a previously selected ROI from an earlier frame. In at least one embodiment, the previously selected ROI is selected by combining regions in the earlier frame, such as with respect to Figure 4 as described in steps 406-410.

[0102] In at least one embodiment, at step 412, the processor creates an overlay that visually indicates the ROI designated for active reasoning. In at least one embodiment, a monitor or display (not shown) outputs live video along with the overlay to display the current ROI size and position to the user. In at least one embodiment, as the ROI changes, the overlay also changes, allowing the user to visually identify any changes in reasoning activity.

[0103] In at least one embodiment, processor 604 uses Figure 6One or more modules described in the process 400 perform one or more steps in the process 400. In at least one embodiment, one or more steps in the process 400 are combined in other ways, executed in series and / or executed in parallel. In at least one embodiment, some or all of the process 400 (or any other process described herein, or a variant and / or combination thereof) are executed under the control of one or more computer systems configured with computer executable instructions, and are implemented as codes (e.g., computer executable instructions, one or more computer programs, or one or more applications) jointly executed by hardware, software, or a combination thereof on one or more processors. In at least one embodiment, the code is stored on a computer-readable storage medium in the form of a computer program, which includes a plurality of computer-readable instructions executable by one or more processors. In at least one embodiment, the computer-readable storage medium is a non-transitory computer-readable medium. In at least one embodiment, at least some of the computer-readable instructions that can be used to perform the process 400 are not stored using only transient signals (e.g., propagated transient electrical or electromagnetic transmissions). In at least one embodiment, the non-transitory computer-readable medium does not necessarily include non-transitory data storage circuits (e.g., buffers, caches, and queues) within the transient signal transceiver. In at least one embodiment, process 400 is performed at least in part on a computer system (such as a computer system described elsewhere in this disclosure). In at least one embodiment, logic (eg, hardware, software, or a combination of hardware and software) performs process 400.

[0104] Figure 5 An exemplary process 500 for adjusting a previously selected region of interest is shown in accordance with at least one embodiment. Figure 5 The process 500 includes a processor of one or more circuits to adjust the size and / or shape of the region of interest based at least in part on one or more locations of one or more objects in one or more previous images. In at least one embodiment, for example, referring to Figure 5 As discussed, these one or more locations are combined to generate a segment of a region of interest in which object detection is performed. In at least one embodiment, a processor including a neural network (e.g., region of interest neural network 108) fully performs process 400. In at least one embodiment, multiple processors with multiple neural networks perform the steps or functions of process 400 in combination.

[0105] In at least one embodiment, at step 502, a neural network (e.g., Figure 1A processor of the object detection neural network 112 in the ROI performs object detection within the currently selected region of interest. In at least one embodiment, after object detection has been performed for a certain threshold (e.g., after N frames, seconds, or other units of measurement, where N is an integer), the processor re-evaluates the current ROI to determine whether the ROI should be adjusted based on current conditions. For example, when tracking traffic conditions, fewer cars are expected in the evening, so processing power and resources can be saved by performing object detection on a reduced or shrunk ROI during this time.

[0106] In at least one embodiment, at step 504, a neural network (e.g., Figure 1 A processor of the region of interest neural network 108) evaluates the reasoning activity of the segmented segments within the current region of interest to determine whether any boundaries of the ROI need to be reduced. Figure 3 Course 300 and / or Figure 4 In at least one embodiment, if the reasoning activity indicates that the current segmented segment is still relevant to the ROI, the processor identifies the segmented segment using a flag, relative coordinates, and / or metadata to indicate that it should remain within the ROI, similar to Figure 3 Step 310 or Figure 4 Step 406. In at least one embodiment, if the reasoning activity does not indicate that the segmented segment is still relevant to the current ROI, the processor does not add or otherwise removes an indication of the segmented segment. In at least one embodiment, if the segmented segment is no longer relevant to the ROI, the ROI is reduced to exclude the segmented segment.

[0107] In at least one embodiment, at step 506, a neural network (e.g., Figure 1 The processor of the region of interest neural network 108 evaluates the reasoning activity of the segmented segment outside the current region of interest (e.g., a segmented segment outside the current ROI boundary) to determine whether the ROI needs to be enlarged. Figure 3 Course 300 and / or Figure 4The segmented or divided segments of the process 400 are saved. In at least one embodiment, if at least reasoning activity is detected outside the current ROI or within a segment outside the current ROI, the processor identifies the segmented segment using a flag, relative coordinates, and / or metadata to indicate that the current segmented segment is newly associated with the ROI and the ROI should be enlarged to include the additional segmented segment. In at least one embodiment, if the reasoning activity does not indicate that the segmented segment is newly associated with the current ROI, the processor does not add an indication for the segmented segment, and the ROI will not be enlarged to include the segmented segment.

[0108] In at least one embodiment, at step 508, the processor identifies whether any segmented segments of the ROI have changed, as determined in steps 504 and 506. In at least one embodiment, when the reasoning activity has not changed (no at step 510), then the previous ROI is maintained without change, and normal object detection within the ROI is restored at step 502.

[0109] In at least one embodiment, when it is determined that the reasoning activity has changed (yes at step 508), the processor proceeds to step 512 and adjusts the ROI to expand to include newly relevant segmented segments and / or shrink to exclude segmented segments that are no longer relevant. In at least one embodiment, after adjusting the ROI at step 512, the processor generates a new overlay at step 514 for display to the user, which indicates the newly adjusted ROI.

[0110] In at least one embodiment, determining whether the ROI should be reduced (e.g., at step 504) or expanded (e.g., at step 506) occurs at similar times or immediately after each other. In at least one embodiment, the timing of determining the ROI reduction is different from the timing of determining the ROI expansion (e.g., once every 5 seconds for reduction and once every 15 seconds for expansion). In at least one embodiment, by performing the process 500 described herein, the ROI can be readjusted without additional user input or manual intervention, thereby maintaining reduced processing and power requirements even if the activity of the captured scene changes.

[0111] In at least one embodiment, processor 604 uses Figure 6One or more modules described in the embodiment of the present invention perform one or more steps in process 500. In at least one embodiment, one or more steps in process 500 are combined in other ways, performed in series and / or performed in parallel. In at least one embodiment, part or all of process 500 (or any other process described herein, or a variant and / or combination thereof) is executed under the control of one or more computer systems configured with computer executable instructions, and is implemented as a code (e.g., computer executable instructions, one or more computer programs, or one or more applications) jointly executed by hardware, software, or a combination thereof on one or more processors. In at least one embodiment, the code is stored on a computer-readable storage medium in the form of a computer program, which includes a plurality of computer-readable instructions executable by one or more processors. In at least one embodiment, the computer-readable storage medium is a non-transitory computer-readable medium. In at least one embodiment, at least some of the computer-readable instructions that can be used to perform process 500 are not stored using only transient signals (e.g., propagated transient electrical or electromagnetic transmissions). In at least one embodiment, the non-transitory computer-readable medium does not necessarily include non-transitory data storage circuits (e.g., buffers, caches, and queues) within the transient signal transceiver. In at least one embodiment, process 500 is performed at least in part on a computer system (such as a computer system described elsewhere in this disclosure). In at least one embodiment, logic (eg, hardware, software, or a combination of hardware and software) performs process 500.

[0112] Figure 6 An exemplary system 600 for performing region of interest selection according to at least one embodiment is shown. In at least one embodiment, the system is a processor 604 that enables identification of one or more locations of one or more objects in one or more images based at least in part on one or more locations of one or more objects in one or more previous images. In at least one embodiment, the processor 604 is a part of a graphics processing unit (GPU), a general purpose GPU (GPGPU), a parallel processing unit (PPU), a central processing unit (CPU), a data processing unit (DPU), a system on a chip (SoC), or a combination thereof. In at least one embodiment, the processor 604 has stored thereon trained neural networks (e.g., the region of interest neural network 108 and the object detection neural network 112) to perform various tasks. In at least one embodiment, one or more trained neural networks are stored in an inference module 608.

[0113] In at least one embodiment, processor 604 receives a signal from a camera (e.g., Figure 1An input image 602 captured by a camera 102 in the image processing unit 604 or generated by other means is provided. In at least one embodiment, the processor 604 uses an image partitioning module 606 to partition or segment the input image 602 into a plurality of segments. In at least one embodiment, the image partitioning module 606 partitions the input image 602 according to a given partitioning ratio. In at least one embodiment, the partitioning ratio is based on the resolution of the input image 104 (e.g., partitioning a 4K image into segments of 192x108 pixels each), based on a preset number of segments (e.g., partitioning the input image into 50 segments), or other similar techniques. In at least one embodiment, the coordinates, flags, metadata, and / or indication of how the input image is partitioned are stored in the memory 612.

[0114] In at least one embodiment, after the input image 602 is divided into a plurality of segments, the processor 604 evaluates the segments using the reasoning module 608. In at least one embodiment, the processor 604 uses the reasoning module 608 to determine whether a given segmented segment has any reasoning activity, such as regarding Figure 4 and Figure 5 In at least one embodiment, if the reasoning module 608 identifies reasoning activity within a given segmented segment, the processor 604 stores in the memory 612 a flag, coordinates, metadata, and / or indication associated with the segmented segment.

[0115] In at least one embodiment, the reasoning module 608 includes an object detection neural network that is trained to infer and count instances of a particular object that is detected. In at least one embodiment, the reasoning module 608 includes a motion detection neural network that is trained to infer motion vectors for a given field of view. In at least one embodiment, the reasoning module 608 includes other neural networks to perform other reasoning tasks.

[0116] In at least one embodiment, after processor 604 evaluates each segmented segment using reasoning module 608, processor 604 generates a region of interest using ROI selection module 610. In at least one embodiment, ROI selection module 610 aggregates and combines all segments in memory that are indicated as having reasoning activity, similar to Figure 4 and Figure 5 In at least one embodiment, the ROI selection module 610 combines all indicated segments together in a continuous region. In at least one embodiment, the ROI selection module 610 combines the segments together to form multiple discontinuous regions. In at least one embodiment, the ROI selection module 610 also generates an overlay to display the current ROI selection to the user. In at least one embodiment, this overlay is newly generated each time the ROI selection changes.

[0117] In at least one embodiment, after ROI selection module 610 selects a ROI, processor 604 uses reasoning module 608 to perform object detection or other reasoning only within the selected ROI.

[0118] In at least one embodiment, after a predetermined amount of time, reasoning module 608 generates a Figure 5 The ROI selection module 610 performs additional reasoning on the segmented regions within and outside the selected ROI in the manner described to determine whether the ROI should be enlarged or reduced. In at least one embodiment, the ROI selection module 610 performs additional reasoning on the segmented regions within and outside the selected ROI based on the additional reasoning from the reasoning module 608. Figure 5 Adjust the selected ROI as described.

[0119] In at least one embodiment, the processor 604 includes or has access to software, modules, or other instructions to perform operations of the image segmentation module 606, the reasoning module 608, the ROI selection module 610, and the memory 612. For example, the processor 604 may call an application programming interface (API) or execute instructions to segment an input frame into a plurality of segments, determine which segments have reasoning activity, generate an ROI based on the segments with activity, and perform object detection on the input frame only within the ROI.

[0120] Figure 7 An intelligent video analysis architecture 700 (e.g., DeepStream) using a region of interest selection process according to at least one embodiment is shown. In at least one embodiment, the architecture 700 includes a processor (e.g., Figure 6 The processor 604 of the architecture 700 is configured to identify one or more locations of one or more objects in one or more images based at least in part on one or more locations of one or more objects in one or more previous images. In at least one embodiment, the architecture 700 includes a graphics processing unit (GPU), a general purpose GPU (GPGPU), a parallel processing unit (PPU), a central processing unit (CPU), a data processing unit (DPU), a portion of a system on a chip (SoC), or a combination thereof. In at least one embodiment, the processor in the architecture 700 has a trained neural network (e.g., the region of interest neural network 108 and the object detection neural network 112) stored thereon to perform various tasks.

[0121] In at least one embodiment, the camera 702 captures streaming video for processing. In at least one embodiment, the processor (e.g., a CPU) captures the raw video 704 obtained from the camera 702 to the decoder 706 using a local link or a real-time streaming protocol (RTSP). In at least one embodiment, the decoder 706 decodes the input frames using, for example, a video decoder engine (NVDEC) with a GPU. In at least one embodiment, the processor performs various image processing 708 on the decoded video using a GPU or a visual image compositor (VIC), such as scaling, dewarping, color conversion, cropping, and / or other processing techniques. In at least one embodiment, the image processing 708 also includes frame segmentation operations on the input frames, such as with respect to Figure 3 Step 304 and Figure 4 As described in step 404, the input video is divided into a plurality of segments according to the segmentation ratio.

[0122] In at least one embodiment, after image processing 708 completes processing, the input frames are aggregated and batched 710 into sequential frames to achieve optimal performance using the CPU. In at least one embodiment, the processor transmits the batched frames for inference using a neural network 712. In at least one embodiment, the GPU or deep learning accelerator (DLA) performs inference using TensorRT, TensorFlow, PyTorch, and / or other neural network technologies to perform various inference tasks on the batched input frames, such as detection, classification, and / or segmentation. In at least one embodiment, the GPU or DLA also performs region of interest selection, such as respectively with respect to Figure 3-5 The processes 300 , 400 , and 500 are described to select a region of interest in which to perform object detection based on the segmented segments.

[0123] In at least one embodiment, the GPU or CPU performs tracking 714 or visualization 718 (e.g., adding bounding boxes, segmentation masks, or labels) of any objects identified or inferred from the neural network 712. In at least one embodiment, the GPU or VIC also generates an overlay to visually indicate selected regions of interest, such as with respect to Figure 4 In at least one embodiment, the architecture 700 outputs the processed frames to the display / storage 720 by rendering the processed frames to a screen display via HDMI, storing the processed frames to a local disk or to cloud storage via SATA, or streaming the processed frames out via RTSP using a video encoder engine (NVENC).

[0124] Figure 8802 is a block diagram illustrating a driver and / or runtime including one or more libraries to provide one or more application programming interfaces (APIs) according to at least one embodiment. In at least one embodiment, software program 802 is a software module such as Figure 6 In at least one embodiment, the software program 802 includes one or more software modules. In at least one embodiment, the software modules are as follows: Figure 6 810 is further described in a non-exclusive manner. In at least one embodiment, one or more APIs 810 are software instruction sets that, if executed, cause one or more processors to perform one or more computing operations. In at least one embodiment, one or more APIs 810 are distributed or otherwise provided as part of a grouping of one or more libraries 806, runtimes 804, drivers 804, and / or any other software and / or executable code further described herein. In at least one embodiment, one or more APIs 810 perform one or more computing operations in response to a call from a software program 802. In at least one embodiment, a software program 802 is a collection of software codes, commands, instructions, or other text sequences for instructing a computing device to perform one or more computing operations and / or call one or more other instruction sets to be executed, such as an API 810 or an API function 812. In at least one embodiment, the functionality provided by one or more APIs 810 includes a software function 812, such as a software function that can be used to accelerate one or more parts of a software program 802 using one or more parallel processing units (PPUs) (e.g., a graphics processing unit (GPU)). In at least one embodiment, the software program is a compiler.

[0125] In at least one embodiment, the API 810 is a hardware interface of one or more circuits for performing one or more computing operations. In at least one embodiment, one or more software APIs 810 described herein are implemented as one or more circuits for performing the following combined Figures 1 to 7 In at least one embodiment, one or more software programs 802 include instructions that, if executed, cause one or more hardware devices and / or circuits to perform the above combined Figures 1 to 7 One or more techniques described.

[0126] In at least one embodiment, the software program 802 (e.g., a user-implemented software program) utilizes one or more application programming interfaces (APIs) 810 to perform various computational operations, such as memory reservations, matrix multiplications, arithmetic operations, or any computational operations performed by a parallel processing unit (PPU) (e.g., a graphics processing unit (GPU)), as further described herein. In at least one embodiment, the one or more APIs 810 provide a set of callable functions 812, referred to herein as APIs, API functions, and / or functions, which respectively perform one or more computational operations, such as computational operations related to parallel computing. In at least one embodiment, the one or more APIs 810 provide functions 812 to cause 816 the location of an object in an image based on the location of the object in a previous image and / or otherwise perform the operations described herein. In at least one embodiment, the one or more APIs 810 provide functions 812 to cause 816 the neural network to perform one or more operations, such as by returning the called function to a processor, wherein the processor calls the neural network.

[0127] In at least one embodiment, one or more software programs 802 interact with or otherwise communicate with one or more APIs 810 to perform one or more computing operations using one or more PPUs (e.g., GPUs). In at least one embodiment, the one or more computing operations using one or more PPUs include at least one or more groups of computing operations that are accelerated by being performed at least in part by the one or more PPUs. In at least one embodiment, one or more software programs 802 interact with one or more APIs 810 to facilitate parallel computing using remote or local interfaces.

[0128] In at least one embodiment, the interface is software instructions that, if executed, provide access to one or more functions 812 provided by one or more APIs 810. In at least one embodiment, the software programs 802 use the native interface when a software developer compiles one or more software programs 802 in conjunction with one or more libraries 806 that include or otherwise provide access to the one or more APIs 810. In at least one embodiment, the one or more software programs 802 are statically compiled in conjunction with precompiled libraries 806 or uncompiled source code that include instructions to execute the one or more APIs 810. In at least one embodiment, the one or more software programs 802 are dynamically compiled and linked to the one or more precompiled libraries 806 that include the one or more APIs 810 using a linker.

[0129] In at least one embodiment, the software program 802 uses a remote interface when a software developer executes a software program that utilizes or otherwise communicates with a library 806 including one or more APIs 810 over a network or other remote communication medium. In at least one embodiment, the one or more libraries 806 including one or more APIs 810 are to be executed by a remote computing service (e.g., a computing resource service provider). In another embodiment, the one or more libraries 806 including one or more APIs 810 are to be executed by any other computing host that provides the one or more APIs 810 to the one or more software programs 802.

[0130] In at least one embodiment, one or more software programs 802 utilize one or more APIs 810 to allocate and otherwise manage memory to be used by the software programs 802. In at least one embodiment, one or more software programs 802 utilize one or more APIs 810 to allocate and otherwise manage memory to be used by one or more portions of the software programs 802 for acceleration using one or more PPUs (e.g., GPUs or any other accelerators or processors further described herein). These software programs 802 request the neural network to generate one or more portions of an image based at least in part on one or more portions.

[0131] In at least one embodiment, the API 810 is an API for facilitating parallel computing. In at least one embodiment, the API 810 is any other API further described herein. In at least one embodiment, the API 810 is provided by a driver and / or runtime 804. In at least one embodiment, the API 810 is provided by a CUDA user mode driver. In at least one embodiment, the API 810 is provided by a CUDA runtime. In at least one embodiment, the driver 804 is a data value and software instruction that, if executed, performs or otherwise facilitates the operation of one or more functions 812 of the API 810 during the loading and execution of one or more parts of the software program 802. In at least one embodiment, the runtime 804 is a data value and software instruction that, if executed, performs or otherwise facilitates the operation of one or more functions 812 of the API 810 during the execution of the software program 802. In at least one embodiment, one or more software programs 802 utilize one or more APIs 810 implemented or otherwise provided by a driver and / or runtime 804 to perform combined arithmetic operations by the one or more software programs 802 during execution by one or more PPUs (e.g., GPUs).

[0132] In at least one embodiment, one or more software programs 802 utilize one or more APIs 810 provided by a driver and / or runtime 804 to perform combined arithmetic operations for one or more PPUs (e.g., GPUs). In at least one embodiment, the one or more APIs 810 provide combined arithmetic operations through the driver and / or runtime 804, as described above. In at least one embodiment, one or more software programs 802 utilize one or more APIs 810 provided by the driver and / or runtime 804 to allocate or otherwise reserve one or more blocks of memory 814 for one or more PPUs (e.g., GPUs). In at least one embodiment, one or more software programs 802 utilize one or more APIs 810 provided by the driver and / or runtime 804 to allocate or otherwise reserve blocks of memory. In at least one embodiment, the one or more APIs 810 are used to perform combined arithmetic operations, as described below in conjunction with Figures 1 to 7 Any one of the above.

[0133] To improve the usability of a software program 802 to be accelerated by one or more PPUs (e.g., GPUs) and / or optimization of one or more portions of the software program 802, in one embodiment, one or more APIs 810 provide one or more API functions 812 to enable 816 to identify the location of an object in an image based on the location of the object in a previous image, as described above and in conjunction with Figures 1 to 7 Further description. In at least one embodiment, exemplary block diagram 800 depicts a processor comprising one or more circuits for executing one or more software programs to combine two or more application programming interfaces (APIs) into a single API. In at least one embodiment, exemplary block diagram 800 depicts a system comprising one or more processors for executing one or more software programs to combine two or more application programming interfaces (APIs) into a single API. In at least one embodiment, the API is used to cause a neural network to generate one or more portions of an image based at least in part on one or more portions using the neural network.

[0134] In this specification, numerous specific details are set forth to provide a more thorough understanding of at least one embodiment. However, it will be apparent to one skilled in the art that the inventive concepts may be practiced without one or more of these specific details.

[0135] logic

[0136] Fig. 9ALogic 915 is shown according to at least one embodiment, as described elsewhere herein, which may be used in one or more devices to perform operations such as those discussed herein. In at least one embodiment, logic 915 is used to perform reasoning and / or training operations associated with one or more embodiments. In at least one embodiment, logic 915 is reasoning and / or training logic. Fig. 9A and / or Fig. 9B Details are provided regarding logic 915. In at least one embodiment, logic refers to any combination of software logic, hardware logic, and / or firmware logic used to provide the functionality or operations described herein, where the logic may collectively or individually be embodied as circuitry forming part of a larger system (e.g., an integrated circuit (IC), a system on a chip (SoC), or one or more processors (e.g., CPU, GPU)).

[0137] In at least one embodiment, logic 915 may include, but is not limited to, code and / or data storage 901 for storing forward and / or output weights and / or input / output data, and / or other parameters for configuring neurons or layers of a neural network being trained and / or used for inference in aspects of one or more embodiments. In at least one embodiment, logic 915 may include or be coupled to code and / or data storage 901 for storing graph code or other software to control timing and / or sequence, wherein weights and / or other parameter information is loaded to configure logic, the logic including integer and / or floating point units (collectively referred to as arithmetic logic units (ALUs)). In at least one embodiment, code (such as graph code) loads weights or other parameter information into a processor ALU based on the architecture of the neural network to which the code corresponds. In at least one embodiment, code and / or data storage 901 stores weight parameters and / or input / output data for each layer of a neural network trained or used in conjunction with one or more embodiments during forward propagation of input / output data and / or weight parameters during training and / or inference using aspects of one or more embodiments. In at least one embodiment, any portion of code and / or data storage 901 may be included within other on-chip or off-chip data storage, including a processor's L1, L2, or L3 cache or system memory.

[0138] In at least one embodiment, any portion of code and / or data storage 901 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data storage 901 may be cache memory, dynamic random access memory ("DRAM"), static random access memory ("SRAM"), non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether code and / or data storage 901 is internal or external to a processor, for example, or includes DRAM, SRAM, flash memory, or some other storage type, may depend on the available storage on-chip versus off-chip, the latency requirements of the training and / or inference functions being performed, the batch size of the data used in inference and / or training of the neural network, or some combination of these factors.

[0139] In at least one embodiment, logic 915 may include, but is not limited to, code and / or data storage 905 for storing backpropagation and / or output weights and / or input / output data corresponding to neurons or layers of a neural network trained and / or used for inference in aspects of one or more embodiments. In at least one embodiment, code and / or data storage 905 stores weight parameters and / or input / output data for each layer of a neural network trained or used in conjunction with one or more embodiments during backpropagation of input / output data and / or weight parameters during training and / or inference using aspects of one or more embodiments. In at least one embodiment, logic 915 may include or be coupled to code and / or data storage 905 for storing graph code or other software to control timing and / or order, where weight and / or other parameter information is loaded to configure logic, which includes integer and / or floating point units (collectively referred to as arithmetic logic units (ALUs)).

[0140] In at least one embodiment, the code (such as graph code) causes weights or other parameter information to be loaded into the processor ALU based on the architecture of the neural network to which the code corresponds. In at least one embodiment, any portion of the code and / or data storage 905 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. In at least one embodiment, any portion of the code and / or data storage 905 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, the code and / or data storage 905 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether the code and / or data storage 905 is internal or external to the processor, for example, including DRAM, SRAM, flash memory, or some other storage type, may depend on the available storage on-chip versus off-chip, the latency requirements of the training and / or inference functions being performed, the batch size of the data used in the inference and / or training of the neural network, or some combination of these factors.

[0141] In at least one embodiment, code and / or data storage 901 and code and / or data storage 905 may be separate storage structures. In at least one embodiment, code and / or data storage 901 and code and / or data storage 905 may be the same storage structure. In at least one embodiment, code and / or data storage 901 and code and / or data storage 905 may be partially combined and partially separated. In at least one embodiment, any portion of code and / or data storage 901 and code and / or data storage 905 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory.

[0142] In at least one embodiment, logic 915 may include, but is not limited to, one or more arithmetic logic units (“ALUs”) 910 (including integer and / or floating point units) for performing logical and / or mathematical operations based at least in part on or as directed by training and / or inference code (e.g., graph code), the results of which may produce activations (e.g., output values ​​from a layer or neuron within a neural network) stored in activation storage 920, which is a function of input / output and / or weight parameter data stored in code and / or data storage 901 and / or code and / or data storage 905. In at least one embodiment, activations stored in activation storage 920 are generated from linear algebra and / or matrix-based math performed by ALU 910 in response to executing instructions or other code, with weight values ​​stored in code and / or data storage 905 and / or code and / or data storage 901 used as operands, as well as other values, such as bias values, gradient information, momentum values, or other parameters or hyperparameters, any or all of which may be stored in code and / or data storage 905 or code and / or data storage 901 or other on-chip or off-chip storage.

[0143] In at least one embodiment, one or more ALUs 910 are included in one or more processors or other hardware logic devices or circuits, while in another embodiment, one or more ALUs 910 may be external to a processor or other hardware logic device or circuit that uses them (e.g., a coprocessor). In at least one embodiment, ALUs 910 may be included within an execution unit of a processor, or otherwise included in an ALU bank accessible by an execution unit of a processor, which may be within the same processor or distributed between different processors of different types (e.g., a central processing unit, a graphics processing unit, a fixed function unit, etc.). In at least one embodiment, code and / or data storage 901, code and / or data storage 905, and activation storage 920 may share a processor or other hardware logic device or circuit, while in another embodiment, they may be in different processors or other hardware logic devices or circuits or some combination of the same and different processors or other hardware logic devices or circuits. In at least one embodiment, any portion of activation storage 920 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. Additionally, inference and / or training code may be stored with other code accessible to a processor or other hardware logic or circuitry and may be retrieved and / or processed using the processor's fetch, decode, schedule, execute, exit, and / or other logic circuitry.

[0144] In at least one embodiment, activation storage 920 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, activation storage 920 may be completely or partially internal or external to one or more processors or other logic circuits. In at least one embodiment, the choice of whether activation storage 920 is internal or external to a processor, for example, or includes DRAM, SRAM, flash memory, or some other storage type, may depend on the available storage on-chip versus off-chip, the latency requirements for performing training and / or inference functions, the batch size of data used in inferring and / or training neural networks, or some combination of these factors.

[0145] In at least one embodiment, Fig. 9A The logic 915 shown in FIG. 1 may be used in conjunction with an application specific integrated circuit (“ASIC”), such as the ASIC from Google. Processing unit from Graphcore TM Inference Processing Unit (IPU) from Intel (e.g., "Lake Crest") processor. In at least one embodiment, Fig. 9A The illustrated logic 915 may be used in conjunction with central processing unit ("CPU") hardware, graphics processing unit ("GPU") hardware, or other hardware such as a field programmable gate array ("FPGA").

[0146] Fig. 9B Logic 915 is shown according to at least one embodiment. In at least one embodiment, logic 915 is reasoning and / or training logic. In at least one embodiment, logic 915 may include, but is not limited to, hardware logic, where computing resources are dedicated or otherwise used exclusively with weight values ​​or other information corresponding to one or more layers of neurons within a neural network. In at least one embodiment, Fig. 9B The logic 915 shown in FIG. 1 may be used in conjunction with an application specific integrated circuit (ASIC), such as the ASIC from Google. Processing unit from Graphcore TM Inference Processing Unit (IPU) from Intel (e.g., "Lake Crest") processor. In at least one embodiment, Fig. 9BThe logic 915 shown in can be used in conjunction with central processing unit (CPU) hardware, graphics processing unit (GPU) hardware, or other hardware (e.g., field programmable gate array (FPGA)). In at least one embodiment, logic 915 includes, but is not limited to, code and / or data storage 901 and code and / or data storage 905, which can be used to store code (e.g., graph code), weight values, and / or other information, including bias values, gradient information, momentum values, and / or other parameter or hyperparameter information. Fig. 9B In at least one embodiment shown in , each of code and / or data storage 901 and code and / or data storage 905 is associated with a dedicated computing resource, such as computing hardware 902 and computing hardware 906, respectively. In at least one embodiment, each of computing hardware 902 and computing hardware 906 includes one or more ALUs that perform mathematical functions (e.g., linear algebraic functions) solely on the information stored in code and / or data storage 901 and code and / or data storage 905, respectively, with the results being stored in activation storage 920.

[0147] In at least one embodiment, each of the code and / or data stores 901 and 905 and the corresponding computing hardware 902 and 906 corresponds to a different layer of the neural network, such that activations obtained from one storage / compute pair 901 / 902 of the code and / or data store 901 and computing hardware 902 are provided as inputs to the next storage / compute pair 905 / 906 of the code and / or data store 905 and computing hardware 906, so as to reflect the conceptual organization of the neural network. In at least one embodiment, each storage / compute pair 901 / 902 and 905 / 906 can correspond to more than one neural network layer. In at least one embodiment, additional storage / compute pairs (not shown) can be included in the logic 915 after or in parallel with the storage / compute pairs 901 / 902 and 905 / 906.

[0148] Figures 9A-9B The logic and hardware structure can be integrated into Figure 1-8 In the system and processor disclosed in. For example, Figures 9A-9B The logic / hardware structure in can perform at least part or all of process 300, 400 and / or 500. In at least one embodiment, Figures 9A-9BThe system or apparatus disclosed in causes a processor to identify one or more locations of one or more objects in one or more images based at least in part on one or more locations of one or more objects in one or more previous images. In at least one embodiment, by performing at least part or all of processes 300, 400, and / or 500, a processor including one or more circuits divides one or more images into one or more segments and stores in a memory an indication of which of the one or more segments contain one or more identified locations of one or more objects. In at least one embodiment, by performing at least part or all of processes 300, 400, and / or 500, Figures 9A-9B The system or apparatus disclosed in causes a processor to combine one or more positions of one or more objects to generate a region of interest.

[0149] Neural network training and deployment

[0150] Fig.10 The training and deployment of a deep neural network according to at least one embodiment is shown. In at least one embodiment, an untrained neural network 1006 is trained using a training data set 1002. In at least one embodiment, the training framework 1004 is a PyTorch framework, while in other embodiments, the training framework 1004 is TensorFlow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j, or other training frameworks. In at least one embodiment, the training framework 1004 trains an untrained neural network 1006 and enables it to be trained using the processing resources described herein to generate a trained neural network 1008. In at least one embodiment, the weights may be randomly selected or selected by pre-training using a deep belief network. In at least one embodiment, training may be performed in a supervised, partially supervised, or unsupervised manner.

[0151] In at least one embodiment, untrained neural network 1006 is trained using supervised learning, where training data set 1002 includes inputs paired with expected outputs for the inputs, or where training data set 1002 includes inputs with known outputs and the outputs of neural network 1006 are manually graded. In at least one embodiment, untrained neural network 1006 is trained in a supervised manner, and inputs from training data set 1002 are processed and the resulting outputs are compared to a set of expected or desired outputs. In at least one embodiment, errors are then back-propagated through untrained neural network 1006. In at least one embodiment, training framework 1004 adjusts the weights that control untrained neural network 1006. In at least one embodiment, training framework 1004 includes tools for monitoring the degree to which untrained neural network 1006 converges to a model (such as trained neural network 1008) suitable for generating a correct answer (such as result 1014) based on input data (such as new data set 1012). In at least one embodiment, the training framework 1004 repeatedly trains the untrained neural network 1006 while adjusting the weights to refine the output of the untrained neural network 1006 using a loss function and an adjustment algorithm such as stochastic gradient descent. In at least one embodiment, the training framework 1004 trains the untrained neural network 1006 until the untrained neural network 1006 reaches a desired accuracy. In at least one embodiment, the trained neural network 1008 can then be deployed to implement any number of machine learning operations.

[0152] In at least one embodiment, untrained neural network 1006 is trained using unsupervised learning, where untrained neural network 1006 attempts to train itself using unlabeled data. In at least one embodiment, unsupervised learning training data set 1002 will include input data without any associated output data or "ground truth" data. In at least one embodiment, untrained neural network 1006 can learn groupings within training data set 1002 and can determine how individual inputs are related to untrained data set 1002. In at least one embodiment, unsupervised training can be used to generate a self-organizing map in trained neural network 1008, which is capable of performing operations useful for reducing the dimensionality of new data set 1012. In at least one embodiment, unsupervised training can also be used to perform anomaly detection, which allows identification of data points in new data set 1012 that deviate from the normal pattern of new data set 1012.

[0153] In at least one embodiment, semi-supervised learning can be used, which is a technique in which a mixture of labeled and unlabeled data is included in the training data set 1002. In at least one embodiment, the training framework 1004 can be used to perform incremental learning, such as through transfer learning techniques. In at least one embodiment, incremental learning enables the trained neural network 1008 to adapt to the new data set 1012 without forgetting the knowledge that was infused into the trained neural network 1008 during the initial training.

[0154] In at least one embodiment, the training framework 1004 is a framework that is processed in conjunction with a software development kit such as the OpenVINO (Open Visual Reasoning and Neural Network Optimization) toolkit. In at least one embodiment, the OpenVINO toolkit is a toolkit such as that developed by Intel Corporation of Santa Clara, California. In at least one embodiment, OpenVINO includes logic 915 or uses logic 915 to perform the operations described herein. In at least one embodiment, an SoC, an integrated circuit, or a processor uses OpenVINO to perform the operations described herein.

[0155] In at least one embodiment, OpenVINO is a toolkit for facilitating the development of applications (particularly neural network applications) for various tasks and operations (such as human vision simulation, speech recognition, natural language processing, recommendation systems, and / or variants thereof). In at least one embodiment, OpenVINO supports neural networks, such as convolutional neural networks (CNNs), recurrent neural networks, and / or attention-based neural networks, and / or various other neural network models. In at least one embodiment, OpenVINO supports various software libraries, such as OpenCV, OpenCL, and / or variants thereof.

[0156] In at least one embodiment, OpenVINO supports neural network models for various tasks and operations such as classification, segmentation, object detection, face recognition, speech recognition, pose estimation (e.g., people and / or objects), monocular depth estimation, image restoration, style transfer, action recognition, colorization, and / or variants thereof.

[0157] In at least one embodiment, OpenVINO includes one or more software tools and / or modules for model optimization, also referred to as a model optimizer. In at least one embodiment, the model optimizer is a command line tool that facilitates the conversion between training and deployment of a neural network model. In at least one embodiment, the model optimizer optimizes the neural network model to execute on various devices and / or processing units such as GPU, CPU, PPU, GPGPU and / or its variants. In at least one embodiment, the model optimizer generates an internal representation of the model and optimizes the model to generate an intermediate representation. In at least one embodiment, the model optimizer reduces the number of layers of the model. In at least one embodiment, the model optimizer removes the layers of the model for training. In at least one embodiment, the model optimizer performs various neural network operations, such as modifying the input of the model (e.g., adjusting the size of the input of the model), modifying the size of the input of the model (e.g., modifying the batch size of the model), modifying the model structure (e.g., modifying the layer of the model), normalization, standardization, quantization (e.g., converting the weights of the model from a first representation such as a floating point to a second representation such as an integer) and / or its variants.

[0158] In at least one embodiment, OpenVINO includes one or more software libraries for reasoning, also referred to as reasoning engines. In at least one embodiment, the reasoning engine is a C++ library or any suitable programming language library. In at least one embodiment, the reasoning engine is used to reason about input data. In at least one embodiment, the reasoning engine implements various classes to reason about input data and generate one or more results. In at least one embodiment, the reasoning engine implements one or more API functions to process intermediate representations, set input and / or output formats, and / or execute models on one or more devices.

[0159] In at least one embodiment, OpenVINO provides various capabilities for heterogeneous execution of one or more neural network models. In at least one embodiment, heterogeneous execution or heterogeneous computing refers to one or more computing processes and / or systems using one or more types of processors and / or cores. In at least one embodiment, OpenVINO provides various software functions to execute programs on one or more devices. In at least one embodiment, OpenVINO provides various software functions to execute programs and / or parts of programs on different devices. In at least one embodiment, OpenVINO provides various software functions, for example, to run a first code portion on a CPU and a second code portion on a GPU and / or FPGA. In at least one embodiment, OpenVINO provides various software functions to execute one or more layers of a neural network on one or more devices (e.g., executing a first set of layers on a first device (e.g., a GPU), and executing a second set of layers on a second device (e.g., a CPU)).

[0160] In at least one embodiment, OpenVINO includes various functions similar to those associated with the CUDA programming model, such as various neural network model operations associated with frameworks such as TensorFlow, PyTorch, and / or variants thereof. In at least one embodiment, one or more CUDA programming model operations are performed using OpenVINO. In at least one embodiment, the various systems, methods, and / or techniques described herein are implemented using OpenVINO.

[0161] Data Center

[0162] Fig.11 An example data center 1100 is shown in which at least one embodiment may be used. In at least one embodiment, the data center 1100 includes a data center infrastructure layer 1110, a framework layer 1120, a software layer 1130, and an application layer 1140.

[0163] In at least one embodiment, Fig.11As shown, the data center infrastructure layer 1110 may include a resource coordinator 1112, grouped computing resources 1114, and node computing resources ("node CRs") 1116(1)-1116(N), where "N" represents a positive integer (which may be an integer "N" different from the integers used in other figures). In at least one embodiment, the node CRs 1116(1)-1116(N) may include, but are not limited to, any number of central processing units ("CPUs") or other processors (including accelerators, field programmable gate arrays (FPGAs), graphics processors, etc.), memory storage devices 1118(1)-1118(N) (e.g., dynamic read-only memory, solid-state storage, or disk drives), network input / output ("NW I / O") devices, network switches, virtual machines ("VMs"), power modules and cooling modules, etc. In at least one embodiment, one or more of the node CRs 1116(1)-1116(N) may be a server having one or more of the above computing resources.

[0164] In at least one embodiment, the grouped computing resources 1114 may include separate groups of node CRs housed in one or more racks (not shown), or many racks housed in data centers (also not shown) at various geographic locations. In at least one embodiment, separate groups of node CRs within the grouped computing resources 1114 may include computing, networks, memory, or storage resources that can be configured or allocated to support groupings of one or more workloads. In at least one embodiment, several node CRs including a CPU or processor may be grouped in one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches in any combination.

[0165] In at least one embodiment, resource coordinator 1112 may configure or otherwise control one or more nodes CR 1116(1)-1116(N) and / or grouped computing resources 1114. In at least one embodiment, resource coordinator 1112 may include a software design infrastructure ("SDI") management entity for data center 1100. In at least one embodiment, resource coordinator 1112 may include hardware, software, or some combination thereof.

[0166] In at least one embodiment, Fig.11As shown, the framework layer 1120 includes a job scheduler 1122, a configuration manager 1124, a resource manager 1126, and a distributed file system 1128. In at least one embodiment, the framework layer 1120 may include a framework that supports software 1132 of the software layer 1130 and / or one or more applications 1142 of the application layer 1140. In at least one embodiment, the software 1132 or the application 1142 may include web-based service software or applications, such as those provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, the framework layer 1120 may be, but is not limited to, a type of free and open source software web application framework, such as Apache Spark, which can utilize the distributed file system 1128 for large-scale data processing (e.g., "big data"). TM (hereinafter referred to as "Spark"). In at least one embodiment, the job scheduler 1122 may include a Spark driver to facilitate scheduling of workloads supported by various layers of the data center 1100. In at least one embodiment, the configuration manager 1124 may be capable of configuring different layers, such as the software layer 1130 and the framework layer 1120 including Spark and a distributed file system 1128 for supporting large-scale data processing. In at least one embodiment, the resource manager 1126 may be capable of managing clustered or grouped computing resources mapped to or allocated to support the distributed file system 1128 and the job scheduler 1122. In at least one embodiment, the clustered or grouped computing resources may include grouped computing resources 1114 at the data center infrastructure layer 1110. In at least one embodiment, the resource manager 1126 may coordinate with the resource coordinator 1112 to manage these mapped or allocated computing resources.

[0167] In at least one embodiment, software 1132 included in software layer 1130 may include software used by at least portions of node CRs 1116(1)-1116(N), grouped computing resources 1114, and / or distributed file system 1128 of framework layer 1120. In at least one embodiment, one or more types of software may include, but are not limited to, Internet web page search software, email virus scanning software, database software, and streaming video content software.

[0168] In at least one embodiment, one or more applications 1142 included in application layer 1140 may include one or more types of applications used by at least portions of node CRs 1116(1)-1116(N), grouped computing resources 1114, and / or distributed file system 1128 of framework layer 1120. In at least one embodiment, the one or more types of applications may include, but are not limited to, any number of genomics applications, cognitive computing, applications, and machine learning applications, including training or inference software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.), or other machine learning applications used in conjunction with one or more embodiments.

[0169] In at least one embodiment, any of the configuration manager 1124, resource manager 1126, and resource coordinator 1112 can implement any number and type of self-modification actions based on any number and type of data acquired in any technically feasible manner. In at least one embodiment, the self-modification actions can relieve a data center operator of the data center 1100 from making potentially bad configuration decisions and can avoid underutilized and / or poorly performing portions of the data center.

[0170] In at least one embodiment, data center 1100 may include tools, services, software, or other resources for training one or more machine learning models or using one or more machine learning models to predict or infer information according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model may be trained by calculating weight parameters according to a neural network architecture using the software and computing resources described above with respect to data center 1100. In at least one embodiment, by using weight parameters calculated by one or more training techniques described herein, the resources described above with respect to data center 1100 may be used to infer or predict information using a trained machine learning model corresponding to one or more neural networks.

[0171] In at least one embodiment, the data center can use a CPU, an application-specific integrated circuit (ASIC), a GPU, an FPGA, or other hardware to use the above resources to perform training and / or reasoning. In addition, one or more of the above software and / or hardware resources can be configured as a service to allow users to train or perform information reasoning, such as image recognition, speech recognition, or other artificial intelligence services.

[0172] Logic 915 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 9A and / or Fig. 9BDetails are provided regarding logic 915. In at least one embodiment, logic 915 can be used in data center 1100 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0173] Figure 9A-11 The logic and hardware structure can be integrated into Figure 1-8 In the system and processor disclosed in. For example, Figure 9A-11 The logic / hardware structure in can perform at least part or all of process 300, 400 and / or 500. In at least one embodiment, Figure 9A-11 The system or apparatus disclosed in causes a processor to identify one or more locations of one or more objects in one or more images based at least in part on one or more locations of one or more objects in one or more previous images. In at least one embodiment, by performing at least part or all of processes 300, 400, and / or 500, a processor including one or more circuits divides one or more images into one or more segments and stores in a memory an indication of which of the one or more segments contain one or more identified locations of one or more objects. In at least one embodiment, by performing at least part or all of processes 300, 400, and / or 500, Figure 9A-11 The system or apparatus disclosed in causes a processor to combine one or more positions of one or more objects to generate a region of interest.

[0174] Autonomous Vehicles

[0175] Fig. 12A An example of an autonomous vehicle 1200 is shown in accordance with at least one embodiment. In at least one embodiment, autonomous vehicle 1200 (alternatively referred to herein as "vehicle 1200") may be, but is not limited to, a passenger vehicle such as a car, truck, bus, and / or another type of vehicle that accommodates one or more passengers. In at least one embodiment, vehicle 1200 may be a semi-tractor-trailer truck for hauling cargo. In at least one embodiment, vehicle 1200 may be an aircraft, a robotic vehicle, or another type of vehicle.

[0176] An autonomous vehicle may be described according to the automation levels defined by the National Highway Traffic Safety Administration (“NHTSA”) of the U.S. Department of Transportation and the Society of Automotive Engineers (“SAE”) in the “Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles” (e.g., Standard No. J3016-201806, published on June 15, 2018, Standard No. J3016-201609, published on September 30, 2016, and previous and future versions of the standard). In at least one embodiment, the vehicle 1200 may be capable of having one or more functions of Level 1 to Level 5 according to the autonomous driving level. For example, in at least one embodiment, the vehicle 1200 may be capable of conditional automation (Level 3), high automation (Level 4), and / or full automation (Level 5), depending on the embodiment.

[0177] In at least one embodiment, the vehicle 1200 may include, but is not limited to, components such as a chassis, a body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other components of the vehicle. In at least one embodiment, the vehicle 1200 may include, but is not limited to, a propulsion system 1250, such as an internal combustion engine, a hybrid power plant, an all-electric engine, and / or another type of propulsion system. In at least one embodiment, the propulsion system 1250 may be connected to a drive train of the vehicle 1200, which may include, but is not limited to, a transmission, for enabling propulsion of the vehicle 1200. In at least one embodiment, the propulsion system 1250 may be controlled in response to receiving a signal from a throttle / accelerator 1252.

[0178] In at least one embodiment, when propulsion system 1250 is operating (e.g., when vehicle 1200 is in motion), steering system 1254 (which may include, but is not limited to, a steering wheel) is used to steer vehicle 1200 (e.g., along a desired path or route). In at least one embodiment, steering system 1254 may receive signals from steering actuator 1256. In at least one embodiment, the steering wheel may be optional for full automation (Level 5) functionality. In at least one embodiment, brake sensor system 1246 may be used to operate vehicle brakes in response to receiving signals from brake actuator 1248 and / or brake sensors.

[0179] In at least one embodiment, one or more controllers 1236, which may include but are not limited to one or more system on a chip ("SoC") ( Fig. 12A1200) and / or a graphics processing unit ("GPU") to provide signals (e.g., representing commands) to one or more components and / or systems of the vehicle 1200. For example, in at least one embodiment, the one or more controllers 1236 may send signals to operate vehicle brakes via brake actuators 1248, operate steering system 1254 via one or more steering actuators 1256, and operate propulsion system 1250 via one or more throttles / accelerators 1252. In at least one embodiment, the one or more controllers 1236 may include one or more on-board (e.g., integrated) computing devices that process sensor signals and output operating commands (e.g., signals representing commands) to enable autonomous driving and / or assist a human driver in driving the vehicle 1200. In at least one embodiment, the one or more controllers 1236 may include a first controller for autonomous driving functions, a second controller for functional safety functions, a third controller for artificial intelligence functions (e.g., computer vision), a fourth controller for infotainment functions, a fifth controller for redundancy in emergency situations, and / or other controllers. In at least one embodiment, a single controller may handle two or more of the above functions, two or more controllers may handle a single function, and / or any combination thereof.

[0180] In at least one embodiment, the one or more controllers 1236 provide signals for controlling one or more components and / or systems of the vehicle 1200 in response to sensor data received from one or more sensors (e.g., sensor inputs). In at least one embodiment, the sensor data can be received from sensors such as, but not limited to, one or more global navigation satellite system ("GNSS") sensors 1258 (e.g., one or more global positioning system sensors), one or more RADAR sensors 1260, one or more ultrasonic sensors 1262, one or more LIDAR sensors 1264, one or more inertial measurement unit (IMU) sensors 1266 (e.g., one or more accelerometers, one or more gyroscopes, one or more magnetic compasses, one or more magnetometers, etc.), one or more microphones 1296, one or more stereo cameras 1268, one or more wide angle cameras 1270 (e.g., fisheye cameras), one or more infrared cameras 1272, one or more surround cameras 1274 (e.g., 360 degree cameras), telephoto cameras (e.g., infrared cameras), and / or a plurality of other sensors. Fig. 12A Not shown), mid-range camera ( Fig. 12A), one or more speed sensors 1244 (e.g., for measuring the speed of the vehicle 1200), one or more vibration sensors 1242, one or more steering sensors 1240, one or more brake sensors (e.g., as part of a brake sensor system 1246), and / or other sensor types.

[0181] In at least one embodiment, one or more controllers 1236 may receive input (e.g., represented by input data) from a dashboard 1232 of the vehicle 1200 and provide output (e.g., represented by output data, display data, etc.) via a human machine interface (“HMI”) display 1234, an audible annunciator, a speaker, and / or via other components of the vehicle 1200. In at least one embodiment, the output may include information such as vehicle speed, velocity, time, map data (e.g., high definition maps ( Fig. 12A 1200 ), location data (e.g., the location of the vehicle 1200 , such as on a map), directions, locations of other vehicles (e.g., occupancy grid), information about objects and states of objects sensed by one or more controllers 1236 , etc. For example, in at least one embodiment, HMI display 1234 may display information about the presence of one or more objects (e.g., road signs, warning signs, traffic light changes, etc.) and / or information about driving maneuvers the vehicle has, is, or will make (e.g., changing lanes now, reaching exit 34B in two miles, etc.).

[0182] In at least one embodiment, the vehicle 1200 further includes a network interface 1224 that can communicate via one or more networks using one or more wireless antennas 1226 and / or one or more modems. For example, in at least one embodiment, the network interface 1224 can be capable of communicating via Long Term Evolution ("LTE"), Wideband Code Division Multiple Access ("WCDMA"), Universal Mobile Telecommunications System ("UMTS"), Global System for Mobile Communications ("GSM"), IMT-CDMA Multi-Carrier ("CDMA2000") networks, etc. In at least one embodiment, the one or more wireless antennas 1226 can also use one or more local area networks (such as Bluetooth, Bluetooth Low Energy (LE), Z-Wave, ZigBee, etc.) and / or one or more low power wide area networks ("LPWAN") (such as LoRaWAN, SigFox, etc. protocols) to enable communication between objects in the environment (e.g., vehicles, mobile devices, etc.).

[0183] Logic 915 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 9A and / or Fig. 9BDetails are provided regarding logic 915. In at least one embodiment, logic 915 can be used in vehicle 1200 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases as described herein.

[0184] Fig. 12B According to at least one embodiment, Fig. 12A 1200. In at least one embodiment, the cameras and respective fields of view are an example embodiment and are not intended to be limiting. For example, in at least one embodiment, additional and / or alternative cameras may be included and / or the cameras may be located at different locations on the vehicle 1200.

[0185] In at least one embodiment, the camera type for the camera may include, but is not limited to, a digital camera that may be suitable for use with components and / or systems of the vehicle 1200. In at least one embodiment, one or more cameras may operate at Automotive Safety Integrity Level ("ASIL") B and / or other ASILs. In at least one embodiment, the camera type may be capable of having any image capture rate, such as 60 frames per second (fps), 120fps, 240fps, etc., depending on the embodiment. In at least one embodiment, the camera may be capable of using a rolling shutter, a global shutter, other types of shutters, or a combination thereof. In at least one embodiment, the color filter array may include a red transparent transparent transparent ("RCCC") filter array, a red transparent transparent blue ("RCCB") filter array, a red blue green transparent ("RBGC") filter array, a Foveon X3 filter array, a Bayer sensor ("RGGB") filter array, a monochrome sensor filter array, and / or other types of filter arrays. In at least one embodiment, a transparent pixel camera, such as a camera having an RCCC, RCCB, and / or RBGC color filter array, may be used in an effort to improve photosensitivity.

[0186] In at least one embodiment, one or more cameras can be used to perform advanced driver assistance system ("ADAS") functions (e.g., as part of a redundant or fail-safe design). For example, in at least one embodiment, a multi-function monocular camera can be installed to provide functions including lane departure warning, traffic sign assistance, and intelligent headlight control. In at least one embodiment, one or more cameras (e.g., all cameras) can simultaneously record and provide image data (e.g., video).

[0187] In at least one embodiment, one or more cameras can be mounted in a mounting assembly, such as a custom designed (three-dimensional ("3D") printed) assembly, so as to remove stray light and reflected light from within the vehicle 1200 (e.g., reflected light from the dashboard reflecting in the windshield mirror) that may interfere with the camera's image data capture capabilities. With respect to the rearview mirror mounting assembly, in at least one embodiment, the rearview mirror assembly can be 3D printed custom so that the camera mounting plate matches the shape of the rearview mirror. In at least one embodiment, one or more cameras can be integrated into the rearview mirror. In at least one embodiment, for side view cameras, one or more cameras can also be integrated within four pillars at each corner of the cabin.

[0188] In at least one embodiment, a camera (e.g., a forward-facing camera) having a field of view that includes portions of the environment in front of the vehicle 1200 can be used for surround vision to help identify the path ahead and obstacles, as well as assist in providing information critical to generating an occupancy grid and / or determining a preferred vehicle path with the help of one or more controllers 1236 and / or control SoCs. In at least one embodiment, the forward-facing camera can be used to perform many ADAS functions similar to LIDAR, including but not limited to emergency braking, pedestrian detection, and collision avoidance. In at least one embodiment, the forward-facing camera can also be used for ADAS functions and systems, including but not limited to lane departure warning ("LDW"), automatic cruise control ("ACC"), and / or other functions (such as traffic sign recognition).

[0189] In at least one embodiment, a variety of cameras can be used in a forward-facing configuration, including, for example, a monocular camera platform including a CMOS ("complementary metal oxide semiconductor") color imager. In at least one embodiment, a wide-angle camera 1270 can be used to sense objects that enter the view from the periphery (e.g., pedestrians, intersection traffic, or bicycles). Although in Fig. 12B Only one wide-angle camera 1270 is shown, but in other embodiments, there may be any number (including zero) of wide-angle cameras on the vehicle 1200. In at least one embodiment, any number of remote cameras 1298 (e.g., a pair of telescopic stereo cameras) may be used for depth-based object detection, especially for objects for which a neural network has not been trained. In at least one embodiment, one or more remote cameras 1298 may also be used for object detection and classification and basic object tracking.

[0190] In at least one embodiment, any number of stereo cameras 1268 may also be included in the forward configuration. In at least one embodiment, one or more stereo cameras 1268 may include an integrated control unit including an extensible processing unit that may provide programmable logic ("FPGA") and a multi-core microprocessor with a controller area network ("CAN") or Ethernet interface integrated on a single chip. In at least one embodiment, such a unit may be used to generate a 3D map of the environment of the vehicle 1200, including distance estimates for all points in the image. In at least one embodiment, one or more stereo cameras 1268 may include, but are not limited to, a compact stereo vision sensor, which may include, but are not limited to, two camera lenses (one on each side) and an image processing chip that may measure the distance from the vehicle 1200 to the target object and use the generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning functions. In at least one embodiment, other types of stereo cameras 1268 may be used in addition to or in place of those described herein.

[0191] In at least one embodiment, cameras with a field of view of portions of the environment including the sides of the vehicle 1200 (e.g., side view cameras) can be used for surround view, which provides information for creating and updating occupancy grids, and generating side impact collision warnings. For example, in at least one embodiment, surround cameras 1274 (e.g., Fig. 12B The four surround cameras 1274 shown) can be positioned on the vehicle 1200. In at least one embodiment, the one or more surround cameras 1274 can include, but are not limited to, any number and combination of wide-angle cameras, one or more fish-eye cameras, one or more 360-degree cameras, and / or the like. For example, in at least one embodiment, the four fish-eye cameras can be located at the front, rear, and sides of the vehicle 1200. In at least one embodiment, the vehicle 1200 can use three surround cameras 1274 (e.g., left, right, and rear), and can utilize one or more other cameras (e.g., a forward-facing camera) as a fourth surround camera.

[0192] In at least one embodiment, a camera having a field of view including portions of the environment behind the vehicle 1200 (e.g., a rear view camera) can be used for parking assistance, surround view, rear collision warning, and creating and updating an occupancy grid. In at least one embodiment, a variety of cameras can be used, including but not limited to cameras that are also suitable as one or more forward-facing cameras (e.g., long-range camera 1298 and / or one or more mid-range cameras 1276, one or more stereo cameras 1268, one or more infrared cameras 1272, etc.), as described herein.

[0193] Fig. 12Cis a diagram showing a method according to at least one embodiment Fig. 12A A block diagram of an example system architecture of an autonomous vehicle 1200 is shown. In at least one embodiment, Fig. 12C Each of the components, features, and systems of the vehicle 1200 in FIG. 1 is shown as being connected via a bus 1202. In at least one embodiment, the bus 1202 may include, but is not limited to, a CAN data interface (referred to herein alternatively as a "CAN bus"). In at least one embodiment, the CAN may be a network inside the vehicle 1200 that assists in controlling various features and functions of the vehicle 1200, such as actuation, acceleration, braking, steering, wipers, etc. of the brakes. In at least one embodiment, the bus 1202 may be configured to have dozens or even hundreds of nodes, each with its own unique identifier (e.g., a CAN ID). In at least one embodiment, the bus 1202 may be read to find steering wheel angle, ground speed, engine revolutions per minute ("RPM"), button position, and / or other vehicle status indicators. In at least one embodiment, the bus 1202 may be a CAN bus that complies with ASIL B.

[0194] In at least one embodiment, in addition to or instead of CAN, FlexRay and / or Ethernet protocols may also be used. In at least one embodiment, there may be any number of buses forming bus 1202, which may include but are not limited to zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other types of buses using different protocols. In at least one embodiment, two or more buses may be used to perform different functions, and / or may be used for redundancy. For example, a first bus may be used for a collision avoidance function, and a second bus may be used for actuation control. In at least one embodiment, each bus in bus 1202 may communicate with any component of vehicle 1200, and two or more buses in bus 1202 may communicate with corresponding components. In at least one embodiment, each of any number of systems on a chip (“SoC”) 1204 (e.g., SoC 1204(A) and SoC 1204(B)), each of one or more controllers 1236, and / or each computer within the vehicle can access the same input data (e.g., inputs from sensors of the vehicle 1200) and can be connected to a common bus, such as a CAN bus.

[0195] In at least one embodiment, the vehicle 1200 may include one or more controllers 1236, such as those described herein with respect to Fig. 12AThose described. In at least one embodiment, the controller 1236 can be used for a variety of functions. In at least one embodiment, the controller 1236 can be coupled to any of the various other components and systems of the vehicle 1200 and can be used to control the vehicle 1200, the artificial intelligence of the vehicle 1200, the infotainment and / or other functions of the vehicle 1200.

[0196] In at least one embodiment, the vehicle 1200 may include any number of SoCs 1204. In at least one embodiment, each of the SoCs 1204 may include, but is not limited to, a central processing unit ("CPU(s)") 1206, a graphics processing unit ("GPU(s")) 1208, one or more processors 1210, one or more caches 1212, one or more accelerators 1214, one or more data stores 1216, and / or other components and features not shown. In at least one embodiment, the one or more SoCs 1204 may be used to control the vehicle 1200 in a variety of platforms and systems. For example, in at least one embodiment, the one or more SoCs 1204 may be combined in a system (e.g., a system of the vehicle 1200) along with a high-definition ("HD") map 1222, which may be downloaded from one or more servers (e.g., a system of the vehicle 1200) via a network interface 1224. Fig. 12C ) to obtain map refreshes and / or updates.

[0197] In at least one embodiment, one or more CPUs 1206 may include a CPU cluster or CPU complex (referred to herein alternatively as "CCPLEX"). In at least one embodiment, one or more CPUs 1206 may include multiple cores and / or a secondary ("L2") cache. For example, in at least one embodiment, one or more CPUs 1206 may include eight cores in a coherent multiprocessor configuration. In at least one embodiment, one or more CPUs 1206 may include four dual-core clusters, each with a dedicated L2 cache (e.g., 2 megabytes (MB) L2 cache). In at least one embodiment, one or more CPUs 1206 (e.g., CCPLEX) may be configured to support simultaneous cluster operations, which enables any combination of clusters of one or more CPUs 1206 to be active at any given time.

[0198] In at least one embodiment, one or more CPUs 1206 may implement power management functions including, but not limited to, one or more of the following features: each hardware block may be automatically clock gated when idle to save dynamic power; each core clock may be gated when the core is not actively executing instructions due to executing a wait for interrupt ("WFI") / wait for event ("WFE") instruction; each core may be independently power gated; each core cluster may be independently clock gated when all cores are clock gated or power gated; and / or each core cluster may be independently power gated when all cores are power gated. In at least one embodiment, one or more CPUs 1206 may further implement an enhanced algorithm for managing power states, wherein allowed power states and expected wakeup times are specified, and hardware / microcode determines the optimal power state to enter for the core, cluster, and CCPLEX. In at least one embodiment, the processing core may support a simplified power state entry sequence in software, wherein work is offloaded to the microcode.

[0199] In at least one embodiment, one or more GPUs 1208 may include an integrated GPU (referred to herein alternatively as an "iGPU"). In at least one embodiment, one or more GPUs 1208 may be programmable and may be efficient for parallel workloads. In at least one embodiment, one or more GPUs 1208 may use an enhanced tensor instruction set. In at least one embodiment, one or more GPUs 1208 may include one or more streaming microprocessors, wherein each streaming microprocessor may include a level 1 ("L1") cache (e.g., an L1 cache with a storage capacity of at least 96KB), and two or more streaming microprocessors may share an L2 cache (e.g., an L2 cache with a storage capacity of 512KB). In at least one embodiment, one or more GPUs 1208 may include at least eight streaming microprocessors. In at least one embodiment, one or more GPUs 1208 may use one or more computer application programming interfaces (APIs). In at least one embodiment, one or more GPUs 1208 may use one or more parallel computing platforms and / or programming models (e.g., NVIDIA's CUDA model).

[0200] In at least one embodiment, one or more GPUs 1208 may be power optimized to achieve optimal performance in automotive and embedded use cases. For example, in at least one embodiment, one or more GPUs 1208 may be manufactured on fin field effect transistor (“FinFET”) circuits. In at least one embodiment, each streaming microprocessor may include multiple mixed precision processing cores partitioned into multiple blocks. For example, but not limited to, 64 FP32 cores and 32 FP64 cores may be partitioned into four processing blocks. In at least one embodiment, 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two mixed precision NVIDIA tensor cores for deep learning matrix arithmetic, a zero-level (“L0”) instruction cache, a scheduler (e.g., a warp scheduler) or sequencer, a dispatch unit, and / or a 64KB register file may be allocated to each processing block. In at least one embodiment, the streaming microprocessor may include independent parallel integer and floating point data paths for providing efficient execution of workloads using a mix of computation and addressing operations. In at least one embodiment, the streaming microprocessor may include independent thread scheduling capabilities to enable finer-grained synchronization and cooperation between parallel threads. In at least one embodiment, the streaming microprocessor may include a combined L1 data cache and shared memory unit to improve performance while simplifying programming.

[0201] In at least one embodiment, one or more GPUs 1208 may include high bandwidth memory ("HBM") and / or a 16GB HBM2 memory subsystem, in some examples, to provide a peak memory bandwidth of approximately 900GB / sec. In at least one embodiment, synchronous graphics random access memory ("SGRAM"), such as a fifth generation graphics double data rate type synchronous random access memory ("GDDR5"), may be used in addition to or in lieu of HBM memory.

[0202] In at least one embodiment, one or more GPUs 1208 may include unified memory technology. In at least one embodiment, address translation service (“ATS”) support may be used to allow one or more GPUs 1208 to directly access one or more CPU 1206 page tables. In at least one embodiment, when a memory management unit (“MMU”) of a GPU in one or more GPUs 1208 experiences a miss, an address translation request may be sent to one or more CPUs 1206. In response, in at least one embodiment, 2 of the one or more CPUs 1206 may look up the virtual-physical mapping of the address in its page table and send the translation back to the one or more GPUs 1208. In at least one embodiment, unified memory technology may allow a single unified virtual address space to be used for memory of both one or more CPUs 1206 and one or more GPUs 1208, thereby simplifying programming of one or more GPUs 1208 and porting applications to one or more GPUs 1208.

[0203] In at least one embodiment, one or more GPUs 1208 may include any number of access counters that may track the frequency of accesses to other processors' memory by one or more GPUs 1208. In at least one embodiment, the one or more access counters may help ensure that memory pages are moved to the physical memory of the processor that accesses the page most frequently, thereby increasing the efficiency with which memory ranges are shared between processors.

[0204] In at least one embodiment, one or more SoCs 1204 may include any number of caches 1212, including those described herein. For example, in at least one embodiment, one or more caches 1212 may include a level 3 ("L3") cache that may be used for both (e.g., connected to) one or more CPUs 1206 and one or more GPUs 1208. In at least one embodiment, one or more caches 1212 may include a write-back cache that may track the state of each line, such as by using a cache coherence protocol (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, the L3 cache may include 4MB of memory or more, depending on the embodiment, although smaller cache sizes may be used.

[0205] In at least one embodiment, one or more SoCs 1204 may include one or more accelerators 1214 (e.g., hardware accelerators, software accelerators, or a combination thereof). In at least one embodiment, one or more SoCs 1204 may include a hardware acceleration cluster, which may include optimized hardware accelerators and / or large on-chip memory. In at least one embodiment, large on-chip memory (e.g., 4MB of SRAM) may enable the hardware acceleration cluster to accelerate neural networks and other calculations. In at least one embodiment, the hardware acceleration cluster may be used to supplement one or more GPUs 1208 and unload some tasks of one or more GPUs 1208 (e.g., to free up more cycles of one or more GPUs 1208 to perform other tasks). In at least one embodiment, one or more accelerators 1214 may be used for target workloads that are sufficiently stable to withstand acceleration (e.g., perception, convolutional neural networks ("CNN"), recurrent neural networks ("RNN"), etc.). In at least one embodiment, CNNs may include regional or regional convolutional neural networks ("RCNN") and fast RCNNs (e.g., such as for object detection) or other types of CNNs.

[0206] In at least one embodiment, one or more accelerators 1214 (e.g., a hardware acceleration cluster) may include one or more deep learning accelerators ("DLA"). In at least one embodiment, one or more DLAs may include, but are not limited to, one or more tensor processing units ("TPUs"), which may be configured to provide an additional 10 trillion operations per second for deep learning applications and reasoning. In at least one embodiment, a TPU may be an accelerator configured and optimized to perform image processing functions (e.g., for CNN, RCNN, etc.). In at least one embodiment, one or more DLAs may be further optimized for a specific set of neural network types and floating point operations and reasoning. In at least one embodiment, the design of one or more DLAs may provide higher performance per millimeter than a typical general-purpose GPU, and generally greatly exceeds the performance of a CPU. In at least one embodiment, one or more TPUs may perform several functions, including single instance convolution functions that support, for example, INT8, INT16, and FP16 data types for features and weights, and post-processor functions. In at least one embodiment, one or more DLAs can quickly and efficiently execute neural networks, particularly CNNs, on processed or unprocessed data for any of a variety of functions, including, for example, but not limited to: a CNN for object recognition and detection using data from a camera sensor; a CNN for distance estimation using data from a camera sensor; a CNN for emergency vehicle detection and recognition and detection using data from a microphone; a CNN for face recognition and vehicle owner recognition using data from a camera sensor; and / or a CNN for protection and / or safety related events.

[0207] In at least one embodiment, one or more DLAs can perform any function of one or more GPUs 1208, and by using an inference accelerator, for example, a designer can target one or more DLAs or one or more GPUs 1208 for any function. For example, in at least one embodiment, a designer can focus the processing and floating point operations of a CNN on one or more DLAs and leave other functions to one or more GPUs 1208 and / or one or more accelerators 1214.

[0208] In at least one embodiment, one or more accelerators 1214 may include a programmable vision accelerator ("PVA"), which may alternatively be referred to herein as a computer vision accelerator. In at least one embodiment, the PVA may be designed and configured to accelerate computer vision algorithms for advanced driver assistance systems ("ADAS") 1238, autonomous driving, augmented reality ("AR") applications, and / or virtual reality ("VR") applications. In at least one embodiment, the PVA may provide a balance between performance and flexibility. For example, in at least one embodiment, each PVA may include, for example, but not limited to, any number of reduced instruction set computer ("RISC") cores, direct memory access ("DMA"), and / or any number of vector processors.

[0209] In at least one embodiment, the RISC core can interact with an image sensor (e.g., an image sensor of any camera described herein), an image signal processor, and the like. In at least one embodiment, each RISC core can include any amount of memory. In at least one embodiment, the RISC core can use any of a variety of protocols, depending on the embodiment. In at least one embodiment, the RISC core can execute a real-time operating system ("RTOS"). In at least one embodiment, the RISC core can be implemented using one or more integrated circuit devices, application specific integrated circuits ("ASICs"), and / or memory devices. For example, in at least one embodiment, the RISC core can include an instruction cache and / or a tightly coupled RAM.

[0210] In at least one embodiment, the DMA may enable components of the PVA to access system memory independently of one or more CPUs 1206. In at least one embodiment, the DMA may support any number of features for providing optimizations to the PVA, including, but not limited to, support for multi-dimensional addressing and / or circular addressing. In at least one embodiment, the DMA may support up to six or more dimensions of addressing, which may include, but are not limited to, block width, block height, block depth, horizontal block stepping, vertical block stepping, and / or depth stepping.

[0211] In at least one embodiment, the vector processor may be a programmable processor that may be designed to efficiently and flexibly execute programming for computer vision algorithms and provide signal processing capabilities. In at least one embodiment, the PVA may include a PVA core and two vector processing subsystem partitions. In at least one embodiment, the PVA core may include a processor subsystem, one or more DMA engines (e.g., two DMA engines), and / or other peripherals. In at least one embodiment, the vector processing subsystem may operate as the main processing engine of the PVA and may include a vector processing unit ("VPU"), an instruction cache, and / or a vector memory (e.g., "VMEM"). In at least one embodiment, the VPU core may include a digital signal processor, such as, for example, a single instruction multiple data ("SIMD"), a very long instruction word ("VLIW") digital signal processor. In at least one embodiment, the combination of SIMD and VLIW may improve throughput and speed.

[0212] In at least one embodiment, each vector processor may include an instruction cache and may be coupled to a dedicated memory. Thus, in at least one embodiment, each vector processor may be configured to execute independently of other vector processors. In at least one embodiment, the vector processors included in a particular PVA may be configured to employ data parallelism. For example, in at least one embodiment, multiple vector processors included in a single PVA may execute a general computer vision algorithm, but on different regions of an image. In at least one embodiment, the vector processors included in a particular PVA may execute different computer vision algorithms simultaneously on an image, or even execute different algorithms on a sequence of images or portions of an image. In at least one embodiment, any number of PVAs may be included in a hardware acceleration cluster, and any number of vector processors may be included in each PVA. In at least one embodiment, the PVA may include additional error correction code ("ECC") memory to enhance overall system security.

[0213] In at least one embodiment, one or more accelerators 1214 may include an on-chip computer vision network and static random access memory ("SRAM") to provide high bandwidth, low latency SRAM for one or more accelerators 1214. In at least one embodiment, the on-chip memory may include at least 4MB of SRAM, including, for example, but not limited to, eight field-configurable memory blocks that can be accessed by both the PVA and the DLA. In at least one embodiment, each pair of memory blocks may include an advanced peripheral bus ("APB") interface, configuration circuits, controllers, and multiplexers. In at least one embodiment, any type of memory may be used. In at least one embodiment, the PVA and DLA may access the memory via a backbone that provides high-speed access to the memory for the PVA and the DLA. In at least one embodiment, the backbone may include an on-chip computer vision network that interconnects the PVA and the DLA to the memory (e.g., using APB).

[0214] In at least one embodiment, the on-chip computer vision network may include an interface that determines that both the PVA and DLA provide ready and valid signals before transmitting any control signals / addresses / data. In at least one embodiment, the interface may provide separate phases and separate channels for sending control signals / addresses / data, as well as burst-type communications for continuous data transmission. In at least one embodiment, the interface may comply with the International Organization for Standardization ("ISO") 26262 or International Electrotechnical Commission ("IEC") 61508 standards, although other standards and protocols may be used.

[0215] In at least one embodiment, one or more SoCs 1204 may include a real-time ray tracing hardware accelerator. In at least one embodiment, the real-time ray tracing hardware accelerator may be used to quickly and efficiently determine the location and range of objects (e.g., within a world model) to generate real-time visual simulations for use in RADAR signal interpretation, for sound propagation synthesis and / or analysis, for simulation of SONAR systems, for general wave propagation simulations, for comparison with LIDAR data for positioning and / or other functions, and / or for other uses.

[0216] In at least one embodiment, one or more accelerators 1214 may have a wide range of uses for autonomous driving. In at least one embodiment, the PVA may be used for key processing stages in ADAS and autonomous vehicles. In at least one embodiment, the ability of the PVA at low power consumption and low latency is well matched to the algorithm domain that requires predictable processing. In other words, the PVA excels in semi-intensive or intensive conventional computations, even on small data sets, which may require predictable runtimes with low latency and low power consumption. In at least one embodiment, such as in vehicle 1200, the PVA may be designed to run classic computer vision algorithms because they can be efficient in object detection and integer math operations.

[0217] For example, according to at least one embodiment of the technology, PVA is used to perform computer stereo vision. In at least one embodiment, a semi-global matching based algorithm may be used in some examples, but this is not meant to be limiting. In at least one embodiment, applications for Level 3-5 autonomous driving use motion estimation / stereo matching in operation (e.g., structure from motion, pedestrian recognition, lane detection, etc.). In at least one embodiment, PVA can perform computer stereo vision functions on input from two monocular cameras.

[0218] In at least one embodiment, the PVA can be used to perform dense optical flow. For example, in at least one embodiment, the PVA can process raw RADAR data (e.g., using a 4D Fast Fourier Transform) to provide processed RADAR data. In at least one embodiment, for example, the PVA is used to perform time-of-flight depth processing by processing raw time-of-flight data to provide processed time-of-flight data.

[0219] In at least one embodiment, the DLA can be used to run any type of network to enhance control and driving safety, including, for example, but not limited to, a neural network that outputs a measure of confidence for each object detection. In at least one embodiment, the confidence can be expressed or interpreted as a probability, or as providing a relative "weight" of each detection compared to other detections. In at least one embodiment, the confidence measurement enables the system to make further decisions about which detections should be considered true positive detections rather than false positive detections. In at least one embodiment, the system can set a threshold for the confidence and only consider detections that exceed the threshold as true positive detections. In an embodiment using an automatic emergency braking ("AEB") system, a false positive detection will cause the vehicle to automatically perform emergency braking, which is obviously undesirable. In at least one embodiment, a highly confident detection can be considered a trigger for AEB. In at least one embodiment, the DLA can run a neural network for regressing confidence values. In at least one embodiment, the neural network may take as its input at least some subset of parameters, such as bounding box dimensions, a ground plane estimate obtained (e.g., from another subsystem), outputs of one or more IMU sensors 1266 associated with vehicle 1200 orientation, distance, 3D position estimates of objects obtained from the neural network and / or other sensors (e.g., one or more LIDAR sensors 1264 or one or more RADAR sensors 1260).

[0220] In at least one embodiment, one or more SoCs 1204 may include one or more data stores 1216 (e.g., memory). In at least one embodiment, one or more data stores 1216 may be on-chip memory of one or more SoCs 1204 that may store neural networks to be executed on one or more GPUs 1208 and / or DLAs. In at least one embodiment, one or more data stores 1216 may have a capacity large enough to store multiple instances of a neural network for redundancy and safety. In at least one embodiment, one or more data stores 1216 may include one or more L2 or L3 caches.

[0221] In at least one embodiment, one or more SoCs 1204 may include any number of processors 1210 (e.g., embedded processors). In at least one embodiment, one or more processors 1210 may include a boot and power management processor, which may be a dedicated processor and subsystem for handling boot power and management functions and related security execution. In at least one embodiment, the boot and power management processor may be part of the boot sequence of one or more SoCs 1204 and may provide runtime power management services. In at least one embodiment, the boot power and management processor may provide clock and voltage programming, assist system low power state transitions, one or more SoCs 1204 thermal and temperature sensor management, and / or one or more SoCs 1204 power state management. In at least one embodiment, each temperature sensor may be implemented as a ring oscillator whose output frequency is proportional to the temperature, and one or more SoCs 1204 may use the ring oscillator to detect the temperature of one or more CPUs 1206, one or more GPUs 1208, and / or one or more accelerators 1214. In at least one embodiment, if the temperature is determined to exceed a threshold, the boot and power management processor can enter a temperature fault routine and place one or more SoCs 1204 into a lower power state and / or place the vehicle 1200 into a driver's safe parking mode (e.g., bringing the vehicle 1200 to a safe stop).

[0222] In at least one embodiment, one or more processors 1210 may further include a set of embedded processors that may be used as an audio processing engine, which may be an audio subsystem that implements full hardware support for multi-channel audio through multiple interfaces and a wide and flexible range of audio I / O interfaces. In at least one embodiment, the audio processing engine is a dedicated processor core having a digital signal processor with dedicated RAM.

[0223] In at least one embodiment, one or more processors 1210 may further include an always-on processor engine that may provide the necessary hardware features to support low-power sensor management and wake-up use cases. In at least one embodiment, the always-on processor engine may include, but is not limited to, a processor core, tightly coupled RAM, supporting peripherals (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic.

[0224] In at least one embodiment, one or more processors 1210 may further include a safety cluster engine, which includes but is not limited to a dedicated processor subsystem for handling safety management of automotive applications. In at least one embodiment, the safety cluster engine may include but is not limited to two or more processor cores, tightly coupled RAM, supporting peripherals (e.g., timers, interrupt controllers, etc.) and / or routing logic. In safe mode, in at least one embodiment, two or more cores may operate in lockstep mode and may be used as a single core with comparison logic for detecting any differences between their operations. In at least one embodiment, one or more processors 1210 may further include a real-time camera engine, which may include but is not limited to a dedicated processor subsystem for handling real-time camera management. In at least one embodiment, one or more processors 1210 may further include a high dynamic range signal processor, which may include but is not limited to an image signal processor, which is a hardware engine as part of the camera processing pipeline.

[0225] In at least one embodiment, one or more processors 1210 may include a video image synthesizer, which may be a processing block (e.g., implemented on a microprocessor) that implements video post-processing functions required by a video playback application to produce a final image for a player window. In at least one embodiment, the video image synthesizer may perform lens distortion correction on one or more wide-angle cameras 1270, one or more surround cameras 1274, and / or one or more in-cabin monitoring camera sensors. In at least one embodiment, the in-cabin monitoring camera sensors are preferably monitored by a neural network running on another instance of SoC1204, which is configured to identify in-cabin events and respond accordingly. In at least one embodiment, the in-cabin system may perform, but is not limited to, lip reading to activate cellular service and make calls, dictate emails, change the vehicle's destination, activate or change the vehicle's infotainment system and settings, or provide voice-activated web surfing. In at least one embodiment, certain functions are available to the driver when the vehicle is operating in autonomous mode, which are otherwise disabled.

[0226] In at least one embodiment, the video image synthesizer may include enhanced temporal noise reduction for both spatial and temporal noise reduction. For example, in at least one embodiment, where motion occurs in the video, the noise reduction appropriately weights the spatial information, thereby reducing the weight of information provided by adjacent frames. In at least one embodiment, where an image or portion of an image does not include motion, the temporal noise reduction performed by the video image synthesizer may use information from previous images to reduce noise in the current image.

[0227] In at least one embodiment, the video image compositor may also be configured to perform stereoscopic rectification on the input stereoscopic lens frames. In at least one embodiment, the video image compositor may also be used for user interface composition when the operating system desktop is being used and does not require one or more GPUs 1208 to continuously render new surfaces. In at least one embodiment, when one or more GPUs 1208 are powered and active for 3D rendering, the video image compositor may be used to offload one or more GPUs 1208 to improve performance and responsiveness.

[0228] In at least one embodiment, one or more of the SoCs 1204 may further include a Mobile Industry Processor Interface ("MIPI") camera serial interface for receiving video and input from a camera, a high-speed interface, and / or a video input block that may be used for a camera and associated pixel input functionality. In at least one embodiment, one or more of the SoCs 1204 may further include an input / output controller that may be controlled by software and may be used to receive I / O signals that are not committed to a specific role.

[0229] In at least one embodiment, one or more of the SoCs 1204 may further include a wide range of peripheral interfaces for enabling communication with peripheral devices, audio encoders / decoders (“codecs”), power management, and / or other devices. In at least one embodiment, one or more of the SoCs 1204 may be used to process data from cameras (e.g., connected via a Gigabit multimedia serial link and an Ethernet channel), sensors (e.g., one or more LIDAR sensors 1264, one or more RADAR sensors 1260, etc., which may be connected via an Ethernet channel), data from the bus 1202 (e.g., speed of the vehicle 1200, steering wheel position, etc.), data from one or more GNSS sensors 1258 (e.g., connected via an Ethernet bus or a CAN bus), etc. In at least one embodiment, one or more of the SoCs 1204 may further include dedicated high-performance large-scale storage controllers, which may include their own DMA engines and may be used to free up one or more CPUs 1206 from routine data management tasks.

[0230] In at least one embodiment, one or more SoC 1204 can be an end-to-end platform with a flexible architecture that spans automation levels 3-5, thereby providing a comprehensive functional safety architecture that utilizes and effectively uses computer vision and ADAS technologies to achieve diversity and redundancy, and provides a platform for flexible, reliable driving software stacks and deep learning tools. In at least one embodiment, one or more SoC 1204 can be faster, more reliable, and even more energy efficient and space efficient than conventional systems. For example, in at least one embodiment, one or more accelerators 1214, when combined with one or more CPUs 1206, one or more GPUs 1208, and one or more data stores 1216, can provide a fast and efficient platform for level 3-5 autonomous vehicles.

[0231] In at least one embodiment, computer vision algorithms can be executed on a CPU, which can be configured using a high-level programming language (e.g., C) to perform various processing algorithms on various visual data. However, in at least one embodiment, CPUs generally cannot meet the performance requirements of many computer vision applications, such as, for example, performance requirements related to execution time and power consumption. In at least one embodiment, many CPUs are unable to execute complex object detection algorithms in real time, which are used in in-vehicle ADAS applications and actual Level 3-5 autonomous vehicles.

[0232] The embodiments described herein allow for multiple neural networks to be executed simultaneously and / or sequentially, and for the results to be combined together to achieve Level 3-5 autonomous driving functionality. For example, in at least one embodiment, a CNN executed on a DLA or discrete GPU (e.g., one or more GPUs 1220) may include text and word recognition, allowing traffic signs to be read and understood, including signs for which the neural network has not been specifically trained. In at least one embodiment, the DLA may also include a neural network that is capable of recognizing, interpreting, and providing semantic understanding of signs and passing that semantic understanding to a path planning module running on the CPU complex.

[0233] In at least one embodiment, for Level 3, 4, or 5 driving, multiple neural networks may be run simultaneously. For example, in at least one embodiment, a warning sign stating "Caution: flashing lights indicate icy conditions," along with electric lights, may be interpreted by several neural networks independently or collectively. In at least one embodiment, the warning sign itself may be recognized as a traffic sign by a first deployed neural network (e.g., an already trained neural network), and the text "flashing lights indicate icy conditions" may be interpreted by a second deployed neural network, which notifies the vehicle's path planning software (preferably executing on a CPU complex) that icy conditions exist when flashing lights are detected. In at least one embodiment, flashing lights may be recognized by operating a third deployed neural network over multiple frames, notifying the vehicle's path planning software of the presence (or absence) of flashing lights. In at least one embodiment, all three neural networks may be run simultaneously, such as within a DLA and / or on one or more GPUs 1208.

[0234] In at least one embodiment, a CNN for face recognition and vehicle owner recognition can use data from the camera sensor to identify the presence of an authorized driver and / or owner of the vehicle 1200. In at least one embodiment, an always-on sensor processing engine can be used to unlock the vehicle when the owner approaches the driver's door and turns on the lights, and in a security mode, can be used to disable the vehicle when the owner leaves the vehicle. In this way, one or more SoCs 1204 provide protection against theft and / or carjacking.

[0235] In at least one embodiment, a CNN for emergency vehicle detection and identification can use data from microphone 1296 to detect and identify emergency vehicle sirens. In at least one embodiment, one or more SoCs 1204 use CNNs to classify environmental and urban sounds, as well as classify visual data. In at least one embodiment, a CNN running on a DLA is trained to identify the relative approaching speed of an emergency vehicle (e.g., by using the Doppler effect). In at least one embodiment, a CNN can also be trained to identify emergency vehicles specific to the local area in which the vehicle is operating, as identified by one or more GNSS sensors 1258. In at least one embodiment, when operating in Europe, the CNN will seek to detect European sirens, while when operating in North America, the CNN will seek to identify only North American sirens. In at least one embodiment, once an emergency vehicle is detected, a control program can be used with the assistance of one or more ultrasonic sensors 1262 to execute emergency vehicle safety routines, slow the vehicle, pull the vehicle to the side of the road, stop the vehicle, and / or idle the vehicle until the emergency vehicle passes.

[0236] In at least one embodiment, the vehicle 1200 may include one or more CPUs 1218 (e.g., one or more discrete CPUs or one or more dCPUs) that may be coupled to one or more SoCs 1204 via a high-speed interconnect (e.g., PCIe). In at least one embodiment, the one or more CPUs 1218 may include, for example, an X86 processor. The one or more CPUs 1218 may be used to perform any of a variety of functions, including, for example, arbitrating between ADAS sensors and one or more SoCs 1204 that may be inconsistent, and / or monitoring the status and health of one or more controllers 1236 and / or an infotainment system on a chip ("infotainment SoC") 1230. In at least one embodiment, the SoC 1204 includes one or more interconnects, and the interconnect may include a Peripheral Component Interconnect Express (PCIe).

[0237] In at least one embodiment, the vehicle 1200 may include one or more GPUs 1220 (e.g., one or more discrete GPUs or one or more dGPUs) that may be coupled to one or more SoCs 1204 via a high-speed interconnect (e.g., NVIDIA's NVLINK channel). In at least one embodiment, the one or more GPUs 1220 may provide additional artificial intelligence functionality, such as by executing redundant and / or different neural networks, and may be used to train and / or update the neural network based at least in part on input from sensors of the vehicle 1200 (e.g., sensor data).

[0238] In at least one embodiment, the vehicle 1200 may further include a network interface 1224, which may include, but is not limited to, one or more wireless antennas 1226 (e.g., one or more wireless antennas for different communication protocols, such as cellular antennas, Bluetooth antennas, etc.). In at least one embodiment, the network interface 1224 may be used to implement wireless connections to Internet cloud services (e.g., with servers and / or other network devices), with other vehicles, and / or with computing devices (e.g., client devices of passengers). In at least one embodiment, in order to communicate with other vehicles, a direct link may be established between the vehicle 1200 and another vehicle and / or an indirect link may be established (e.g., through a network and the Internet). In at least one embodiment, a vehicle-to-vehicle communication link may be used to provide a direct link. In at least one embodiment, the vehicle-to-vehicle communication link may provide information to the vehicle 1200 about vehicles near the vehicle 1200 (e.g., vehicles in front of, to the side of, and / or behind the vehicle 1200). In at least one embodiment, the aforementioned functionality may be part of the cooperative adaptive cruise control functionality of the vehicle 1200.

[0239] In at least one embodiment, the network interface 1224 may include a SoC that provides modulation and demodulation functions and enables one or more controllers 1236 to communicate via a wireless network. In at least one embodiment, the network interface 1224 may include a radio frequency front end for up-conversion from baseband to radio frequency and down-conversion from radio frequency to baseband. In at least one embodiment, frequency conversion may be performed in any technically feasible manner. For example, frequency conversion may be performed by a known process and / or using a super-heterodyne process. In at least one embodiment, the radio frequency front end function may be provided by a separate chip. In at least one embodiment, the network interface may include a wireless function for communicating via LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[0240] In at least one embodiment, the vehicle 1200 may further include one or more data stores 1228, which may include, but are not limited to, off-chip (e.g., one or more off-chip SoC 1204) storage. In at least one embodiment, the one or more data stores 1228 may include, but are not limited to, one or more storage elements, including RAM, SRAM, dynamic random access memory ("DRAM"), video random access memory ("VRAM"), flash memory, hard disk, and / or other components and / or devices that can store at least one bit of data.

[0241] In at least one embodiment, the vehicle 1200 may further include one or more GNSS sensors 1258 (e.g., GPS and / or assisted GPS sensors) to assist with mapping, perception, occupancy grid generation, and / or path planning functions. In at least one embodiment, any number of GNSS sensors 1258 may be used, including, for example but not limited to, GPS using a USB connector with an Ethernet to serial interface (e.g., RS-232) bridge.

[0242] In at least one embodiment, the vehicle 1200 may further include one or more RADAR sensors 1260. In at least one embodiment, one or more RADAR sensors 1260 may be used by the vehicle 1200 for remote vehicle detection, even in darkness and / or inclement weather conditions. In at least one embodiment, the RADAR functional safety level may be ASILB. In at least one embodiment, one or more RADAR sensors 1260 may use a CAN bus and / or bus 1202 (e.g., for transmitting data generated by one or more RADAR sensors 1260) to control and access object tracking data, and in some examples, an Ethernet channel may be accessed to access raw data. In at least one embodiment, a variety of RADAR sensor types may be used. For example, but not limited to, one or more RADAR sensors 1260 may be suitable for front, rear, and side RADAR use. In at least one embodiment, one or more of the one or more RADAR sensors 1260 are pulse Doppler RADAR sensors.

[0243] In at least one embodiment, one or more RADAR sensors 1260 may include different configurations, such as long-range with narrow field of view, short-range with wide field of view, short-range side coverage, etc. In at least one embodiment, the long-range RADAR can be used for adaptive cruise control functions. In at least one embodiment, the long-range RADAR system can provide a wide field of view achieved by two or more independent scans (e.g., within 250m (meters)). In at least one embodiment, one or more RADAR sensors 1260 can help distinguish between static objects and moving objects, and can be used by the ADAS system 1238 for emergency braking assistance and forward collision warning. In at least one embodiment, one or more sensors 1260 included in the long-range RADAR system may include but are not limited to a single-base (monostatic) multi-modal RADAR with multiple (e.g., six or more) fixed RADAR antennas and high-speed CAN and FlexRay interfaces. In at least one embodiment, six antennas are used, and the central four antennas can create a focused beam pattern designed to record the surrounding environment of the vehicle 1200 at a higher speed, while the traffic interference of adjacent lanes is minimal. In at least one embodiment, the other two antennas may extend the field of view, thereby enabling rapid detection of vehicles entering or leaving the lane of vehicle 1200 .

[0244] In at least one embodiment, as an example, the medium-range RADAR system may include a range of up to 160m (front) or 80m (rear), and a field of view of up to 42 degrees (front) or 150 degrees (rear). In at least one embodiment, the short-range RADAR system may include, but is not limited to, any number of RADAR sensors 1260 designed to be mounted at both ends of the rear bumper. When mounted at both ends of the rear bumper, in at least one embodiment, the RADAR sensor system can generate two light beams that constantly monitor the rear direction of the vehicle and nearby blind spots. In at least one embodiment, the short-range RADAR system can be used in the ADAS system 1238 for blind spot detection and / or lane change assistance.

[0245] In at least one embodiment, the vehicle 1200 may further include one or more ultrasonic sensors 1262. In at least one embodiment, one or more ultrasonic sensors 1262 that may be positioned at the front, rear, and / or side positions of the vehicle 1200 may be used for parking assistance and / or creating and updating an occupancy grid. In at least one embodiment, a variety of ultrasonic sensors 1262 may be used, and different ultrasonic sensors 1262 may be used for different detection ranges (e.g., 2.5 m, 4 m). In at least one embodiment, the ultrasonic sensor 1262 may operate at a functional safety level of ASIL B.

[0246] In at least one embodiment, the vehicle 1200 may include one or more LIDAR sensors 1264. In at least one embodiment, the one or more LIDAR sensors 1264 may be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, the one or more LIDAR sensors 1264 may operate at a functional safety level ASIL B. In at least one embodiment, the vehicle 1200 may include multiple (e.g., two, four, six, etc.) LIDAR sensors 1264 that may use an Ethernet channel (e.g., to provide data to a Gigabit Ethernet switch).

[0247] In at least one embodiment, one or more LIDAR sensors 1264 may be capable of providing a list of objects and their distances for a 360-degree field of view. In at least one embodiment, one or more commercially available LIDAR sensors 1264 may, for example, have an advertising range of approximately 100m, have an accuracy of 2cm-3cm, and support 100Mbps Ethernet connections. In at least one embodiment, one or more non-protruding LIDAR sensors may be used. In such an embodiment, one or more LIDAR sensors 1264 may include a small device that can be embedded in the front, rear, side, and / or corner positions of the vehicle 1200. In at least one embodiment, one or more LIDAR sensors 1264, in such an embodiment, may provide up to 120 degrees of horizontal field of view and 35 degrees of vertical field of view, even for low reflectivity objects, and have a range of 200m. In at least one embodiment, one or more forward-mounted LIDAR sensors 1264 may be configured for a horizontal field of view between 45 degrees and 135 degrees.

[0248] In at least one embodiment, LIDAR technology (such as 3D flash LIDAR) can also be used. In at least one embodiment, 3D flash LIDAR uses laser flash as a transmission source to illuminate up to about 200m around the vehicle 1200. In at least one embodiment, the flash LIDAR unit includes but is not limited to a receiver that records the laser pulse propagation time and the reflected light on each pixel, which in turn corresponds to the range from the vehicle 1200 to the object. In at least one embodiment, the flash LIDAR can allow each laser flash to be used to generate a highly accurate and distortion-free image of the surrounding environment. In at least one embodiment, four flash LIDAR sensors can be deployed, one on each side of the vehicle 1200. In at least one embodiment, the 3D flash LIDAR system includes but is not limited to a solid-state 3D staring array LIDAR camera with no moving parts except for the fan (e.g., a non-scanning LIDAR device). In at least one embodiment, the flash LIDAR device can use 5 nanosecond Class I (eye-safe) laser pulses per frame and can capture the reflected laser light as a 3D range point cloud and co-registered intensity data.

[0249] In at least one embodiment, the vehicle 1200 may also include one or more IMU sensors 1266. In at least one embodiment, the one or more IMU sensors 1266 may be located at the rear axle center of the vehicle 1200. In at least one embodiment, the one or more IMU sensors 1266 may include, for example but not limited to, one or more accelerometers, one or more magnetometers, one or more gyroscopes, one or more magnetic compasses, and / or other sensor types. In at least one embodiment, for example in a six-axis application, the one or more IMU sensors 1266 may include but are not limited to accelerometers and gyroscopes. In at least one embodiment, for example in a nine-axis application, the one or more IMU sensors 1266 may include but are not limited to accelerometers, gyroscopes, and magnetometers.

[0250] In at least one embodiment, one or more IMU sensors 1266 may be implemented as a miniature high-performance GPS-aided inertial navigation system ("GPS / INS") that combines a micro-electromechanical system ("MEMS") inertial sensor, a high-sensitivity GPS receiver, and an advanced Kalman filtering algorithm to provide estimates of position, velocity, and attitude. In at least one embodiment, one or more IMU sensors 1266 may enable the vehicle 1200 to estimate its heading by directly observing and correlating velocity changes from GPS to one or more IMU sensors 1266, without input from a magnetic sensor. In at least one embodiment, one or more IMU sensors 1266 and one or more GNSS sensors 1258 may be combined in a single integrated unit.

[0251] In at least one embodiment, the vehicle 1200 can include one or more microphones 1296 positioned within and / or around the vehicle 1200. In at least one embodiment, the one or more microphones 1296 can be used for emergency vehicle detection and identification.

[0252] In at least one embodiment, the vehicle 1200 may further include any number of camera types, including one or more stereo cameras 1268, one or more wide-angle cameras 1270, one or more infrared cameras 1272, one or more surround cameras 1274, one or more long-range cameras 1298, one or more mid-range cameras 1276, and / or other camera types. In at least one embodiment, the cameras may be used to capture image data around the entire periphery of the vehicle 1200. In at least one embodiment, the type of camera used depends on the vehicle 1200. In at least one embodiment, any combination of camera types may be used to provide the necessary coverage around the vehicle 1200. In at least one embodiment, the number of cameras deployed may vary depending on the embodiment. For example, in at least one embodiment, the vehicle 1200 may include six cameras, seven cameras, ten cameras, twelve cameras, or another number of cameras. In at least one embodiment, the cameras may support, by way of example but not limitation, Gigabit Multimedia Serial Link ("GMSL") and / or Gigabit Ethernet communications. In at least one embodiment, the present invention is described herein previously with reference to the accompanying drawings. Fig. 12A and Fig. 12B Each camera is described in more detail.

[0253] In at least one embodiment, the vehicle 1200 may further include one or more vibration sensors 1242. In at least one embodiment, one or more vibration sensors 1242 may measure vibrations of a component (e.g., an axle) of the vehicle 1200. For example, in at least one embodiment, changes in vibration may indicate changes in the road surface. In at least one embodiment, when two or more vibration sensors 1242 are used, the difference between the vibrations may be used to determine friction or slippage of the road surface (e.g., when there is a vibration difference between a powered drive shaft and a freely rotating shaft).

[0254] In at least one embodiment, the vehicle 1200 may include an ADAS system 1238. In at least one embodiment, the ADAS system 1238 may include, but is not limited to, a SoC in some examples. In at least one embodiment, the ADAS system 1238 may include, but is not limited to, any number and any combination of autonomous / adaptive / automatic cruise control ("ACC") systems, cooperative adaptive cruise control ("CACC") systems, forward collision warning ("FCW") systems, automatic emergency braking ("AEB") systems, lane departure warning ("LDW") systems, lane keeping assist ("LKA") systems, blind spot warning ("BSW") systems, rear cross traffic warning ("RCTW") systems, collision warning ("CW") systems, lane centering ("LC") systems, and / or other systems, features, and / or functions.

[0255] In at least one embodiment, the ACC system may use one or more RADAR sensors 1260, one or more LIDAR sensors 1264, and / or any number of cameras. In at least one embodiment, the ACC system may include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, the longitudinal ACC system monitors and controls the distance to another vehicle immediately in front of the vehicle 1200 and automatically adjusts the speed of the vehicle 1200 to maintain a safe distance from the vehicle in front. In at least one embodiment, the lateral ACC system performs distance keeping and suggests that the vehicle 1200 change lanes when necessary. In at least one embodiment, lateral ACC is related to other ADAS applications, such as LC and CW.

[0256] In at least one embodiment, the CACC system uses information from other vehicles, which can be received from other vehicles indirectly via a wireless link or through a network connection (e.g., through the Internet) via a network interface 1224 and / or one or more wireless antennas 1226. In at least one embodiment, the direct link can be provided by a vehicle-to-vehicle ("V2V") communication link, while the indirect link can be provided by an infrastructure-to-vehicle ("I2V") communication link. Typically, V2V communications provide information about the vehicle immediately ahead (e.g., the vehicle immediately ahead of the vehicle 1200 and in the same lane as it), while I2V communications provide information about traffic further ahead. In at least one embodiment, the CACC system can include one or both of the I2V and V2V information sources. In at least one embodiment, given information about the vehicle ahead of the vehicle 1200, the CACC system can be more reliable and have the potential to improve the smoothness of traffic flow and reduce road congestion.

[0257] In at least one embodiment, the FCW system is designed to warn the driver of the hazard so that the driver can take corrective action. In at least one embodiment, the FCW system uses a forward-facing camera and / or one or more RADAR sensors 1260, which are coupled to a dedicated processor, DSP, FPGA and / or ASIC, which are electrically coupled to provide driver feedback, such as a display, speaker and / or vibration component. In at least one embodiment, the FCW system can provide warnings, such as in the form of sounds, visual warnings, vibrations and / or rapid brake pulses.

[0258] In at least one embodiment, the AEB system detects an impending forward collision with another vehicle or other object and may automatically apply brakes if the driver does not take corrective action within specified time or distance parameters. In at least one embodiment, the AEB system may use one or more forward-facing cameras and / or one or more RADAR sensors 1260 coupled to a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, when the AEB system detects a hazard, it typically first warns the driver to take corrective action to avoid the collision, and, if the driver does not take corrective action, the AEB system may automatically apply brakes to try to prevent or at least mitigate the effects of the predicted collision. In at least one embodiment, the AEB system may include technologies such as dynamic brake support and / or collision approach braking.

[0259] In at least one embodiment, the LDW system provides visual, audible, and / or tactile warnings, such as steering wheel or seat vibrations, to warn the driver when the vehicle 1200 crosses a lane marking. In at least one embodiment, the LDW system is not activated when the driver indicates an intentional lane departure, such as by activating a turn signal. In at least one embodiment, the LDW system may use a forward-facing camera coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to provide driver feedback such as a display, speaker, and / or vibration component. In at least one embodiment, the LKA system is a variation of the LDW system. In at least one embodiment, if the vehicle 1200 begins to leave its lane, the LKA system provides steering input or braking to correct the vehicle 1200.

[0260] In at least one embodiment, the BSW system detects and warns the driver that the vehicle is in the blind spot of the car. In at least one embodiment, the BSW system can provide visual, auditory, and / or tactile alerts to indicate that it is unsafe to merge or change lanes. In at least one embodiment, the BSW system can provide additional warnings when the driver uses a turn signal. In at least one embodiment, the BSW system can use one or more rear-facing cameras and / or one or more RADAR sensors 1260 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which are electrically coupled to driver feedback, such as a display, speaker, and / or vibration component.

[0261] In at least one embodiment, the RCTW system can provide visual, audible, and / or tactile notifications when the vehicle 1200 detects an object outside the range of the rear camera while backing up. In at least one embodiment, the RCTW system includes an AEB system to ensure that vehicle brakes are applied to avoid a collision. In at least one embodiment, the RCTW system can use one or more rear-facing RADAR sensors 1260 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which are electrically coupled to provide driver feedback such as a display, speaker, and / or vibration component.

[0262] In at least one embodiment, conventional ADAS systems may be prone to false positive results, which may annoy and distract the driver, but are generally not catastrophic because conventional ADAS systems warn the driver and allow the driver to decide whether the safety situation actually exists and take action accordingly. In at least one embodiment, in the event of conflicting results, the vehicle 1200 decides for itself whether to listen to the results of the main computer or the auxiliary computer (e.g., the first controller or the second controller in the controller 1236). For example, in at least one embodiment, the ADAS system 1238 can be a backup and / or auxiliary computer for providing perception information to the backup computer rationality module. In at least one embodiment, the backup computer rationality monitor can run redundant various software on hardware components to detect faults in perception and dynamic driving tasks. In at least one embodiment, the output from the ADAS system 1238 can be provided to the supervisory MCU. In at least one embodiment, if the output from the main computer and the output from the auxiliary computer conflict, the supervisory MCU decides how to coordinate the conflict to ensure safe operation.

[0263] In at least one embodiment, the primary computer can be configured to provide a confidence score to the supervisory MCU, which indicates the primary computer's confidence in the selected result. In at least one embodiment, if the confidence score exceeds a threshold, the supervisory MCU can follow the instructions of the primary computer regardless of whether the secondary computer provides conflicting or inconsistent results. In at least one embodiment, in the event that the confidence score does not meet the threshold, and in the event that the primary computer and the secondary computer indicate different results (e.g., conflict), the supervisory MCU can arbitrate between the computers to determine the appropriate result.

[0264] In at least one embodiment, the supervisory MCU can be configured to run a neural network that is trained and configured to determine conditions under which the auxiliary computer provides a false alarm based at least in part on outputs from the main computer and outputs from the auxiliary computer. In at least one embodiment, one or more neural networks in the supervisory MCU can learn when the output of the auxiliary computer can be trusted and when it cannot be trusted. For example, in at least one embodiment, when the auxiliary computer is a RADAR-based FCW system, one or more neural networks in the supervisory MCU can learn when the FCW system is identifying metal objects that are not actually dangerous, such as drainage grates or manhole covers that will trigger an alarm. In at least one embodiment, when the auxiliary computer is a camera-based LDW system, when there are cyclists or pedestrians and lane departure is actually the safest operation, the neural network in the supervisory MCU can learn to override LDW. In at least one embodiment, the supervisory MCU may include at least one of a DLA or a GPU suitable for running one or more neural networks with associated memory. In at least one embodiment, the supervisory MCU may include and / or be included as a component of one or more SoCs 1204.

[0265] In at least one embodiment, the ADAS system 1238 may include an auxiliary computer that performs ADAS functions using traditional computer vision rules. In at least one embodiment, the auxiliary computer may use classical computer vision rules (if-then), and the presence of one or more neural networks in the supervisory MCU may improve reliability, safety, and performance. For example, in at least one embodiment, the diverse implementations and intentional non-identity make the entire system more fault-tolerant, especially for failures caused by software (or software-hardware interface) functions. For example, in at least one embodiment, if there is a software vulnerability or error in the software running on the main computer, and the non-identical software code running on the auxiliary computer provides consistent overall results, the supervisory MCU can have greater confidence that the overall results are correct and that the vulnerability in the software or hardware on the main computer will not cause a significant error.

[0266] In at least one embodiment, the output of the ADAS system 1238 can be fed into the perception block of the main computer and / or the dynamic driving task block of the main computer. For example, in at least one embodiment, if the ADAS system 1238 indicates a forward collision warning due to an object directly ahead, the perception block can use that information when the object is identified. In at least one embodiment, the auxiliary computer can have its own neural network that is trained, as described herein, to reduce the risk of false positives.

[0267] In at least one embodiment, the vehicle 1200 may further include an infotainment SoC 1230 (e.g., an in-vehicle infotainment system (IVI)). Although shown and described as a SoC, in at least one embodiment, the infotainment system SoC 1230 may not be a SoC and may include, but is not limited to, two or more discrete components. In at least one embodiment, the infotainment SoC 1230 may include, but is not limited to, a combination of hardware and software that can be used to provide audio (e.g., music, personal digital assistants, navigation instructions, news, radio, etc.), video (e.g., TV, movies, streaming media, etc.), phone (e.g., hands-free calling), network connectivity (e.g., LTE, WiFi, etc.), and / or information services (e.g., navigation system, rear parking assist, radio data system, vehicle-related information such as fuel level, total distance covered, brake fuel level, oil level, door open / closed, air filter information, etc.) to the vehicle 1200. For example, the infotainment SoC 1230 may include a radio, a disk player, a navigation system, a video player, USB and Bluetooth connections, an onboard computer, an onboard entertainment system, WiFi, steering wheel audio controls, hands-free voice control, a head-up display ("HUD"), an HMI display 1234, a telematics device, a control panel (e.g., for controlling and / or interacting with various components, features, and / or systems), and / or other components. In at least one embodiment, the infotainment SoC 1230 may be further used to provide information (e.g., visual and / or auditory information) to one or more users of the vehicle 1200, such as information from an ADAS system 1238, autonomous driving information (such as planned vehicle maneuvers), trajectories, surrounding environment information (e.g., intersection information, vehicle information, road information, etc.), and / or other information.

[0268] In at least one embodiment, the infotainment SoC 1230 may include any number and type of GPU functionality. In at least one embodiment, the infotainment SoC 1230 may communicate with other devices, systems, and / or components of the vehicle 1200 via the bus 1202. In at least one embodiment, the infotainment SoC 1230 may be coupled to a supervisory MCU so that the GPU of the infotainment system may perform some autonomous driving functions in the event that one or more of the main controllers 1236 (e.g., the main computer and / or backup computer of the vehicle 1200) fails. In at least one embodiment, the infotainment SoC 1230 may place the vehicle 1200 in a driver-to-safety parking mode, as described herein.

[0269] In at least one embodiment, the vehicle 1200 may further include a dashboard 1232 (e.g., a digital dashboard, an electronic dashboard, a digital instrument panel, etc.). In at least one embodiment, the dashboard 1232 may include, but is not limited to, a controller and / or a supercomputer (e.g., a discrete controller or a supercomputer). In at least one embodiment, the dashboard 1232 may include, but is not limited to, a set of instruments in any number and combination, such as a speedometer, a fuel level, an oil pressure, a tachometer, an odometer, a turn indicator, a shift position indicator, one or more seat belt warning lights, one or more parking brake warning lights, one or more engine fault lights, supplementary restraint system (e.g., airbag) information, lighting controls, safety system controls, navigation information, etc. In some examples, information may be displayed and / or shared between the infotainment SoC 1230 and the dashboard 1232. In at least one embodiment, the dashboard 1232 may be included as part of the infotainment SoC 1230, and vice versa.

[0270] Fig.12D In accordance with at least one embodiment, one or more cloud-based servers and Fig. 12A1200. In at least one embodiment, the system may include, but is not limited to, one or more servers 1278, one or more networks 1290, and any number and type of vehicles, including vehicle 1200. In at least one embodiment, one or more servers 1278 may include, but are not limited to, multiple GPUs 1284(A)-1284(H) (collectively referred to herein as GPUs 1284), PCIe switches 1282(A)-1282(D) (collectively referred to herein as PCIe switches 1282), and / or CPUs 1280(A)-1280(B) (collectively referred to herein as CPUs 1280). In at least one embodiment, GPUs 1284, CPUs 1280, and PCIe switches 1282 may be interconnected with a high-speed interconnect, such as, for example, but not limited to, NVLink interface 1288 and / or PCIe connection 1286 developed by NVIDIA. In at least one embodiment, the GPUs 1284 are connected via NVLink and / or NVSwitch SoCs, and the GPUs 1284 and PCIe switches 1282 are connected via PCIe interconnects. Although eight GPUs 1284, two CPUs 1280, and four PCIe switches 1282 are shown, this is not intended to be limiting. In at least one embodiment, each of the one or more servers 1278 may include, but is not limited to, any number of GPUs 1284, CPUs 1280, and / or PCIe switches 1282 in any combination. For example, in at least one embodiment, one or more servers 1278 may each include eight, sixteen, thirty-two, and / or more GPUs 1284.

[0271] In at least one embodiment, one or more servers 1278 may receive image data representing an image from a vehicle via one or more networks 1290 that shows an unexpected or changed road condition, such as a recently started road project. In at least one embodiment, one or more servers 1278 may send updated neural networks 1292 and / or map information 1294 to the vehicle via one or more networks 1290, including, but not limited to, information about traffic and road conditions. In at least one embodiment, updates to the map information 1294 may include, but are not limited to, updates to the HD map 1222, such as information about construction sites, potholes, access roads, flooding, and / or other obstacles. In at least one embodiment, the neural network 1292 and / or map information 1294 may have been generated by new training and / or experience represented in data received from any number of vehicles in the environment, and / or based at least on training performed at a data center (e.g., using one or more servers 1278 and / or other servers).

[0272] In at least one embodiment, one or more servers 1278 can be used to train a machine learning model (e.g., a neural network) based at least in part on the training data. In at least one embodiment, the training data can be generated by the vehicle, and / or can be generated in simulation (e.g., using a game engine). In at least one embodiment, any amount of the training data is labeled (e.g., where the associated neural network benefits from supervised learning) and / or undergoes other preprocessing. In at least one embodiment, no amount of the training data is labeled and / or preprocessed (e.g., where the associated neural network does not require supervised learning). In at least one embodiment, once the machine learning model is trained, the machine learning model can be used by the vehicle (e.g., sent to the vehicle via one or more networks 1290, and / or the machine learning model can be used by one or more servers 1278 to remotely monitor the vehicle.

[0273] In at least one embodiment, one or more servers 1278 may receive data from the vehicle and apply the data to the latest real-time neural network for real-time intelligent reasoning. In at least one embodiment, one or more servers 1278 may include a deep learning supercomputer and / or a dedicated AI computer powered by one or more GPUs 1284, such as the DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, one or more servers 1278 may include a deep learning infrastructure of a data center powered by a CPU.

[0274] In at least one embodiment, the deep learning infrastructure of one or more servers 1278 may be capable of fast, real-time inference, and may use this capability to assess and validate the health of the processors, software, and / or associated hardware in the vehicle 1200. For example, in at least one embodiment, the deep learning infrastructure may receive periodic updates from the vehicle 1200, such as a sequence of images and / or objects that the vehicle 1200 has located in the sequence of images (e.g., via computer vision and / or other machine learning object classification techniques). In at least one embodiment, the deep learning infrastructure may run its own neural network to identify objects and compare them to those identified by the vehicle 1200, and, if the results do not match and the deep learning infrastructure concludes that the AI ​​in the vehicle 1200 is malfunctioning, the one or more servers 1278 may send a signal to the vehicle 1200 instructing the fail-safe computer of the vehicle 1200 to take control, notify passengers, and complete a safe parking maneuver.

[0275] In at least one embodiment, one or more servers 1278 may include one or more GPUs 1284 and one or more programmable inference accelerators (e.g., NVIDIA's TensorRT 3 device). In at least one embodiment, the combination of GPU-driven servers and inference acceleration can enable real-time response. In at least one embodiment, such as in situations where performance is not critical, servers driven by CPUs, FPGAs, and other processors can be used for inference. In at least one embodiment, one or more hardware structures 915 are used to execute one or more embodiments. This article combines Fig. 9A and / or Fig. 9B Provides details about the hardware structure 915.

[0276] Figures 12A-12D The logic and hardware structure can be integrated into Figure 1-8 In the system and processor disclosed in. For example, Figures 12A-12D The logic / hardware structure in can perform at least part or all of process 300, 400 and / or 500. In at least one embodiment, Figures 12A-12D The system or apparatus disclosed in causes a processor to identify one or more locations of one or more objects in one or more images based at least in part on one or more locations of one or more objects in one or more previous images. In at least one embodiment, by performing at least part or all of processes 300, 400, and / or 500, a processor including one or more circuits divides one or more images into one or more segments and stores in a memory an indication of which of the one or more segments contain one or more identified locations of one or more objects. In at least one embodiment, by performing at least part or all of processes 300, 400, and / or 500, Figures 12A-12D The system or apparatus disclosed in causes a processor to combine one or more positions of one or more objects to generate a region of interest.

[0277] Computer Systems

[0278] Fig.131300 is a block diagram illustrating an exemplary computer system according to at least one embodiment, which may be a system of interconnected devices and components, a system on a chip (SOC), or some combination thereof formed with a processor, which may include an execution unit for executing instructions. In at least one embodiment, in accordance with the present disclosure, such as in the embodiments described herein, computer system 1300 may include, but is not limited to, components, such as processor 1302, for executing algorithms for process data using execution units (including logic). In at least one embodiment, computer system 1300 may include a processor, such as a processor available from Intel Corporation of Santa Clara, California. Processor family, Xeon TM , XScale TM and / or StrongARM TM , Core TM or Nervana TM microprocessor, although other systems (including PCs with other microprocessors, engineering workstations, set-top boxes, etc.) may also be used. In at least one embodiment, computer system 1300 may execute a version of the WINDOWS operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (e.g., UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0279] Embodiments may be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol (Internet Protocol) devices, digital cameras, personal digital assistants ("PDAs"), and handheld PCs. In at least one embodiment, the embedded application may include a microcontroller, a digital signal processor ("DSP"), a system on a chip, a network computer ("NetPC"), a set-top box, a network hub, a wide area network ("WAN") switch, or any other system that can execute one or more instructions according to at least one embodiment.

[0280] In at least one embodiment, computer system 1300 may include, but is not limited to, a processor 1302, which may include, but is not limited to, one or more execution units 1308 for performing machine learning model training and / or reasoning according to the techniques described herein. In at least one embodiment, computer system 1300 is a single processor desktop or server system, but in another embodiment, computer system 1300 may be a multi-processor system. In at least one embodiment, processor 1302 may include, but is not limited to, for example, a complex instruction set computer ("CISC") microprocessor, a reduced instruction set computing ("RISC") microprocessor, a very long instruction word ("VLIW") microprocessor, a processor that implements an instruction set combination, or any other processor device, such as a digital signal processor. In at least one embodiment, processor 1302 may be coupled to a processor bus 1310, which may transmit data signals between processor 1302 and other components in computer system 1300.

[0281] In at least one embodiment, processor 1302 may include, but is not limited to, level 1 ("L1") internal cache memory ("cache") 1304. In at least one embodiment, processor 1302 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory may reside external to processor 1302. Other embodiments may also include a combination of internal and external caches, depending on the particular implementation and requirements. In at least one embodiment, register file 1306 may store different types of data in various registers, including but not limited to integer registers, floating point registers, status registers, and instruction pointer registers.

[0282] In at least one embodiment, an execution unit 1308, including but not limited to logic to perform integer and floating point operations, is also located in the processor 1302. In at least one embodiment, the processor 1302 may also include a microcode ("ucode") read-only memory ("ROM") that stores microcode for certain macroinstructions. In at least one embodiment, the execution unit 1308 may include logic to process a packed instruction set 1309. In at least one embodiment, by including the packed instruction set 1309 in the instruction set of a general purpose processor and associated circuitry to execute the instructions, operations used by many multimedia applications may be performed using packed data in the processor 1302. In at least one embodiment, many multimedia applications may be accelerated and executed more efficiently by performing operations on packed data using the full width of the processor's data bus, which may eliminate the need to transfer smaller units of data on the processor's data bus to perform one or more operations on one data element at a time.

[0283] In at least one embodiment, execution unit 1308 may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. In at least one embodiment, computer system 1300 may include, but is not limited to, memory 1320. In at least one embodiment, memory 1320 may be a dynamic random access memory ("DRAM") device, a static random access memory ("SRAM") device, a flash memory device, or other memory device. In at least one embodiment, memory 1320 may store one or more instructions 1319 and / or data 1321 represented by data signals that may be executed by processor 1302.

[0284] In at least one embodiment, the system logic chip may be coupled to the processor bus 1310 and the memory 1320. In at least one embodiment, the system logic chip may include, but is not limited to, a memory controller hub ("MCH") 1316, and the processor 1302 may communicate with the MCH 1316 via the processor bus 1310. In at least one embodiment, the MCH 1316 may provide a high bandwidth memory path 1318 to the memory 1320 for instruction and data storage and for storage of graphics commands, data, and textures. In at least one embodiment, the MCH 1316 may direct data signals between the processor 1302, the memory 1320, and other components in the computer system 1300, and bridge data signals between the processor bus 1310, the memory 1320, and the system I / O interface 1322. In at least one embodiment, the system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 1316 may be coupled to the memory 1320 via a high bandwidth memory path 1318 , and the graphics / video card 1312 may be coupled to the MCH 1316 via an accelerated graphics port (“AGP”) interconnect 1314 .

[0285] In at least one embodiment, computer system 1300 may use system I / O interface 1322 as a proprietary hub interface bus to couple MCH 1316 to I / O controller hub ("ICH") 1330. In at least one embodiment, ICH 1330 may provide direct connection to certain I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus used to connect peripheral devices to memory 1320, chipsets, and processor 1302. Examples may include, but are not limited to, an audio controller 1329, a firmware hub ("flash BIOS") 1328, a wireless transceiver 1326, a data store 1324, a traditional I / O controller 1323 including a user input and keyboard interface 1325, a serial expansion port 1327 (such as a universal serial bus ("USB") port), and a network controller 1334. In at least one embodiment, data store 1324 may include a hard drive, a floppy drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0286] In at least one embodiment, Fig.13 The system is shown as comprising interconnected hardware devices or "chips", while in other embodiments, Fig.13 An exemplary SoC may be shown. In at least one embodiment, Fig.13 The devices shown in the can be interconnected using a proprietary interconnect, a standardized interconnect (eg, PCIe), or some combination thereof. In at least one embodiment, one or more components of computer system 1300 are interconnected using a compute express link (CXL) interconnect.

[0287] Logic 915 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 9A and / or Fig. 9B Details are provided regarding logic 915. In at least one embodiment, logic 915 can be used in computer system 1300 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0288] Fig.13 The logic and hardware structure can be integrated into Figure 1-8 In the system and processor disclosed in. For example, Fig.13 The logic / hardware structure in can perform at least part or all of process 300, 400 and / or 500. In at least one embodiment, Fig.13The system or apparatus disclosed in causes a processor to identify one or more locations of one or more objects in one or more images based at least in part on one or more locations of one or more objects in one or more previous images. In at least one embodiment, by performing at least part or all of processes 300, 400, and / or 500, a processor including one or more circuits divides one or more images into one or more segments and stores in a memory an indication of which of the one or more segments contain one or more identified locations of one or more objects. In at least one embodiment, by performing at least part or all of processes 300, 400, and / or 500, Fig.13 The system or apparatus disclosed in causes a processor to combine one or more positions of one or more objects to generate a region of interest.

[0289] Fig.14 1 is a block diagram illustrating an electronic device 1400 for utilizing a processor 1410 according to at least one embodiment. In at least one embodiment, the electronic device 1400 may be, for example but not limited to, a notebook computer, a tower server, a rack server, a blade server, a laptop computer, a desktop computer, a tablet computer, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0290] In at least one embodiment, electronic device 1400 may include, but is not limited to, a processor 1410 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices. In at least one embodiment, processor 1410 is coupled using a bus or interface, such as an I 2 C bus, system management bus ("SMBus"), low pin count (LPC) bus, serial peripheral interface ("SPI"), high-definition audio ("HDA") bus, serial advanced technology attachment ("SATA") bus, universal serial bus ("USB") (version 1, 2, 3, etc.), or universal asynchronous receiver / transmitter ("UART") bus. In at least one embodiment, Fig.14 A system is shown that includes interconnected hardware devices or "chips", while in other embodiments, Fig.14 An exemplary SoC may be shown. In at least one embodiment, Fig.14 The devices shown in can be interconnected using a proprietary interconnect, a standardized interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, Fig.14 One or more components of the system are interconnected using a Compute Express Link (CXL) interconnect.

[0291] In at least one embodiment, Fig.14It may include a display 1424, a touch screen 1425, a touch pad 1430, a near field communication unit (“NFC”) 1445, a sensor hub 1440, a thermal sensor 1446, a fast chipset (“EC”) 1435, a trusted platform module (“TPM”) 1438, a BIOS / firmware / flash (“BIOS, FW Flash”) 1422, a DSP 1460, a drive 1420 (such as a solid state disk (“SSD”) or a hard disk drive (“HDD”)), a wireless local area network unit (“WLAN”) 1450, a Bluetooth unit 1452, a wireless wide area network unit (“WWAN”) 1456, a global positioning system (GPS) unit 1455, a camera (“USB 3.0 camera”) 1454 (such as a USB 3.0 camera), and / or a low power double data rate (“LPDDR”) memory unit (“LPDDR3”) 1415 implemented with, for example, the LPDDR3 standard. These components may each be implemented in any suitable manner.

[0292] In at least one embodiment, other components may be communicatively coupled to the processor 1410 through the components described herein. In at least one embodiment, the accelerometer 1441, ambient light sensor (“ALS”) 1442, compass 1443, and gyroscope 1444 may be communicatively coupled to the sensor hub 1440. In at least one embodiment, the thermal sensor 1439, fan 1437, keyboard 1436, and touchpad 1430 may be communicatively coupled to the EC 1435. In at least one embodiment, the speaker 1463, earphone 1464, and microphone (“mic”) 1465 may be communicatively coupled to the audio unit (“audio codec and class D amplifier”) 1462, which in turn may be communicatively coupled to the DSP 1460. In at least one embodiment, the audio unit 1462 may include, for example, but not limited to, an audio encoder / decoder (“codec”) and a class D amplifier. In at least one embodiment, the SIM card (“SIM”) 1457 may be communicatively coupled to the WWAN unit 1456. In at least one embodiment, components such as the WLAN unit 1450 and the Bluetooth unit 1452 and the WWAN unit 1456 may be implemented as a next generation form factor ("NGFF").

[0293] Logic 915 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 9A and / or Fig. 9B Details are provided regarding logic 915. In at least one embodiment, logic 915 may be used in electronic device 1400 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0294] Fig.14 The logic and hardware structure can be integrated into Figure 1-8 In the system and processor disclosed in. For example, Fig.14 The logic / hardware structure in can perform at least part or all of process 300, 400 and / or 500. In at least one embodiment, Fig.14 The system or apparatus disclosed in causes a processor to identify one or more locations of one or more objects in one or more images based at least in part on one or more locations of one or more objects in one or more previous images. In at least one embodiment, by performing at least part or all of processes 300, 400, and / or 500, a processor including one or more circuits divides one or more images into one or more segments and stores in a memory an indication of which of the one or more segments contain one or more identified locations of one or more objects. In at least one embodiment, by performing at least part or all of processes 300, 400, and / or 500, Fig.14 The system or apparatus disclosed in causes a processor to combine one or more positions of one or more objects to generate a region of interest.

[0295] Fig.15 A computer system 1500 is shown in accordance with at least one embodiment. In at least one embodiment, the computer system 1500 is configured to implement the various processes and methods described throughout this disclosure.

[0296] In at least one embodiment, computer system 1500 includes, but is not limited to, at least one central processing unit ("CPU") 1502 connected to a communication bus 1510 implemented using any suitable protocol, such as PCI ("Peripheral Component Interconnect"), Peripheral Component Interconnect Express ("PCI-Express"), AGP ("Accelerated Graphics Port"), HyperTransport, or any other bus or point-to-point communication protocol. In at least one embodiment, computer system 1500 includes, but is not limited to, main memory 1504 and control logic (e.g., implemented as hardware, software, or a combination thereof), and data is stored in main memory 1504, which may take the form of random access memory ("RAM"). In at least one embodiment, a network interface subsystem ("network interface") 1522 provides an interface to other computing devices and networks for receiving data from other systems and sending data to other systems using computer system 1500.

[0297] In at least one embodiment, computer system 1500 includes, but is not limited to, input device 1508, parallel processing system 1512, and display device 1506, which may be implemented using conventional cathode ray tubes ("CRTs"), liquid crystal displays ("LCDs"), light emitting diode ("LED") displays, plasma displays, or other suitable display technologies. In at least one embodiment, user input is received from input device 1508 (such as a keyboard, mouse, touch pad, microphone, etc.). In at least one embodiment, each of the modules described herein may be located on a single semiconductor platform to form a processing system.

[0298] Logic 915 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 9A and / or Fig. 9B Details are provided regarding logic 915. In at least one embodiment, logic 915 can be used in computer system 1500 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0299] Fig.15 The logic and hardware structure can be integrated into Figure 1-8 In the system and processor disclosed in. For example, Fig.15 The logic / hardware structure in can perform at least part or all of process 300, 400 and / or 500. In at least one embodiment, Fig.15 The system or apparatus disclosed in causes a processor to identify one or more locations of one or more objects in one or more images based at least in part on one or more locations of one or more objects in one or more previous images. In at least one embodiment, by performing at least part or all of processes 300, 400, and / or 500, a processor including one or more circuits divides one or more images into one or more segments and stores in a memory an indication of which of the one or more segments contain one or more identified locations of one or more objects. In at least one embodiment, by performing at least part or all of processes 300, 400, and / or 500, Fig.15 The system or apparatus disclosed in causes a processor to combine one or more positions of one or more objects to generate a region of interest.

[0300] Fig.16A computer system 1600 is shown according to at least one embodiment. In at least one embodiment, the computer system 1600 includes, but is not limited to, a computer 1610 and a USB disk 1620. In at least one embodiment, the computer 1610 may include, but is not limited to, any number and type of processors (not shown) and memories (not shown). In at least one embodiment, the computer 1610 includes, but is not limited to, a server, a cloud instance, a laptop computer, and a desktop computer.

[0301] In at least one embodiment, the USB disk 1620 includes, but is not limited to, a processing unit 1630, a USB interface 1640, and a USB interface logic 1650. In at least one embodiment, the processing unit 1630 may be any instruction execution system, device, or apparatus capable of executing instructions. In at least one embodiment, the processing unit 1630 may include, but is not limited to, any number and type of processing cores (not shown). In at least one embodiment, the processing unit 1630 includes an application specific integrated circuit ("ASIC") that is optimized to perform any number and type of operations associated with machine learning. For example, in at least one embodiment, the processing unit 1630 is a tensor processing unit ("TPC") that is optimized to perform machine learning reasoning operations. In at least one embodiment, the processing unit 1630 is a visual processing unit ("VPU") that is optimized to perform machine vision and machine learning reasoning operations.

[0302] In at least one embodiment, USB interface 1640 can be any type of USB connector or USB socket. For example, in at least one embodiment, USB interface 1640 is a USB 3.0 Type-C socket for data and power. In at least one embodiment, USB interface 1640 is a USB 3.0 Type-A connector. In at least one embodiment, USB interface logic 1650 can include any number and type of logic that enables processing unit 1630 to interface with a device (e.g., computer 1610) via USB connector 1640.

[0303] Logic 915 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 9A and / or Fig. 9B Details are provided regarding logic 915. In at least one embodiment, logic 915 can be used in computer system 1600 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0304] Fig.16 The logic and hardware structure can be integrated into Figure 1-8In the system and processor disclosed in. For example, Fig.16 The logic / hardware structure in can perform at least part or all of process 300, 400 and / or 500. In at least one embodiment, Fig.16 The system or apparatus disclosed in causes a processor to identify one or more locations of one or more objects in one or more images based at least in part on one or more locations of one or more objects in one or more previous images. In at least one embodiment, by performing at least part or all of processes 300, 400, and / or 500, a processor including one or more circuits divides one or more images into one or more segments and stores in a memory an indication of which of the one or more segments contain one or more identified locations of one or more objects. In at least one embodiment, by performing at least part or all of processes 300, 400, and / or 500, Fig.16 The system or apparatus disclosed in causes a processor to combine one or more positions of one or more objects to generate a region of interest.

[0305] Fig.17A An exemplary architecture is shown in which multiple GPUs 1710(1)-1710(N) are communicatively coupled to multiple multi-core processors 1705(1)-1705(M) via high-speed links 1740(1)-1740(N) (e.g., a bus, a point-to-point interconnect, etc.). In at least one embodiment, the high-speed links 1740(1)-1740(N) support 4GB / s, 30GB / s, 80GB / s, or higher communication throughput. In at least one embodiment, various interconnect protocols can be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0. In the various figures, "N" and "M" represent positive integers, whose values ​​may vary from figure to figure. In at least one embodiment, one or more of the multiple GPUs 1710(1)-1710(N) include the following: Fig. 20A and Fig. 20B 2000. In at least one embodiment, one or more graphics cores 2000 may be referred to as streaming multiprocessors ("SMs"), stream processors ("SPs"), stream processing units ("SPUs"), compute units ("CUs"), execution units ("EUs"), and / or slices, where, in this context, a slice may refer to a portion of processing resources in a processing unit (e.g., 16 cores, a ray tracing unit, a thread director, or a scheduler).

[0306] In addition, in at least one embodiment, two or more GPUs 1710 are interconnected via high-speed links 1729(1)-1729(2), which may be implemented using protocols / links similar to or different from those used for high-speed links 1740(1)-1740(N). Similarly, two or more multi-core processors 1705 may be connected via high-speed link 1728, which may be a symmetric multiprocessor (SMP) bus operating at 20 GB / s, 30 GB / s, 120 GB / s, or more. Alternatively, similar protocols / links may be used (e.g., via a common interconnect fabric) to accomplish this. Fig.17A All communications between the various system components shown in .

[0307] In at least one embodiment, each multi-core processor 1705 is communicatively coupled to processor memory 1701(1)-1701(M) via memory interconnects 1726(1)-1726(M), respectively, and each GPU 1710(1)-1710(N) is communicatively coupled to GPU memory 1720(1)-1720(N) via GPU memory interconnects 1750(1)-1750(N), respectively. In at least one embodiment, memory interconnects 1726 and 1750 may utilize similar or different memory access technologies. By way of example and not limitation, processor memory 1701(1)-1701(M) and GPU memory 1720 may be volatile memory, such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or may be non-volatile memory, such as 3D XPoint or Nano-Ram. In at least one embodiment, some portion of the processor memory 1701 may be volatile memory while another portion may be non-volatile memory (eg, using a two-level memory (2LM) hierarchy).

[0308] As described herein, although each multi-core processor 1705 and GPU 1710 may be physically coupled to a specific memory 1701, 1720, respectively, and / or a unified memory architecture may be implemented in which a virtual system address space (also referred to as an "effective address" space) is distributed among the various physical memories. For example, processor memories 1701(1)-1701(M) may each include 64GB of system memory address space, and GPU memories 1720(1)-1720(N) may each include 32GB of system memory address space, resulting in a total of 256GB of addressable memory when M=2 and N=4. Other values ​​of N and M are possible.

[0309] Fig. 17B Additional details for the interconnection between the multi-core processor 1707 and the graphics acceleration module 1746 are shown according to an exemplary embodiment. In at least one embodiment, the graphics acceleration module 1746 may include one or more GPU chips integrated on a line card that is coupled to the processor 1707 via a high-speed link 1740 (e.g., PCIe bus, NVLink, etc.). In at least one embodiment, the graphics acceleration module 1746 may alternatively be integrated on a package or chip with the processor 1707.

[0310] In at least one embodiment, the processor 1707 includes a plurality of cores 1760A-1760D (which may be referred to as "execution units"), each core having a translation lookaside buffer ("TLB") 1761A-1761D and one or more caches 1762A-1762D. In at least one embodiment, the cores 1760A-1760D may include various other components not shown for executing instructions and processing data. In at least one embodiment, the caches 1762A-1762D may include level 1 (L1) and level 2 (L2) caches. In addition, one or more shared caches 1756 may be included in the caches 1762A-1762D and shared by each group of cores 1760A-1760D. For example, one embodiment of the processor 1707 includes 24 cores, each core having its own L1 cache, 12 shared L2 caches, and 12 shared L3 caches. In this embodiment, two adjacent cores share one or more L2 and L3 caches. In at least one embodiment, processor 1707 and graphics acceleration module 1746 are connected to system memory 1714, which may include Fig.17A Processor memory 1701(1)-1701(M) in.

[0311] In at least one embodiment, coherency is maintained for data and instructions stored in the various caches 1762A-1762D, 1756, and system memory 1714 via inter-core communications over coherency bus 1764. In at least one embodiment, for example, each cache may have cache coherency logic / circuitry associated therewith to communicate over coherency bus 1764 in response to detecting a read or write to a particular cache line. In at least one embodiment, a cache snooping protocol is implemented over coherency bus 1764 to snoop cache accesses.

[0312] In at least one embodiment, the proxy circuit 1725 communicatively couples the graphics acceleration module 1746 to the coherence bus 1764, thereby allowing the graphics acceleration module 1746 to participate in a cache coherence protocol as a peer of the cores 1760A-1760D. In particular, in at least one embodiment, the interface 1735 provides a connection to the proxy circuit 1725 via the high-speed link 1740, and the interface 1737 connects the graphics acceleration module 1746 to the high-speed link 1740.

[0313] In at least one embodiment, the accelerator integrated circuit 1736 provides cache management, memory access, context management and interrupt management services on behalf of the plurality of graphics processing engines 1731(1)-1731(N) of the graphics acceleration module 1746. In at least one embodiment, the graphics processing engines 1731(1)-1731(N) may each comprise a separate graphics processing unit (GPU). In at least one embodiment, the plurality of graphics processing engines 1731(1)-1731(N) of the graphics acceleration module 1746 may comprise, for example, a combination of Fig. 20A and Fig. 20B One or more graphics cores 2000 discussed. In at least one embodiment, graphics processing engines 1731(1)-1731(N) may alternatively include different types of graphics processing engines within a GPU, such as a graphics execution unit, a media processing engine (e.g., a video encoder / decoder), a sampler, and a blit engine. In at least one embodiment, graphics acceleration module 1746 may be a GPU having multiple graphics processing engines 1731(1)-1731(N), or graphics processing engines 1731(1)-1731(N) may be individual GPUs integrated on a common package, line card, or chip.

[0314] In at least one embodiment, the accelerator integrated circuit 1736 includes a memory management unit (MMU) 1739 for performing various memory management functions, such as virtual to physical memory translation (also known as effective to real memory translation), and a memory access protocol for accessing system memory 1714. In at least one embodiment, the MMU 1739 may also include a translation lookaside buffer ("TLB") (not shown) for caching virtual / effective to physical / real address translations. In at least one embodiment, the cache 1738 may store commands and data for efficient access by the graphics processing engines 1731(1)-1731(N). In at least one embodiment, the data stored in the cache 1738 and graphics memory 1733(1)-1733(M) may be kept consistent with the core caches 1762A-1762D, 1756, and system memory 1714, possibly using a fetch unit 1744. As previously described, this can be implemented on behalf of cache 1738 and memory 1733(1)-1733(M) via proxy circuit 1725 (e.g., sending updates related to modifications / accesses of cache lines on processor caches 1762A-1762D, 1756 to cache 1738 and receiving updates from cache 1738).

[0315] In at least one embodiment, a set of registers 1745 stores context data for threads executed by graphics processing engines 1731(1)-1731(N), and context management circuitry 1748 manages thread contexts. For example, context management circuitry 1748 may perform save and restore operations to save and restore contexts for various threads during context switches (e.g., where a first thread is saved and a second thread is stored so that the second thread can be executed by the graphics processing engine). For example, context management circuitry 1748 may store current register values ​​to a specified area in memory (e.g., identified by a context pointer) upon context switching. The register values ​​may then be restored upon returning to the context. In at least one embodiment, interrupt management circuitry 1747 receives and processes interrupts received from system devices.

[0316] In at least one embodiment, the MMU 1739 converts virtual / effective addresses from the graphics processing engine 1731 to real / physical addresses in the system memory 1714. In at least one embodiment, the accelerator integrated circuit 1736 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 1746 and / or other accelerator devices. In at least one embodiment, the graphics accelerator module 1746 can be dedicated to a single application executing on the processor 1707, or can be shared among multiple applications. In at least one embodiment, a virtualized graphics execution environment is presented in which the resources of the graphics processing engines 1731 (1)-1731 (N) are shared with multiple applications or virtual machines (VMs). In at least one embodiment, the resources can be subdivided into "slices" that are allocated to different VMs and / or applications based on the processing requirements and priorities associated with the VMs and / or applications.

[0317] In at least one embodiment, accelerator integrated circuit 1736 performs as a bridge to the system of graphics acceleration modules 1746 and provides address translation and system memory cache services. In addition, in at least one embodiment, accelerator integrated circuit 1736 can provide virtualization facilities for the host processor to manage virtualization, interrupts, and memory management of graphics processing engines 1731(1)-1731(N).

[0318] In at least one embodiment, since the hardware resources of graphics processing engines 1731(1)-1731(N) are explicitly mapped into the real address space seen by host processor 1707, any host processor can directly address these resources using effective address values. In at least one embodiment, one function of accelerator integrated circuit 1736 is the physical separation of graphics processing engines 1731(1)-1731(N) so that they appear to the system as independent units.

[0319] In at least one embodiment, one or more graphics memories 1733(1)-1733(M) are coupled to each graphics processing engine 1731(1)-1731(N), respectively, and N=M. In at least one embodiment, graphics memories 1733(1)-1733(M) store instructions and data being processed by each graphics processing engine 1731(1)-1731(N). In at least one embodiment, graphics memories 1733(1)-1733(M) may be volatile memory, such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or may be non-volatile memory, such as 3D XPoint or Nano-Ram.

[0320] In at least one embodiment, to reduce data traffic on high-speed link 1740, biasing techniques may be used to ensure that data stored in graphics memory 1733(1)-1733(M) is data that is most frequently used by graphics processing engines 1731(1)-1731(N), and preferably data that is not used (at least not frequently) by cores 1760A-1760D. Similarly, in at least one embodiment, the biasing mechanism attempts to keep data that is needed by the cores (and preferably not needed by graphics processing engines 1731(1)-1731(N)) in caches 1762A-1762D, 1756, and system memory 1714.

[0321] Fig. 17C Another exemplary embodiment is shown in which an accelerator integrated circuit 1736 is integrated within the processor 1707. In this embodiment, the graphics processing engines 1731(1)-1731(N) communicate directly with the accelerator integrated circuit 1736 via interface 1737 and interface 1735 (again, which can be any form of bus or interface protocol) over a high-speed link 1740. In at least one embodiment, the accelerator integrated circuit 1736 can perform operations related to Fig. 17B The operations described above are similar to the operations described above, but may have higher throughput due to its close proximity to the coherent bus 1764 and caches 1762A-1762D, 1756. In at least one embodiment, the accelerator integrated circuit supports different programming models, including a process-specific programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization), which may include a programming model controlled by the accelerator integrated circuit 1736 and a programming model controlled by the graphics acceleration module 1746.

[0322] In at least one embodiment, graphics processing engines 1731(1)-1731(N) are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application can funnel other application requests to graphics processing engines 1731(1)-1731(N), thereby providing virtualization within a VM / partition.

[0323] In at least one embodiment, graphics processing engines 1731(1)-1731(N) can be shared by multiple VM / application partitions. In at least one embodiment, the sharing model can use a system hypervisor to virtualize graphics processing engines 1731(1)-1731(N) to allow each operating system to access. In at least one embodiment, for a single partition system without a hypervisor, the operating system owns graphics processing engines 1731(1)-1731(N). In at least one embodiment, the operating system can virtualize graphics processing engines 1731(1)-1731(N) to provide access to each process or application.

[0324] In at least one embodiment, the graphics acceleration module 1746 or individual graphics processing engines 1731(1)-1731(N) uses a process handle to select a process element. In at least one embodiment, the process element is stored in the system memory 1714 and can be addressed using the effective address to real address translation techniques described herein. In at least one embodiment, the process handle can be an implementation-specific value that is provided to the host process when registering its context with the graphics processing engine 1731(1)-1731(N) (i.e., calling system software to add the process element to the process element linked list). In at least one embodiment, the lower 16 bits of the process handle can be the offset of the process element in the process element linked list.

[0325] Fig.17D An exemplary accelerator integrated slice 1790 is shown. In at least one embodiment, a "slice" comprises a designated portion of the processing resources of the accelerator integrated circuit 1736. In at least one embodiment, the application is an effective address space 1782 in the system memory 1714, which stores a process element 1783. In at least one embodiment, the process element 1783 is stored in response to a GPU call 1781 from an application 1780 executing on the processor 1707. In at least one embodiment, the process element 1783 contains the process state of the corresponding application 1780. In at least one embodiment, the work descriptor (WD) 1784 contained in the process element 1783 can be a single job requested by the application, or can contain a pointer to a job queue. In at least one embodiment, the WD 1784 is a pointer to a job request queue in the effective address space 1782 of the application.

[0326] In at least one embodiment, the graphics acceleration module 1746 and / or the individual graphics processing engines 1731(1)-1731(N) can be shared by all processes or a subset of processes in the system. In at least one embodiment, infrastructure for setting process state and sending WD 1784 to the graphics acceleration module 1746 to start a job in a virtualized environment can be included.

[0327] In at least one embodiment, the process-specific programming model is implementation specific. In at least one embodiment, in this model, a single process owns a graphics acceleration module 1746 or an individual graphics processing engine 1731. In at least one embodiment, when the graphics acceleration module 1746 is owned by a single process, the hypervisor initializes the accelerator integrated circuit for the owned partition, and when the graphics acceleration module 1746 is assigned, the operating system initializes the accelerator integrated circuit 1736 for the owned process.

[0328] In operation, in at least one embodiment, a WD acquisition unit 1791 in the accelerator integrated slice 1790 acquires a next WD 1784, which includes an indication of work to be completed by one or more graphics processing engines of the graphics acceleration module 1746. In at least one embodiment, data from the WD 1784 may be stored in registers 1745 and used by the MMU 1739, interrupt management circuitry 1747, and / or context management circuitry 1748, as shown. For example, one embodiment of the MMU 1739 includes a segment / page walk circuit for accessing a segment / page table 1786 within the OS virtual address space 1785. In at least one embodiment, the interrupt management circuitry 1747 may process an interrupt event 1792 received from the graphics acceleration module 1746. In at least one embodiment, when performing graphics operations, effective addresses 1793 generated by the graphics processing engines 1731(1)-1731(N) are converted to real addresses by the MMU 1739.

[0329] In at least one embodiment, registers 1745 are replicated for each graphics processing engine 1731(1)-1731(N) and / or graphics acceleration module 1746 and can be initialized by a hypervisor or operating system. In at least one embodiment, each of these replicated registers can be included in an accelerator integrated slice 1790. Exemplary registers that can be initialized by a hypervisor are shown in Table 1.

[0330] Table 1 - Registers initialized by the hypervisor

[0331]

[0332] Example registers that may be initialized by the operating system are shown in Table 2.

[0333] Table 2 - Registers initialized by the operating system

[0334]

[0335] In at least one embodiment, each WD 1784 is specific to a particular graphics acceleration module 1746 and / or graphics processing engine 1731(1)-1731(N). In at least one embodiment, it contains all the information needed by the graphics processing engine 1731(1)-1731(N) to complete the work, or it can be a pointer to a memory location where the application has set up a command queue for the work to be done.

[0336] Fig.17E Additional details of an exemplary embodiment of a sharing model are shown. This embodiment includes a hypervisor real address space 1798 in which a process element list 1799 is stored. In at least one embodiment, the hypervisor real address space 1798 can be accessed via a hypervisor 1796 that virtualizes a graphics acceleration module engine for an operating system 1795.

[0337] In at least one embodiment, the shared programming model allows all processes or subsets of processes from all partitions or subsets of partitions in the system to use the graphics acceleration module 1746. In at least one embodiment, there are two programming models where the graphics acceleration module 1746 is shared by multiple processes and partitions, mid-run slice sharing and graphics-directed sharing.

[0338] In at least one embodiment, in this model, the hypervisor 1796 owns the graphics acceleration module 1746 and makes its functionality available to all operating systems 1795. In at least one embodiment, for the graphics acceleration module 1746 to support virtualization through the hypervisor 1796, the graphics acceleration module 1746 may comply with certain requirements, such as (1) the application's job request must be autonomous (i.e., no state needs to be maintained between jobs), or the graphics acceleration module 1746 must provide a context save and restore mechanism, (2) the graphics acceleration module 1746 guarantees that the application's job request is completed within a specified amount of time, including any transition errors, or the graphics acceleration module 1746 provides the ability to preempt job processing, and (3) when operating in a directed shared programming model, the graphics acceleration module 1746 must ensure fairness between processes.

[0339] In at least one embodiment, the application 1780 is required to make an operating system 1795 system call using a graphics acceleration module type, a work descriptor (WD), an authority mask register (AMR) value, and a context save / restore region pointer (CSRP). In at least one embodiment, the graphics acceleration module type describes the target acceleration function for the system call. In at least one embodiment, the graphics acceleration module type can be a system-specific value. In at least one embodiment, the WD is formatted specifically for the graphics acceleration module 1746 and can take the form of a graphics acceleration module 1746 command, an effective address pointer to a user-defined structure, an effective address pointer to a command queue, or any other data structure that describes the work to be done by the graphics acceleration module 1746.

[0340] In at least one embodiment, the AMR value is the AMR state for the current process. In at least one embodiment, the value passed to the operating system is similar to the application that sets the AMR. In at least one embodiment, if the implementation of the accelerator integrated circuit 1736 (not shown) and the graphics acceleration module 1746 does not support the user authority mask overwrite register (UAMOR), the operating system can apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. In at least one embodiment, the hypervisor 1796 can selectively apply the current authority mask overwrite register (AMOR) value before placing the AMR in the process element 1783. In at least one embodiment, the CSRP is one of the registers 1745, which contains the effective address of the area in the effective address space 1782 of the application for the graphics acceleration module 1746 to save and restore the context state. In at least one embodiment, if it is not necessary to save the state between jobs or when the job is preempted, the pointer is optional. In at least one embodiment, the context save / restore area can be a fixed system memory.

[0341] Upon receiving the system call, the operating system 1795 can verify that the application 1780 has been registered and granted permission to use the graphics acceleration module 1746. Then, in at least one embodiment, the operating system 1795 calls the hypervisor 1796 using the information shown in Table 3.

[0342] Table 3 - OS to hypervisor call parameters

[0343]

[0344] In at least one embodiment, upon receiving the hypervisor call, hypervisor 1796 verifies that operating system 1795 has registered and been granted permission to use graphics acceleration module 1746. Then, in at least one embodiment, hypervisor 1796 places process element 1783 into a linked list of process elements of the corresponding graphics acceleration module 1746 type. In at least one embodiment, the process element may include the information shown in Table 4.

[0345] Table 4 - Process element information

[0346]

[0347] In at least one embodiment, the hypervisor initializes the plurality of accelerator integrated slices 1790 registers 1745 .

[0348] like Fig.17F As shown, in at least one embodiment, a unified memory is used, which is addressable via a common virtual memory address space for accessing physical processor memory 1701(1)-1701(N) and GPU memory 1720(1)-1720(N). In this implementation, operations executed on GPUs 1710(1)-1710(N) utilize the same virtual / effective memory address space to access processor memory 1701(1)-1701(M), and vice versa, thereby simplifying programmability. In at least one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 1701(1), a second portion is allocated to second processor memory 1701(N), a third portion is allocated to GPU memory 1720(1), and so on. In at least one embodiment, the entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed across each of processor memory 1701 and GPU memory 1720, thereby allowing any processor or GPU to access that memory using a virtual address mapped to any physical memory.

[0349] In at least one embodiment, bias / coherency management circuits 1794A-1794E within one or more MMUs 1739A-1739E ensure cache coherency between caches of one or more host processors (e.g., 1705) and GPU 1710 and implement biasing techniques that indicate physical memory where certain types of data should be stored. Fig.17F Multiple instances of bias / consistency management circuits 1794A- 1794E are shown in , but bias / consistency circuits may be implemented within an MMU of one or more host processors 1705 and / or within an accelerator integrated circuit 1736 .

[0350] One embodiment allows GPU memory 1720 to be mapped as part of system memory and accessed using shared virtual memory (SVM) technology, but without suffering the performance drawbacks associated with full system cache coherence. In at least one embodiment, the ability of GPU memory 1720 to be accessed as system memory without heavy cache coherence overhead provides a favorable operating environment for GPU offloading. In at least one embodiment, the arrangement allows software of host processor 1705 to set operands and access calculation results without the overhead of traditional I / O DMA data copying. In at least one embodiment, such traditional copying includes driver calls, interrupts, and memory mapped I / O (MMIO) accesses, which are all less efficient than simple memory accesses. In at least one embodiment, the ability to access GPU memory 1720 without cache coherence overhead may be critical to the execution time of offloaded calculations. In at least one embodiment, for example, in the case of a large amount of streaming write memory traffic, cache coherence overhead can significantly reduce the effective write bandwidth seen by GPU 1710. In at least one embodiment, the efficiency of operand setting, the efficiency of result access, and the efficiency of GPU calculation may play a role in determining the effectiveness of GPU offloading.

[0351] In at least one embodiment, the selection of GPU bias and host processor bias is driven by a bias tracker data structure. In at least one embodiment, for example, a bias table can be used, which can be a page granular structure (e.g., controlled at the granularity of a memory page) that includes 1 or 2 bits of memory page per GPU addition. In at least one embodiment, with or without a bias cache in GPU 1710 (e.g., for caching frequently / recently used entries of the bias table), the bias table can be implemented in a stolen memory range of one or more GPU memories 1720. Alternatively, in at least one embodiment, the entire bias table can be maintained within the GPU.

[0352] In at least one embodiment, the bias table entry associated with each access to the GPU attached memory 1720 is accessed before the GPU memory is actually accessed, resulting in the following operations. In at least one embodiment, local requests from GPU 1710 that find their pages in the GPU bias are forwarded directly to the corresponding GPU memory 1720. In at least one embodiment, local requests from the GPU that find their pages in the host bias are forwarded to the processor 1705 (e.g., via the high-speed link described herein). In at least one embodiment, the request from the processor 1705 to find the requested page in the host processor bias completes a request similar to a normal memory read. Alternatively, a request directed to a GPU bias page can be forwarded to the GPU 1710. In at least one embodiment, if the GPU is not currently using the page, the GPU can migrate the page to the host processor bias. In at least one embodiment, the bias state of a page can be changed by a software-based mechanism, a hardware-assisted software-based mechanism, or a purely hardware-based mechanism in a limited set of cases.

[0353] In at least one embodiment, a mechanism for changing the bias state employs an API call (e.g., OpenCL) that in turn calls the GPU's device driver, which in turn sends a message (or queues a command descriptor) to the GPU, directing the GPU to change the bias state and, in certain migrations, perform a cache flush operation in the host. In at least one embodiment, the cache flush operation is used for migrations from host processor 1705 bias to GPU bias, but not for the reverse migration.

[0354] In at least one embodiment, cache coherence is maintained by temporarily rendering GPU biased pages that cannot be cached by host processor 1705. In at least one embodiment, to access these pages, processor 1705 may request access from GPU 1710, which may or may not immediately grant access. Therefore, in at least one embodiment, to reduce communication between processor 1705 and GPU 1710, it is beneficial to ensure that GPU biased pages are pages required by the GPU and not by the host processor 1705, and vice versa.

[0355] One or more hardware structures 915 are used to implement one or more embodiments. Fig. 9A and / or Fig. 9B Details regarding one or more hardware structures 915 are provided.

[0356] Figures 17A-17F The logic and hardware structure can be integrated into Figure 1-8In the system and processor disclosed in. For example, Figures 17A-17F The logic / hardware structure in can perform at least part or all of process 300, 400 and / or 500. In at least one embodiment, Figures 17A-17F The system or apparatus disclosed in causes a processor to identify one or more locations of one or more objects in one or more images based at least in part on one or more locations of one or more objects in one or more previous images. In at least one embodiment, by performing at least part or all of processes 300, 400, and / or 500, a processor including one or more circuits divides one or more images into one or more segments and stores in a memory an indication of which of the one or more segments contain one or more identified locations of one or more objects. In at least one embodiment, by performing at least part or all of processes 300, 400, and / or 500, Figures 17A-17F The system or apparatus disclosed in causes a processor to combine one or more positions of one or more objects to generate a region of interest.

[0357] Fig.18 An exemplary integrated circuit and associated graphics processor according to various embodiments described herein are shown, which can be manufactured using one or more IP cores. In addition to the illustrated, other logic and circuits may also be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0358] Fig.18 1800 is a block diagram illustrating an exemplary system on a chip integrated circuit 1800 that can be manufactured using one or more IP cores according to at least one embodiment. In at least one embodiment, the integrated circuit 1800 includes one or more application processors 1805 (e.g., CPU), at least one graphics processor 1810, and may additionally include an image processor 1815 and / or a video processor 1820, any of which may be a modular IP core. In at least one embodiment, the integrated circuit 1800 includes peripheral or bus logic, which includes a USB controller 1825, a UART controller 1830, an SPI / SDIO controller 1835, and an I 2 S / I 2C controller 1840. In at least one embodiment, the integrated circuit 1800 may include a display device 1845 coupled to one or more of a High Definition Multimedia Interface (HDMI) controller 1850 and a Mobile Industry Processor Interface (MIPI) display interface 1855. In at least one embodiment, storage may be provided by a flash memory subsystem 1860, which includes flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 1865 for accessing SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits also include an embedded security engine 1870.

[0359] Logic 915 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 9A and / or Fig. 9B Details are provided regarding logic 915. In at least one embodiment, logic 915 may be used in integrated circuit 1800 to infer or predict operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0360] Fig.18 The logic and hardware structure can be integrated into Figure 1-8 In the system and processor disclosed in. For example, Fig.18 The logic / hardware structure in can perform at least part or all of process 300, 400 and / or 500. In at least one embodiment, Fig.18 The system or apparatus disclosed in causes a processor to identify one or more locations of one or more objects in one or more images based at least in part on one or more locations of one or more objects in one or more previous images. In at least one embodiment, by performing at least part or all of processes 300, 400, and / or 500, a processor including one or more circuits divides one or more images into one or more segments and stores in a memory an indication of which of the one or more segments contain one or more identified locations of one or more objects. In at least one embodiment, by performing at least part or all of processes 300, 400, and / or 500, Fig.18 The system or apparatus disclosed in causes a processor to combine one or more positions of one or more objects to generate a region of interest.

[0361] Fig.19A and Fig.19BAn exemplary integrated circuit and associated graphics processor according to various embodiments described herein are shown, which can be manufactured using one or more IP cores. In addition to the illustrated, other logic and circuits may be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0362] Fig.19A and Fig.19B is a block diagram illustrating an exemplary graphics processor for use within a SoC according to embodiments described herein. Fig.19A An exemplary graphics processor 1910 of a system-on-chip integrated circuit is shown, which may be manufactured using one or more IP cores, in accordance with at least one embodiment. Fig.19B An additional exemplary graphics processor 1940 of a system-on-chip integrated circuit is shown, which may be manufactured using one or more IP cores, according to at least one embodiment. In at least one embodiment, Fig.19A The graphics processor 1910 is a low power graphics processor core. In at least one embodiment, Fig.19B The graphics processor 1940 of FIG. 19 is a higher performance graphics processor core. In at least one embodiment, each graphics processor 1910, 1940 may be a variation of the graphics processor 1910 of FIG. 19.

[0363] In at least one embodiment, the graphics processor 1910 includes a vertex processor 1905 and one or more fragment processors 1915A-1915N (e.g., 1915A, 1915B, 1915C, 1915D to 1915N-1 and 1915N). In at least one embodiment, the graphics processor 1910 can execute different shader programs via separate logic, so that the vertex processor 1905 is optimized to perform operations for the vertex shader program, while one or more fragment processors 1915A-1915N perform fragment (e.g., pixel) shading operations for fragment or pixel shader programs. In at least one embodiment, the vertex processor 1905 performs the vertex processing stage of the 3D graphics pipeline and generates primitives and vertex data. In at least one embodiment, the one or more fragment processors 1915A-1915N use the primitives and vertex data generated by the vertex processor 1905 to generate a frame buffer displayed on a display device. In at least one embodiment, one or more fragment processors 1915A-1915N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform similar operations as pixel shader programs provided in the Direct 3D API.

[0364] In at least one embodiment, graphics processor 1910 additionally includes one or more memory management units (MMUs) 1920A-1920B, one or more caches 1925A-1925B, and one or more circuit interconnects 1930A-1930B. In at least one embodiment, one or more MMUs 1920A-1920B provide virtual to physical address mapping for graphics processor 1910 (including for vertex processor 1905 and / or fragment processors 1915A-1915N), which can reference vertex or image / texture data stored in memory in addition to vertex or image / texture data stored in one or more caches 1925A-1925B. In at least one embodiment, one or more MMUs 1920A-1920B can be synchronized with other MMUs within the system, including one or more MMUs associated with one or more application processors 1905, image processor 1915, and / or video processor 1920 of FIG. 19, so that each processor 1905-1920 can participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1930A-1930B enable graphics processor 1910 to interface with other IP cores within the SoC via an internal bus of the SoC or via a direct connection.

[0365] In at least one embodiment, graphics processor 1940 includes: Fig.19B One or more shader cores 1955A-1955N (e.g., 1955A, 1955B, 1955C, 1955D, 1955E, 1955F to 1955N-1 and 1955N) are shown, which provide a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, the graphics processor 1940 includes an inter-core task manager 1945 that acts as a thread dispatcher for dispatching execution threads to one or more shader cores 1955A-1955N and a tiling unit 1958 to accelerate tiling operations for tile-based rendering, in which rendering operations of a scene are subdivided in image space, for example, to exploit local spatial coherence within a scene or to optimize the use of internal caches.

[0366] Logic 915 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 9A and / or Fig. 9BDetails are provided regarding logic 915. In at least one embodiment, logic 915 may be used in an integrated circuit of graphics processors 1910 and / or 1940 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0367] Fig.19A and Fig.19B The logic and hardware structure can be integrated into Figure 1-8 In the system and processor disclosed in. For example, Fig.19A and Fig.19B The logic / hardware structure in can perform at least part or all of process 300, 400 and / or 500. In at least one embodiment, Fig.19A and Fig.19B The system or apparatus disclosed in causes a processor to identify one or more locations of one or more objects in one or more images based at least in part on one or more locations of one or more objects in one or more previous images. In at least one embodiment, by performing at least part or all of processes 300, 400, and / or 500, a processor including one or more circuits divides one or more images into one or more segments and stores in a memory an indication of which of the one or more segments contain one or more identified locations of one or more objects. In at least one embodiment, by performing at least part or all of processes 300, 400, and / or 500, Fig.19A and Fig.19B The system or apparatus disclosed in causes a processor to combine one or more positions of one or more objects to generate a region of interest.

[0368] Fig. 20A and Fig. 20B Additional exemplary graphics processor logic according to embodiments described herein is shown. In at least one embodiment, in conjunction with Fig. 20A and Fig. 20B The components shown and described are integrated into a single system, such as a graphics processing unit (GPU), SoC, or another type of processor. In at least one embodiment, Fig. 20A shows that it can be included in Fig.18 The graphics core 2000 within the graphics processor 1810 of FIG. 1800 and, in at least one embodiment, may be as follows: Fig.19B Unified shader cores 1955A-1955N are shown. Fig. 20BA highly parallel general purpose graphics processing unit ("GPGPU", which may also be referred to as a "graphics processing unit") 2030 suitable for deployment on a multi-chip module in at least one embodiment is shown. In at least one embodiment, the graphics processing unit 2030 is a GPGPU including a graphics processor. In at least one embodiment, the integrated circuit 1800 includes the graphics core 2000, for example, for forming an integrated circuit and / or for forming a SoC, wherein such an integrated circuit and / or such a SoC performs the operations described herein.

[0369] In at least one embodiment, graphics core 2000 includes a shared instruction cache 2002, texture unit 2018, and cache / shared memory 2020 (e.g., including L1, L2, L3, last level cache, or other caches) that are common to execution resources within graphics core 2000. In at least one embodiment, graphics core 2000 may include multiple slices 2001A-2001N or partitions of each core, and the graphics processor may include multiple instances of graphics core 2000. In at least one embodiment, each slice 2001A-2001N refers to graphics core 2000. In at least one embodiment, slices 2001A-2001N have multiple sub-slices that are part of slices 2001A-2001N. In at least one embodiment, slices 2001A-2001N are independent of other slices or dependent on other slices. In at least one embodiment, the slices 2001A-2001N may include support logic including a local instruction cache 2004A-2004N, a thread scheduler (sequencer) 2006A-2006N, a thread dispatcher 2008A-2008N, and a set of registers 2010A-2010N. In at least one embodiment, the slices 2001A-2001N may include a set of additional function units (AFU 2012A-2012N), floating point units (FPU 2014A-2014N), integer arithmetic logic units (ALU 2016A-2016N), address calculation units (ACU 2013A-2013N), double precision floating point units (DPFPU 2015A-2015N), and matrix processing units (MPU 2017A-2017N). In at least one embodiment, the MPU 2017A-2017N is referred to as a matrix engine.

[0370] In at least one embodiment, each slice 2001A-2001N includes one or more engines for floating point and integer vector operations and one or more engines for accelerating convolution and matrix operations in AI, machine learning or large data set workloads. In at least one embodiment, one or more slices 2001A-2001N include one or more vector engines for calculating vectors (e.g., calculating mathematical operations of vectors). In at least one embodiment, the vector engine can calculate vector operations in 16-bit floating point (also known as "FP16"), 32-bit floating point (also known as "FP32"), or 64-bit floating point (also known as "FP64"). In at least one embodiment, one or more slices 2001A-2001N include 16 vector engines, which are paired with 16 matrix math units to calculate matrix / tensor operations, where the vector engines and math units are displayed through matrix expansion. In at least one embodiment, a slice of a specified portion of the processing resources of a processing unit (e.g., 16 cores and a ray tracing unit or 8 cores), a thread scheduler, a thread dispatcher, and additional functional units for the processor. In at least one embodiment, graphics core 2000 includes one or more matrix engines for computing matrix operations, such as when computing tensor operations.

[0371] In at least one embodiment, one or more slices 2001A-2001N include one or more ray tracing units (e.g., 16 ray tracing units per slice 2001A-2001N) for computing ray tracing operations. In at least one embodiment, the ray tracing units compute ray traversals, triangle intersections, bounding box intersections, or other ray tracing operations.

[0372] In at least one embodiment, one or more slices 2001A-2001N include a media slice that encodes, decodes, and / or transcodes data; scales and / or format converts data; and / or performs video quality operations on video data.

[0373] In at least one embodiment, one or more slices 2001A-2001N are linked to L2 cache and memory structures, link connectors, high bandwidth memory (HBM) (e.g., HBM2e, HDM3) stacks, and media engines. In at least one embodiment, one or more slices 2001A-2001N include multiple cores (e.g., 16 cores) and multiple ray tracing units (e.g., 16) paired with each core. In at least one embodiment, one or more slices 2001A-2001N have one or more L1 caches. In at least one embodiment, one or more slices 2001A-2001N include one or more vector engines; one or more instruction caches for storing instructions; one or more L1 caches for caching data; one or more shared local memories (SLMs) for storing, for example, data corresponding to instructions; one or more samplers for sampling data; one or more ray tracing units for performing ray tracing operations; one or more geometry units for performing operations in a geometry pipeline and / or applying geometry transformations to vertices or polygons; one or more rasterizers for describing an image in a vector graphics format (e.g., a shape) and converting it into a raster image (e.g., a series of pixels, points, or lines that, when displayed together, create an image represented by the shape); one or more hierarchical depth buffers (Hiz) for caching data; and / or one or more pixel backends. In at least one embodiment, slices 2001A-2001N include memory structures, such as an L2 cache.

[0374] In at least one embodiment, the FPU 2014A-2014N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while the DPFPU 2015A-2015N performs double-precision (64-bit) floating-point operations. In at least one embodiment, the ALU 2016A-2016N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed-precision operations. In at least one embodiment, the MPU 2017A-2017N can also be configured for mixed-precision matrix operations, including half-precision floating-point operations and 8-bit integer operations. In at least one embodiment, the MPU 2017A-2017N can perform various matrix operations to accelerate the machine learning application framework, including enabling general matrix-to-matrix multiplication (GEMM) that supports acceleration. In at least one embodiment, the AFU 2012A-2012N can perform additional logical operations that are not supported by the floating-point unit or integer unit, including trigonometric operations (e.g., sine, cosine, etc.).

[0375] Logic 915 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 9A and / or Fig. 9B Details are provided regarding logic 915. In at least one embodiment, logic 915 may be used in graphics core 2000 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0376] In at least one embodiment, graphics core 2000 includes an interconnect and link fabric sublayer attached to a switch and a GPU-GPU bridge that enables multiple graphics processors 2000 (e.g., 8) to interconnect without being attached to each other through load / store units (LSUs), data transfer units, and synchronization semantics of multiple graphics processors 2000. In at least one embodiment, the interconnect includes a standardized interconnect (e.g., PCIe) or some combination thereof.

[0377] In at least one embodiment, the graphics core 2000 includes a plurality of tiles. In at least one embodiment, a tile is an individual die or one or more dies, wherein the individual dies may be connected using an interconnect (e.g., an embedded multi-die interconnect bridge (EMIB)). In at least one embodiment, the graphics core 2000 includes a computing tile, a memory tile (e.g., wherein the memory tile may be exclusively accessed by different tiles or different chipsets (such as Rambo tiles)), a substrate tile, a base tile, an HMB tile, a link tile, and an EMIB tile, wherein all tiles are packaged together in the graphics core 2000 as part of a GPU. In at least one embodiment, the graphics core 2000 may include a plurality of tiles in a single package (also referred to as a "multi-tile package"). In at least one embodiment, a computing tile may have 8 graphics cores 2000, an L1 cache; and a base tile may have a host interface with PCIe 5.0, HBM2e, MDFI, and EMIB, and a link tile has 8 links and 8 ports with an embedded switch. In at least one embodiment, each tile is connected using fine pitch 36 micron micro bumps (e.g., copper pillars) with face-to-face (F2F) chip-on-chip bonding. In at least one embodiment, the graphics core 2000 includes a memory structure (the memory structure includes memory) and is a tile accessible by multiple tiles. In at least one embodiment, the graphics core 2000 stores, accesses, or loads its own hardware context into memory, where the hardware context is a set of data loaded from registers before a process resumes, and where the hardware context can indicate the state of the hardware (e.g., the state of the GPU).

[0378] In at least one embodiment, graphics core 2000 includes serializer / deserializer (SERDES) circuitry that converts a serial data stream to a parallel data stream, or converts a parallel data stream to a serial data stream.

[0379] In at least one embodiment, graphics core 2000 includes a high-speed coherent unified fabric (GPU to GPU), load / store units, bulk data transfer and synchronization semantics, and GPUs connected via an embedded switch, where the GPU-GPU bridge is controlled by a controller.

[0380] In at least one embodiment, graphics core 2000 executes an API that abstracts the hardware of graphics core 2000 and uses instructions to access libraries to perform mathematical operations (e.g., math kernel libraries), deep neural network operations (e.g., deep neural network libraries), vector operations, collective communications, thread building blocks, video processing, data analysis libraries, and / or ray tracing operations.

[0381] Fig. 20B A GPGPU 2030 according to at least one embodiment is shown, which can be configured to enable highly parallel computing operations to be performed by an array of graphics processing units. In at least one embodiment, GPGPU 2030 can be directly linked to other instances of GPGPU 2030 to create a multi-GPU cluster to increase the training speed for deep neural networks. In at least one embodiment, GPGPU 2030 includes a host interface 2032 for connecting to a host processor. In at least one embodiment, host interface 2032 is a PCI Express interface. In at least one embodiment, host interface 2032 can be a manufacturer-specific communication interface or communication structure. In at least one embodiment, GPGPU 2030 receives commands from a host processor and uses a global scheduler 2034 (which can be referred to as a thread sequencer and / or asynchronous computing engine) to assign execution threads associated with those commands to a group of computing clusters 2036A-2036H. In at least one embodiment, computing clusters 2036A-2036H share cache memory 2038. In at least one embodiment, cache memory 2038 may be used as a higher level cache for cache memory within computing clusters 2036A-2036H. In at least one embodiment, computing clusters 2036A-2036H include slices or are referred to as "slices". In at least one embodiment, GPGPU 2030 is part of a SoC, such as part of integrated circuit 1800 ( Fig.18 ).

[0382] In at least one embodiment, GPGPU 2030 includes memory 2044A-2044B coupled to compute cluster 2036A-2036H via a set of memory controllers 2042A-2042B (e.g., one or more controllers for HBM2e). In at least one embodiment, memory 2044A-2044B may include various types of memory devices including dynamic random access memory (DRAM) or graphics random access memory such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory.

[0383] In at least one embodiment, computing clusters 2036A-2036H each include a set of graphics cores, such as Fig. 20A The graphics core 2000 may include multiple types of integer and floating point logic units that can perform computational operations over a range of precisions including those suitable for machine learning computations. For example, in at least one embodiment, at least a subset of the floating point units in each computing cluster 2036A-2036H may be configured to perform 16-bit or 32-bit floating point operations, while a different subset of the floating point units may be configured to perform 64-bit floating point operations.

[0384] In at least one embodiment, multiple instances of GPGPU 2030 may be configured to operate as a computing cluster. In at least one embodiment, the communications used by computing clusters 2036A-2036H for synchronization and data exchange vary between embodiments. In at least one embodiment, multiple instances of GPGPU 2030 communicate through host interface 2032. In at least one embodiment, GPGPU 2030 includes an I / O hub 2039 that couples GPGPU 2030 with a GPU link 2040 that enables direct connection to other instances of GPGPU 2030. In at least one embodiment, GPU link 2040 is coupled to a dedicated GPU to GPU bridge that enables communication and synchronization between multiple instances of GPGPU 2030. In at least one embodiment, GPU link 2040 is coupled to a high-speed interconnect to send and receive data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 2030 are located in separate data processing systems and communicate via network devices accessible via host interface 2032. In at least one embodiment, GPU link 2040 may also be configured to enable connection to a host processor in addition to or in lieu of host interface 2032 .

[0385] In at least one embodiment, the GPGPU 2030 may be configured to train a neural network. In at least one embodiment, the GPGPU 2030 may be used within an inference platform. In at least one embodiment, when the GPGPU 2030 is used for inference, the GPGPU 2030 may include fewer computing clusters 2036A-2036H relative to when the GPGPU 2030 is used to train a neural network. In at least one embodiment, the memory technology associated with the memory 2044A-2044B may differ between the inference and training configurations, with higher bandwidth memory technology being dedicated to the training configuration. In at least one embodiment, the inference configuration of the GPGPU 2030 may support inference specific instructions. For example, in at least one embodiment, the inference configuration may provide support for one or more 8-bit integer dot product instructions that may be used during inference operations of a deployed neural network.

[0386] Logic 915 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 9A and / or Fig. 9B Details are provided regarding logic 915. In at least one embodiment, logic 915 may be used in GPGPU 2030 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0387] Fig. 20A and Fig. 20B The logic and hardware structure can be integrated into Figure 1-8 In the system and processor disclosed in. For example, Fig. 20A and Fig. 20B The logic / hardware structure in can perform at least part or all of process 300, 400 and / or 500. In at least one embodiment, Fig. 20A and Fig. 20B The system or apparatus disclosed in causes a processor to identify one or more locations of one or more objects in one or more images based at least in part on one or more locations of one or more objects in one or more previous images. In at least one embodiment, by performing at least part or all of processes 300, 400, and / or 500, a processor including one or more circuits divides one or more images into one or more segments and stores in a memory an indication of which of the one or more segments contain one or more identified locations of one or more objects. In at least one embodiment, by performing at least part or all of processes 300, 400, and / or 500, Fig. 20A and Fig. 20BThe system or apparatus disclosed in causes a processor to combine one or more positions of one or more objects to generate a region of interest.

[0388] Fig.21 2100 and a processor 2102 that communicates via an interconnect path that may include a memory hub 2105. In at least one embodiment, the memory hub 2105 may be a separate component within a chipset component or may be integrated within one or more processors 2102. In at least one embodiment, the memory hub 2105 is coupled to an I / O subsystem 2111 via a communication link 2106. In at least one embodiment, the I / O subsystem 2111 includes an I / O hub 2107 that may enable the computing system 2100 to receive input from one or more input devices 2108. In at least one embodiment, the I / O hub 2107 may enable a display controller that may be included in one or more processors 2102 to provide output to one or more display devices 2110A. In at least one embodiment, the one or more display devices 2110A coupled to the I / O hub 2107 may include local, internal, or embedded display devices.

[0389] In at least one embodiment, the processing subsystem 2101 includes one or more parallel processors 2112 coupled to the memory hub 2105 via a bus or other communication link 2113. In at least one embodiment, the communication link 2113 can use one of any number of standards based on communication link technology or protocol (such as but not limited to PCI Express), or can be a vendor-specific communication interface or communication structure. In at least one embodiment, the one or more parallel processors 2112 form a parallel or vector processing system in a computational concentration, which can include a large number of processing cores and / or processing clusters, such as an integrated many-core (MIC) processor. In at least one embodiment, some or all of the one or more parallel processors 2112 form a graphics processing subsystem, which can output pixels to one of the one or more display devices 2110A coupled via the I / O hub 2107. In at least one embodiment, the one or more parallel processors 2112 can also include a display controller and display interface (not shown) for enabling direct connection to one or more display devices 2110B. In at least one embodiment, the one or more parallel processors 2112 include one or more cores, such as the graphics core 2000 discussed herein.

[0390] In at least one embodiment, a system storage unit 2114 can be connected to the I / O hub 2107 to provide a storage mechanism for the computing system 2100. In at least one embodiment, an I / O switch 2116 can be used to provide an interface mechanism for enabling connections between the I / O hub 2107 and other components, such as a network adapter 2118 and / or a wireless network adapter 2119 that can be integrated into the platform, as well as various other devices that can be added via one or more additional devices 2120. In at least one embodiment, the network adapter 2118 can be an Ethernet adapter or another wired network adapter. In at least one embodiment, the wireless network adapter 2119 can include one or more of Wi-Fi, Bluetooth, near field communication (NFC), or other network devices including one or more radio devices.

[0391] In at least one embodiment, the computing system 2100 may include other components not explicitly shown that may also be connected to the I / O hub 2107, including USB or other port connections, optical storage drives, video capture devices, etc. In at least one embodiment, the interconnection may be implemented using any suitable protocol, such as a PCI (Peripheral Component Interconnect) based protocol (e.g., PCI-Express) or other bus or point-to-point communication interface and / or protocol (such as NV-Link high-speed interconnect or interconnect protocol). Fig.21 The communication paths between the components in the

[0392] In at least one embodiment, one or more parallel processors 2112 include circuits optimized for graphics and video processing, including, for example, video output circuits, and constitute a graphics processing unit (GPU), for example, one or more parallel processors 2112 include graphics core 2000. In at least one embodiment, one or more parallel processors 2112 include circuits optimized for general processing. In at least one embodiment, the components of the computing system 2100 can be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processors 2112, memory hub 2105, one or more processors 2102, and I / O hub 2107 can be integrated into a system-on-chip (SoC) integrated circuit. In at least one embodiment, the components of the computing system 2100 can be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of the computing system 2100 can be integrated into a multi-chip module (MCM), which can be interconnected with other multi-chip modules into a modular computing system.

[0393] Logic 915 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 9A and / or Fig. 9B Details are provided regarding logic 915. In at least one embodiment, logic 915 can be used in computing system 2100 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0394] Fig.21 The logic and hardware structure can be integrated into Figure 1-8 In the system and processor disclosed in. For example, Fig.21 The logic / hardware structure in can perform at least part or all of process 300, 400 and / or 500. In at least one embodiment, Fig.21 The system or apparatus disclosed in causes a processor to identify one or more locations of one or more objects in one or more images based at least in part on one or more locations of one or more objects in one or more previous images. In at least one embodiment, by performing at least part or all of processes 300, 400, and / or 500, a processor including one or more circuits divides one or more images into one or more segments and stores in a memory an indication of which of the one or more segments contain one or more identified locations of one or more objects. In at least one embodiment, by performing at least part or all of processes 300, 400, and / or 500, Fig.21 The system or apparatus disclosed in causes a processor to combine one or more positions of one or more objects to generate a region of interest.

[0395] processor

[0396] Fig.22A 2200 according to at least one embodiment. In at least one embodiment, the various components of the parallel processor 2200 may be implemented using one or more integrated circuit devices, such as a programmable processor, an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA). In at least one embodiment, the parallel processor 2200 shown is a processor according to an exemplary embodiment. Fig.21 A variation of the one or more parallel processors 2112 is shown. In at least one embodiment, parallel processors 2200 include one or more graphics cores 2000.

[0397] In at least one embodiment, parallel processor 2200 includes parallel processing unit 2202. In at least one embodiment, parallel processing unit 2202 includes I / O unit 2204, which enables communication with other devices, including other instances of parallel processing unit 2202. In at least one embodiment, I / O unit 2204 can be directly connected to other devices. In at least one embodiment, I / O unit 2204 is connected to other devices via the use of a hub or switch interface (e.g., memory hub 2205). In at least one embodiment, the connection between memory hub 2205 and I / O unit 2204 forms a communication link 2213. In at least one embodiment, I / O unit 2204 is connected to a host interface 2206 and a memory crossbar switch 2216, wherein host interface 2206 receives commands for performing processing operations and memory crossbar switch 2216 receives commands for performing memory operations.

[0398] In at least one embodiment, when the host interface 2206 receives command buffers via the I / O unit 2204, the host interface 2206 can direct work operations for executing those commands to the front end 2208. In at least one embodiment, the front end 2208 is coupled with a scheduler 2210 (which can be referred to as a sequencer), which is configured to assign commands or other work items to the processing cluster array 2212. In at least one embodiment, the scheduler 2210 ensures that the processing cluster array 2212 is properly configured and in a valid state before assigning tasks to clusters in the processing cluster array 2212. In at least one embodiment, the scheduler 2210 is implemented via firmware logic executed on a microcontroller. In at least one embodiment, the microcontroller-implemented scheduler 2210 can be configured to perform complex scheduling and work distribution operations at coarse and fine granularity, thereby achieving fast preemption and context switching of threads executed on the processing cluster array 2212. In at least one embodiment, the host software can prove a workload for scheduling on the processing cluster array 2212 via one of a plurality of graphics processing paths. In at least one embodiment, the workload may then be automatically distributed across the processing cluster array 2212 by scheduler 2210 logic within a microcontroller that includes scheduler 2210 .

[0399] In at least one embodiment, the processing cluster array 2212 may include up to "N" processing clusters (e.g., cluster 2214A, cluster 2214B to cluster 2214N), where "N" represents a positive integer (which may be an integer "N" different from the integers used in other figures). In at least one embodiment, each cluster 2214A-2214N of the processing cluster array 2212 may execute a large number of concurrent threads. In at least one embodiment, the scheduler 2210 may allocate work to the clusters 2214A-2214N in the processing cluster array 2212 using various scheduling and / or work allocation algorithms, which may vary depending on the workload generated for each type of program or calculation. In at least one embodiment, scheduling may be handled dynamically by the scheduler 2210, or may be partially assisted by compiler logic during the compilation of program logic configured to be executed by the processing cluster array 2212. In at least one embodiment, different clusters 2214A-2214N in the processing cluster array 2212 may be allocated to process different types of programs or to perform different types of calculations.

[0400] In at least one embodiment, processing cluster array 2212 can be configured to perform various types of parallel processing operations. In at least one embodiment, processing cluster array 2212 is configured to perform general-purpose parallel computing operations. For example, in at least one embodiment, processing cluster array 2212 can include logic for performing processing tasks including filtering video and / or audio data, performing modeling operations including physics operations, and performing data transformations.

[0401] In at least one embodiment, the processing cluster array 2212 is configured to perform parallel graphics processing operations. In at least one embodiment, the processing cluster array 2212 may include additional logic for supporting the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, the processing cluster array 2212 may be configured to execute shader programs related to graphics processing, such as but not limited to vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, the parallel processing unit 2202 may transfer data from the system memory via the I / O unit 2204 for processing. In at least one embodiment, during processing, the transferred data may be stored in an on-chip memory (e.g., parallel processor memory 2222) during processing and then written back to the system memory.

[0402] In at least one embodiment, when the parallel processing unit 2202 is used to perform graphics processing, the scheduler 2210 can be configured to divide the processing workload into tasks of approximately equal size to better implement the distribution of graphics processing operations to multiple clusters 2214A-2214N in the processing cluster array 2212. In at least one embodiment, the portions of the processing cluster array 2212 can be configured to perform different types of processing. For example, in at least one embodiment, a first portion can be configured to perform vertex shading and topology generation, a second portion can be configured to perform tessellation and geometry shading, and a third portion can be configured to perform pixel shading or other screen space operations to generate a rendered image for display. In at least one embodiment, intermediate data generated by one or more of the clusters 2214A-2214N can be stored in a buffer to allow the intermediate data to be transferred between the clusters 2214A-2214N for further processing.

[0403] In at least one embodiment, the processing cluster array 2212 can receive processing tasks to be performed via the scheduler 2210, which receives commands defining the processing tasks from the front end 2208. In at least one embodiment, the processing tasks can include an index of the data to be processed, such as surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands defining how to process the data (e.g., what program to execute). In at least one embodiment, the scheduler 2210 can be configured to obtain the index corresponding to the task, or can receive the index from the front end 2208. In at least one embodiment, the front end 2208 can be configured to ensure that the processing cluster array 2212 is configured to be in a valid state before starting the workload specified by the incoming command buffer (e.g., batch-buffer, push buffer, etc.).

[0404] In at least one embodiment, each of the one or more instances of parallel processing unit 2202 can be coupled to parallel processor memory 2222. In at least one embodiment, parallel processor memory 2222 can be accessed via memory crossbar switch 2216, which can receive memory requests from processing cluster array 2212 and I / O unit 2204. In at least one embodiment, memory crossbar switch 2216 can access parallel processor memory 2222 via memory interface 2218. In at least one embodiment, memory interface 2218 can include multiple partition units (e.g., partition unit 2220A, partition unit 2220B to partition unit 2220N), which can each be coupled to a portion of parallel processor memory 2222 (e.g., memory units). In at least one embodiment, the number of partition units 2220A-2220N is configured to be equal to the number of memory cells, such that the first partition unit 2220A has a corresponding first memory cell 2224A, the second partition unit 2220B has a corresponding second memory cell 2224B, and the Nth partition unit 2220N has a corresponding Nth memory cell 2224N. In at least one embodiment, the number of partition units 2220A-2220N may not be equal to the number of memory cells.

[0405] In at least one embodiment, the memory units 2224A-2224N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, the memory units 2224A-2224N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM, HBM2e, or HDM3). In at least one embodiment, rendering targets such as frame buffers or texture maps can be stored across the memory units 2224A-2224N, allowing the partition units 2220A-2220N to write to portions of each rendering target in parallel to efficiently use the available bandwidth of the parallel processor memory 2222. In at least one embodiment, local instances of the parallel processor memory 2222 can be excluded to facilitate a unified memory design that utilizes system memory as well as local cache memory.

[0406] In at least one embodiment, any of the clusters 2214A-2214N in the processing cluster array 2212 can process data to be written to any memory unit 2224A-2224N within the parallel processor memory 2222. In at least one embodiment, the memory crossbar 2216 can be configured to transmit the output of each cluster 2214A-2214N to any partition unit 2220A-2220N or another cluster 2214A-2214N, which can perform additional processing operations on the output. In at least one embodiment, each cluster 2214A-2214N can communicate with the memory interface 2218 through the memory crossbar 2216 to read from or write to various external memory devices. In at least one embodiment, memory crossbar switch 2216 has connections to memory interface 2218 for communicating with I / O unit 2204, and connections to local instances of parallel processor memory 2222, which enables processing units within different processing clusters 2214A-2214N to communicate with system memory or other memory that is not local to parallel processing unit 2202. In at least one embodiment, memory crossbar switch 2216 can use virtual channels to separate traffic flows between clusters 2214A-2214N and partition units 2220A-2220N.

[0407] In at least one embodiment, multiple instances of parallel processing unit 2202 may be provided on a single add-in card, or multiple add-in cards may be interconnected. In at least one embodiment, different instances of parallel processing unit 2202 may be configured to interoperate, even if different instances have different numbers of processing cores, different numbers of local parallel processor memories, and / or other configuration differences. For example, in at least one embodiment, some instances of parallel processing unit 2202 may include higher precision floating point units relative to other instances. In at least one embodiment, a system including one or more instances of parallel processing unit 2202 or parallel processor 2200 may be implemented in a variety of configurations and form factors, including but not limited to desktop computers, laptop computers or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0408] Fig. 22B is a block diagram of a partition unit 2220 according to at least one embodiment. In at least one embodiment, the partition unit 2220 is Fig.22A220N。 In at least one embodiment, the partition unit 2220 includes an L2 cache 2221, a frame buffer interface 2225, and an ROP 2226 (raster operation unit). In at least one embodiment, the L2 cache 2221 is a read / write cache that is configured to perform load and store operations received from the memory crossbar switch 2216 and the ROP 2226. In at least one embodiment, the L2 cache 2221 outputs read misses and urgent write-back requests to the frame buffer interface 2225 for processing. In at least one embodiment, updates can also be sent to the frame buffer via the frame buffer interface 2225 for processing. In at least one embodiment, the frame buffer interface 2225 communicates with memory units (such as ROPs) in parallel processor memories. Fig.22A One of the memory units 2224A-2224N (e.g., within parallel processor memory 2222)) is coupled.

[0409] In at least one embodiment, ROP 2226 is a processing unit that performs raster operations such as stencils, z-tests, blending, etc. In at least one embodiment, ROP 2226 then outputs processed graphics data stored in graphics memory. In at least one embodiment, ROP 2226 includes compression logic for compressing depth or color data written to memory and decompressing depth or color data read from memory. In at least one embodiment, the compression logic can be lossless compression logic that utilizes one or more of a variety of compression algorithms. In at least one embodiment, the type of compression performed by ROP 2226 can vary based on the statistical characteristics of the data to be compressed. For example, in at least one embodiment, incremental color compression is performed on depth and color data on a per-tile basis.

[0410] In at least one embodiment, ROP 2226 is included within each processing cluster (e.g., Fig.22A In at least one embodiment, read and write requests for pixel data rather than pixel fragment data are transmitted through memory crossbar switch 2216. In at least one embodiment, the processed graphics data can be displayed on a display device such as a Fig.21 2100), routed by processor 2102 for further processing, or by Fig.22A One of the processing entities within parallel processor 2200 is routed for further processing.

[0411] Fig. 22C is a block diagram of a processing cluster 2214 within a parallel processing unit according to at least one embodiment. In at least one embodiment, a processing cluster is Fig.22AIn at least one embodiment, processing cluster 2214 can be configured to execute many threads in parallel, where a "thread" refers to an instance of a specific program executed on a specific set of input data. In at least one embodiment, single instruction multiple data (SIMD) instruction issuance technology is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, single instruction multiple thread (SIMT) technology is used to support the parallel execution of a large number of generally synchronized threads using a common instruction unit, which is configured to issue instructions to a set of processing engines within each processing cluster.

[0412] In at least one embodiment, the operation of the processing cluster 2214 can be controlled via a pipeline manager 2232 that allocates processing tasks to SIMT parallel processors. In at least one embodiment, the pipeline manager 2232 Fig.22A The scheduler 2210 receives instructions and manages the execution of these instructions via the graphics multiprocessor 2234 and / or the texture unit 2236. In at least one embodiment, the graphics multiprocessor 2234 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors of different architectures may be included in the processing cluster 2214. In at least one embodiment, one or more instances of the graphics multiprocessor 2234 may be included in the processing cluster 2214. In at least one embodiment, the graphics multiprocessor 2234 may process data, and the data crossbar 2240 may be used to distribute the processed data to one of a plurality of possible destinations (including other shader units). In at least one embodiment, the pipeline manager 2232 may facilitate the distribution of the processed data by specifying the destination of the processed data to be distributed via the data crossbar 2240.

[0413] In at least one embodiment, each graphics multiprocessor 2234 within a processing cluster 2214 may include the same set of function execution logic (e.g., arithmetic logic units, load-store units, etc.). In at least one embodiment, the function execution logic may be configured in a pipelined manner, where new instructions may be issued before previous instructions are completed. In at least one embodiment, the function execution logic supports a variety of operations, including integer and floating point arithmetic, comparison operations, Boolean operations, bit shifts, and calculations of various algebraic functions. In at least one embodiment, the same functional unit hardware may be utilized to perform different operations, and any combination of functional units may be present.

[0414] In at least one embodiment, the instructions transmitted to the processing cluster 2214 constitute threads. In at least one embodiment, a group of threads executed across a group of parallel processing engines is a thread group. In at least one embodiment, the thread group executes a common program on different input data. In at least one embodiment, each thread within a thread group can be assigned to a different processing engine within the graphics multiprocessor 2234. In at least one embodiment, the thread group may include fewer threads than the number of processing engines within the graphics multiprocessor 2234. In at least one embodiment, when the number of threads included in the thread group is less than the number of processing engines, one or more processing engines may be idle during the cycle in which the thread group is being processed. In at least one embodiment, the thread group may also...

Claims

1. A processor, comprising: One or more circuits for causing one or more locations of one or more objects in one or more images to be identified based at least in part on one or more locations of the one or more objects in one or more previous images.

2. The processor of claim 1 , wherein the one or more circuits are configured to: A region of interest (ROI) is generated based at least in part on using at least one of the one or more positions of the one or more objects.

3. The processor of claim 1 , wherein the one or more circuits are configured to use one or more neural networks to perform object detection only within a region of interest (ROI). 4 . The processor of claim 1 , wherein the one or more circuits are configured to modify a region of interest (ROI) in the one or more images based at least in part on object detection. 5 . The processor of claim 1 , wherein the one or more circuits are configured to adjust a region of interest (ROI) based at least in part on a number of times the one or more objects appear in the one or more locations in the one or more images.

6. A processor according to claim 1, wherein the one or more circuits are used to divide the one or more images into one or more segments and store indications in a memory identifying which of the one or more segments contain one or more identified locations of the one or more objects.

7. The processor of claim 1 , wherein the one or more circuits are configured to use one or more neural networks to indicate one or more regions of the one or more images to be used to perform object detection based at least in part on one or more locations of one or more objects in one or more second images.

8. A system comprising: One or more processors for causing one or more locations of one or more objects in one or more images to be identified based at least in part on the one or more locations of the one or more objects in one or more previous images.

9. The system of claim 8, wherein the one or more processors are configured to: generating a region of interest (ROI) by combining two or more locations of one or more objects; and The ROI is modified based at least in part on performing object detection using one or more second images.

10. The system of claim 8, wherein the one or more processors are configured to use one or more neural networks to infer the one or more objects based at least in part on selecting one or more portions of a video frame that include the one or more objects that have appeared in a previous video frame.

11. The system of claim 8, wherein the one or more processors are configured to: dividing a field of view captured by the one or more cameras into one or more segments; and The number of times the one or more objects appear in each of the one or more sections is counted.

12. The system of claim 8, wherein the one or more processors are configured to dynamically adjust a region of interest (ROI) in the one or more images by comparing one or more first images including one or more objects with one or more second images including the one or more objects.

13. The system of claim 8, wherein the one or more processors are configured to: identifying one or more portions of the one or more images; and An indication identifying which of the one or more portions contain the one or more identified locations of the one or more objects is stored.

14. The system of claim 8, wherein the one or more processors are configured to cause the autonomous vehicle to use one or more neural networks to infer one or more objects in the identified one or more locations of the one or more objects in the one or more images.

15. A method comprising: One or more locations of one or more objects in one or more images are caused to be identified based at least in part on one or more locations of the one or more objects in one or more previous images.

16. The method according to claim 15, further comprising: A region of interest (ROI) is generated based at least in part on the one or more locations where the one or more objects have appeared within the one or more locations in the one or more previous images.

17. The method according to claim 15, further comprising: A region of interest (ROI) is enlarged to include the one or more locations based at least in part on detecting one or more different locations that include the one or more objects.

18. The method according to claim 15, further comprising: A region of interest (ROI) including the one or more locations is reduced based at least in part on failure to detect one or more objects in at least one of the one or more locations.

19. The method according to claim 15, further comprising: One or more neural networks are used to perform object detection only within a region of interest (ROI) that includes the one or more locations of the one or more objects.

20. The method of claim 15, further comprising: One or more traffic cameras are used to generate the one or more images corresponding to the driving environment.

Images