Deep learning method and system for printed circuit board defect identification and medium

Abstract

The invention relates to the technical field of electronic manufacturing, in particular to a deep learning method and system for printed circuit board defect identification and a medium. The method comprises the following steps: acquiring an X-ray scanning image of the printed circuit board, and carrying out interlayer dislocation detection on the X-ray scanning image of the printed circuit board so as to obtain interlayer dislocation data of the circuit board; performing via hole dislocation feature extraction and pad offset feature extraction according to the circuit board interlayer dislocation data so as to obtain via hole dislocation data and pad offset data; conducting failure analysis according to the via hole dislocation data and the pad offset data so as to obtain circuit board conducting failure data; and performing binarization conversion according to the X-ray scanning image of the printed circuit board to obtain a binarization image of the printed circuit board. Based on the electronic manufacturing technology, the accuracy and efficiency of defect detection are improved.

Description

Technical Field

[0001] The present invention relates to the field of electronic manufacturing technology, and in particular to a deep learning method, system and medium for printed circuit board defect recognition. Background Art

[0002] The training of deep learning models usually requires a large amount of annotated data, and obtaining high-quality annotated data is time-consuming and laborious, especially for scenarios with many and complex types of defects in printed circuit boards, where the cost of generating annotated data is high. The training process of deep learning models takes a long time, especially when using large-scale data sets. The required computing resources are huge and require specialized hardware support, which increases the development cost and implementation difficulty. In addition, there are processing delays for application scenarios with high real-time requirements. Deep learning models are highly complex, especially models such as convolutional neural networks, which contain a large number of parameters and hierarchical structures, resulting in large computational complexity and high deployment difficulty, which will affect the real-time performance of the system and its application in resource-constrained environments. Existing models have limitations in their ability to recognize different types of printed circuit boards, production processes, and images of circuit boards of different sizes, and lack a certain degree of robustness, especially when processing low-quality images or images containing noise, resulting in inaccurate recognition results. Summary of the invention

[0003] Based on this, it is necessary for the present invention to provide a deep learning method, system and medium for printed circuit board defect identification to solve at least one of the above technical problems.

[0004] To achieve the above purpose, a deep learning method for printed circuit board defect recognition includes the following steps:

[0005] Step S1: obtaining an X-ray scanning image of a printed circuit board, and performing interlayer misalignment detection on the X-ray scanning image of the printed circuit board, thereby obtaining interlayer misalignment data of the circuit board;

[0006] Step S2: extracting via misalignment features and pad offset features based on the inter-layer misalignment data of the circuit board, thereby obtaining via misalignment data and pad offset data; performing conduction failure analysis based on the via misalignment data and pad offset data, thereby obtaining circuit board conduction failure data;

[0007] Step S3: performing binary conversion according to the X-ray scanning image of the printed circuit board, thereby obtaining a binary image of the printed circuit board; performing solder joint area recognition according to the binary image of the printed circuit board, thereby obtaining solder joint area data; performing fracture detection according to the solder joint area data, thereby obtaining solder joint area fracture data;

[0008] Step S4: construct a defect recognition model based on the circuit board conduction failure data and the solder joint area fracture data to obtain the circuit board defect recognition model; perform defect recognition on the printed circuit board X-ray scanning image according to the circuit board defect recognition model to obtain the printed circuit board defect data, and upload it to the printed circuit board management platform to perform the defect recognition task.

[0009] The present invention can accurately identify the misalignment of the internal interlayer structure of the circuit board by acquiring the X-ray scanning image of the printed circuit board and performing interlayer misalignment detection, and provide reliable basic data for the subsequent extraction of via misalignment and pad offset features, thereby effectively improving the accuracy and reliability of the data. Based on the interlayer misalignment data, the via misalignment and pad offset features can be extracted, and the spatial offset of the vias and pads can be comprehensively analyzed, laying the foundation for the analysis of conduction failures. By analyzing the conduction failures, the conductivity defects inside the circuit board can be effectively detected, and the electrical conduction failure problems caused by abnormal interlayer structures can be quickly identified, thereby improving the electrical performance detection efficiency of the circuit board. By performing binary conversion on the X-ray scanning image, the information processing of complex images can be simplified, the solder joint area in the image can be clarified, and the fracture detection can be performed in combination with the solder joint area data, so that the fracture problems existing in the solder joints can be accurately identified, and the accuracy of solder joint fracture detection can be effectively improved, and the mechanical connection performance of the circuit board can be guaranteed. By building a defect recognition model based on comprehensive conduction failure data and solder joint fracture data, we can make full use of multi-source data for modeling, improve the accuracy and robustness of the defect recognition model, and the model can be widely applied to circuit boards of different types, different processes and different sizes, improve recognition performance and reduce dependence on specific application scenarios. By automatically identifying defects on circuit board images through defect recognition models, we can quickly locate specific defects of the circuit board, and upload defect data to the management platform, which is convenient for real-time monitoring and centralized management of defect information, greatly improving the automation level and efficiency of circuit board defect detection, reducing manual participation, reducing detection costs, and improving the real-time performance and application breadth of the system. The present invention, combined with deep learning technology, can overcome the limitations of traditional circuit board defect detection methods, realize accurate, fast and efficient circuit board defect recognition, and has broad industrial application prospects.

[0010] Optionally, step S1 specifically includes:

[0011] Step S11: Acquire an X-ray scanning image of a printed circuit board;

[0012] Step S12: performing interlayer edge detection according to the X-ray scanning image of the printed circuit board to obtain interlayer edge data;

[0013] Step S13: acquiring inter-layer template data, and performing inter-layer template matching on inter-layer edge data according to the inter-layer template data, thereby obtaining inter-layer template matching data;

[0014] Step S14: Calculate the inter-layer offset according to the inter-layer template matching data, so as to obtain the inter-layer offset data;

[0015] Step S15: marking the dislocation area of ​​the interlayer edge data according to the interlayer offset data, so as to obtain the interlayer dislocation data of the circuit board.

[0016] The present invention can intuitively reflect the details of the internal structure of the circuit board by acquiring the X-ray scanning image of the printed circuit board, provide a high-resolution data basis for subsequent image processing, and ensure the accuracy of detection. By using the interlayer edge detection technology, the edge features between the layers of the circuit board can be accurately extracted, effectively reducing the interference of the complex background, and providing reliable data support for the precise positioning of the interlayer structure. Template matching can be performed in combination with the interlayer template data, and the interlayer edge data can be accurately calibrated using a standardized template, and the accuracy and consistency of the detection can be further improved through matching analysis. The calculation of the interlayer offset can quantify the offset degree of the interlayer structure, and provide a quantitative basis for the subsequent misaligned area marking, so as to quickly and intuitively mark the misaligned area in the multi-layer circuit board. By generating the interlayer misalignment data of the circuit board, high-quality annotation data can be provided for the training of the deep learning model, reducing the cost and difficulty of manual annotation, and at the same time improving the recognition performance of the deep learning model for misalignment defects. It significantly improves the automation level of circuit board detection and reduces the errors introduced by human factors. It is suitable for complex circuit board structures and diversified production process environments. It has high versatility and robustness, and provides an efficient and reliable solution for quality inspection and defect management of circuit boards in industrial production, significantly improving production efficiency and product quality.

[0017] Optionally, step S2 specifically includes:

[0018] Step S21: extracting via misalignment features and pad offset features based on the inter-layer misalignment data of the circuit board, thereby obtaining via misalignment data and pad offset data;

[0019] Step S22: performing electrical conduction failure analysis on the via misalignment data, thereby obtaining via electrical conduction failure data;

[0020] Step S23: performing thermal expansion failure analysis on the pad offset data, thereby obtaining pad thermal expansion failure data;

[0021] Step S24: integrating the circuit board conduction failure data according to the via electrical conduction failure data and the pad thermal expansion failure data, thereby obtaining the circuit board conduction failure data.

[0022] The present invention realizes the defect feature analysis and integration of vias and pads by further processing the data of misalignment between layers of the circuit board, and has significant technical advantages and beneficial effects. By extracting the via misalignment features and the pad offset features, the physical offset of the vias and pads can be accurately captured and located, laying the foundation for subsequent failure analysis. By conducting electrical conduction failure analysis on the via misalignment data, it is possible to deeply explore the electrical connection performance problems inside the vias, identify the open circuit or short circuit faults caused by misalignment, and provide a scientific basis for the electrical performance diagnosis of the circuit board. By conducting thermal expansion failure analysis on the pad offset data, the stress distribution and deformation behavior of the pad under temperature change conditions can be effectively evaluated, revealing the pad peeling or cracking phenomenon caused by thermal expansion, thereby improving the prediction ability of thermal stress failure. By integrating the via electrical conduction failure data and the pad thermal expansion failure data, the conduction failure information of the circuit board is comprehensively summarized, forming a complete fault characterization system. This solution not only achieves a comprehensive evaluation of the two main failure modes of electrical conduction and thermal expansion, but can also effectively deal with diverse defects in complex production environments, improving the robustness and accuracy of failure detection. The generated circuit board conduction failure data can be directly used as training samples for deep learning models, reducing the labor cost of data annotation and improving the generalization ability of the model. It provides strong technical support for the automated upgrade and precision development of printed circuit board defect recognition systems, and significantly optimizes the quality control process in industrial manufacturing.

[0023] Optionally, step S22 is specifically:

[0024] Step S221: performing signal waveform statistics on the via misalignment data, thereby obtaining via misalignment signal waveform data;

[0025] Step S222: performing an eye diagram test according to the via misalignment signal waveform data, thereby obtaining the via misalignment signal eye diagram data;

[0026] Step S223: Acquire standard eye height data of via hole signal and standard eye width data of via hole signal;

[0027] Step S224: comparing the eye diagram data of the via misalignment signal with the standard eye height data of the via signal, so as to obtain the via signal data with insufficient eye height;

[0028] Step S225: comparing the eye diagram data of the via misalignment signal with the standard eye width data of the via signal, thereby obtaining the via signal data with insufficient eye width;

[0029] Step S226: performing electrical conduction failure intersection operation according to the via signal data of insufficient eye height and the via signal data of insufficient eye width, so as to obtain via electrical conduction failure data.

[0030] The present invention comprehensively improves the detection accuracy and efficiency of via electrical conduction failure by comparing the eye diagram analysis of via misalignment signals with standard data, and has significant technical advantages and beneficial effects. By performing signal waveform statistics on via misalignment data, the dynamic behavior of via misalignment signals can be accurately obtained, laying the foundation for subsequent eye diagram testing. The eye diagram test method can intuitively display the transmission quality and integrity of via signals, and quantify the key parameters of via signals in the form of data, such as eye height and eye width, to provide a reliable basis for signal failure assessment. By acquiring and introducing the standard eye height and standard eye width data of via signals, a unified quality benchmark is established, so that the signal detection results have quantifiable and comparable characteristics, thereby enhancing the versatility and standardization of the detection system. By comparing the eye diagram data of via misalignment signals with the standard eye height data, via signals with insufficient eye height due to insufficient signal amplitude can be effectively identified, thereby locating areas with transmission attenuation or impedance mismatch problems. By comparing with the standard eye width data, it is possible to detect via signals with insufficient eye width caused by signal timing offset or distortion, revealing the hidden dangers of reduced conduction performance caused by jitter or noise. By performing intersection operations on the signal data of insufficient eye height and insufficient eye width, the common impact of the two types of failures is comprehensively evaluated, and the via electrical conduction failure data is generated, achieving a deep fusion analysis of complex signal failures. It can not only quickly capture multi-dimensional signal anomalies, but also significantly reduce the missed detection rate and false detection rate, providing an efficient and reliable technical path for the accurate diagnosis of the conduction performance of printed circuit boards, and further enriching the means of failure analysis and the training samples of deep learning models, improving the comprehensiveness and robustness of defect identification.

[0031] Optionally, step S222 is specifically:

[0032] Perform signal frequency statistics according to the waveform data of the via misalignment signal, thereby obtaining signal frequency data;

[0033] The sampling rate is set according to the signal frequency data, thereby obtaining the sampling rate data;

[0034] Extract signal source characteristics according to the waveform data of the via misalignment signal, thereby obtaining signal source characteristic data, and set the trigger source according to the signal source data, thereby obtaining trigger source data;

[0035] Perform stability calculation based on the waveform data of the via misalignment signal, thereby obtaining the instability data of the via misalignment signal;

[0036] A single-trigger mode is set for the instability data of the via misalignment signal, thereby obtaining single-trigger mode data;

[0037] The eye diagram is displayed according to the single trigger mode data and the trigger source data, so as to obtain the eye diagram data of the hole misalignment signal.

[0038] The present invention can accurately extract the frequency characteristics of signal transmission by frequency statistics of the waveform data of the via misaligned signal, and provide basic reference data for subsequent analysis. By setting the sampling rate based on the signal frequency data, efficient signal acquisition can be achieved, ensuring that the sampling frequency matches the signal frequency, thereby improving the integrity and accuracy of data acquisition. By extracting the signal source characteristics, the core characteristics of signal transmission can be accurately obtained, which is convenient for further locating and analyzing the signal source problem. At the same time, the trigger source is set according to the signal source data, and accurate triggering can be achieved for a specific signal source, thereby improving the test efficiency and trigger sensitivity. The signal stability calculation quantitatively evaluates the fluctuation of the signal waveform and effectively identifies abnormal behavior during signal transmission. The generated via misaligned signal instability data provides an important basis for failure analysis. By setting a single trigger mode for the signal instability data, a single signal anomaly can be quickly locked, thereby improving the ability to capture dynamic signal behavior and ensuring the complete extraction of abnormal signal characteristics. Combining the single trigger mode data with the trigger source data, the comprehensive performance of signal transmission is intuitively presented through the eye diagram display, and the obtained hole misaligned signal eye diagram data provides a comprehensive visual analysis of signal integrity, timing characteristics and jitter behavior. This method systematically optimizes each link of signal processing, improves the accuracy and efficiency of signal analysis, and enhances the ability to diagnose complex signal failure problems. It lays a solid technical foundation for the identification of printed circuit board conduction failures and significantly improves the training data quality and robustness of deep learning models.

[0039] Optionally, step S23 is specifically:

[0040] Step S231: Calculating the base point contact area of ​​the pad offset data to obtain base point contact area data;

[0041] Step S232: performing stress distribution simulation on the base point contact area data, thereby obtaining base point contact stress distribution data;

[0042] Step S233: performing pad warpage area identification on the pad offset data according to the base point contact stress distribution data and the base point contact area data, thereby obtaining the pad warpage area;

[0043] Step S234: calculating the warpage ratio of the base point contact area data according to the pad warpage area, thereby obtaining the base point contact pad warpage ratio;

[0044] Step S235: performing thermal failure simulation on the pad offset data according to the base point contact pad warpage ratio, thereby obtaining pad thermal expansion failure data.

[0045] The present invention can accurately evaluate the actual contact situation of the pad by calculating the base point contact area of ​​the pad offset data, and provide a key geometric parameter basis for subsequent analysis. Stress distribution simulation of the base point contact area data is helpful to fully understand the stress distribution of the pad under the stress state, so as to locate the high stress area and evaluate its reliability. The pad offset data is identified by using the base point contact stress distribution data and the base point contact area data, and the deformation or warping area of ​​the pad can be accurately marked, providing a clear direction for further failure analysis. The warping ratio calculation based on the pad warping area can quantify the severity of the pad warping, and the generated base point contact pad warping ratio data provides an intuitive indicator for reliability assessment. Combined with the pad warping ratio, the pad offset data is simulated for thermal failure, which can effectively predict the thermal expansion failure of the pad under high temperature conditions, and the obtained pad thermal expansion failure data lays the foundation for the comprehensive evaluation of conduction failure. The key links of pad failure analysis have been optimized, which not only improves the analysis accuracy, but also enhances the diagnostic capability of complex pad offset problems. At the same time, it provides higher quality and more comprehensive feature information for the input data of the deep learning model, which helps to further improve the robustness and generalization ability of the model.

[0046] Optionally, step S233 is specifically:

[0047] The pad warping contact stress threshold is set according to the base point contact stress distribution data, so as to obtain the pad warping contact stress threshold;

[0048] The base point contact stress distribution data is divided into warpage risk areas according to the pad warpage contact stress threshold, so as to obtain pad warpage risk area data;

[0049] Monitor the change of base point contact area data to obtain base point contact area reduction data;

[0050] The pad warpage feature is fused according to the base point contact area reduction data and the pad warpage risk area data, so as to obtain the pad warpage data;

[0051] The pad offset data is divided into warpage areas according to the pad warpage data, thereby obtaining the pad warpage area data.

[0052] The present invention sets the pad warping contact stress threshold through base point contact stress distribution data, which can provide a clear benchmark for judging the potential risks of the pad warping area, and effectively improve the standardization and accuracy of risk assessment. Using the pad warping contact stress threshold to divide the base point contact stress distribution data into warping risk areas can quickly locate the key areas where the pad may fail, which is convenient for further optimization design in a targeted manner. Monitoring the changes in the base point contact area data helps to capture the reduction in contact area of ​​the pad due to force or environmental changes in real time, and provides a dynamic basis for evaluating the reliability of the pad. Based on the base point contact area reduction data and the pad warping risk area data, the warping feature fusion can integrate multi-dimensional feature information, thereby comprehensively characterizing the pad warping behavior and laying a data foundation for subsequent processing and model optimization. The pad offset data is divided into warping areas through the pad warping data, which can not only more accurately mark the warping area of ​​the pad, but also improve the visualization effect of the pad warping behavior, which is convenient for subsequent analysis and optimization. The above steps enhance the accuracy and comprehensiveness of pad warpage failure analysis through a multi-level and multi-feature data processing flow, provide high-quality labeled data for the deep learning model, further improve the robustness and generalization ability of the model in complex scenarios, and provide a scientific basis for printed circuit board quality control and reliability optimization.

[0053] Optionally, step S3 specifically includes:

[0054] Step S31: performing a binary conversion according to the X-ray scanning image of the printed circuit board, thereby obtaining a binary image of the printed circuit board;

[0055] Step S32: performing Hough transform on the binary image of the printed circuit board to obtain solder joint area data;

[0056] Step S33: performing linear width statistics according to the solder joint area data, thereby obtaining narrow linear width data;

[0057] Step S34: dividing the solder joint area data into regions according to the narrow linear width data, thereby obtaining narrow linear width area data;

[0058] Step S35: performing corrosion according to the narrow linear width area data, thereby obtaining narrow linear width corrosion area data;

[0059] Step S36: dilating the narrow linear width eroded area data to obtain the narrow linear width dilated area data;

[0060] Step S37: performing crack density calculation on the narrow linear width expansion area data to obtain crack density data, and performing high-density area division on the narrow linear width expansion area data according to the crack density data to obtain high-density narrow linear area data;

[0061] Step S38: Calculate the crack length of the narrow linear width expansion area data to obtain crack length data, and perform length statistics on the narrow linear width expansion area data according to the crack length data to obtain long crack area data;

[0062] Step S39: performing a region intersection operation based on the high-density narrow linear region data and the long crack region data to obtain the weld region fracture data.

[0063] The present invention can effectively highlight the key features in the image by performing binary conversion on the X-ray scanning image of the printed circuit board, and provide basic image segmentation conditions for subsequent processing. By using Hough transform to extract solder joint area data, the position and shape of the solder joint can be accurately located, providing reliable input data for solder joint characteristic analysis. By statistics on the linear width of the solder joint area, the distribution of narrow linear areas and their potential risk characteristics are clarified, providing a target area for defect detection. Corrosion and expansion operations are performed on the narrow linear width area, which can not only remove noise, but also enhance the significance of the linear structure, thereby enhancing the accuracy of subsequent analysis. Through crack density calculation and high-density area division, high-risk areas where cracks gather in the solder joint area can be identified, providing an important basis for solder joint failure analysis. Crack length calculation and long crack area division can identify potential fracture risk areas, and combined with data intersection operations of high-density narrow linear areas, further focus on the key fracture areas of the solder joints. Through layer-by-layer data processing and feature extraction, a refined solder joint defect detection process was constructed, which not only improved the annotation accuracy of the model, but also provided high-quality input for the application of deep learning models in complex defect scenarios of printed circuit boards, and ultimately achieved comprehensive quantification and accurate assessment of solder joint fracture risks.

[0064] Optionally, the present specification also provides a computer-readable storage medium storing a computer program, wherein when the computer program is executed by a processor, the deep learning method for printed circuit board defect identification described in any one of the above is implemented.

[0065] Optionally, the present specification also provides a deep learning system for printed circuit board defect recognition, which is used to execute the deep learning method for printed circuit board defect recognition as described above, and the deep learning system for printed circuit board defect recognition includes:

[0066] A circuit board interlayer misalignment detection module is used to obtain an X-ray scanning image of a printed circuit board and perform interlayer misalignment detection on the X-ray scanning image of the printed circuit board, thereby obtaining interlayer misalignment data of the circuit board;

[0067] The circuit board conduction failure analysis module is used to extract via misalignment features and pad offset features according to the inter-layer misalignment data of the circuit board, so as to obtain via misalignment data and pad offset data; conduction failure analysis is performed according to the via misalignment data and pad offset data, so as to obtain circuit board conduction failure data;

[0068] The solder joint area fracture detection module is used to perform binary conversion according to the X-ray scanning image of the printed circuit board, so as to obtain the binary image of the printed circuit board; perform solder joint area recognition according to the binary image of the printed circuit board, so as to obtain solder joint area data; perform fracture detection according to the solder joint area data, so as to obtain solder joint area fracture data;

[0069] The circuit board defect recognition module is used to construct a defect recognition model based on the circuit board conduction failure data and the solder joint area fracture data, so as to obtain the circuit board defect recognition model; according to the circuit board defect recognition model, the X-ray scanning image of the printed circuit board is used to identify defects, so as to obtain the printed circuit board defect data, and upload it to the printed circuit board management platform to perform the defect recognition task.

[0070] A deep learning system for printed circuit board defect identification of the present invention can implement any deep learning method for printed circuit board defect identification of the present invention, and is used to combine the operations between various modules and the medium of signal transmission to complete the deep learning method for printed circuit board defect identification. The internal modules of the system cooperate with each other to improve the accuracy and efficiency of defect detection. BRIEF DESCRIPTION OF THE DRAWINGS

[0071] Other features, objects and advantages of the present invention will become more apparent from the detailed description of non-limiting embodiments thereof made with reference to the following drawings:

[0072] Figure 1 A schematic flow chart of the steps of the deep learning method for printed circuit board defect recognition of the present invention;

[0073] Figure 2 Detailed step flow diagram of step S1 in the present invention;

[0074] Figure 3 Detailed step flow diagram of step S2 in the present invention;

[0075] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0076] The following is a clear and complete description of the technical method of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by technicians in this field without creative work are within the scope of protection of the present invention.

[0077] In addition, the accompanying drawings are only schematic illustrations of the present invention and are not necessarily drawn to scale. The same reference numerals in the figures represent the same or similar parts, and their repeated description will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities and do not necessarily correspond to physically or logically independent entities. The functional entities can be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor methods and / or microcontroller methods.

[0078] It should be understood that, although the terms "first", "second", etc. may be used herein to describe various units, these units should not be limited by these terms. These terms are used only to distinguish one unit from another unit. For example, without departing from the scope of the exemplary embodiments, the first unit may be referred to as the second unit, and similarly the second unit may be referred to as the first unit. The term "and / or" used herein includes any and all combinations of one or more of the listed associated items.

[0079] To achieve this, please refer to Figures 1 to 3 The present invention provides a deep learning method for printed circuit board defect recognition, the method comprising the following steps:

[0080] Step S1: obtaining an X-ray scanning image of a printed circuit board, and performing interlayer misalignment detection on the X-ray scanning image of the printed circuit board, thereby obtaining interlayer misalignment data of the circuit board;

[0081] In this embodiment, the operation of obtaining the X-ray scanning image of the printed circuit board uses an X-ray scanning device, which generates an image with sufficient resolution and contrast by adjusting the light source energy and exposure time parameters. The typical setting of the resolution is ≥50μm, and the exposure time is set to a range of 500ms to 2000ms according to the material thickness. Interlayer misalignment detection is achieved by image preprocessing and interlayer edge feature extraction. Gaussian filtering is performed on the X-ray image to reduce noise, and then the Sobel operator is used to extract the interlayer edge features to generate edge data. According to the interlayer edge data, the acquired image is matched with a predefined interlayer template. The template is designed based on a standard circuit board CAD drawing. The matching adopts the normalized cross-correlation method, and the template matching result must meet the matching threshold ≥0.8. The interlayer offset is further calculated. The offset is obtained by statistically calculating the pixel offset value of each interlayer matching point and taking the average value. The offset result is output as numerical interlayer misalignment data and marked in the corresponding image area.

[0082] Step S2: extracting via misalignment features and pad offset features based on the inter-layer misalignment data of the circuit board, thereby obtaining via misalignment data and pad offset data; performing conduction failure analysis based on the via misalignment data and pad offset data, thereby obtaining circuit board conduction failure data;

[0083] In this embodiment, the via misalignment feature extraction is based on the image-based connected domain analysis method to identify and mark the via center point, and the difference between the actual center point position and the standard template position is calculated as the misalignment amount in microns. The pad offset feature extraction performs a Hough transform on the pad area to fit the circular contour, and matches it with the standard pad template to extract the offset vector and offset angle data. Based on the extracted via misalignment data and pad offset data, conduction failure analysis is performed. The via conduction failure analysis relies on the via electrical conduction model, uses simulation tools such as ANSYS to simulate the electric field distribution, and combines the empirical relationship curve between the misalignment amount and the conductivity to evaluate the failure probability; the pad offset conduction failure is calculated by analyzing the thermal expansion effect, inputs the offset data and the temperature variation range (usually -40°C to 125°C), outputs the pad thermal expansion failure rate, and finally generates the conduction failure comprehensive evaluation data, recording the failure type and location.

[0084] Step S3: performing binary conversion according to the X-ray scanning image of the printed circuit board, thereby obtaining a binary image of the printed circuit board; performing solder joint area recognition according to the binary image of the printed circuit board, thereby obtaining solder joint area data; performing fracture detection according to the solder joint area data, thereby obtaining solder joint area fracture data;

[0085] In this embodiment, grayscale enhancement technology is used to optimize the image contrast, and a contrast stretching method is selected and a grayscale range (such as 0-255) is set. The adaptive threshold method (OTSU algorithm) is selected in the binarization operation, and the optimal threshold is automatically calculated according to the image grayscale histogram to ensure clear details. After binarization, the noise points are removed by morphological opening operation to obtain a binary image with smooth edges. Subsequently, the Hough transform technology is used to identify the solder joint area. The solder joint is mainly circular, and its position and size range are determined by detecting the center coordinates and radius of the circle. The fracture detection of the solder joint area is achieved through regional segmentation and texture analysis. The fracture point is manifested as an isolated feature with a brightness value significantly lower than that of the surrounding area. The fracture area is segmented by density clustering (DBSCAN) and its crack length, density and distribution are counted to generate the solder joint area fracture data.

[0086] Step S4: construct a defect recognition model based on the circuit board conduction failure data and the solder joint area fracture data to obtain the circuit board defect recognition model; perform defect recognition on the printed circuit board X-ray scanning image according to the circuit board defect recognition model to obtain the printed circuit board defect data, and upload it to the printed circuit board management platform to perform the defect recognition task.

[0087] In this embodiment, the defect recognition model is constructed by combining the circuit board conduction failure data and the solder joint area fracture data. The model is based on a physical parameter library, including variables such as offset, conduction failure probability, fracture density, and crack length. Data annotation uses professional image analysis software, combined with manual annotation verification to ensure data accuracy. Through custom threshold rules (such as conduction failure rate ≥ 80% or crack density > 5 / mm 2 Defined as a defect), directly perform logical operations to determine the defect type. Upload the processed defect data to the printed circuit board management platform in a standard JSON file format, including information such as defect location, type, and feature description. Finally, the platform scheduling function is used to generate a report on the defect identification task for real-time feedback on the production line and subsequent process adjustments.

[0088] Optionally, step S1 specifically includes:

[0089] Step S11: Acquire an X-ray scanning image of a printed circuit board;

[0090] In this embodiment, the scanning parameters are set to ensure that the resolution of the image is at least 50μm to ensure the clarity of the interlayer structure. The exposure time and voltage of the X-ray device are adjusted according to the material and thickness of the circuit board. The typical voltage is set to 60kV to 120kV, and the exposure time is set to 500ms to 1500ms. The specific parameters are obtained from preliminary experiments to ensure that the scanned image can clearly display the structure of each layer of the circuit board. During the scanning process, the X-ray beam passes through the circuit board, and the information of each layer is captured layer by layer and recorded as a two-dimensional grayscale image. After scanning, image processing software is used to save and convert the image to generate a digital X-ray scan image for subsequent processing.

[0091] Step S12: performing interlayer edge detection according to the X-ray scanning image of the printed circuit board to obtain interlayer edge data;

[0092] In this embodiment, the operation of performing interlayer edge detection on the X-ray scanned image of the printed circuit board first preprocesses the original image. Image preprocessing includes denoising and contrast enhancement, and image smoothing is performed using a Gaussian filter with a filter size of 3x3 or 5x5 and a standard deviation of 1.0. Subsequently, the Sobel operator is used for edge detection, and the gradient values ​​in the horizontal and vertical directions are selected to determine the edge information between layers in the image. The Sobel operator uses a convolution operation to calculate the gradient values ​​of each pixel in the horizontal and vertical directions to generate an edge image. The edge image is binarized by setting a threshold (such as 50-150), filtering out noise and strengthening important edge features to obtain clear interlayer edge data. The interlayer edge data is output in the form of coordinates, indicating the boundary position between each layer.

[0093] Step S13: acquiring inter-layer template data, and performing inter-layer template matching on inter-layer edge data according to the inter-layer template data, thereby obtaining inter-layer template matching data;

[0094] In this embodiment, the operation of obtaining interlayer template data generates a template file by analyzing the CAD drawing of a standard printed circuit board. The template data includes the standard boundary position, size and relative position relationship of each layer of the circuit board, and is usually stored in a standard CAD file format (such as a DXF or Gerber file). According to the acquired standard template data, interlayer template matching in image processing is performed. The matching operation adopts a template matching algorithm based on cross-correlation, and the best match is found by calculating the correlation between the image to be matched and the template. The edge data in the template image is selected and compared layer by layer with the interlayer edge data obtained in step S12. The calculation method adopts the normalized cross-correlation coefficient (NCC), and the best matching area is determined by the maximum value of the coefficient. The matching threshold is set to be above 0.8 to ensure the matching accuracy. The interlayer template matching data is obtained through this step, which represents the relative position and size deviation between each layer.

[0095] Step S14: Calculate the inter-layer offset according to the inter-layer template matching data, so as to obtain the inter-layer offset data;

[0096] In this embodiment, the interlayer offset refers to the deviation between the actual interlayer position and the standard template position. The template matching data is used to extract the matching position coordinates of each layer and compare them with the standard template coordinates. The interlayer offset is calculated by subtracting the standard coordinates from the actual coordinates to obtain the horizontal and vertical components of the offset. The specific calculation uses the Euclidean distance formula to quantify the offset of each layer in microns. For the matching results between each layer, if the offset exceeds the set threshold (such as 10μm), it is considered that the layer has a large misalignment and the offset data is recorded. Detailed interlayer offset data is obtained by this method, including the specific position deviation of each layer.

[0097] Step S15: marking the dislocation area of ​​the interlayer edge data according to the interlayer offset data, so as to obtain the interlayer dislocation data of the circuit board.

[0098] In this embodiment, the interlayer offset data is combined with the interlayer edge data, and each area where the offset exceeds the set threshold is marked. The offset threshold is usually set to 10μm. If the offset exceeds this value, it is marked as a misaligned area. The misaligned area is marked with a rectangular or polygonal frame to frame the offset area, and the size of the frame is determined according to the distribution of the offset. By marking the misaligned area, the interlayer misalignment data of the circuit board is formed, including the position, size and offset information of the misaligned area. The misaligned area marking results can be directly displayed in the image, and a marking file can be generated for subsequent quality control and process adjustment.

[0099] Optionally, step S2 specifically includes:

[0100] Step S21: extracting via misalignment features and pad offset features based on the inter-layer misalignment data of the circuit board, thereby obtaining via misalignment data and pad offset data;

[0101] In this embodiment, the interlayer misalignment data is analyzed to extract the specific position of each via and pad. The extraction of via misalignment features first identifies the via area in the image, uses the image segmentation algorithm to process the circuit board image, extracts the outline of the via, and calculates the deviation between the position of each via and the standard position. A threshold value is set, for example, when the deviation exceeds 10μm, it is considered that a via misalignment exists. For pad offset feature extraction, by identifying the circular or rectangular area of ​​the pad, a template matching algorithm is used to compare it with the standard pad position. When the offset exceeds the set threshold (such as 10μm), it is recorded as a pad offset. Through these feature extractions, via misalignment data and pad offset data are obtained, which are stored in the form of coordinate deviation and size change of each via and pad, respectively.

[0102] Step S22: performing electrical conduction failure analysis on the via misalignment data, thereby obtaining via electrical conduction failure data;

[0103] In this embodiment, the operation of performing electrical conduction failure analysis on the via misalignment data is first based on the electrical connection characteristics of the via. Each via serves to connect the upper and lower layers in the circuit board. If the via position is misaligned, poor electrical conduction will result. According to the via misalignment data, the misalignment amount of each via and its effect on electrical conduction are analyzed. The electrical connection information of the via is obtained. If the via misalignment amount exceeds the set threshold (such as 10μm), the electrical connectivity between the via and the adjacent circuit is further analyzed. Use circuit simulation software (such as ANSYS Maxwell) to perform electrical simulation and calculate the effect of via misalignment on current passage. If the misalignment is too large, the current will not be able to pass effectively, resulting in electrical conduction failure. Through this analysis process, the via electrical conduction failure data is obtained, and the electrical conduction state and failure risk of each via are recorded.

[0104] Step S23: performing thermal expansion failure analysis on the pad offset data, thereby obtaining pad thermal expansion failure data;

[0105] In this embodiment, the operation of thermal expansion failure analysis of pad offset data takes into account the expansion characteristics of pads during thermal cycling. The material of each pad will expand or contract due to temperature changes during welding. If the pad is offset, it will cause uneven thermal expansion effects, thereby affecting welding quality. According to the pad offset data, the original position and offset of the pad are obtained. Thermal analysis software (such as ANSYS or COMSOL) is used to simulate the expansion behavior of the pad under high temperature conditions, and the deformation of the pad at different temperatures is calculated. For the case where the pad offset exceeds a threshold value (such as 10 μm), the effect of thermal expansion on welding is further analyzed. Considering the difference in thermal expansion coefficient between the pad and the printed circuit board, the stress distribution and deformation of the offset pad under thermal cycling are calculated. Through this analysis, the pad thermal expansion failure data is obtained, including the position information, offset and thermal expansion stress of the failed pad on the solder joint.

[0106] Step S24: integrating the circuit board conduction failure data according to the via electrical conduction failure data and the pad thermal expansion failure data, thereby obtaining the circuit board conduction failure data.

[0107] In this embodiment, each failure data is weighted. The via electrical conduction failure and the pad thermal expansion failure each have different degrees of influence on the electrical performance of the circuit board, and need to be weighted according to their severity. The weight of the via electrical conduction failure is set to 0.7, and the weight of the pad thermal expansion failure is set to 0.3. The specific weight value is determined by experimental analysis and historical data. For each circuit board, its failure score is calculated according to the via electrical conduction failure data and the pad thermal expansion failure data, and the failure score is obtained by multiplying each failure data with its corresponding weight and adding them together to obtain a comprehensive failure score. If the score exceeds the set threshold (such as 80 points), it is considered that the circuit board has a serious conduction failure problem. Finally, based on the integrated failure data, the conduction failure data of the circuit board is generated, including the conduction state, failure location and failure type of each circuit board, as a basis for quality control and further repair.

[0108] Optionally, step S22 is specifically:

[0109] Step S221: performing signal waveform statistics on the via misalignment data, thereby obtaining via misalignment signal waveform data;

[0110] In this embodiment, the signal waveform data of each via in the circuit board is obtained by electrical testing equipment. The signal waveform is obtained by applying a certain voltage and monitoring the current change, and the electrical signal of the via is obtained using a test tool such as an oscilloscope. The data of the via misalignment is used to compare the difference between the actual measured signal waveform and the ideal signal waveform. For each via, multiple signal sampling points within a certain time period are obtained, and the signal is spectrally analyzed using techniques such as fast Fourier transform (FFT). When statistics are taken, the main parameters of the waveform need to be recorded, including the peak value, effective value and noise level of the signal. In this process, a certain waveform threshold is set (such as when the signal peak value is greater than a certain value) to identify whether the signal meets the standard requirements of the via, and then the via misalignment signal waveform data is counted. The final result is the signal waveform characteristic data of each via, including information such as the amplitude and frequency characteristics of the signal.

[0111] Step S222: performing an eye diagram test according to the via misalignment signal waveform data, thereby obtaining the via misalignment signal eye diagram data;

[0112] In this embodiment, the signal waveform of each via is digitized and converted into a data format suitable for eye diagram display. The eye diagram test observes the degree of distortion of the signal during transmission by superimposing multiple cycles of the signal. The sampling points of each signal cycle are obtained by an oscilloscope and transmitted to a computer, and the signal is superimposed in the time domain using signal analysis software (such as MATLAB or LabVIEW) to draw an eye diagram. In this operation, the opening size of the eye diagram represents the quality of the signal. The larger the opening, the better the signal quality; the smaller the opening, the more serious the signal distortion. The signal waveform data is used to generate the eye diagram, and the effect of the via misalignment on signal transmission is evaluated by comparing the standard eye diagram. The standard opening size of the eye diagram is set (such as the standard value of the eye height is 200mV, and the standard value of the eye width is 100ns). When the difference between the actual eye diagram and the standard eye diagram exceeds the threshold, it is considered that the via is at risk of failure. Through this test, the via misalignment signal eye diagram data is obtained.

[0113] Step S223: Acquire standard eye height data of via hole signal and standard eye width data of via hole signal;

[0114] In this embodiment, the eye diagram standard of the via signal is defined. Eye height refers to the maximum vertical height of the signal waveform in the eye diagram, which represents the distinction between the amplitude of the signal and the noise; eye width is the horizontal width of the signal waveform in the eye diagram, which represents the temporal stability of the signal. By testing the standard via signal, the eye diagram data under ideal conditions (without misalignment) is recorded. The standard eye height data is obtained by analyzing the eye diagrams of multiple standard via signals and can be set to a common value (such as an eye height of 200mV). The standard eye width data is also obtained by analyzing the eye diagrams of multiple ideal via signals and is set to a typical eye width value (such as 100ns). These standard data are used for subsequent comparison of the eye diagram performance of the actual signal.

[0115] Step S224: comparing the eye diagram data of the via misalignment signal with the standard eye height data of the via signal, so as to obtain the via signal data with insufficient eye height;

[0116] In this embodiment, the eye diagram of the via misalignment signal is extracted by signal analysis software (such as MATLAB). The eye height data is compared with the standard eye height data. If the eye height of the via misalignment signal is lower than the standard eye height threshold (such as the eye height is less than 150mV), it is considered that the signal is insufficient. Via signals with insufficient eye height will cause the signal quality to deteriorate, thereby affecting the electrical conduction performance. The comparison operation is implemented by a simple numerical comparison, marking all via signal data with insufficient eye height. These data will serve as the basis for further analysis, indicating that the signal quality is reduced due to via misalignment.

[0117] Step S225: comparing the eye diagram data of the via misalignment signal with the standard eye width data of the via signal, thereby obtaining the via signal data with insufficient eye width;

[0118] In this embodiment, the eye width data of the via misalignment signal is extracted. The eye width indicates the temporal stability of the signal, and insufficient eye width leads to signal distortion or data transmission errors. By comparing the eye width of each via misalignment signal with the standard eye width data (such as the standard eye width is 100ns), if the eye width is less than the threshold of the standard eye width (for example, less than 90ns), it is considered that the signal eye width is insufficient. This operation detects the eye diagram of the via misalignment signal by setting an appropriate threshold, and records the via signal data with insufficient eye width. These data point out the signal transmission problems caused by via misalignment and provide a basis for electrical conduction failure analysis.

[0119] Step S226: performing electrical conduction failure intersection operation according to the via signal data of insufficient eye height and the via signal data of insufficient eye width, so as to obtain via electrical conduction failure data.

[0120] In this embodiment, an intersection operation is performed on the data of insufficient eye height and insufficient eye width. The purpose of the intersection operation is to identify via signals that meet both insufficient eye height and insufficient eye width, which will lead to more serious electrical conduction failures. Through logical operations, those via signals with insufficient eye height and insufficient eye width are screened out, and the electrical conduction failure risks of these vias are recorded. When calculating, a threshold for the intersection operation needs to be set. For example, only when the signals of insufficient eye height and insufficient eye width exceed the set threshold, is it considered that there is a risk of electrical conduction failure. The obtained via electrical conduction failure data includes the failure risk degree and failure type of each via signal, providing data support for subsequent quality control and repair.

[0121] Optionally, step S222 is specifically:

[0122] Perform signal frequency statistics according to the waveform data of the via misalignment signal, thereby obtaining signal frequency data;

[0123] In this embodiment, the signal waveform data of each via in the circuit board is obtained by electrical testing equipment (such as an oscilloscope). The signal waveform data is obtained by applying voltage or current to the via, and the signal waveform represents the characteristics of the signal changing over time. When performing frequency analysis on each via signal, the signal is converted into the frequency domain using a fast Fourier transform (FFT) to extract the frequency components of the signal. By performing FFT processing on the collected signal data, the spectrum data of the signal can be obtained. It is necessary to set the frequency range (for example, 0Hz to 1GHz) and the frequency resolution (such as 1Hz) to ensure the accuracy of the frequency statistics. The frequency data of different vias are aggregated to obtain the overall frequency statistics of the via misalignment signal, including information such as the amplitude and frequency distribution of each frequency band.

[0124] The sampling rate is set according to the signal frequency data, thereby obtaining the sampling rate data;

[0125] In this embodiment, according to the signal frequency statistics, a suitable sampling rate is set to ensure the data accuracy during the signal acquisition process. The sampling rate is set according to the Nyquist sampling theorem, that is, the sampling rate needs to be greater than twice the highest frequency in the signal. Assuming that the highest frequency of the via signal is 100MHz, the sampling rate should be set to 200MHz or higher. The sampling rate determines the number of times the signal is sampled per second. A too low sampling rate causes signal distortion and affects subsequent analysis results. After determining the effective frequency range of the signal through signal frequency statistics, the optimal sampling rate is further calculated and set to ensure the integrity and accuracy of the signal.

[0126] Extract signal source characteristics according to the waveform data of the via misalignment signal, thereby obtaining signal source characteristic data, and set the trigger source according to the signal source data, thereby obtaining trigger source data;

[0127] In this embodiment, key features are extracted from the waveform data, such as the amplitude, phase, frequency, and rise and fall time of the signal. The time domain analysis technology is used to extract the features of each via signal, and the characteristics of the signal such as pulse width, waveform symmetry and waveform distortion are calculated. The spectrum characteristics of the signal are obtained by Fourier transform, so as to analyze the frequency characteristics of the signal source and the stability of the signal source. Further, according to the extracted signal source characteristics, such as frequency, amplitude, etc., a suitable trigger source is set. The trigger source determines the timing of signal acquisition, and is usually triggered according to a specific feature of the signal source (such as the amplitude exceeds a certain threshold or reaches a preset frequency). By analyzing the characteristics of each via signal source, a suitable trigger condition is set. The role of the trigger source is to determine the acquisition timing of the signal, so that the sampling instrument can collect when a specific change occurs in the signal. When setting the trigger source, it is necessary to select a specific feature of the signal (such as amplitude change, frequency response, etc.) as the trigger condition. For example, when the signal amplitude exceeds the set threshold (such as 500mV), the acquisition device starts sampling. The setting of the trigger source needs to be combined with the actual waveform data of the via signal and relies on the analysis of the waveform characteristics to ensure that the sampling instrument can effectively capture the key information in the signal.

[0128] Perform stability calculation based on the waveform data of the via misalignment signal, thereby obtaining the instability data of the via misalignment signal;

[0129] In this embodiment, the waveform of the via signal is sampled multiple times, and the amplitude of the waveform change in each sampling period is calculated. If the waveform of the signal changes greatly in multiple samplings, it means that the instability of the signal is high. Statistical methods such as standard deviation and variance can be used to quantify the instability of the signal. For example, by calculating the standard deviation of the signal in multiple periods, if the standard deviation exceeds a certain threshold (such as 10%), it is determined that the signal is unstable. The instability data helps to identify the source of faults in the signal, such as signal distortion or noise interference, and provides a basis for subsequent trigger mode settings.

[0130] A single trigger mode is set for the instability data of the via misalignment signal, thereby obtaining single trigger mode data;

[0131] In this embodiment, the instability characteristics of the via signal are analyzed, and the signal with higher instability is selected for single triggering. The single trigger mode means that the signal acquisition instrument only samples once when the signal is triggered, rather than continuously. Therefore, it is necessary to set the parameters of the trigger mode according to the instability value of the signal. For example, when the instability exceeds the set threshold (such as the standard deviation exceeds 5%), the acquisition device enters the single trigger mode and performs a signal capture. This operation can reduce the error during continuous sampling and focus on capturing abnormal changes in the signal.

[0132] The eye diagram is displayed according to the single trigger mode data and the trigger source data, so as to obtain the eye diagram data of the hole misalignment signal.

[0133] In this embodiment, in the single trigger mode, the via misalignment signal data is collected and an eye diagram is generated according to the signal trigger condition and the trigger source data. The eye diagram display shows the change trend of the signal waveform by superimposing the sampling data of multiple cycles. When generating the eye diagram, the signal waveform is captured according to the data of the single trigger mode, and the signal waveform is superimposed on the time axis. The opening size, waveform shape, etc. of the eye diagram are analyzed to determine whether the signal is stable. The eye diagram display helps to intuitively observe the distortion of the signal. The larger the opening of the eye diagram, the better the signal quality. Through further analysis of the eye diagram, the quality evaluation data of the via misalignment signal can be obtained.

[0134] Optionally, step S23 is specifically:

[0135] Step S231: Calculating the base point contact area of ​​the pad offset data to obtain base point contact area data;

[0136] In this embodiment, when the pad offset data is used to calculate the base point contact area, it is necessary to determine the specific geometric shape of the pad surface and the contact point. Based on the pad offset data of the printed circuit board, the two-dimensional plane coordinate information of the pad offset is extracted, and then the contact area of ​​the base point is calculated according to the geometric features of the pad (such as the roundness, squareness, etc. of the pad) and the relative position of the contact point. During the calculation, the contact area of ​​the pad surface is analyzed using a geometric algorithm. Considering that the pad surface is deformed due to factors such as thermal stress, the pad surface is accurately modeled using differential geometry methods. The base point contact area data is obtained by calculating the area size of the contact area. These contact area data are crucial for subsequent stress simulation, warpage analysis and other steps, and are usually automatically calculated using software tools (such as finite element analysis tools).

[0137] Step S232: performing stress distribution simulation on the base point contact area data, thereby obtaining base point contact stress distribution data;

[0138] In the present embodiment, when the base point contact area data is subjected to stress distribution simulation, a finite element model is constructed according to the geometric shape and material properties of the pad. Using the principle of structural mechanics, combined with the contact area data, stress analysis is performed. During specific operation, the contact area of ​​the pad is meshed using finite element analysis software (such as ANSYS, ABAQUS, etc.), and the mechanical properties of the material (such as Young's modulus, Poisson's ratio, etc.) are defined. External load conditions (such as temperature changes, mechanical pressure, etc.) and boundary conditions (such as the support of the pad) are applied, and the stress distribution in the contact area is obtained through simulation calculation. The stress distribution data includes the stress intensity of each contact point, which helps to determine whether there is an excessive stress concentration phenomenon in the pad. Through the stress simulation results, the weak areas in the pad can be identified, and a basis is provided for subsequent pad warpage analysis.

[0139] Step S233: performing pad warpage area identification on the pad offset data according to the base point contact stress distribution data and the base point contact area data, thereby obtaining the pad warpage area;

[0140] In this embodiment, it is necessary to combine the base point contact stress distribution data with the contact area data to identify the area on the pad surface where warping occurs due to stress concentration. Analyze the areas where the stress in the stress distribution data exceeds the set threshold, which are usually related to the offset, deformation or excessive thermal expansion of the pad. Based on the stress data, a threshold is set (for example, when the yield strength of the material is exceeded, it is the pad warping area). Then, a geometric analysis method is used to verify the actual deformation of these stress concentration areas through the base point contact area data to identify the warping area of ​​the pad. In the identification process, combined with experimental data or existing engineering standards (such as IPC-2221 standard), it is determined whether these areas meet the actual conditions of pad offset and warping. This step can locate the specific warping area of ​​the pad and provide specific data for subsequent thermal failure analysis.

[0141] Step S234: calculating the warpage ratio of the base point contact area data according to the pad warpage area, thereby obtaining the base point contact pad warpage ratio;

[0142] In this embodiment, it is necessary to determine the actual contact area of ​​the warping area based on the warping area obtained in the previous step, combined with the initial geometry and offset data of the pad. During the calculation, the area of ​​the warping area of ​​the pad is extracted and compared with the total contact area of ​​the pad. Use a geometric calculation tool (such as CAD software or a finite element simulation tool) to accurately measure the contact area of ​​the warping area, and use the ratio formula: warping ratio = contact area of ​​the warping area / total contact area to obtain the warping ratio of the pad. This ratio reflects the degree of influence of the pad warping on the contact area. If the warping ratio exceeds the preset standard (such as 10%), it affects the electrical connection quality of the pad. The calculation results of the warping ratio provide important reference data for subsequent thermal failure analysis.

[0143] Step S235: performing thermal failure simulation on the pad offset data according to the base point contact pad warpage ratio, thereby obtaining pad thermal expansion failure data.

[0144] In this embodiment, it is necessary to set the thermal expansion model of the pad according to the warpage ratio of the base point contact pad. The thermal failure of the pad is usually related to the mismatch of thermal expansion. Especially in the welding process, the uneven expansion caused by temperature change will aggravate the warpage, thereby causing electrical contact failure. During operation, the thermal expansion behavior of the pad is simulated using thermodynamic simulation software (such as ANSYS, COMSOL, etc.). During the simulation process, according to the warpage ratio and the thermal expansion coefficient of the pad material, the temperature change range is set (such as from room temperature to the welding temperature of 500°C), and the heat source conditions (such as the heat generated during the welding process) are applied. Through simulation, the stress and deformation of the pad in a thermal environment are obtained, and then whether thermal failure will occur is analyzed. The results of the thermal failure simulation will reflect whether the thermal expansion difference caused by temperature change will cause the contact failure of the pad, which is crucial to ensure the long-term stable operation of the pad.

[0145] Optionally, step S233 is specifically:

[0146] The pad warping contact stress threshold is set according to the base point contact stress distribution data, so as to obtain the pad warping contact stress threshold;

[0147] In this embodiment, when setting the pad warpage contact stress threshold, the stress peak area is extracted from the base point contact stress distribution data. These stress data are calculated based on the previous finite element simulation and the stress characteristics of the pad material, taking into account the stress changes to which the pad is subjected during the actual welding process. Through statistical analysis of these data, a contact stress threshold is set, usually based on the material yield strength of the pad and the contact conditions between the pad and the substrate. For example, the pad warpage contact stress threshold is set to 60% of the material yield strength, which means that when this stress value is exceeded, the pad will warp significantly. The threshold setting process also needs to be combined with experimental data or industry standards (such as IPC-2221) to verify whether the setting meets actual production requirements. This threshold will be used to identify potential warpage risk areas in subsequent steps.

[0148] The base point contact stress distribution data is divided into warpage risk areas according to the pad warpage contact stress threshold, so as to obtain pad warpage risk area data;

[0149] In this embodiment, when the base point contact stress distribution data is divided into warping risk areas according to the pad warping contact stress threshold, the base point contact stress distribution data is screened according to the threshold set in the previous step. By comparing the stress value of each contact point with the set contact stress threshold, those areas where the stress exceeds the threshold are screened out, and these areas are the pad warping risk areas. In specific implementation, data analysis software (such as MATLAB, NumPy library in Python, etc.) is used to compare the stress data with the threshold, mark the areas where the stress exceeds the standard, and form the warping risk area data. On this basis, the stress concentration degree, warping direction, etc. of these areas can be further analyzed to evaluate the probability of warping of the pad in subsequent use, and provide a basis for subsequent optimization design.

[0150] Monitor the change of base point contact area data to obtain base point contact area reduction data;

[0151] In this embodiment, it is necessary to collect historical data of the base point contact area and compare it with the current contact area data. At this time, the actual value of the base point contact area is obtained by image processing technology (for example, using laser scanning, image recognition technology or high-precision measurement tools). Using these data, time series analysis is performed to compare the changes in the base point contact area at different times. If the reduction in the base point contact area exceeds the set threshold (for example, more than 5%), it is marked as a reduction in contact area. In order to obtain accurate data change monitoring, a sensor data acquisition system (such as pressure sensors, contact sensors, etc.) is combined to perform real-time monitoring and data recording. The change monitoring results help to evaluate whether the contact performance of the pad is affected, thereby affecting the long-term reliability of the pad.

[0152] The pad warpage feature is fused according to the base point contact area reduction data and the pad warpage risk area data, so as to obtain the pad warpage data;

[0153] In this embodiment, the relationship between the two is analyzed by combining the base point contact area reduction data and the pad warpage risk area data. Based on the contact area reduction data, it can be inferred whether the contact condition of the pad has deteriorated. If the contact area is reduced and there is a warpage risk area at the same time, the failure risk of the pad is aggravated. At this time, the weighted average method or the multi-factor analysis method can be used to merge the reduction of the base point contact area with the severity of the warpage risk area to calculate the warpage risk index of the pad. During the fusion process, different weight coefficients need to be set according to the stress and contact area reduction of different risk areas. For example, the weight coefficient of the contact area reduction data can be set to 0.7, while the weight coefficient of the warpage risk area data is 0.3. Through feature fusion, a pad warpage data is finally obtained, which reflects the overall warpage risk of the pad and provides an important basis for the subsequent warpage area division.

[0154] The pad offset data is divided into warpage areas according to the pad warpage data, thereby obtaining the pad warpage area data.

[0155] In this embodiment, it is necessary to combine the pad warpage data obtained previously with the pad offset data. Analyze the original geometry of the pad and compare it with the offset of the pad during the actual welding process. Use the pad warpage data to calibrate the area where warpage occurs. The specific method includes using three-dimensional modeling technology (such as CAD software) to merge with the pad warpage data to obtain the actual warpage morphology of the pad under thermal stress. By setting a warpage threshold, if the pad offset area coincides with the high-risk area in the warpage data, the area is identified as the pad warpage area. Furthermore, image processing and geometric analysis technology are used to accurately mark the warpage area of ​​the pad, and the spatial position and offset data of these areas are recorded to provide a basis for subsequent product quality monitoring and optimized design.

[0156] Optionally, step S3 specifically includes:

[0157] Step S31: performing a binary conversion according to the X-ray scanning image of the printed circuit board, thereby obtaining a binary image of the printed circuit board;

[0158] In this embodiment, image data of the printed circuit board is obtained by X-ray scanning, and the image resolution needs to be ensured to be no less than 1000 DPI to ensure clear image details. Next, the image is grayed by applying an image processing algorithm to convert the color information of the image into a grayscale value. Then, the threshold method is used for binarization, and the pixels in the image whose grayscale value is greater than the set threshold (for example: the threshold is set to 150) are converted to white (255), and the remaining pixels are converted to black (0). This threshold is adjusted according to the actual test and image characteristics to ensure that the outlines of the solder joints and circuits in the image are clear. After the binarization process, the obtained image contains only black and white colors, which is convenient for subsequent feature extraction and analysis.

[0159] Step S32: performing Hough transform on the binary image of the printed circuit board to obtain solder joint area data;

[0160] In this embodiment, when performing the Hough transform, all edge information is first extracted from the binary image. The Canny edge detection algorithm is used to perform edge detection on the binary image to obtain the edge position of the solder joint and the line. Then, the Hough transform algorithm is applied to process the edge image to detect the straight line shape and identify the solder joint area. The Hough transform extracts the geometric features of the solder joint area by mapping the points in the image space to the Hough space and using the straight line representation method of the polar coordinate system. By setting a minimum threshold (for example, the circular area with a solder joint radius less than 1 mm is ignored), the solder joint and related areas can be accurately identified. Through this process, the obtained solder joint area data will provide a basis for subsequent width statistics and area division.

[0161] Step S33: performing linear width statistics according to the solder joint area data, thereby obtaining narrow linear width data;

[0162] In this embodiment, when performing linear width statistics, it is necessary to extract the center position and size of all welds through the weld area data. The connected region analysis method is used to identify adjacent linear regions in the weld area. The width of each weld or welding area is obtained by calculating the distance and width between adjacent welds. During the statistical process, the linear width of the weld area is divided into different categories by setting a threshold (for example, a linear region with a width less than 0.5 mm is regarded as a narrow linear region). The width data of all linear regions are counted to obtain narrow linear width data, which provides preliminary features for subsequent regional division, corrosion, expansion and crack analysis.

[0163] Step S34: dividing the solder joint area data into regions according to the narrow linear width data, thereby obtaining narrow linear width area data;

[0164] In this embodiment, when the weld area data is divided into regions, the regions in the weld area with a width less than a set value (e.g., less than 0.5 mm) are determined based on the narrow linear width data. These narrow regions are marked separately and distinguished from other width regions. A region growth algorithm (such as a Flood fill algorithm) is used to expand from the starting point of each narrow linear region along a path with a width less than 0.5 mm to form an independent narrow linear region. Through this process, narrow linear width region data can be obtained to further divide defective weld areas, which will affect welding quality or structural stability.

[0165] Step S35: performing corrosion according to the narrow linear width area data, thereby obtaining narrow linear width corrosion area data;

[0166] In this embodiment, when the narrow linear width area data is corroded, the narrow area is processed using a morphological corrosion operation (e.g., a 3x3 structural element) according to the shape of the solder joint area and its contour data. The corrosion operation shrinks the edge of the solder joint area by comparing each pixel value in the area with the minimum value of its neighborhood. This process helps to highlight the narrow part in the area and reduce background noise. By setting the number of corrosion operations (e.g., 5 corrosion operations), the processed area is more concentrated and unimportant small-scale changes are removed. Finally, the narrow linear width corrosion area data is obtained, which lays the foundation for subsequent expansion and crack analysis.

[0167] Step S36: dilating the narrow linear width eroded area data to obtain the narrow linear width dilated area data;

[0168] In this embodiment, the expansion operation is performed on the basis of the narrow linear width area data after corrosion, with the purpose of restoring the original shape of the area after corrosion. The corroded area is expanded using a morphological expansion operation (e.g., a 3x3 structural element). The expansion operation compares each pixel value in the area with the maximum value of its neighborhood, thereby expanding the edge of the weld area and restoring it to a larger area. By setting the number of expansions (e.g., 3 expansion operations), the influence range of the narrow area is expanded, and potential welding defect areas are further extracted. This process generates narrow linear width expansion area data, which is helpful for subsequent crack density and crack length analysis.

[0169] Step S37: performing crack density calculation on the narrow linear width expansion area data to obtain crack density data, and performing high-density area division on the narrow linear width expansion area data according to the crack density data to obtain high-density narrow linear area data;

[0170] In this embodiment, when calculating the crack density, it is necessary to identify all cracks or defects in the expansion area through morphological analysis. Use edge detection algorithms (such as Sobel operators) to extract crack edges and calculate the distribution density of these cracks in the narrow linear width expansion area. Crack density refers to the number of cracks per unit area or the sum of crack lengths. According to actual needs, a density threshold can be set (for example, crack density exceeds 10 / mm 2 By analyzing the crack distribution, the high-density crack area is further divided, and the high-density narrow linear area data is obtained, which helps to identify the parts with serious defects in the solder joint area.

[0171] Step S38: Calculate the crack length of the narrow linear width expansion area data to obtain crack length data, and perform length statistics on the narrow linear width expansion area data according to the crack length data to obtain long crack area data;

[0172] In this embodiment, the crack length is calculated by detecting the starting and ending positions of the cracks in the solder joint area and using image processing technology to extract the crack contour. The edge tracking algorithm is used to extract the complete path of the crack and calculate the length of the crack. According to the crack length data, different crack areas can be further divided. In particular, for longer cracks, a length threshold can be set (for example, cracks greater than 2 mm are considered long cracks). By counting the crack lengths, the long crack area data is obtained, which is used for subsequent regional intersection analysis and solder joint area fracture prediction.

[0173] Step S39: performing a region intersection operation based on the high-density narrow linear region data and the long crack region data to obtain the weld region fracture data.

[0174] In this embodiment, the regional intersection operation extracts the regions that meet both conditions by overlapping and analyzing the high-density narrow linear region data with the long crack region data. These regions contain both high-density crack regions and long crack regions, indicating that these regions have serious welding defects. The intersection calculation of the two regions is performed using geometric operations or image analysis software (such as OpenCV or MATLAB) to obtain the weld region fracture data. Through this process, high-risk regions of fracture in the weld can be identified, and timely measures can be taken to repair or optimize the welding process.

[0175] Optionally, the present specification also provides a computer-readable storage medium storing a computer program, wherein when the computer program is executed by a processor, the deep learning method for printed circuit board defect identification described in any one of the above is implemented.

[0176] Optionally, the present specification also provides a deep learning system for printed circuit board defect recognition, which is used to execute the deep learning method for printed circuit board defect recognition as described above, and the deep learning system for printed circuit board defect recognition includes:

[0177] A circuit board interlayer misalignment detection module is used to obtain an X-ray scanning image of a printed circuit board and perform interlayer misalignment detection on the X-ray scanning image of the printed circuit board, thereby obtaining interlayer misalignment data of the circuit board;

[0178] The circuit board conduction failure analysis module is used to extract via misalignment features and pad offset features according to the inter-layer misalignment data of the circuit board, so as to obtain via misalignment data and pad offset data; conduction failure analysis is performed according to the via misalignment data and pad offset data, so as to obtain circuit board conduction failure data;

[0179] The solder joint area fracture detection module is used to perform binary conversion according to the X-ray scanning image of the printed circuit board, so as to obtain the binary image of the printed circuit board; perform solder joint area recognition according to the binary image of the printed circuit board, so as to obtain solder joint area data; perform fracture detection according to the solder joint area data, so as to obtain solder joint area fracture data;

[0180] The circuit board defect recognition module is used to construct a defect recognition model based on the circuit board conduction failure data and the solder joint area fracture data, so as to obtain the circuit board defect recognition model; according to the circuit board defect recognition model, the X-ray scanning image of the printed circuit board is used to identify defects, so as to obtain the printed circuit board defect data, and upload it to the printed circuit board management platform to perform the defect recognition task.

[0181] A deep learning system for printed circuit board defect identification of the present invention can implement any deep learning method for printed circuit board defect identification of the present invention, and is used to combine the operations between various modules and the medium of signal transmission to complete the deep learning method for printed circuit board defect identification. The internal modules of the system cooperate with each other to improve the accuracy and efficiency of defect detection.

[0182] Therefore, the embodiments should be regarded as illustrative and non-restrictive from all points, and the scope of the present invention is limited by the appended claims rather than the above description, and it is intended that all changes falling within the meaning and range of equivalent elements of the application documents are included in the present invention.

[0183] The above description is only a specific embodiment of the present invention, so that those skilled in the art can understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but should conform to the widest scope consistent with the principles and novel features invented herein.

Claims

1. A deep learning method for printed circuit board defect recognition, characterized in that: The following steps are involved: Step S1: obtaining an X-ray scanning image of a printed circuit board, and performing interlayer misalignment detection on the X-ray scanning image of the printed circuit board, thereby obtaining interlayer misalignment data of the circuit board; Step S2: extracting via misalignment features and pad offset features based on the inter-layer misalignment data of the circuit board, thereby obtaining via misalignment data and pad offset data; performing conduction failure analysis based on the via misalignment data and pad offset data, thereby obtaining circuit board conduction failure data; Step S3: performing binary conversion according to the X-ray scanning image of the printed circuit board, thereby obtaining a binary image of the printed circuit board; performing solder joint area recognition according to the binary image of the printed circuit board, thereby obtaining solder joint area data; Perform fracture detection according to the solder joint area data, thereby obtaining the solder joint area fracture data; Step S4: construct a defect recognition model based on the circuit board conduction failure data and the solder joint area fracture data to obtain the circuit board defect recognition model; perform defect recognition on the printed circuit board X-ray scanning image according to the circuit board defect recognition model to obtain the printed circuit board defect data, and upload it to the printed circuit board management platform to perform the defect recognition task.

2. The deep learning method for printed circuit board defect recognition according to claim 1, characterized in that: Step S1 is specifically as follows: Step S11: Acquire an X-ray scanning image of a printed circuit board; Step S12: performing interlayer edge detection according to the X-ray scanning image of the printed circuit board, thereby obtaining interlayer edge data; Step S13: acquiring inter-layer template data, and performing inter-layer template matching on inter-layer edge data according to the inter-layer template data, thereby obtaining inter-layer template matching data; Step S14: Calculating the inter-layer offset according to the inter-layer template matching data, thereby obtaining inter-layer offset data; Step S15: marking the dislocation area of ​​the interlayer edge data according to the interlayer offset data, so as to obtain the interlayer dislocation data of the circuit board.

3. The deep learning method for printed circuit board defect recognition according to claim 1, characterized in that: Step S2 is specifically as follows: Step S21: extracting via misalignment features and pad offset features based on the inter-layer misalignment data of the circuit board, thereby obtaining via misalignment data and pad offset data; Step S22: performing electrical conduction failure analysis on the via misalignment data, thereby obtaining via electrical conduction failure data; Step S23: performing thermal expansion failure analysis on the pad offset data, thereby obtaining pad thermal expansion failure data; Step S24: integrating the circuit board conduction failure data according to the via electrical conduction failure data and the pad thermal expansion failure data, thereby obtaining the circuit board conduction failure data.

4. The deep learning method for printed circuit board defect recognition according to claim 3, characterized in that: Step S22 is specifically as follows: Step S221: performing signal waveform statistics on the via misalignment data, thereby obtaining via misalignment signal waveform data; Step S222: performing an eye diagram test according to the via misalignment signal waveform data, thereby obtaining the via misalignment signal eye diagram data; Step S223: Acquire standard eye height data of via signal and standard eye width data of via signal; Step S224: comparing the eye diagram data of the via misalignment signal with the standard eye height data of the via signal, so as to obtain the via signal data with insufficient eye height; Step S225: comparing the eye diagram data of the via misalignment signal with the standard eye width data of the via signal, thereby obtaining the via signal data with insufficient eye width; Step S226: performing electrical conduction failure intersection operation according to the via signal data of insufficient eye height and the via signal data of insufficient eye width, so as to obtain via electrical conduction failure data.

5. The deep learning method for printed circuit board defect recognition according to claim 4, characterized in that: Step S222 is specifically as follows: Perform signal frequency statistics according to the waveform data of the via misalignment signal, thereby obtaining signal frequency data; The sampling rate is set according to the signal frequency data, thereby obtaining the sampling rate data; Extract signal source characteristics according to the waveform data of the via misalignment signal, thereby obtaining signal source characteristic data, and set the trigger source according to the signal source data, thereby obtaining trigger source data; Perform stability calculation based on the waveform data of the via misalignment signal, thereby obtaining the instability data of the via misalignment signal; A single trigger mode is set for the instability data of the via misalignment signal, thereby obtaining single trigger mode data; The eye diagram is displayed according to the single trigger mode data and the trigger source data, so as to obtain the eye diagram data of the hole misalignment signal.

6. The deep learning method for printed circuit board defect recognition according to claim 3, characterized in that: Step S23 is specifically as follows: Step S231: performing base point contact area calculation on the pad offset data, thereby obtaining base point contact area data; Step S232: performing stress distribution simulation on the base point contact area data, thereby obtaining base point contact stress distribution data; Step S233: identifying the pad warping area of ​​the pad offset data according to the base point contact stress distribution data and the base point contact area data, thereby obtaining the pad warping area; Step S234: calculating the warpage ratio of the base point contact area data according to the pad warpage area, thereby obtaining the base point contact pad warpage ratio; Step S235: performing thermal failure simulation on the pad offset data according to the base point contact pad warpage ratio, thereby obtaining pad thermal expansion failure data.

7. The deep learning method for printed circuit board defect recognition according to claim 6, characterized in that: Step S233 is specifically as follows: The pad warping contact stress threshold is set according to the base point contact stress distribution data, so as to obtain the pad warping contact stress threshold; The base point contact stress distribution data is divided into warpage risk areas according to the pad warpage contact stress threshold, so as to obtain pad warpage risk area data; Monitor the change of base point contact area data to obtain base point contact area reduction data; The pad warpage feature is fused according to the base point contact area reduction data and the pad warpage risk area data, so as to obtain the pad warpage data; The pad offset data is divided into warpage areas according to the pad warpage data, thereby obtaining the pad warpage area data.

8. The deep learning method for printed circuit board defect recognition according to claim 1, characterized in that: Step S3 is specifically as follows: Step S31: performing a binary conversion according to the X-ray scanning image of the printed circuit board, thereby obtaining a binary image of the printed circuit board; Step S32: performing Hough transform on the binary image of the printed circuit board to obtain solder joint area data; Step S33: performing linear width statistics according to the solder joint area data, thereby obtaining narrow linear width data; Step S34: dividing the solder joint area data into regions according to the narrow linear width data, thereby obtaining narrow linear width area data; Step S35: performing corrosion according to the narrow linear width area data, thereby obtaining narrow linear width corrosion area data; Step S36: dilating the narrow linear width eroded area data to obtain the narrow linear width dilated area data; Step S37: performing crack density calculation on the narrow linear width expansion area data to obtain crack density data, and performing high-density area division on the narrow linear width expansion area data according to the crack density data to obtain high-density narrow linear area data; Step S38: Calculate the crack length of the narrow linear width expansion area data to obtain crack length data, and perform length statistics on the narrow linear width expansion area data according to the crack length data to obtain long crack area data; Step S39: performing a region intersection operation based on the high-density narrow linear region data and the long crack region data to obtain the weld region fracture data.

9. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the deep learning method for printed circuit board defect identification as described in any one of claims 1 to 8 is implemented.

10. A deep learning system for printed circuit board defect recognition, characterized in that: A deep learning method for printed circuit board defect recognition as claimed in claim 1, wherein the deep learning system for printed circuit board defect recognition comprises: A circuit board interlayer misalignment detection module is used to obtain an X-ray scanning image of a printed circuit board and perform interlayer misalignment detection on the X-ray scanning image of the printed circuit board, thereby obtaining interlayer misalignment data of the circuit board; The circuit board conduction failure analysis module is used to extract via misalignment features and pad offset features according to the inter-layer misalignment data of the circuit board, so as to obtain via misalignment data and pad offset data; conduction failure analysis is performed according to the via misalignment data and pad offset data, so as to obtain circuit board conduction failure data; The solder joint area fracture detection module is used to perform binary conversion according to the X-ray scanning image of the printed circuit board, so as to obtain the binary image of the printed circuit board; perform solder joint area recognition according to the binary image of the printed circuit board, so as to obtain solder joint area data; perform fracture detection according to the solder joint area data, so as to obtain solder joint area fracture data; The circuit board defect recognition module is used to construct a defect recognition model based on the circuit board conduction failure data and the solder joint area fracture data, so as to obtain the circuit board defect recognition model; according to the circuit board defect recognition model, the X-ray scanning image of the printed circuit board is used to identify defects, so as to obtain the printed circuit board defect data, and upload it to the printed circuit board management platform to perform the defect recognition task.

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