Display panel and display device

Abstract

The display panel and the display device provided by the embodiment of the present application are characterized in that: the display area and the lower frame area in the display panel are arranged along a first direction, the lower frame area comprises a plurality of pins; the number of pixels arranged along the first direction in the display panel is N1, the number of pixels arranged along a second direction is N2, N1>N2, the first direction intersects the second direction; the display panel is provided with scan lines extending along the first direction and electrically connected with the plurality of pixels arranged along the first direction. The embodiment of the present application is beneficial to driving the pixels by the scan lines column by column, thereby reserving more time for the pixels in each column to write data voltage under the same refresh frequency, preparing for the display panel to have a display technology with a higher refresh frequency, and is beneficial to improving the time for each pixel in the display panel to receive data voltage under the same refresh frequency, thereby improving the accuracy of the data voltage received by the pixels, improving the luminous brightness accuracy of the pixels, and improving the display effect of the display panel in high-frequency operation.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0002] A plurality of pixels are included in the display panel, and in the case of high-frequency operation of the display panel, the pixel charging time is insufficient, which can cause the data voltage received by the pixel to be inaccurate, and is not conducive to the display panel adapting to high-frequency operation and improving the display effect of the display panel. SUMMARY

[0003] Therefore, the present application provides a display panel and a display device to solve the above problems.

[0004] In a first aspect, the present application provides a display panel, comprising: a display area and a lower frame area, the display area and the lower frame area are arranged along a first direction, the lower frame area comprises a plurality of pins;

[0005] A plurality of pixels, the number of pixels arranged along the first direction is N1, the number of pixels arranged along the second direction is N2, N1>N2, the first direction intersects the second direction; a plurality of scanning lines arranged along the second direction, the scanning lines extend along the first direction and are electrically connected to the plurality of pixels arranged along the first direction.

[0006] In a second aspect, the present application provides a display device comprising the display panel of the first aspect.

[0007] In the present application, the scanning lines in the display panel are arranged to extend in the first direction and arranged in the second direction, which is conducive to driving the pixels column by column, thereby reserving more time for the pixels in each column to write data voltage under the same refresh frequency, preparing the display panel for higher refresh frequency display technology, and improving the time for each pixel in the display panel to receive data voltage under the same refresh frequency, thereby improving the accuracy of the data voltage received by the pixel, improving the luminous brightness accuracy of the pixel, and improving the display effect of the display panel in high-frequency operation. BRIEF DESCRIPTION OF DRAWINGS

[0008] In order to more clearly illustrate the technical solutions of the present application, the following will briefly introduce the drawings needed in the embodiments. Obviously, the drawings described below are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0009] Figure 1 A plan view of a display panel provided by the present application is shown in the following figure.

[0010] Figure 2 A plan view of still another display panel provided by an embodiment of the present application;

[0011] Figure 3 A plan view of still another display panel provided by an embodiment of the present application;

[0012] Figure 4 A plan view of still another display panel provided by an embodiment of the present application; Figure 2 A sectional view along the direction of A-A' of the display panel provided by the embodiment of the present application;

[0013] Figure 5 A plan view of still another display panel provided by an embodiment of the present application;

[0014] Figure 6 A plan view of still another display panel provided by an embodiment of the present application;

[0015] Figure 7 A plan view of still another display panel provided by an embodiment of the present application;

[0016] Figure 8 A plan view of still another display panel provided by an embodiment of the present application;

[0017] Figure 9 A plan view of still another display panel provided by an embodiment of the present application; Figure 6 A sectional view along the direction of B-B' of the display panel provided by the embodiment of the present application;

[0018] Figure 10 A plan view of still another display panel provided by an embodiment of the present application;

[0019] Figure 11 A plan view of still another display panel provided by an embodiment of the present application;

[0020] Figure 12 A plan view of still another display panel provided by an embodiment of the present application;

[0021] Figure 13 A plan view of still another display device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0022] In order to better understand the technical solutions of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0023] It should be clear that the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor fall within the scope of protection of the present application.

[0024] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The singular forms “a,” “the,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0025] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0026] In the description of this specification, it should be understood that the terms "substantially", "approximately", "about", "about", "generally", "largely" used in the claims and embodiments of this application refer to values ​​that can be generally agreed upon within a reasonable range of process operations or tolerances, rather than a precise value.

[0027] It should be understood that although terms such as "first," "second," etc., may be used to describe directions, connecting lines, etc., in the embodiments of this application, these should not be limited to these terms. These terms are only used to distinguish directions, connecting lines, etc., from one another. For example, without departing from the scope of the embodiments of this application, a first direction may also be referred to as a second direction, and similarly, a second direction may also be referred to as a first direction. Through meticulous and in-depth research, the applicant of this case has provided a solution to the problems existing in the prior art.

[0028] Figure 1 This is a plan view of a display panel provided in an embodiment of this application.

[0029] This application provides a display panel 100, such as... Figure 1 As shown, the display panel 100 includes a display area A10 and a lower border area A20, which are arranged along a first direction X1. The lower border area A20 includes a plurality of pins. Optionally, the plurality of pins in the lower border area A20 of the display panel 100 can be used to transmit data voltage, panel control signals, etc., and at least a portion of the plurality of pins in the lower border area A20 is electrically connected to a flexible circuit board. In this embodiment, the direction in which the lower border area A20 and the display area A10, including pins, are arranged along the first direction X1 in the display panel 100 is taken as the column direction for description.

[0030] The display panel 100 further includes a plurality of pixels 10, the number of pixels 10 arranged along the first direction X1 is N1, the number of pixels 20 arranged along the second direction X2 is N2, N1>N2, and the first direction X1 intersects the second direction X2. In combination with the above, it can be seen that the display area A10 and the lower frame area A20 of the display panel 100 are arranged along the column direction, and accordingly, the second direction X2 is the row direction. Then, the number of pixels 10 in the display panel 100 in the first direction X1 is greater than the number of pixels 10 arranged in the second direction X2, and the display panel 100 provided in the embodiment of the present application has a shape of a panel with a length in the column direction greater than a length in the row direction. For example, the display panel 100 included in a display device such as a mobile phone or a vertical computer display screen.

[0031] In the related art, when the display panel 100 is working, the pixels 10 are usually scanned row by row, and the pixels 10 turned on by scanning driving start to receive the data voltage Vdata, and the same data line is electrically connected to a plurality of pixels 10 arranged along the first direction X1. Thus, the same data line also writes the data voltage Vdata to the plurality of pixels 10 arranged in the first direction X1 one by one. It can be understood that in the process of turning on the pixels 10 row by row, the time left for each row of pixels 10 to write the data voltage Vdata is the time left for a row of pixels 10 to be turned on at a frame refresh frequency. For example, when the refresh frequency of a frame in the display panel 100 is 120 Hz, and the number of pixel rows in the display panel 100 is 2800, for example, the time left for each row of pixels 10 to write data is about 2.9 μs, which is close to the time limit of charging the pixels 10. However, in order to further improve the refresh frequency of the display panel 100, the challenge of insufficient charging time of the pixels 10 also exists, especially under high-frequency driving, there is a serious problem of display quality uniformity.

[0032] In order to improve the charging time of the display panel 100 to the pixels 10 under high frequency, ensure that the pixels 10 can also receive accurate data voltage under high-frequency driving of the display panel 100, so as to generate accurate luminous brightness, improve the display effect of the display panel 100 under high-frequency working, the technical scheme of the present application is proposed.

[0033] In the embodiment of the present application, the display panel 100 further comprises a plurality of scan lines 20 arranged along the second direction X2. Optionally, the scan lines 20 are used to drive the pixels 10 to turn on and receive the data voltage Vdata. The scan lines 20 extend along the first direction X1 and are electrically connected with the plurality of pixels 10 arranged along the first direction X1. Thus, the scan lines 20 extend in the column direction, and the plurality of scan lines 20 arranged along the second direction X2 transmit effective signals in sequence to drive the pixels 10 to turn on and receive the data voltage Vdata. At this time, the plurality of pixels 10 in the display panel 100 are turned on in columns, and the pixels 10 are scanned column by column. In combination with the above, it can be seen that the number of the pixels 10 arranged along the first direction X1 in the display panel 100 provided in the embodiment of the present application is greater than the number of the pixels 10 arranged along the second direction X2, and thus the number of times of scanning the pixels 10 according to the pixel columns is less than the number of times of scanning the pixels 10 according to the pixel rows, which is conducive to increasing the time reserved for each pixel 10 to write data under the same refresh frequency. For example, when the refresh frequency of a frame in the display panel 100 is 120 Hz, and the number of the pixel rows in the display panel 100 is 2800 rows and the number of the pixel columns is 1260 columns, the time reserved for the pixels 10 in each column to write data is increased to about 6.2 μs, and it can be seen that the time reserved for the pixels 10 to charge is relatively sufficient. Thus, when the refresh frequency of the display panel 100 is increased, for example, the refresh frequency of the same display panel 100 is increased to 165 Hz, the time reserved for the pixels 10 in each column to write data is about 4.52 μs, which is still a relatively ideal charging time.

[0034] In the embodiment of the present application, the scan lines 20 in the display panel 100 extend along the first direction X1 and are arranged along the second direction X2, which is conducive to driving the pixels 10 column by column by the scan lines 20, thereby reserving more time for the pixels 10 in each column to write data voltage under the same refresh frequency, preparing for the display panel 100 to have a higher refresh frequency display technology, and improving the time for each pixel 10 in the display panel 100 to receive the data voltage Vdata under the same refresh frequency, thereby improving the accuracy of the data voltage Vdata received by the pixels 10, improving the luminance accuracy of the pixels 10, and improving the display effect of the display panel 100 in high-frequency operation.

[0035] Figure 2 A plan view of another display panel provided in the embodiment of the present application.

[0036] In one embodiment of the present application, as Figure 2As shown, the display panel 100 further includes a frame area AA0, the frame area AA0 includes a lower frame area A20 and a side frame area A30, and the frame area AA0 surrounds the display area A10. The frame area A40 of the display panel 100 can be used to protect the display area A10 and can be used to prepare various circuits for driving the display panel 100 to work. The side frame area A30 includes a first sub-frame area A31, and the first sub-frame area A31 is located on opposite sides of the display area A10 in the second direction X2.

[0037] The display panel 100 further includes a plurality of cascaded shift register circuits 30, and at least part of the shift register circuits 30 are located in the first sub-frame area A31. Since the length of the display panel 100 in the first direction X1 is greater than the length in the second direction X2, and the length of the first sub-frame area A31 is greater than the length of the lower frame area A20, preparing the plurality of cascaded shift register circuits 30 in the first sub-frame area A31 is beneficial to provide sufficient space for the preparation of the shift register circuits 30 and avoid circuit congestion between the shift register circuits 30.

[0038] The shift register circuit 30 includes an output terminal 301, and the display area A10 further includes a plurality of first connection lines SL1, and at least part of the scan lines 20 are electrically connected to the output terminal 301 of the shift register circuit 30 through the first connection lines SL1. In the embodiments of the present application, the shift register circuit 30 is taken as an example to generate an enable signal for controlling the pixel 10 to start receiving the data voltage Vdata, and of course in some other embodiments, the shift register circuit 30 can be used to generate other control signals, and the scan line 20 can be used to transmit other control signals. The shift register circuit 30 is electrically connected to the scan line 20, and since the display panel 100 in the embodiments of the present application is refreshed by column by column, and the number of pixel columns is less than the number of pixel rows, which is beneficial to reduce the number of shift register circuits 30 prepared in the display panel 100.

[0039] In the embodiments of the present application, the scan lines 20 in the display panel 100 are arranged to scan column by column, which is beneficial to reduce the number of shift register circuits 30 prepared, reduce the circuit preparation cost of the display panel 100, and improve the preparation efficiency. Moreover, referring to Figure 2 As shown, the shift register circuit 30 and the scan line 20 are electrically connected through the first connection line SL1, which is beneficial to make the electrical connection between the shift register circuit 30 and the scan line 20 in the display area A10, thereby avoiding the problem of increasing the wiring distance when the shift register circuit 30 and the scan line 20 are wired in the frame area AA0, and is also beneficial to reduce the wiring congestion degree in the frame area AA0.

[0040] Figure 3 Another planar schematic view of a display panel provided in the embodiments of the present application.

[0041] In an embodiment of the present application, as shown in Figure 3 The frame area AA0 further includes an upper frame area A32, and the upper frame area A32 and the lower frame area A20 are respectively located on opposite sides of the display panel 100 in the first direction X1.

[0042] In an embodiment of the present application, at least part of the shift register circuit 30 is arranged in the upper frame area A32, which is conducive to reducing the space pressure of manufacturing the shift register circuit 30 in the first sub-frame area A31. Moreover, the shift register circuit 30 is electrically connected with the scan line 20, and the scan line 20 extends along the first direction X1. When the shift register circuit 30 is arranged in the upper frame area A32, it is conducive to aligning at least part of the shift register circuit 30 with the corresponding column of pixels 10 in the first direction X1, which provides conditions for directly electrically connecting the output end 301 of the shift register circuit 30 with the scan line 20, thereby facilitating the reduction of the number of first connection lines SL1 to be manufactured. Alternatively, the distance between part of the shift register circuit 30 manufactured in the upper frame area A32 and the corresponding column of pixels is also closer, which is conducive to reducing the winding distance of part of the first connection line SL1.

[0043] When at least part of the shift register circuit 30 is arranged in the upper frame area A32, as shown in Figure 3 It is conducive to distributing the manufacturing of the shift register circuit 30 in the first sub-frame area A31 and the upper frame area A32, and it is possible that the shift register circuit 30 does not completely occupy the first sub-frame area A31 and the upper frame area A32. It is conducive to manufacturing the shift register circuit 30 in a way of semi-surrounding the display area A10, reserving space in the first sub-frame area A31 and the upper frame area A32 for manufacturing the power line and other global traces, which is conducive to making the distribution of the traces in the display panel 100 more uniform, and avoiding the problem of signal deviation caused by trace impedance due to the distribution of the traces in different positions of the display panel 100.

[0044] Figure 4 A cross-sectional view of the present application along the direction of A-A' is provided. Figure 2

[0045] In an embodiment of the present application, in combination with Figure 2 , Figure 4 ​As shown, the first connection line SL1 and the scan line 20 are arranged in different film layers. In the embodiment of the present application, the scan line 20 is arranged in the display area A10 and electrically connected to the plurality of pixels 10 along the first direction X1, and at least part of the shift register circuit 30 is arranged in the first sub-frame area A31. The shift register circuit 30 is arranged in the second direction X2, and at least part of the first connection line SL1 in the display area A10 extends to the position of the scan line 20 along the second direction X2. Therefore, arranging the scan line 20 and the first connection line SL1 in different film layers can avoid the case that the two are arranged in the same layer, thereby ensuring the accuracy of the control signal transmitted by the scan line 20. Alternatively, the first connection line SL1 and the scan line 20 are electrically connected by punching.

[0046] Figure 5 Another planar schematic diagram of a display panel is provided in the embodiment of the present application.

[0047] In one embodiment of the present application, as shown in Figure 5 The display panel 100 further includes a first power signal line SL2 and a second power signal line SL3. At least part of the first power signal line SL2 and / or at least part of the second power signal line SL3 are arranged in the frame area AA0. Alternatively, the first power signal line SL2 is used to transmit a positive voltage PVDD to the display panel 100, and the second power signal line SL3 is used to transmit a negative voltage PVEE to the display panel 100. Alternatively, the first power signal line SL2 and the second power signal line SL3 are used to transmit a positive voltage PVDD, a negative voltage PVEE, a reset voltage Vref, a compensation data voltage DVH, and other global signals.

[0048] In the embodiment of the present application, at least part of the shift register circuit 30 is arranged in a first region A311 in the first sub-frame area A31, and at least part of the first power signal line SL2 and / or at least part of the second power signal line SL3 are arranged in a second region A312 in the first sub-frame area A31. The first region A311 and the second region A312 are arranged along the first direction X1, which is beneficial to arranging at least one of the first power signal line SL2 and the second power signal line SL3 in the first sub-frame area A31, which is left empty by reducing the number of shift register circuits 30. This is beneficial to improving the distribution of the first power signal line SL2 and the second power signal line SL3 in the display panel 100, thereby improving the uniformity of the display panel 100 and solving the problem of voltage drop of the signal line in the display panel 100. It should be noted that the first power signal line SL2 and the second power signal line SL3 are not only arranged in the first sub-frame area A31, but also arranged in other positions in the display panel 100.

[0049] Figure 6 Another planar schematic view of a display panel is provided in an embodiment of the present application.

[0050] In an embodiment of the present application, as shown in Figure 6 the pixel 10 includes the sub-pixel 101, and the display panel 100 further includes a plurality of data lines 40 extending along the second direction X2 and electrically connected with the plurality of sub-pixels 101 arranged along the second direction X2. Optionally, the plurality of sub-pixels 101 arranged along the first direction X1 are different in color. The plurality of sub-pixels 101 distributed along the second direction X2 are electrically connected with the same data line 40, and the data line 40 sequentially inputs the data voltage Vdata to the plurality of sub-pixels 101 distributed along the second direction X2.

[0051] In an embodiment of the present application, the plurality of data lines 40 extending along the second direction X2 and electrically connected with the plurality of sub-pixels 101 arranged along the second direction X2 are provided, which is conducive to making the data line 40 transmit the data voltage Vdata to the sub-pixel 101 which is turned on column by column, and is conducive to realizing the pixel 10 which is turned on column by column in the embodiment of the present application, thereby increasing the data writing time for each pixel 10.

[0052] In an embodiment of the present application, continuing to refer to Figure 6 the display area A10 includes a plurality of second connection lines SL4, and the lower frame area A20 includes a plurality of data lead lines P1, and at least part of the data lines 40 are electrically connected with the data lead lines P1 of the lower frame area A20 through the second connection lines SL4. Optionally, the data lead lines P1 can be used to provide different data voltages Vdata to the data lines 40.

[0053] From the above, it can be seen that the number of the pixels 10 in the first direction X1 is greater than that in the second direction X2 in the embodiment of the present application, and accordingly, the number of the sub-pixels 101 arranged along the first direction X1 is greater than that arranged along the second direction X2 in the display panel 100. Taking an example that one data line 40 is electrically connected with each row of sub-pixels 101, the number of the data lines 40 which need to be electrically connected in the display panel 100 greatly increases, and accordingly, the number of the data lead lines P1 required by the increase of the number of the data lines 40 also increases.

[0054] In an embodiment of the present application, the data lead lines P1 are electrically connected with the data lines 40 through the second connection lines SL4 located in the display area A10, and referring to Figure 6As shown, one end of the second connection line SL4 is electrically connected with the data lead P1, and the other end is electrically connected with the data line 40 in the display area A10. This is conducive to reducing the position correspondence condition of the data lead P1 and the data line 40, and can also achieve good electrical connection of the data lead P1 and the data line 40, and is conducive to reducing the wiring preparation pressure in the lower frame area A20 by winding in the display area A10 through the second connection line SL4, and is conducive to achieving the condition of increasing the number of data lines 40 in the technical scheme of the present application, and better completing the technical scheme of driving the pixels 10 by columns in the embodiment of the present application.

[0055] Figure 7 A plan view of another display panel provided in an embodiment of the present application is shown in FIG. 6. Figure 8 A plan view of another display panel provided in an embodiment of the present application is shown in FIG. 6.

[0056] In an embodiment of the present application, as shown in FIG. 1, Figures 7-8 As shown, the display panel 100 further includes a side frame area A30, and the side frame area A30 further includes a first sub-frame area A31, and the first sub-frame area A31 is located on opposite sides of the display area A10 in the second direction X2.

[0057] In an embodiment of the present application, as shown in FIG. 1, Figure 7 As shown, a plurality of data leads P1 arranged along the first direction X1 are arranged in the first sub-frame area A31, and the data line 40 is electrically connected with the data lead P1. Alternatively, as shown in FIG. 6, Figure 8 As shown, the data lead P1 is arranged in the first sub-frame area A31 and the lower frame area A20. Alternatively, the data lead P1 is arranged in the part of the first sub-frame area A31 where the shift register circuit 30 is not arranged. In the embodiment of the present application, the data lead P1 is arranged in the first sub-frame area A31, which is conducive to reducing the wiring preparation pressure in the lower frame area A20. Furthermore, the first sub-frame area A31 is adjacent to the display area A10 in the second direction X2, and the data line 40 extends along the second direction X2, so that at least part of the data lead P1 is arranged to correspond to the data line 40 in the second direction X2, so that the data line 40 and the data lead P1 are directly electrically connected without the second connection line SL4, which is conducive to reducing the number of second connection lines SL4 arranged in the display area A10, thereby providing more available space for the display panel 100.

[0058] In an embodiment of the present application, continuing to refer to Figures 6-8As shown, a first gap M1 is arranged between two adjacent pixels 10, and the at least partial second connection line SL4 passes through the first gap M1 to be electrically connected with the data line 40. This facilitates the electrical connection between the data lead P1 and the data line 40 through the second connection line SL4, and the second connection line SL4 can pass through multiple first gaps M1 when winding in the display area A10, which facilitates the flexibility in the process of manufacturing the second connection line SL4 and makes the wiring more reasonable.

[0059] In an embodiment of the present application, with continued reference to Figures 6-8 As shown, N3 second connection lines SL4 pass through the first gap M1, and N3≥1.

[0060] In the embodiment of the present application, multiple second connection lines SL4 can pass through the same first gap M1. For example, the number of the second connection lines SL4 is equal to that of the data lines 40, which facilitates the utilization of the wiring space in the display panel 100 when the number of the data lines 40 increases, and achieves the electrical connection between the data lines 40 and the data lead P1.

[0061] Figure 9 A display panel provided in an embodiment of the present application includes Figure 6 A cross-sectional view of the display panel along the direction of B-B'.

[0062] In an embodiment of the present application, with continued reference to Figure 6 、 Figure 9 As shown, the second connection line SL4 and the data line 40 are arranged in different film layers. As described above, part of the data lead P1 is arranged in the lower frame area A20, so the second connection line SL4 may have a part of the wiring extending along the first direction X1 when winding to be electrically connected with the data line 40, while the data line 40 extends along the second direction X2. Therefore, the second connection line SL4 and the data line 40 are arranged in different film layers, which facilitates the avoidance of the intersection of the second connection line SL4 and the data line 40 in the same film layer, thereby ensuring the transmission of accurate data voltage Vdata by the data line 40. Alternatively, the second connection line SL4 and the data line 40 are electrically connected through punching.

[0063] In some other embodiments, most of the second connection line SL4 and the data line 40 can be arranged in the same film layer, and the second connection line SL4 and the data line 40 can cross the film layer when winding at the intersection position, thereby avoiding the intersection of the second connection line SL4 and the data line 40 in the same film layer.

[0064] Figure 10 A plan view of a display panel provided in an embodiment of the present application.

[0065] In an embodiment of the present application, as Figure 10As shown, the display panel 100 further includes a plurality of multiplexing circuits 50, each of which includes a plurality of switches 501, the input ends of the plurality of switches 501 of the multiplexing circuit 50 are electrically connected to the same data lead P1, and the output ends of the plurality of switches 501 of the multiplexing circuit 50 are respectively electrically connected to different data lines 40. The control ends of the switches 501 in the same multiplexing circuit 50 are respectively electrically connected to different control signal lines, so that the plurality of switches 501 are opened in time division. Alternatively, the switches 501 of the multiplexing circuit 50 provided in the embodiment of the present application are switch transistors. In combination with the technical solution of the plurality of pixels 10 being driven column by column provided in the embodiment of the present application, the plurality of data lines 40 to which the plurality of switches 501 of the multiplexing circuit 50 are electrically connected are respectively electrically connected to different rows of sub-pixels 101. When a certain column of sub-pixels 101 in the display panel 100 starts to receive the data voltage Vdata, the data lead P1 electrically connected to the multiplexing circuit 50 sequentially transmits the data voltage Vdata required by the plurality of sub-pixels 101 located in different rows.

[0066] In the embodiment of the present application, the display panel 100 is provided with a plurality of multiplexing circuits 50, one of which is electrically connected to one data lead P1, so that the same multiplexing circuit 50 can sequentially transmit the data voltage Vdata required by the sub-pixels 101 in different rows, which is beneficial to reduce the number of data leads P1 that need to be prepared in the frame area AA0 and improve the problem of the increase in the number of data leads P1 caused by the increase in the number of data lines 40. Thus, it is beneficial to improve the problem of the large number of power supply ends required in the frame area AA0 and reduce the preparation pressure of the power supply ends in the frame area AA0.

[0067] In one embodiment of the present application, continuing to refer to Figure 10 As shown, the plurality of switches 501 of the multiplexing circuit 50 are located in the lower frame area A20, and the output ends of the plurality of switches 501 are respectively electrically connected to the data lines 40 through the second connection lines SL4.

[0068] In the embodiment of the present application, the plurality of switches 401 of the multiplexing circuit 50 are electrically connected to the data lines 40 through the second connection lines SL4, which is beneficial to reduce the positional correspondence accuracy of the multiplexing circuit 50 and the data lines 40 and improve the flexibility of the position of the multiplexing circuit 50 and the layout flexibility of the display panel 100.

[0069] Figure 11 Another plan view of a display panel is provided in the embodiment of the present application.

[0070] In one embodiment of the present application, as Figure 11As shown, the plurality of switches 501 of the multiplexing circuit 50 are located in the first sub-bezel area A31, the input ends of the plurality of switches 501 are electrically connected to the data lead P1 extending from the lower bezel area A31 to the first sub-bezel area A31 through the display area A10, the power supply end of the data lead P1 is located in the lower bezel area A20, and the data lead P1 electrically connected to the multiplexing circuit 50 extends from the lower bezel area A20 to the first sub-bezel area A31. The power supply end generating the data voltage generates different time signals at different times, which are transmitted to the input ends of the multiplexing circuit 50 through the data lead P1, and the plurality of switches 501 in the multiplexing circuit 50 are activated at different times to receive the corresponding data voltage Vdata.

[0071] In the embodiment of the present application, the plurality of switches of the multiplexing circuit 50 are located in the first sub-bezel area A31, which is beneficial to make the switches 501 adjacent to the data lines 40 in the second direction X2, and provides conditions for the data lines 40 to be directly electrically connected to the output ends of the switches 501, thereby reducing the wiring. The data lead P1 extends from the lower bezel area A20 to the first sub-bezel area A31, which is beneficial to reduce the wiring pressure of the multiplexing circuit 50 and the power supply end generating the output data voltage Vdata in two bezel areas, and is beneficial to reduce the width of the bezel area AA0 required for the display panel 100 by reducing the wiring in one of the bezel areas, thereby improving the area of the display area A10 of the display panel 100.

[0072] Figure 12 Another plan view of a display panel is provided in the embodiment of the present application.

[0073] In one embodiment of the present application, as shown in Figure 12 The multiplexing circuit 50 includes N3 switches 501, and the first switch 50A of the multiplexing circuit 50 is located in the lower bezel area A20 and its input end is electrically connected to the data lead P1. The remaining N3-1 switches of the multiplexing circuit 50 are located in the first sub-bezel area A31, and the output end of each of the N3-1 switches is electrically connected to the corresponding data line 40. In the embodiment of the present application, N3=3 is taken as an example for description. As shown in Figure 12 The multiplexing circuit 50 includes three switches 501, of which the first switch 50A is located in the lower bezel area A20, and the remaining two switches are located in the first sub-bezel area A31. Preparing the switches of the multiplexing circuit 50 in the lower bezel area A20 and the first sub-bezel area A31 is beneficial to improve the space for preparing the multiplexing circuit 50 and reduce the pressure of preparing the circuit in different positions of the bezel area.

[0074] In the embodiment of the present application, the output end of the switch located in the lower frame area A20 in the multiplexing circuit 50 is electrically connected with the data line 40 through the second connection line SL4, and the input end of the remaining N3-1 switches located in the first sub-frame area A31 in the multiplexing circuit 50 is electrically connected with the data line 40 electrically connected with the first switch. That is, the first switch 50A is used not only for transmitting the data voltage Vdata required by the sub-pixels 101 in one row, but also for transmitting the data voltage Vdata required by the sub-pixels 101 in the remaining two rows. When the data line 40 electrically connected with the switch 501 located in the first sub-frame area A31 needs the data voltage Vdata, the first switch 50A is also turned on and outputs the corresponding data voltage Vdata, at this time, the row of the sub-pixels 101 directly electrically connected with the first switch 50A does not start to receive the data voltage Vdata, which is beneficial to improve the utilization rate of the first switch 50A in the multiplexing circuit 50 and save the number of lines electrically connected in the multiplexing circuit 50, and improve the available space in the display panel 100.

[0075] In one embodiment of the present application, continuing to refer to Figure 12 As shown in the figure, the output end of each of the plurality of switches 501 included in the multiplexing circuit 50 is electrically connected with N3 rows of sub-pixels 101 arranged in the first direction X1 in sequence. In combination with the above description, N3=3, and taking an example that each of the plurality of switches 501 included in the multiplexing circuit 50 is electrically connected with adjacent 3 rows of sub-pixels 101. The data lead P1 electrically connected with the first switch 50A in the multiplexing circuit 50 first sequentially transmits the data voltage Vdata required by the sub-pixels 101 electrically connected with the N3-1 switches located in the first sub-frame area A31, and finally transmits the data voltage Vdata required by the sub-pixels 101 electrically connected with the first switch 50A.

[0076] Since the data voltage Vdata required by the sub-pixels 101 electrically connected with the 2 switches located in the first sub-frame area A31 needs to be transmitted through the first switch 50A, when the first switch 50A transmits the data voltage Vdata required by the sub-pixels 101 electrically connected with the switches located in the first sub-frame area A31, the data voltage Vdata will also be pre-stored in the data line 40 electrically connected with the first switch.

[0077] In the embodiment of the present application, when the data lead P1 transmits the data voltage Vdata, the data voltage Vdata required by the sub-pixel 101 electrically connected to the data line 40 electrically connected to the switch 501 located in the first sub-frame area A31 is transmitted first, and the data voltage Vdata required by the sub-pixel 101 electrically connected to the data line 40 directly electrically connected to the first switch 50A is transmitted last, which is beneficial to cover the data voltage Vdata pre-stored in the data line 40 electrically connected to the first switch 50A, so that the sub-pixel 101 electrically connected to the first switch 50A receives accurate data voltage Vdata, thereby ensuring the luminance accuracy of each sub-pixel 101.

[0078] Figure 13 Another planar schematic diagram of a display device provided by an embodiment of the present application.

[0079] An embodiment of the present application provides a display device 200, as shown in the figure, the display device 200 includes the display panel 100 provided by the above-mentioned embodiment. The display device 200 can be a computer, a mobile phone or the like for display. Figure 13

[0080] In the display device 200, the scan line 20 in the display panel 100 extends in the first direction X1 and is arranged in the second direction X2, which is beneficial to drive the pixel 10 column by column, thereby reserving more time for the pixel 10 in each column to write data voltage under the same refresh frequency, which is beneficial to prepare the display panel 100 to have a higher refresh frequency display technology, and is beneficial to improve the time for each pixel 10 in the display panel 100 to receive the data voltage Vdata under the same refresh frequency, thereby improving the accuracy of the data voltage Vdata received by the pixel 10, improving the luminance accuracy of the pixel 10, and improving the display effect of the display panel 100 in high-frequency operation.

[0081] The above only describes the preferred embodiments of the present application and is not intended to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the scope of protection of the present application.​

Claims

1. A display panel, characterized by, The display panel comprises: a display area and a lower bezel area, the display area and the lower bezel area are arranged along a first direction, the lower bezel area comprises a plurality of pins; the display panel further comprises a bezel area, the bezel area comprises the lower bezel area and a side bezel area, the side bezel area comprises a first sub-bezel area located on opposite sides of the display area in a second direction; a plurality of pixels, the number of pixels arranged along the first direction is N1, the number of pixels arranged along the second direction is N2, N1>N2, the first direction intersects the second direction; a plurality of scan lines arranged along the second direction, the scan lines extend along the first direction and are electrically connected to a plurality of pixels arranged along the first direction; the display panel further comprises a plurality of multiplexing circuits, the multiplexing circuit comprises a switch, the output terminals of a plurality of switches of the multiplexing circuit are respectively electrically connected to different data lines; wherein the multiplexing circuit comprises N3 switches, the first switch of the multiplexing circuit is located in the lower bezel area and its input terminal is electrically connected to a data lead; the remaining N3-1 switches of the multiplexing circuit are located in the first sub-bezel area; the input terminals of the remaining N3-1 switches of the multiplexing circuit located in the first sub-bezel area are electrically connected to the data line of the first switch.

2. The display panel of claim 1, wherein, The bezel area surrounds the display area; the display panel further comprises a plurality of cascaded shift register circuits, at least part of the shift register circuits are located in the first sub-bezel area; the shift register circuit comprises an output terminal, the display area further comprises a plurality of first connection lines, at least part of the scan lines are electrically connected to the output terminal of the shift register circuit through the first connection lines.

3. The display panel of claim 2, wherein, The bezel area further comprises an upper bezel area, the upper bezel area and the lower bezel area are respectively located on opposite sides of the display panel in the first direction; at least part of the shift register circuits are located in the upper bezel area.

4. The display panel of claim 2, wherein, The first connection line and the scan line are located in different film layers.

5. The display panel of claim 2, wherein, The display panel further comprises a first power signal line and a second power signal line, at least part of the first power signal line and / or at least part of the second power signal line are located in the bezel area; at least part of the shift register circuits are located in a first region in the first sub-bezel area, at least part of the first power signal line and / or at least part of the second power signal line are located in a second region in the first sub-bezel area, the first region and the second region are arranged along the first direction.

6. The display panel of claim 1, wherein, The pixel comprises a sub-pixel, the display panel further comprises a plurality of data lines, the data lines extend along the second direction and are electrically connected to a plurality of sub-pixels arranged along the second direction.

7. The display panel of claim 6, wherein, The display area comprises a plurality of second connection lines, the lower bezel area comprises a plurality of data leads, at least part of the data lines are electrically connected to the data leads of the lower bezel area through the second connection lines.

8. The display panel of claim 6 or 7, wherein, The first sub-bezel area comprises a plurality of data leads arranged along the first direction, the data lines are electrically connected to the data leads.

9. The display panel of claim 7, wherein, A first gap is included between two adjacent pixels, and at least part of the second connection line passes through the first gap to electrically connect with the data line.

10. The display panel of claim 9, wherein, N3 second connection lines pass through the first gap. N3>1.

11. The display panel of claim 7, wherein, The second connection line and the data line are located in different film layers.

12. The display panel of claim 11, wherein, Each output terminal of the N3-1 switches is electrically connected with a corresponding data line. The output terminal of the switch located in the lower frame area in the multiplexing circuit is electrically connected with the data line through the second connection line.

13. The display panel of claim 12, wherein, The output terminals of the switches in the multiplexing circuit are electrically connected with N3 rows of sub-pixels arranged in sequence in the first direction; the data lead electrically connected with the first switch in the multiplexing circuit first sequentially transmits the data voltage required by the sub-pixels electrically connected with the N3-1 switches located in the first sub-frame area, and finally transmits the data voltage required by the sub-pixels electrically connected with the first switch.

14. A display device comprising: The display panel includes any one of claims 1-13.

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