Display panel and display device

Abstract

The embodiment of the invention provides a display panel and a display device. According to the display panel, a gate driving circuit comprises multiple stages of first gate driving units and at least one stage of second gate driving unit which are cascaded, the first gate driving units are configured to output scanning signals, and the second gate driving units are configured to output stage transmission signals to the first gate driving units, in the direction perpendicular to the arrangement direction of the first gate driving units, the width of the second gate driving units is smaller than that of the first gate driving units, so that the space, occupied by the second gate driving units, of the lower frame can be reduced, and the space for arranging other wires in the lower frame is increased; therefore, the risks of wiring short circuit and open circuit of the lower frame are reduced, and the yield of the display panel is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] GOA (Gate On Array, array substrate row drive) technology refers to a driving method that realizes row-by-row scanning of the gate by making the gate row scanning drive signal on the array substrate. Since GOA technology can eliminate the gate drive chip and circuit board, save the space of the gate drive chip and circuit board, and realize narrow borders, GOA technology is widely used in display panels. Existing display devices generally set the gate drive circuit on the borders on both sides and bind the drive chip to the lower border. However, in the actual preparation process, it is found that the gate drive circuit will be set at the junction of the two side borders and the lower side border of the display device, occupying the lower border of the display device, resulting in a smaller setting space for the wiring of the lower border, which is easy to cause problems such as short circuit and open circuit in the wiring, affecting the yield and performance of the display device.

[0003] Therefore, the existing display device has a technical problem that the gate driving circuit occupies the lower frame of the display device, causing other wiring to be prone to abnormalities, thereby affecting the yield of the display device. Summary of the invention

[0004] The embodiments of the present application provide a display panel and a display device to solve the technical problem that a gate driving circuit of an existing display device occupies a lower frame of the display device, causing other wiring to be prone to abnormalities, thereby affecting the yield of the display device.

[0005] In order to achieve the above object, according to a first aspect of the present application, a display panel is provided, the display panel comprising a gate driving circuit, the gate driving circuit comprising a cascaded multi-stage first gate driving unit and at least one stage of a second gate driving unit, the first gate driving unit is configured to output a scan signal, and the second gate driving unit is configured to output a stage transmission signal to the first gate driving unit;

[0006] Wherein, in a direction perpendicular to an arrangement direction of the first gate driving units of each level, a width of the second gate driving unit is smaller than a width of the first gate driving unit.

[0007] According to a second aspect of the present application, a display device is provided, comprising a display panel as described in any one of the above embodiments.

[0008] The embodiments of the present application provide a display panel and a display device; the display panel includes a gate driving circuit including a cascade of multiple first gate driving units and at least one second gate driving unit, the first gate driving unit is configured to output a scanning signal, and the second gate driving unit is configured to output a stage transmission signal to the first gate driving unit, wherein in a direction perpendicular to the arrangement direction of the first gate driving units of each stage, the width of the second gate driving unit is smaller than the width of the first gate driving unit, which can reduce the space of the lower frame occupied by the second gate driving unit, so that the space for setting other wiring in the lower frame is increased, thereby reducing the risk of wiring short circuit and open circuit in the lower frame, and improving the yield of the display panel.

[0009] Other features and advantages of the present application will be described in detail in the subsequent detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can obtain other drawings based on these drawings without creative work.

[0011] In order to more completely understand the present application and its beneficial effects, the following description will be given in conjunction with the accompanying drawings, wherein the same figure numbers represent the same parts in the following description.

[0012] Figure 1 A schematic plan view of a display panel provided in an embodiment of the present application.

[0013] Figure 2 A schematic diagram of the cascade connection of the gate driving circuit of the display panel provided in an embodiment of the present application.

[0014] Figure 3 A circuit diagram of a first gate driving unit provided in an embodiment of the present application.

[0015] Figure 4 A first circuit diagram of a second gate driving unit provided in an embodiment of the present application.

[0016] Figure 5 A second circuit diagram of a second gate driving unit provided in an embodiment of the present application.

[0017] Figure 6 A schematic cross-sectional view of a display panel provided in an embodiment of the present application.

[0018] Figure 7 A first stacking diagram of each film layer in the first gate driving unit and the second gate driving unit provided in an embodiment of the present application.

[0019] Figure 8 A second stacking diagram of each film layer in the first gate driving unit and the second gate driving unit provided in an embodiment of the present application.

[0020] Fig. 9 A timing diagram of the output signal of the gate drive circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0021] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0022] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", and "electrically connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or can communicate with each other; it can be directly connected, or indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0023] In order to illustrate the principle of the technical problem of the present application, the embodiment of the present application provides a comparative display device. It can be understood that the comparative display device cannot be used as the prior art of the embodiment of the present application. Specifically, the comparative display device includes a cascaded multi-stage gate drive circuit. In order to realize the normal operation of the gate drive circuit, three types of gate drive circuits are generally set. The first type of gate drive circuit, the second type of gate drive circuit and the third type of gate drive circuit are arranged in sequence from the upper frame to the lower frame. The first type of gate drive circuit will be connected to the start signal line, so that the gate drive circuit works according to the signal of the start signal line and outputs the level transmission signal and the scanning signal; the second type of gate drive circuit will input the level transmission signal and the scanning signal connection of the other level gate drive circuit, and output the level transmission signal and the scanning signal; the third type of gate drive circuit only outputs the level transmission signal to other gate drive circuits, so that the gate drive circuit can work normally, and will not be connected to the scanning line in the comparative display device.

[0024] However, in the comparison display device, the circuit designs in the three types of gate drive circuits are the same. The difference between the first type of gate drive circuit and the second type of gate drive circuit and the third type of gate drive circuit is that the input end of the first type of gate drive circuit is connected to the start signal line, and the input end of the second type of gate drive circuit and the third type of gate drive circuit is connected to the level transfer signal line and the signal output line; the difference between the third type of gate drive circuit and the first type of gate drive circuit and the second type of gate drive circuit is that the third type of gate drive circuit will not be connected to the scan line, and the first type of gate drive circuit and the second type of gate drive circuit will be connected to the scan line. Generally, a single-stage circuit requires more than 15 transistors to realize its function of outputting a scan signal, and the circuit designs in the three types of gate drive circuits are the same, so that the third type of gate drive circuit occupies the space of the lower frame, and the lower frame generally sets a data signal line to connect the source driver chip, which will lead to a reduction in the setting space for setting the data signal line, which is easy to cause a short circuit or a disconnection between the data signal lines, or cause the impedance of the data signal line to become larger, and the signal voltage drop is too large, resulting in poor display or display failure. Therefore, the existing display device has a technical problem that the gate driving circuit occupies the lower frame of the display device, causing other wiring to be prone to abnormalities, thereby affecting the yield of the display device.

[0025] In view of the above technical problems, the embodiments of the present application provide a display panel and a display device to solve the above technical problems.

[0026] Figure 1 A schematic plan view of a display panel provided in an embodiment of the present application. Figure 2 A schematic diagram of the cascade connection of the gate driving circuit of the display panel provided in an embodiment of the present application. Figure 3 A circuit diagram of a first gate driving unit provided in an embodiment of the present application. Figure 4 A first circuit diagram of a second gate driving unit provided in an embodiment of the present application. Figure 5 A second circuit diagram of a second gate driving unit provided in an embodiment of the present application. Figure 6 A schematic cross-sectional view of a display panel provided in an embodiment of the present application. Figure 7 A first stacking diagram of each film layer in the first gate driving unit and the second gate driving unit provided in an embodiment of the present application. Figure 8 A second stacking diagram of each film layer in the first gate driving unit and the second gate driving unit provided in an embodiment of the present application. Fig. 9 A timing diagram of the output signal of the gate drive circuit provided in an embodiment of the present application.

[0027] like Figures 1 to 9As shown, an embodiment of the present application provides a display panel, the display panel 1 includes a gate driving circuit 21, the gate driving circuit 21 includes a cascaded multi-stage first gate driving unit 211 and at least one stage of second gate driving unit 212, the first gate driving unit 211 is configured to output a scan signal, and the second gate driving unit 212 is configured to output a stage transmission signal to the first gate driving unit 211;

[0028] In the direction X perpendicular to the arrangement direction Y of the first gate driving units of each level, the width H2 of the second gate driving unit 212 is smaller than the width H1 of the first gate driving unit 211 .

[0029] An embodiment of the present application provides a display panel, wherein the display panel 1 includes a gate driving circuit 21 including a cascade of multiple first gate driving units 211 and at least one second gate driving unit 212, wherein the first gate driving unit 211 is configured to output a scan signal, and the second gate driving unit 212 is configured to output a stage transmission signal to the first gate driving unit 211, wherein in a direction perpendicular to the arrangement direction of the first gate driving units 211 of each stage, the width of the second gate driving unit 212 is smaller than the width of the first gate driving unit, so that the space of the lower frame occupied by the second gate driving unit 212 can be reduced, so that the space for setting other wiring in the lower frame is increased, thereby reducing the risk of short circuit and open circuit of the wiring of the lower frame, and improving the yield of the display panel.

[0030] Specifically, the scanning signal output by the first gate driving unit 211 refers to the signal output to the scanning line 22, and the level transmission signal output by the second gate driving unit 212 to the first gate driving unit 211 refers to the signal output from the level transmission signal end or the signal output end of the second gate driving unit 212. It can be understood that when the second gate driving unit 212 has a level transmission signal end, the level transmission signal output by the second gate driving unit 212 is the signal output by the level transmission signal end, and when the second gate driving unit 212 does not have a level transmission signal end, the signal output end of the second gate driving unit 212 is multiplexed as the level transmission signal end, and the signal output end of the second gate driving unit 212 outputs the level transmission signal.

[0031] Specifically, the arrangement direction of the first gate driving units 211 is the Y direction, and the direction perpendicular to the arrangement direction of the first gate driving units 211 of each level is the X direction.

[0032] like Figures 1 to 9As shown, an embodiment of the present application provides a display panel, the display panel 1 includes a gate driving circuit 21 and a scan line 22, the gate driving circuit 21 includes a cascaded multi-stage first gate driving unit 211 and at least one stage of second gate driving unit 212, the signal output end of each first gate driving unit 211 (for example, the signal output end G(n) of the n-th stage first gate driving unit) is connected to the scan line 22, and the stage transmission signal end of the second gate driving unit 212 (for example, the stage transmission signal end ST(n+m) of the M-th stage second gate driving unit) or the signal output end of the second gate driving unit 212 is electrically connected to the first gate driving unit 211;

[0033] The channel width of the transistor of at least one stage of the second gate driving unit 212 is smaller than the channel width of the corresponding transistor in the first gate driving unit 211 (for example, Figure 6 , Figure 7 The channel width L1 of the first pull-up transistor T21 in the second gate driving unit 212 is smaller than the channel width L3 of the first pull-up transistor T21 in the first gate driving unit 211);

[0034] And / or, the number of transistors in at least one stage of the second gate driving unit 212 is smaller than the number of transistors in the first gate driving unit 211 (for example Figure 3 , Figure 4 The second gate driving unit 212 has only 4 transistors, while the first gate driving unit has 19 transistors).

[0035] The embodiment of the present application provides a display panel, wherein the gate driving circuit 21 includes a cascaded multi-stage first gate driving unit 211 and at least one stage of the second gate driving unit 212, the signal output end of each first gate driving unit 211 is connected to the scan line 22, and the stage transmission signal end or the signal output end of the second gate driving unit 212 is electrically connected to the first gate driving unit 211; the channel width of the transistor in at least one stage of the second gate driving unit 212 is smaller than the channel width of the corresponding transistor in the first gate driving unit 211, and / or the number of transistors in at least one stage of the second gate driving unit 212 is smaller than the number of transistors in the first gate driving unit 211, so that the space occupied by the second gate driving unit 212 in the lower frame can be reduced, so that the space for setting other wiring in the lower frame is increased, thereby reducing the risk of wiring short circuit and open circuit in the lower frame, and improving the yield of the display panel.

[0036] Specifically, Figure 1As shown, the display panel 1 includes a display area 101 and a non-display area 102. The non-display area 102 can be arranged around the display area 101, but the embodiment of the present application is not limited thereto. The non-display area 102 can be arranged on two sides or three sides of the display area 101, and the non-display area 102 can be bent to the back side of the display panel. The non-display area 102 may include an upper frame area (not shown), a left frame area (not shown), a right frame area (not shown) and a lower frame area (not shown). The left frame area and the right frame area may include a gate drive circuit setting area 102a, and the lower frame area may include a binding area 102b. The scan line 22 is arranged in the display area 101, and the gate drive circuit 21 is arranged in the gate drive circuit setting area 102a. However, the embodiment of the present application is not limited thereto, and the gate drive circuit area can be arranged on one side of the display area, and accordingly, the gate drive circuit is arranged on one side of the display area.

[0037] Specifically, the binding area 102b in the embodiment of the present application may include all areas located on the lower side of the display area 101 except the gate drive circuit setting area 102a, and may include a fan-out area. It can be understood that the binding area 102b may overlap with the gate drive circuit setting area 102a. Since the gate drive circuit setting area 102a will not set the wiring of the binding area 102b, the area can be divided into the gate drive circuit setting area 102a, but it can be understood that some wiring in the gate drive circuit setting area 102a may pass through the binding area or the gate drive circuit setting area may be bound to the chip.

[0038] Specifically, when the second gate driving unit includes a signal output terminal and a level transmission signal terminal, the level transmission signal terminal of the second gate driving unit will be electrically connected to the first gate driving unit. When the second gate driving unit is only provided with a signal output terminal, it can be understood that the signal output terminal is multiplexed as the level transmission signal terminal. At this time, the signal output terminal of the second gate driving unit can be electrically connected to the first gate driving unit.

[0039] Specifically, it can be understood that in order to achieve normal operation of the gate drive circuit, Figure 2As shown, taking the gate driving circuit including N-level first gate driving units and M-level second gate driving units as an example, the first-level first gate driving unit 211a will be connected to the start signal line STV and the signal end of the K-th level first gate driving unit 211b, the K-th level first gate driving unit 211b will be connected to the signal end of the other level first gate driving units, and the N-th level first gate driving unit 211c will be connected to the level transmission signal end or signal output end of the M-th level second gate driving unit 212a, so that each first gate driving unit has an input signal and can be used as the output signal of the other level first gate driving unit. The specific value of K can be determined according to different designs of the gate driving circuit, and the embodiment of the present application takes the connection of the N-th level first gate driving unit 211c with the level transmission signal end of the M-th level second gate driving unit 212a as an example, but the embodiment of the present application is not limited thereto, and the N-th level first gate driving unit can be connected to the level transmission signal end of the L-th level second gate driving unit.

[0040] Specifically, N may be greater than or equal to 2 and is a positive integer, K may be greater than or equal to 1 and is less than or equal to N and is a positive integer; M may be greater than or equal to 1 and is a positive integer, L may be greater than or equal to 1 and is less than or equal to M and is a positive integer.

[0041] Specifically, the gate driving circuit 21 may include N+M stages of gate driving units.

[0042] It can be seen that the first gate driving unit is connected to the scan line 22, while the second gate driving unit is not connected to the scan line 22 (it can be connected to the virtual signal line). The comparison display device will make the circuit design of the second gate driving circuit and the third type of gate driving circuit the same, which will cause the space occupied by the second type of gate driving circuit and the third type of gate driving circuit to be similar or even the same. Figure 1 It can be seen that applying the design of the comparative display device in the embodiment of the present application will cause the second gate driving unit to occupy more space, while the embodiment of the present application can reduce the space occupied by the second gate driving unit through the above design, so that the line width and / or line spacing of the routing in the binding area 102b can be increased, the impedance of the routing can be reduced, the risk of routing disconnection and short circuit can be reduced, and the display effect and yield of the display panel can be improved.

[0043] Specifically, it can be understood that when N scan lines 22 are required to be driven in the display panel 1, at least N levels of first gate driving units are set in the display panel, so that each scan line 22 can be connected to a first level of first gate driving unit to achieve driving of the scan line 22. As for the setting method of the N levels of first gate driving units, it is not limited in the embodiment of the present application. For example, a single-sided gate driving circuit design can be adopted, and a double-sided gate driving circuit design can also be adopted; for example, the odd-numbered first gate driving units can be set in the left frame area, and the even-numbered first gate driving units can be set in the right frame area, or the odd-numbered first gate driving units and the even-numbered first gate driving units can be set in a gate driving circuit setting area (if a double-sided gate driving circuit is adopted, there are odd-numbered and even-numbered first gate driving units on both sides).

[0044] Specifically, in order to illustrate the difference between the first gate driving unit and the second gate driving unit, the embodiment of the present application names and grades the two separately, but it can be understood that the two are actually gate driving units of different levels in the gate driving circuit. When the N-th-level first gate driving unit is the N-th-level gate driving unit, the first-level second gate driving unit is actually the N+1-th-level gate driving unit, and the M-th-level second gate driving unit is actually the N+M-th-level gate driving unit.

[0045] Specifically, since the input signal in the first gate driving unit needs to use the output signal of the lower gate driving unit, at least one level of second gate driving unit is generally set, and the number of second gate driving units is determined accordingly according to different cascading methods. For example, when the first gate driving unit is connected to the lower M levels of second gate driving units, M levels of second gate driving units can be set, for example, M can be greater than or equal to 2, and M can be specifically 8; for example, the last level of the first gate driving unit is connected to the signal output terminal or the level transmission signal terminal of the gate driving unit of the next level, then only one level of second gate driving unit can be set, and M can be 1 at this time. However, the embodiments of the present application are not limited thereto. For example, the second gate driving unit also needs the output signal of the lower second gate driving unit as an input signal, so multiple levels of second gate driving units can be set.

[0046] Specifically, due to the different numbers of start signal lines set in different gate drive circuits, there may be some gate drive units in the first gate drive unit whose signal input terminals are connected to signal terminals different from those connected to signal input terminals of other gate drive units. It may be that the signal input terminal of the first gate drive unit of one level is connected to a signal terminal different from that connected to signal input terminals of the first gate drive units of other levels. It may be that the signal input terminal of the signal input terminal of the first gate drive unit of multiple levels is connected to a signal terminal different from that connected to signal input terminals of the first gate drive units of other levels. For example, some gate drive circuits may only have one start signal line STV connected to the start signal line STV. The input signal end of the first gate driving unit of the first level, the first gate driving units of other levels will be connected to the signal output end and / or the level transmission signal end of the first gate driving units of other levels, or the first gate driving units of other levels will be connected to the signal output end and / or the level transmission signal end of the second gate driving unit; in other gate driving circuits, multiple starting signal lines will be set to connect the input signal ends of the first gate driving units of the previous levels respectively, the first gate driving units of other levels will be connected to the signal output end and / or the level transmission signal end of the first gate driving units of other levels, or the first gate driving units of other levels will be connected to the signal output end and / or the level transmission signal end of the second gate driving unit.

[0047] Specifically, since the signal input end of at least one level of the first gate driving unit in the first gate driving unit needs to be connected to the starting signal line, and the signal input end of at least one level of the first gate driving unit is not connected to the starting signal line, the first gate driving unit can be divided into a first starting gate driving unit and a first conventional gate driving unit, the signal input end of the first starting gate driving unit is connected to the starting signal line, and the signal input end of the first conventional gate driving unit is connected to the level transmission signal end and the signal output end of other levels of gate driving units; the circuit designs in the first starting gate driving unit and the first conventional gate driving unit can be the same or different.

[0048] Specifically, the signal input end described in the embodiment of the present application refers to the input end of the first pull-up control module (when the first gate driving unit includes the second pull-up control module, it can also be the second pull-up control module, and when the second gate driving unit includes the third pull-up module, it can also be the third pull-up control module) (when the first pull-up control module is connected to only one signal end, the signal end is the input end of the first pull-up control module, and when the first pull-up control module is connected to two signal ends, both signal ends are input ends of the first pull-up control module).

[0049] Specifically, Figure 2The figure shows a connection relationship between each first gate driving unit 211 and the second gate driving unit 212 in a gate driving circuit 21. It can be understood that the embodiment of the present application does not limit the connection relationship between the first gate driving unit and the second gate driving unit. Depending on the circuit and the cascade method, the connection relationship between the first gate driving unit and the second gate driving unit is not the same.

[0050] Specifically, the channel width of the transistor in the second gate driving unit 212 is smaller than the channel width of the corresponding transistor in the first gate driving unit 211, which means that a transistor is provided in the second gate driving unit 212, and this transistor is also provided in the first gate driving unit 211, and the channel width of this transistor in the second gate driving unit 212 is smaller than the channel width of this transistor in the first gate driving unit 211. For example, the first gate driving unit 211 and the second gate driving unit 212 are both provided with a first pull-up transistor T21, and the transistor corresponding to the first pull-up transistor T21 in the second gate driving unit 212 is the first pull-up transistor T21 in the first gate driving unit 211.

[0051] In some embodiments, the first gate driving unit includes a first starting gate driving unit and a first conventional gate driving unit. The first conventional gate driving unit is provided with a reset transistor, and the gate of the reset transistor is connected to the starting signal line. The first starting gate driving unit is not provided with a reset transistor, and the signal input end of the first starting gate driving unit is connected to the starting signal line.

[0052] In some embodiments, the first gate driving unit includes a first starting gate driving unit and a first conventional gate driving unit, the first starting gate driving unit and the first conventional gate driving unit both include a reset transistor, and the gate of the reset transistor is connected to the reset signal line, the signal input end of the first starting gate driving unit is connected to the starting signal line STV, and the signal input end of the first conventional gate driving unit is connected to the signal output end and the stage transmission signal end in the first gate driving unit.

[0053] In some embodiments, Figures 1 to 9 As shown, the channel width of the transistor of at least one stage of the second gate driving unit 212 is smaller than the channel width of the corresponding transistor in the first gate driving unit 211 (for example Figure 6 , Figure 7The channel width L1 of the first pull-up transistor T21 in the second gate driving unit 212 is smaller than the channel width L3 of the first pull-up transistor T21 in the first gate driving unit 211). By making the channel width of the transistor in at least one level of the second gate driving unit 212 smaller than the channel width of the corresponding transistor in the first gate driving unit 211, the space of the lower frame occupied by the second gate driving unit 212 can be reduced, so that the space for arranging other wirings in the lower frame is increased, thereby reducing the risk of short circuit and open circuit of the wiring of the lower frame, and improving the yield of the display panel.

[0054] In some embodiments, Figure 3 to Figure 4 , Figures 6 to 8 As shown, the first gate driving unit 211 and the second gate driving unit 212 both include a first pull-up control module 311, a first pull-up module 312 and a first pull-down module 313; the first pull-up module 312 and the first pull-up control module 311 are connected to a first node Q1; the first pull-down module 313 and the first pull-up module 312 are connected to the first node Q1; wherein, the channel width of at least one transistor in the first pull-up module 312 of the second gate driving unit 212 is greater than the channel width of the corresponding transistor in the first pull-up module 312 of the first gate driving unit 211 (for example, the channel width L1 of the first pull-up transistor T21 in the first pull-up module 312 of the second gate driving unit 212 is less than the channel width L3 of the first pull-up transistor T21 in the first pull-up module 312 of the first gate driving unit 211). By making the channel width of at least one transistor in the first pull-up module 312 of the second gate driving unit 212 smaller than the channel width of the corresponding transistor in the first pull-up module 312 of the first gate driving unit 211, the space occupied by the second gate driving unit can be reduced, so that the spacing and / or width of the fan-out wiring, binding terminals and other wiring and terminals in the binding area can be set relatively large, thereby avoiding the problem of short circuit or open circuit caused by too small spacing and width between the wiring and terminals in the binding area, thereby improving the yield of the display panel.

[0055] Specifically, the first gate driving unit may be Figure 3 As shown, the circuit design in the second gate driving unit is as follows: Figure 4 As shown, at this time, the signal output terminal of the first-level second gate driving unit is G(N+1), the signal output terminal of the m-th-level second gate driving unit is G(N+m), m belongs to M, m is greater than or equal to 1, m is less than or equal to M, and m is a positive integer. The other signal terminals can be determined in the same way. It can be understood that Figure 4 and Figure 3The first gate driving unit and the second gate driving unit are shown separately to distinguish them. The actual circuit structures are the same, but the number of stages is different. It can be understood that when the gate driving circuit is regarded as an N+M-stage gate driving unit, Figure 3 and Figure 4 Can be merged.

[0056] Specifically, Figure 3 , Figure 4 As shown, the first pull-up control module 311 includes a pull-up control transistor T11. In the first gate driving unit 211, when n is 1, the gate and the first electrode of the pull-up control transistor T11 of the n-th first gate driving unit are connected to the start signal line STV. When n is greater than 5, the gate of the pull-up control transistor T11 of the n-th first gate driving unit is connected to the stage transmission signal terminal ST(n-4) of the first four stages of the first gate driving unit, and the gate of the pull-up control transistor T11 of the n-th first gate driving unit is connected to the first four stages of the first gate driving unit. The gate of the pull-up control transistor T11 of the m-th second gate driving unit is connected to the signal output terminal G(n-4) of the first 4 gate driving units (which can be the first gate driving unit or the second gate unit), and the first electrode of the pull-up control transistor T11 of the m-th second gate driving unit is connected to the signal output terminal G(N+m-4) of the first 4 gate driving units (which can be the first gate driving unit or the second gate unit).

[0057] Specifically, it can be understood that when m is less than or equal to 4, the signal output terminal G(N+m-4) corresponds to the signal output terminal of the first gate driving unit, and when m is greater than 4, the signal output terminal G(N+m-4) corresponds to the signal output terminal of the second gate driving unit.

[0058] Specifically, n belongs to N, n is greater than or equal to 1, n is less than or equal to N, and n is a positive integer. When n is 2, 3, or 4, a plurality of start signal lines may be provided to be connected to the signal input terminals of the second-stage first gate driving unit, the third-stage first gate driving unit, and the fourth-stage first gate driving unit, respectively.

[0059] Specifically, the gate driving circuit includes a multi-stage gate driving unit, and the multi-stage gate driving unit includes a first gate driving unit and a second gate driving unit. It can be understood that the n-th-stage first gate driving unit is the n-th-stage gate driving unit; the m-th-stage second gate driving unit is actually the N+m-th-stage gate driving unit.

[0060] In some embodiments, Figure 3 , Figure 4 , Figures 6 to 8As shown, the first pull-up module 312 includes a first pull-up transistor T21 and a second pull-up transistor T22, the gate of the first pull-up transistor T21 is connected to the first node Q1, the first electrode of the first pull-up transistor T21 is connected to the clock signal line CK, and the second electrode of the first pull-up transistor T21 is connected to the signal output terminal G(n) of the first gate driving unit 211 or the signal output terminal G(N+m) of the second gate driving unit 212; the gate of the second pull-up transistor T22 is connected to the first node Q1, the first electrode of the second pull-up transistor T22 is connected to the clock signal line CK, and the second electrode of the second pull-up transistor T22 is connected to the stage transmission signal terminal ST(n) of the first gate driving unit 211 or the stage transmission signal terminal ST(N+m) of the second gate driving unit 212;

[0061] Wherein, the channel width of the first pull-up transistor T21 in the first gate driving unit 211 is greater than the channel width of the first pull-up transistor T21 in the second gate driving unit 212;

[0062] and / or the channel width of the second pull-up transistor T22 in the first gate driving unit 211 is greater than the channel width of the second pull-up transistor T22 in the second gate driving unit 212. By making the channel width of the first pull-up transistor in the first gate driving unit greater than the channel width of the first pull-up transistor in the second gate driving unit, and / or the channel width of the second pull-up transistor in the first gate driving unit greater than the channel width of the second pull-up transistor in the second gate driving unit, the space occupied by the second gate driving unit can be reduced, so that the spacing and / or width of the fan-out wiring, binding terminals and other wirings and terminals in the binding area can be set relatively large, thereby avoiding the problem of short circuit or open circuit caused by too small spacing and width of wiring and terminals in the binding area, thereby improving the yield of the display panel.

[0063] Specifically, the channel width of the first pull-up transistor in the first gate driving unit may be greater than the channel width of the first pull-up transistor in the second gate driving unit; the channel width of the second pull-up transistor in the first gate driving unit may be greater than the channel width of the second pull-up transistor in the second gate driving unit; the channel width of the first pull-up transistor in the first gate driving unit may be greater than the channel width of the first pull-up transistor in the second gate driving unit, and the channel width of the second pull-up transistor in the first gate driving unit may be greater than the channel width of the second pull-up transistor in the second gate driving unit.

[0064] Specifically, it can be understood that the display panel will be provided with multiple clock signal lines, and each clock signal line will be multiplexed to drive each gate driving unit. For example, when the display panel has gate driving circuits only on both sides, and the gate driving units in the gate driving circuits on both sides are correspondingly arranged to input signals to the same scanning line from both sides, two groups of clock signal lines will be arranged on both sides of the display area, and the two groups of clock signal lines can be symmetrically arranged and have the same signals; each group of clock signal lines can include multiple clock signal lines, and connection with gate driving circuits of different levels is achieved through multiplexing of multiple clock signal lines; for example, a group of clock signal lines includes 8 clock signal lines, then the first gate driving unit of the first level to the first gate driving unit of the eighth level can be connected to the 8 clock signal lines respectively, and the first gate driving unit of the ninth level to the first gate driving unit of the sixteenth level can be connected to the 16th level respectively. The first-stage first gate driving unit to the eighth-stage first gate driving unit are connected to the same clock signal line. Similarly, the clock signal lines connected to other first gate driving units are determined. As for the second gate driving unit, it can be understood that when the number of first gate driving units is an integer multiple of the number of clock signal lines, the connection relationship between the second gate driving units at each stage and the clock signal line can refer to the connection relationship between the first gate driving unit and the clock signal line. When the number of first gate driving units is not an integer multiple of the number of clock signal lines, for example, there are 23 first gate driving units in total, and the 24th gate driving unit is the second gate driving unit. Then the first-stage second gate driving unit can be connected to the same clock signal line as the eighth-stage first gate driving unit, and the second-stage second gate driving unit is connected to the same clock signal line as the first-stage second gate driving unit.

[0065] Specifically, Figure 6 As shown, the display panel 1 includes a substrate 411, an active layer 412, a gate insulating layer 413, a gate layer 414, an interlayer insulating layer 415, and a source-drain electrode layer 416. Here, the relative positions of the active layer, the gate layer, and the source-drain electrode layer are schematically illustrated with a top-gate bottom-contact design, but the embodiment of the present application is not limited thereto. The relative positions of the gate layer, the active layer, and the source-drain electrode layer can be other designs, such as a bottom-gate top-contact structure. The embodiment of the present application only schematically illustrates one gate layer, one active layer, and one source-drain electrode layer, but the embodiment of the present application is not limited thereto. Multiple gate layers, multiple active layers, and multiple source-drain electrode layers can be provided.

[0066] Specifically, Figure 8 As shown, Figure 8 (a) is a schematic diagram of the stacking of the active layer and the source-drain layer in the second gate driving unit 212, Figure 8 (b) is a schematic diagram of the stacking of the active layer and the source and drain layer in the first gate driving unit 211. Figure 8As can be seen in the figure, the active layer 412 includes the active pattern T21A of the first pull-up transistor T21 of the first gate driving unit 211, the active pattern T22A of the second pull-up transistor T22 of the first gate driving unit 211, the active pattern T21A of the first pull-up transistor T21 of the second gate driving unit 212, and the active pattern T22A of the second pull-up transistor T22 of the second gate driving unit 212; the source-drain layer 416 includes the active layer 412 including the first electrode T21S of the first pull-up transistor T21 of the first gate driving unit 211, the first pull-up transistor T21 of the first gate driving unit 211 a second electrode T21D of the transistor T21, a first electrode T21S of the second pull-up transistor T22 of the first gate driving unit 211, a second electrode T21D of the second pull-up transistor T22 of the first gate driving unit 211, a first electrode T21S of the first pull-up transistor T21 of the second gate driving unit 212, a second electrode T21D of the first pull-up transistor T21 of the second gate driving unit 212, a first electrode T21S of the second pull-up transistor T22 of the second gate driving unit 212, and a second electrode T21D of the second pull-up transistor T22 of the second gate driving unit 212.

[0067] from Figure 8 It can be seen that the channel width L3 of the first pull-up transistor T21 in the first gate driving unit 211 is greater than the channel width L1 of the first pull-up transistor T21 in the second gate driving unit 212, and the channel width L4 of the second pull-up transistor T22 in the first gate driving unit 211 is greater than the channel width L2 of the second pull-up transistor T22 in the second gate driving unit 212.

[0068] from Figure 7 As can be seen in FIG. 1 , since the channel width of the first pull-up transistor T21 in the second gate driving unit 212 is reduced, the width of the second gate driving unit 212 can be reduced, thereby reducing the area occupied by the second gate driving unit.

[0069] In some embodiments, Figure 3 , Figure 4 As shown, the first pull-down module 313 includes a first pull-down transistor T41. In the first gate driving unit 211, the gate of the first pull-down transistor T41 is connected to the level transmission signal terminal ST(n+8) of the next 8-level gate driving unit (which can be the first gate driving unit or the second gate driving unit). In the second gate driving unit 212, the gate of the first pull-down transistor T41 is connected to the level transmission signal terminal ST(N+m+8) of the next 8-level second gate driving unit. The first electrode of the first pull-down transistor T41 is connected to the first low-potential power supply terminal VSSQ, and the second electrode of the first pull-down transistor T41 is connected to the first node Q1.

[0070] Specifically, the first pull-down module 313 may also include a second pull-down transistor, the gate of the second pull-down transistor is connected to the gate of the first pull-down transistor, the first electrode of the second pull-down transistor is connected to the second low-potential power supply terminal VSSG, and the second electrode of the second pull-down transistor is connected to the signal output terminal G(n) of the first gate driving unit 211 or the signal output terminal G(N+m) of the second gate driving unit 212.

[0071] Specifically, the embodiment of the present application is described by taking the example of a gate driving circuit having a first low potential power supply terminal and a second low potential power supply terminal, but the embodiment of the present application is not limited to this, and only one low potential power supply terminal may be provided.

[0072] In some embodiments, Figure 3 , Figure 4As shown, the first gate driving unit 211 and the second gate driving unit 212 both include a pull-down maintaining module 314, the pull-down maintaining module 314 includes a first pull-down maintaining module 314a and a second pull-down maintaining module 314b, the first pull-down maintaining module 314a includes a first pull-down maintaining transistor T32, a second pull-down maintaining transistor T42, a third pull-down maintaining transistor T72, a first inverting transistor T51, a second inverting transistor T52, a third inverting transistor T53 and a fourth inverting transistor T54, the gate of the first pull-down maintaining transistor T32 is connected to The third node P, the first electrode of the first pull-down maintenance transistor T32 is connected to the second low potential power supply terminal VSSG, and the second electrode of the first pull-down maintenance transistor T32 is connected to the signal output terminal G(n) of the first gate driving unit 211 or the signal output terminal G(N+m) of the second gate driving unit 212; the gate of the second pull-down maintenance transistor T42 is connected to the third node P, the first electrode of the second pull-down maintenance transistor T42 is connected to the first low potential power supply terminal VSSQ, and the second electrode of the second pull-down maintenance transistor T42 is connected to the first node Q1; the The gate of the third pull-down sustaining transistor T72 is connected to the third node P, the first electrode of the third pull-down sustaining transistor T72 is connected to the first low potential power supply terminal VSSQ, the second electrode of the third pull-down sustaining transistor T72 is connected to the level transmission signal terminal ST(n) of the first gate driving unit 211 or the level transmission signal terminal ST(N+m) of the second gate driving unit 212, the gate of the first inverting transistor T51 and the first electrode of the first inverting transistor T51 are connected to the first low frequency signal terminal LC1, the second electrode of the first inverting transistor T51 is connected to the second inverting transistor The second electrode of the transistor T52 is connected to the gate of the third inverting transistor T53, the gate of the second inverting transistor T52 is connected to the first node Q1, the first electrode of the second inverting transistor T52 is connected to the first low potential power supply terminal VSSQ, the first electrode of the third inverting transistor T53 is connected to the first low frequency signal terminal LC1, the second electrode of the third inverting transistor T53 is connected to the second electrode of the fourth inverting transistor T54, the gate of the fourth inverting transistor T54 is connected to the first node Q1, and the first electrode of the fourth inverting transistor T54 is connected to the first low potential power supply terminal VSSQ;

[0073] The second pull-down maintaining module 314b includes a fourth pull-down maintaining transistor T33, a fifth pull-down maintaining transistor T43, a sixth pull-down maintaining transistor T73, a fifth inverting transistor T61, a sixth inverting transistor T62, a seventh inverting transistor T63 and an eighth inverting transistor T64, wherein the gate of the fourth pull-down maintaining transistor T33 is connected to the fourth node O, the first electrode of the fourth pull-down maintaining transistor T33 is connected to the second low potential power supply terminal VSSG, and the second electrode of the fourth pull-down maintaining transistor T33 is connected to the signal output terminal G(n) of the first gate driving unit 211 or the signal output terminal G(N+m) of the second gate driving unit 212; the gate of the fifth pull-down maintaining transistor T43 is connected to the fourth node O, the first electrode of the fifth pull-down maintaining transistor T43 is connected to the first low potential power supply terminal VSSQ, and the second electrode of the fifth pull-down maintaining transistor T43 is connected to the first node Q1; the gate of the sixth pull-down maintaining transistor T73 is connected to the fourth node O, the first electrode of the sixth pull-down maintaining transistor T73 is connected to the second low potential power supply terminal VSSQ, and the second electrode of the fifth pull-down maintaining transistor T43 is connected to the first node Q1; The first electrode of the sixth pull-down sustaining transistor T73 is connected to the first low potential power supply terminal VSSQ, the second electrode of the sixth pull-down sustaining transistor T73 is connected to the stage transmission signal terminal ST(n) of the first gate driving unit 211 or the stage transmission signal terminal ST(N+m) of the second gate driving unit 212, the gate of the fifth inverting transistor T61 and the first electrode of the fifth inverting transistor T61 are connected to the second low frequency signal terminal LC2, the second electrode of the fifth inverting transistor T61 is connected to the second electrode of the sixth inverting transistor T62 and the gate of the seventh inverting transistor T63, the gate of the sixth inverting transistor T62 is connected to the first node Q1, the first electrode of the sixth inverting transistor T62 is connected to the first low potential power supply terminal VSSQ, the first electrode of the seventh inverting transistor T63 is connected to the first low frequency signal terminal LC1, the second electrode of the seventh inverting transistor T63 is connected to the second electrode of the eighth inverting transistor T64, the gate of the eighth inverting transistor T64 is connected to the first node Q1, and the first electrode of the eighth inverting transistor T64 is connected to the first low potential power supply terminal VSSQ.

[0074] Specifically, the first pull-down maintaining module 314a also includes a first node pull-down transistor T55 and a second node pull-down transistor T56, the gate of the first node pull-down transistor T55 is connected to the fifth node Q3, the first electrode of the first node pull-down transistor T55 is connected to the first low potential power supply terminal VSSQ, and the second electrode of the first node pull-down transistor T55 is connected to the second electrode of the second inverting transistor T52; the gate of the second node pull-down transistor T56 is connected to the fifth node Q3, the first electrode of the second node pull-down transistor T56 is connected to the first low potential power supply terminal VSSQ, and the second electrode of the second node pull-down transistor T56 is connected to the third node P.

[0075] Specifically, the second pull-down maintaining module 314b also includes a third node pull-down transistor T65 and a fourth node pull-down transistor T66, the gate of the third node pull-down transistor T65 is connected to the fifth node Q3, the first electrode of the third node pull-down transistor T65 is connected to the first low potential power supply terminal VSSQ, and the second electrode of the third node pull-down transistor T65 is connected to the second electrode of the sixth inverting transistor T62; the gate of the fourth node pull-down transistor T66 is connected to the fifth node Q3, the first electrode of the fourth node pull-down transistor T66 is connected to the first low potential power supply terminal VSSQ, and the second electrode of the fourth node pull-down transistor T66 is connected to the fourth node O.

[0076] Specifically, the fifth node Q3 is the first node Q1 in the upper two-stage gate driving units.

[0077] In some embodiments, Figure 3 , Figure 4 As shown, the first gate driving unit 211 and the second gate driving unit 212 both include a reset module 315, the reset module 315 includes a reset transistor Tr, the gate of the reset transistor Tr is connected to the reset signal line Reset or the start signal line STV, the first electrode of the reset transistor Tr is connected to the first low potential power supply terminal VSSQ, and the second electrode of the reset transistor Tr is connected to the first node Q1.

[0078] Specifically, Figure 3 As shown, the gate and the first electrode of the pull-up control transistor T11 of the first-stage first gate driving unit are connected to the start signal line STV, the gate of the pull-up control transistor T11 of the n-th stage first gate driving unit is connected to the stage transmission signal terminal ST(n-4) of the first 4-stage first gate driving units, and the gate of the pull-up control transistor T11 of the n-th stage first gate driving unit is connected to the signal output terminal G(n-4) of the first 4-stage first gate driving units. When the reset transistor Tr is connected to the start signal line STV, the first-stage first gate driving unit may not be provided with the reset transistor Tr, or the reset transistor Tr of the first gate driving unit may be connected to the reset signal line Reset; when the reset transistor Tr is connected to the reset signal line Reset, the reset transistor Tr of the first-stage first gate driving unit is also connected to the reset signal line Reset.

[0079] Specifically, Figure 3 , Figure 4 As shown, the first gate driving unit 211 and the second gate driving unit 212 both include a storage capacitor Cbt, one plate of the storage capacitor Cbt is connected to the first node Q1, and the other plate of the storage capacitor is connected to the signal output terminal G(n) of the first gate driving unit 211 or the signal output terminal G(N+m) of the second gate driving unit 212.

[0080] Specifically, the channel width of the first pull-up transistor in the second gate driving unit is 0.7 to 0.9 times, and specifically may be 0.8 times, the channel width of the first pull-up transistor in the first gate driving unit.

[0081] Specifically, the channel width of the second pull-up transistor in the second gate driving unit is 0.7 to 0.9 times, and specifically may be 0.8 times, the channel width of the second pull-up transistor in the first gate driving unit.

[0082] The gate driving circuit is tested with the first gate driving unit and the second gate driving unit having the same circuit structure, a second pull-down transistor T31 is provided in the first gate driving unit and the second gate driving unit, the channel width of the first pull-up transistor in the second gate driving unit is 0.8 times the channel width of the first pull-up transistor in the first gate driving unit, and the channel width of the second pull-up transistor in the second gate driving unit is 0.8 times the channel width of the second pull-up transistor in the first gate driving unit, and the following Table 1 is obtained:

[0083] Table 1. Test results of gate drive circuit

[0084]

[0085] The "Size Design" column refers to Figure 3 , Figure 4The channel width design of each transistor in, "W11" refers to the channel width of the first pull-up control transistor T11. Similarly, the meanings of other parameters can be determined. The difference between the first gate driving unit and the second gate driving unit is that the channel width of the first pull-up transistor T21 in the first gate driving unit is W21, the channel width of the first pull-up transistor T21 in the second gate driving unit is W21*0.8, the channel width of the second pull-up transistor T22 in the first gate driving unit is W22, and the channel width of the second pull-up transistor T22 in the second gate driving unit is W22*0.8. The "Simulation Evaluation" column refers to the data obtained by simulating and evaluating the display device, where the "Project" column refers to the test items, "VGH Margin" refers to the normal operation simulation at the highest voltage, "Von Margin" is the on-state voltage boundary simulation, "P Shift Margin" refers to the positive threshold voltage shift simulation, "N Shift Margin" refers to the negative threshold voltage shift simulation, "HT Margin" refers to high temperature simulation, "LT Margin" refers to low temperature simulation, and "RAMargin" refers to reliability simulation. From the simulation results, the simulation structure of each transistor is "A+", indicating good performance, thereby reducing the space occupied by the second gate drive unit and improving the yield of the display panel without affecting the performance of the display panel.

[0086] In some embodiments, Figures 1 to 9 As shown, the number of transistors in at least one stage of the second gate driving unit 212 is smaller than the number of transistors in the first gate driving unit 211 (for example Figure 3 , Figure 4 The second gate driving unit 212 has only 4 transistors, and the first gate driving unit has 19 transistors. By making the number of transistors in at least one level of the second gate driving unit 212 smaller than the number of transistors in the first gate driving unit 211, the space of the lower frame occupied by the second gate driving unit 212 can be reduced, so that the space for arranging other wirings in the lower frame is increased, thereby reducing the risk of short circuit and open circuit of the wiring of the lower frame, and improving the yield of the display panel.

[0087] In some embodiments, Figure 3 , Figure 5As shown, the first gate driving unit 211 includes a second pull-up control module 311a, a second pull-up module 312a, a second pull-down module 313a and a pull-down maintaining module 314, the second pull-up module 312a and the second pull-up control module 311a are connected to the first node Q1, the second pull-down module 313a and the second pull-up module 312a are connected to the first node Q1, and the pull-down maintaining module 314 and the second pull-up module 312a are connected to the first node Q1;

[0088] The second gate driving unit 212 includes a third pull-up control module 321, a third pull-up module 322 and a third pull-down module 323, wherein the third pull-up module 322 and the third pull-up control module 321 are connected to the second node Q2, and the third pull-down module 323 and the third pull-up module 322 are connected to the second node Q2;

[0089] Among them, the number of transistors in the third pull-up module 322 is less than the number of transistors in the second pull-up module 312a; and / or, the second gate driving unit 212 is not provided with the pull-down maintaining module 314. By making the number of transistors in the third pull-up module less than the number of transistors in the second pull-up module, and / or, the second gate driving unit 212 is not provided with the pull-down maintaining module 314, the number of transistors in the second gate driving unit can be reduced, thereby reducing the occupied space of the second gate driving unit, avoiding the problem of short circuit or open circuit caused by too small spacing and width of the wiring and terminals in the binding area, and improving the yield of the display panel.

[0090] Specifically, the number of transistors in the third pull-up module may be less than the number of transistors in the second pull-up module; the number of transistors in the third pull-up module may be equal to the number of transistors in the second pull-up module, and the pull-down maintaining module may not be provided in the second gate driving unit; or the number of transistors in the third pull-up module may be less than the number of transistors in the second pull-up module, and the pull-down maintaining module may not be provided in the second gate driving unit.

[0091] Specifically, the second gate driving unit 212 does not have a level transmission signal terminal. By not having a level transmission signal terminal in the second gate driving unit 212, the number of signal lines can be reduced, the space occupied by the second gate driving unit can be reduced, and the transistor connected to the level transmission signal terminal can be removed, further reducing the space occupied by the second gate driving unit.

[0092] In some embodiments, Figure 3 , Figure 5As shown, in the first gate driving unit 211, the second pull-up module 312a includes a first pull-up transistor T21 and a second pull-up transistor T22, the first pull-up transistor T21 is electrically connected to the signal output terminal G(n) of the first gate driving unit 211, and in the second gate driving unit 212, the third pull-up module 322 includes the first pull-up transistor T21, and the first pull-up transistor T21 is electrically connected to the signal output terminal G(N+m) of the second gate driving unit 212. By not providing the second pull-up transistor in the second gate driving unit, the occupied space of the second gate driving unit can be reduced, and the problem of short circuit or open circuit caused by too small spacing and width of the wiring and terminals in the binding area can be avoided, thereby improving the yield of the display panel.

[0093] Specifically, Figure 3 As shown, in the first gate driving unit 211, the connection relationship between the first pull-up transistor T21 and the second pull-up transistor T22 and each wiring, transistor, node and signal terminal can refer to the connection relationship between the first pull-up transistor T21 and the second pull-up transistor T22 and each wiring, transistor, node and signal terminal in the above embodiment. Figure 5 As shown, in the second gate driving unit 212, the gate of the first pull-up transistor T21 is connected to the second node Q2, the first electrode of the first pull-up transistor T21 is connected to the clock signal line CK, and the second electrode of the first pull-up transistor T21 is connected to the signal output terminal G(n) of the first gate driving unit 211 or the signal output terminal G(N+m) of the second gate driving unit 212.

[0094] In some embodiments, Figure 3 , Figure 5 As shown, the second pull-up control module 311a includes a pull-up control transistor T11, and the third pull-up control module 321 includes the pull-up control transistor T11. In the first gate driving unit 211, the gate of the pull-up control transistor T11 is connected to the stage signal transmission end of the first gate driving unit 211 of the other stage, and the first electrode of the pull-up control transistor T11 is connected to the signal output end of the first gate driving unit 211 of the other stage;

[0095] In the second gate driving unit 212 , the gate of the pull-up control transistor T11 and the first electrode of the pull-up control transistor T11 are connected to the signal output end of the other stage first gate driving unit 211 or the other stage second gate driving unit 212 .

[0096] Specifically, Figure 3As shown, in the first gate driving unit 211, the connection relationship between the pull-up control transistor T11 and each wiring, transistor, node and signal terminal can refer to the connection relationship between the pull-up control transistor T11 and each wiring, transistor, node and signal terminal in the above embodiment. Figure 5 As shown, in the second gate driving unit 212, the gate and the first electrode of the pull-up control transistor T11 of the m-th level second gate driving unit are connected to the signal output terminal G(N+mX) of the previous X-level gate driving unit (which can be the first gate driving unit or the second gate unit).

[0097] Specifically, X is greater than or equal to 1, and X is a positive integer. Specifically, X may be half of the number of clock signal lines in a group of clock signal lines. For example, if a gate drive circuit on one side is connected to a group of clock signal lines, and the number of clock signal lines in a group of clock signal lines is 8, then X may be 4.

[0098] In some embodiments, Figure 3 , Figure 5 As shown, in the first gate driving unit 211, the second pull-down module 313a includes a first pull-down transistor T41, and the gate of the first pull-down transistor T41 is connected to the stage signal transmission end of the first gate driving unit 211 of another stage or the signal output end of the second gate driving unit 212 of another stage;

[0099] In the second gate driving unit 212 , the third pull-down module 323 includes the first pull-down transistor T41 , and the gate of the first pull-down transistor T41 is connected to the signal output terminal of the second gate driving unit 212 of another stage.

[0100] Specifically, Figure 3 As shown, in the first gate driving unit 211, the connection relationship between the first pull-down transistor T41 and each wiring, transistor, node and signal terminal can refer to the connection relationship between the first pull-down transistor T41 and each wiring, transistor, node and signal terminal in the above embodiment. Figure 5 As shown, in the second gate driving unit 212, the gate of the first pull-down transistor T41 of the m-th second gate driving unit 212 is connected to the signal output terminal G(N+m+X) of the second gate driving unit of the subsequent X levels, the first electrode of the first pull-down transistor T41 of the m-th second gate driving unit 212 is connected to the first low potential power supply terminal VSSQ, and the second electrode of the first pull-down transistor T41 of the m-th second gate driving unit 212 is connected to the second node Q2.

[0101] In some embodiments, Figure 5As shown, in the second gate driving unit 212, the third pull-down module 323 also includes a second pull-down transistor T31, the gate of the second pull-down transistor T31 is connected to the gate of the first pull-down transistor T41, the second pull-down transistor T31 is connected to the signal output end of the second gate driving unit 212, and the second pull-down transistor T31 is electrically connected to the second node Q2.

[0102] Specifically, Figure 5 As shown, the gate of the second pull-down transistor T31 of the m-th second gate driving unit 212 is connected to the signal output terminal G(N+m+X) of the second gate driving unit of the next X levels, the first electrode of the second pull-down transistor T31 of the m-th second gate driving unit 212 is connected to the first low potential power supply terminal VSSQ, and the second electrode of the second pull-down transistor T31 of the m-th second gate driving unit 212 is connected to the signal output terminal G(N+m) of the second gate driving unit of this level.

[0103] Specifically, the second pull-down module 313a in the first gate driving unit may also include a second pull-down transistor, the gate of the second pull-down transistor is connected to the gate of the first pull-down transistor, the first electrode of the second pull-down transistor is connected to the second low potential power supply terminal VSSG, and the second electrode of the second pull-down transistor is connected to the signal output terminal G(n) of the first gate driving unit 211.

[0104] Specifically, the design and connection relationship of the transistors in the pull-down maintaining module 314 can refer to the above embodiments, which will not be described in detail here.

[0105] Specifically, the above-mentioned embodiment is described by taking the case where no pull-down maintaining module is provided in the second gate driving unit as an example, but the embodiments of the present application are not limited to this. In the second gate driving unit, only some transistors in the pull-down maintaining module can be removed. For example, a pull-down maintaining module is provided in the second gate driving unit, and the pull-down maintaining module does not include the third pull-down maintaining transistor T72 and the sixth pull-down maintaining transistor T73.

[0106] In some embodiments, Figure 3 As shown, the first gate driving unit 211 further includes a reset module 315 , and the reset module 315 and the first pull-up control module 311 are connected to the first node Q1 .

[0107] Specifically, Figure 3 As shown, the reset module 315 includes the connection relationship between the reset transistor Tr and each wiring, transistor, node and signal terminal, and the connection relationship between the reset transistor Tr and each wiring, transistor, node and signal terminal in the above embodiment can be referred to.

[0108] In some embodiments, Figure 5As shown, the reset module 315 is not provided in the second gate driving unit 212. By not providing the reset module in the second gate driving unit, the occupied space of the second gate driving unit is further reduced, thereby avoiding the problem of short circuit or open circuit caused by too small spacing and width of the wiring and terminals in the binding area, thereby improving the yield of the display panel.

[0109] In some embodiments, Figure 3 , Figure 5 As shown, the first gate driving unit 211 also includes a storage capacitor Cbt, and the second gate driving unit 212 is not provided with a storage capacitor. By not providing a storage capacitor in the second gate driving unit, the occupied space of the second gate driving unit can be further reduced, thereby avoiding the problem of short circuit or open circuit caused by too small spacing and width of the wiring and terminals in the binding area, thereby improving the yield of the display panel.

[0110] In some embodiments, the display panel 1 includes multiple stages of the second gate driving units 212 , and each stage of the second gate driving units 212 is the same, or each stage of the second gate driving units 212 is different.

[0111] Specifically, since the gate driving circuits in different display panels are different, correspondingly, different numbers of second gate driving units need to be set to output stage transmission signals, then one-stage second gate driving unit or multiple-stage second gate driving units can be set accordingly. When multiple-stage second gate driving units are set, each stage of the second gate driving units can be the same, for example, all use Figure 4 or Figure 5 The design can also make some of the second gate drive units different, for example, the first-level second gate drive unit adopts Figure 4 and Figure 7 , Figure 8 The design of the first-level second gate drive unit adopts Figure 5 design.

[0112] Specifically, the above embodiments are described by taking as an example that the channel width of the transistor in at least one level of the second gate driving unit is smaller than the channel width of the corresponding transistor in the first gate driving unit, and the number of transistors in at least one level of the second gate driving unit is smaller than the number of transistors in the first gate driving unit. It can be understood that when there is no conflict between the embodiments, the embodiments can be combined or separated and then combined. For example, the first gate driving unit includes a second pull-up control module, a second pull-up module, a second pull-down module and a pull-down maintaining module. The second pull-up module and the second pull-up control module are connected to the first node, and the second pull-down module and the second pull-up module are connected to the first node. The pull-down maintaining module and the second pull-up module are connected to the first node; the second gate driving unit includes a third pull-up control module, a third pull-up module and a third pull-down module, the third pull-up module and the third pull-up control module are connected to the second node, and the third pull-down module and the third pull-up module are connected to the second node; wherein the number of transistors in the third pull-up module is less than the number of transistors in the second pull-up module; the second pull-up module includes a first pull-up transistor, the third pull-up module includes the first pull-up transistor, and the channel width of the first pull-up transistor in the first gate driving unit is greater than the channel width of the first pull-up transistor in the second gate driving unit.

[0113] In another example, the first gate driving unit includes a second pull-up control module, a second pull-up module, a second pull-down module, a pull-down maintaining module and a reset module, the second pull-up module and the second pull-up control module are connected to a first node, the second pull-down module and the second pull-up module are connected to the first node, and the pull-down maintaining module and the second pull-up module are connected to the first node; the second gate driving unit includes a third pull-up control module, a third pull-up module and a third pull-down module, the third pull-up module and the third pull-up control module are connected to the second node, and the third pull-down module and the third pull-up module are connected to the second node; wherein the number of transistors in the third pull-up module is less than the number of transistors in the second pull-up module; and / or at least one of the pull-down maintaining module and the reset module is not provided in the second gate driving unit.

[0114] The gate drive circuit uses Figure 3 and Figure 5 When the circuit shown in the figure is designed, the display panel is tested and the Fig. 9 , Fig. 9 The horizontal axis is time, in microseconds. Fig. 9The vertical axis in is voltage, in volts, and curve 01 is the timing of the signal output end of the second gate driving unit. It can be seen that the timing of the second gate driving unit is similar to or even the same as the timing of the first gate driving unit, indicating that the embodiment of the present application can ensure the normal operation of the gate driving circuit.

[0115] Specifically, each transistor in the embodiment of the present application may be an N-type transistor.

[0116] Specifically, each transistor in the embodiment of the present application can be a silicon semiconductor transistor (for example, a low-temperature polycrystalline silicon thin film transistor) to reduce power consumption, but the embodiment of the present application is not limited to this. Each transistor can be an oxide semiconductor transistor (for example, an indium gallium zinc oxide thin film transistor), or some transistors can be silicon semiconductor transistors (for example, low-temperature polycrystalline silicon thin film transistors) and some transistors can be oxide semiconductor transistors (for example, indium gallium zinc oxide thin film transistors).

[0117] Specifically, the first electrode may be a source electrode and the second electrode may be a drain electrode; or the first electrode may be a drain electrode and the second electrode may be a source electrode.

[0118] At the same time, an embodiment of the present application provides a display device, which includes a display panel as described in any of the above embodiments.

[0119] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0120] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0121] The embodiments, implementation methods and related technical features of the present application can be combined and replaced with each other without conflict.

[0122] The above are only preferred embodiments of the present application and do not constitute any form of limitation to the present application. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A display panel, characterized in that: The gate driving circuit includes a cascaded multi-stage first gate driving unit and at least one stage of a second gate driving unit, wherein the first gate driving unit is configured to output a scanning signal, and the second gate driving unit is configured to output a stage transmission signal to the first gate driving unit; Wherein, in a direction perpendicular to an arrangement direction of the first gate driving units of each level, a width of the second gate driving unit is smaller than a width of the first gate driving unit.

2. The display panel according to claim 1, characterized in that: A channel width of a transistor in at least one stage of the second gate driving unit is smaller than a channel width of a corresponding transistor in the first gate driving unit.

3. The display panel according to claim 2, characterized in that: The first gate driving unit and the second gate driving unit both include: A first pull-up control module; A first pull-up module, connected to the first pull-up control module at a first node; A first pull-down module connected to the first pull-up module at the first node; Wherein, a channel width of at least one transistor in the first pull-up module of the second gate driving unit is smaller than a channel width of a corresponding transistor in the first pull-up module of the first gate driving unit.

4. The display panel according to claim 3, characterized in that: The first pull-up module comprises: a first pull-up transistor, wherein a gate of the first pull-up transistor is connected to the first node, a first electrode of the first pull-up transistor is connected to a clock signal line, and a second electrode of the first pull-up transistor is connected to a signal output terminal of the first gate driving unit or a signal output terminal of the second gate driving unit; a second pull-up transistor, wherein a gate of the second pull-up transistor is connected to the first node, a first electrode of the second pull-up transistor is connected to a clock signal line, and a second electrode of the second pull-up transistor is connected to a level transmission signal terminal of the first gate driving unit or a level transmission signal terminal of the second gate driving unit; wherein a channel width of the first pull-up transistor in the first gate driving unit is greater than a channel width of the first pull-up transistor in the second gate driving unit; And / or, a channel width of the second pull-up transistor in the first gate driving unit is greater than a channel width of the second pull-up transistor in the second gate driving unit.

5. The display panel according to any one of claims 1 to 2, characterized in that: The number of transistors in at least one stage of the second gate driving unit is smaller than the number of transistors in the first gate driving unit.

6. The display panel according to claim 5, characterized in that: The first gate driving unit includes a second pull-up control module, a second pull-up module, a second pull-down module and a pull-down maintaining module, the second pull-up module and the second pull-up control module are connected to a first node, the second pull-down module and the second pull-up module are connected to the first node, and the pull-down maintaining module and the second pull-up module are connected to the first node; The second gate driving unit includes a third pull-up control module, a third pull-up module and a third pull-down module, wherein the third pull-up module and the third pull-up control module are connected to a second node, and the third pull-down module and the third pull-up module are connected to the second node; Wherein, the number of transistors in the third pull-up module is less than the number of transistors in the second pull-up module; And / or, the second gate driving unit is not provided with the pull-down maintaining module.

7. The display panel according to claim 6, characterized in that: In the first gate driving unit, the second pull-up module includes a first pull-up transistor and a second pull-up transistor, and the first pull-up transistor is electrically connected to the signal output terminal of the first gate driving unit; In the second gate driving unit, the third pull-up module includes the first pull-up transistor, and the first pull-up transistor is electrically connected to the signal output terminal of the second gate driving unit.

8. The display panel according to claim 6, characterized in that: The second pull-up control module includes a pull-up control transistor, the third pull-up control module includes the pull-up control transistor, in the first gate driving unit, the gate of the pull-up control transistor is connected to the stage signal transmission end of the first gate driving unit of the other stage, and the first electrode of the pull-up control transistor is connected to the signal output end of the first gate driving unit of the other stage; In the second gate driving unit, the gate of the pull-up control transistor and the first electrode of the pull-up control transistor are connected to the signal output end of the first gate driving unit of another stage or the second gate driving unit of another stage.

9. The display panel according to claim 6, characterized in that: In the first gate driving unit, the second pull-down module includes a first pull-down transistor, and the gate of the first pull-down transistor is connected to the stage signal transmission terminal of the first gate driving unit of another stage or the signal output terminal of the second gate driving unit of another stage; In the second gate driving unit, the third pull-down module includes the first pull-down transistor, and a gate of the first pull-down transistor is connected to a signal output terminal of a second gate driving unit at another stage.

10. The display panel according to claim 9, characterized in that: In the second gate driving unit, the third pull-down module also includes a second pull-down transistor, the gate of the second pull-down transistor is connected to the gate of the first pull-down transistor, the second pull-down transistor is connected to the signal output end of the second gate driving unit, and the first pull-down transistor is electrically connected to the second node.

11. The display panel according to claim 6, characterized in that: The first gate driving unit further includes a reset module, and the reset module and the second pull-up control module are connected to the first node.

12. The display panel according to claim 11, characterized in that: The second gate driving unit is not provided with the reset module.

13. The display panel according to claim 1, characterized in that: The display panel includes a plurality of stages of the second gate driving units, and the second gate driving units at each stage are the same, or the second gate driving units at each stage are different.

14. A display device, characterized in that: Comprising the display panel as claimed in any one of claims 1 to 13.

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