Display panel driving method and device, and display device

Abstract

The present invention discloses a driving method and device for a display panel, and a display device, and belongs to the field of display technology. In the display panel, a first scanning circuit and a second scanning circuit are connected to different clock signals, and the second scanning circuit is also connected to a partition enable signal; the voltages of each clock signal and the partition enable signal are provided by the same power supply; the first scanning circuit is used to provide a first scanning signal to each pixel circuit, and the second scanning circuit is used to control the frequency of the second scanning signal provided to each pixel circuit according to the partition enable signal; the driving method of the display panel includes: when the display panel displays at least two display partitions with different refresh frequencies, controlling the voltage jump edges in all clock signals connected to the first scanning circuit to not overlap in time with the voltage jump edges in the same voltage jump direction in all clock signals connected to the second scanning circuit. The present invention can solve the problem of horizontal stripes when the display panel displays in partitioned multi-frequency mode.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a method and device for driving a display panel, and a display device. Background Art

[0002] With the development of display technology, zoned multi-frequency technology is gaining increasing attention. Dividing a screen into different areas and using different refresh rates based on the displayed content allows for refined scene control while reducing power consumption. However, related technologies have been associated with horizontal stripes on display panels when using zoned multi-frequency display. Summary of the Invention

[0003] The present invention provides a display panel driving method and device, and a display device, so as to solve the problem of horizontal stripes when the display panel performs partitioned multi-frequency display.

[0004] In a first aspect, an embodiment of the present invention provides a method for driving a display panel, the display panel comprising: a first scanning circuit, a second scanning circuit, and a plurality of pixel circuits; the first scanning circuit and the second scanning circuit are connected to different clock signals, and the second scanning circuit is also connected to a partition enable signal; the voltages of the clock signals and the partition enable signal are provided by the same power supply; the first scanning circuit is configured to provide a first scanning signal to each pixel circuit, and the second scanning circuit is configured to control the frequency of a second scanning signal provided to each pixel circuit according to the partition enable signal;

[0005] The driving method of the display panel includes:

[0006] When the display panel displays in at least two display partitions with different refresh frequencies, the voltage jump edges in all clock signals connected to the first scanning circuit are controlled to not overlap in time with the voltage jump edges in the same voltage jump direction in all clock signals connected to the second scanning circuit.

[0007] Optionally, each of the clock signals is a pulse signal in which a first voltage and a second voltage appear alternately; the second scanning circuit is connected to at least one of the partition enable signals;

[0008] The display panel driving method further includes:

[0009] When the display panel needs to display in at least two display partitions with different refresh frequencies, controlling at least part of the partition enable signals to be signals that alternate between a first voltage and a second voltage, so that the frequencies of the second scanning signals received by at least two display partitions are different; wherein the refresh frequency of any display partition is the frequency of the second scanning signal received by the display partition; the first voltage of each clock signal and each partition enable signal is provided by the same power supply, and the second voltage of each clock signal and each partition enable signal is provided by the same power supply;

[0010] Preferably, the display panel further comprises a plurality of light-emitting devices arranged in an array, each of the pixel circuits being connected to each of the light-emitting devices in a one-to-one correspondence; the second scanning circuit comprises a plurality of second shift registers connected in cascade, each of the second shift registers being connected to a corresponding partition enable signal, and one of the second shift registers providing the second scanning signal to each of the pixel circuits connected to at least one row of the light-emitting devices;

[0011] For any pixel circuit, in the gate initialization phase and the data writing phase of any display frame, the second shift register controls the voltage of the second scanning signal output to be equal to the voltage of the input partition enable signal.

[0012] Optionally, the driving method of the display panel also includes: controlling at least part of the voltage jump edges in at least part of the clock signal connected to the first scanning circuit to overlap in time with at least part of the voltage jump edges in the opposite direction of the voltage jump of at least part of the clock signal connected to the second scanning circuit.

[0013] Optionally, controlling at least some of the voltage transition edges in at least some of the clock signals connected to the first scanning circuit to overlap in time with at least some of the voltage transition edges in opposite directions in at least some of the clock signals connected to the second scanning circuit includes:

[0014] Controlling at least part of the voltage rising edges of at least one clock signal connected to the first scanning circuit to overlap in time with at least part of the voltage falling edges of at least one clock signal connected to the second scanning circuit;

[0015] or,

[0016] Controlling at least part of the voltage falling edges of at least one clock signal connected to the first scanning circuit to overlap in time with at least part of the voltage rising edges of at least one clock signal connected to the second scanning circuit;

[0017] Preferably, the frequencies and pulse widths of all clock signals connected to the first scanning circuit and the second scanning circuit are the same.

[0018] Optionally, the driving method of the display panel also includes: controlling the voltage jump edges in all clock signals connected to the first scanning circuit to avoid overlapping in time with the voltage jump edges in the opposite direction of the voltage jump in all clock signals connected to the second scanning circuit.

[0019] Optionally, the pixel circuit includes: a driving transistor, a threshold compensation transistor and a first initialization transistor; the threshold compensation transistor is connected between the gate and the second electrode of the driving transistor, and the first initialization transistor is connected to the second electrode of the driving transistor;

[0020] The first scanning circuit is used to provide the first scanning signal to the gate of each of the first initialization transistors, and the second scanning circuit is used to provide the second scanning signal to the gate of each of the threshold compensation transistors;

[0021] Preferably, the threshold compensation transistor and the first initialization transistor have the same channel type;

[0022] Preferably, the first scanning circuit is further connected to a first start signal, and is used to generate each first scanning signal according to the first start signal and the connected clock signal; the second scanning circuit is further connected to a second start signal, and is used to generate each second scanning signal according to the second start signal, the partition enable signal, and the connected clock signal; the first start signal and the second start signal have the same frequency but different pulse widths;

[0023] The display panel driving method further includes:

[0024] Controlling the pulse width of the first start signal to be smaller than the pulse width of the second start signal; and controlling each pulse of the second start signal to temporally overlap each pulse of the first start signal;

[0025] Preferably, the pixel circuit further includes a data writing transistor connected to the first electrode of the driving transistor; the display panel further includes a third scanning circuit, the third scanning circuit receiving a third start signal, the third scanning circuit being configured to provide a third scanning signal to the gate of the data writing transistor in each pixel circuit according to the third start signal; wherein the third start signal has the same frequency as the first start signal;

[0026] The display panel driving method further includes:

[0027] Controlling the pulse width of the third start signal to be one line time; controlling the starting time of the first pulse of the third start signal to be later than or simultaneous with the ending time of the first pulse of the first start signal; and controlling each pulse of the second start signal to temporally overlap each pulse of the first start signal and each pulse of the third start signal;

[0028] Preferably, the first scanning circuit is connected to two clock signals; the pulse start time of the first start signal overlaps with a voltage transition edge of one of the clock signals connected to the first scanning circuit;

[0029] The second scanning circuit is connected to the two clock signals; the pulse start moment of the second start signal overlaps in time with a voltage jump edge of one of the clock signals connected to the second scanning circuit.

[0030] Optionally, the pulse width of the first start signal is: L1∈[2H, 10H], where L1 is the pulse width of the first start signal and H is the line time.

[0031] Optionally, the display panel further includes a plurality of light-emitting devices arranged in an array, and each pixel circuit is connected to each light-emitting device in a one-to-one correspondence; each pixel circuit connected to each of the light-emitting devices in every k rows receives the same second scanning signal; k is a positive integer;

[0032] The pulse width of the second start signal satisfies: L2≥k*(L1+H); wherein L2 is the pulse width of the second start signal;

[0033] Preferably, L2≥18H;

[0034] Preferably, k=2, L1=2H, and L2=18H.

[0035] In a second aspect, an embodiment of the present invention further provides a driving device for a display panel, comprising:

[0036] The time phase control module is used to control the voltage jump edges in all clock signals connected to the first scanning circuit to avoid temporal overlap with the voltage jump edges in the same voltage jump direction in all clock signals connected to the second scanning circuit when the display panel displays in at least two display partitions with different refresh frequencies.

[0037] In a third aspect, an embodiment of the present invention further provides a display device, comprising: a display panel and a driving chip, wherein the driving chip is used to execute the display panel driving method provided by any embodiment of the present invention.

[0038] In the driving method of the display panel provided by an embodiment of the present invention, by controlling the voltage transition edges in all clock signals connected to the first scanning circuit and the voltage transition edges in the same voltage transition direction in all clock signals connected to the second scanning circuit, so that they do not overlap in time, the load on the power supply used to provide voltage to the clock signals and partition enable signals can be effectively dispersed, avoiding sudden changes in the load that cause significant jitter in the voltage output of the power supply. In this way, the voltage jitter of the partition enable signal can be effectively reduced. In the partition multi-frequency display mode, the partition enable signal itself needs to undergo a voltage transition corresponding to the intersection position of adjacent display partitions. By reducing the voltage jitter on the partition enable signal, the voltage jitter of the second scanning signal can be reduced, thereby reducing the impact on the on-off state of the transistor connected to the second scanning signal in the pixel circuit, reducing the voltage fluctuation of the gate of the driving transistor in the pixel circuit, and effectively improving the horizontal stripe problem during partition multi-frequency display.

[0039] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0041] Figure 1 is a schematic structural diagram of a display panel provided by an embodiment of the present invention;

[0042] Figure 2 It is a timing relationship diagram of each clock signal in the related art;

[0043] Figure 3 This is a timing relationship diagram of various clock signals provided by an embodiment of the present invention;

[0044] Figure 4 is another timing relationship diagram of various clock signals provided by an embodiment of the present invention;

[0045] Figure 5 This is another timing relationship diagram of various clock signals provided by an embodiment of the present invention;

[0046] Figure 6 is a structural diagram of another display panel provided by an embodiment of the present invention;

[0047] Figure 7is a structural diagram of a second shift register provided by an embodiment of the present invention;

[0048] Figure 8 is a structural schematic diagram of a pixel circuit provided by an embodiment of the present invention;

[0049] Figure 9 This is a driving timing diagram of a pixel circuit provided by an embodiment of the present invention;

[0050] Figure 10 This is a driving timing diagram of a display panel provided by an embodiment of the present invention;

[0051] Figure 11 is a structural diagram of a second scanning circuit provided by an embodiment of the present invention;

[0052] Figure 12 is a driving timing diagram of another display panel provided by an embodiment of the present invention;

[0053] Figure 13 This is a driving timing diagram of another pixel circuit provided by an embodiment of the present invention;

[0054] Figure 14 It is a structural schematic diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0055] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0056] It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and the accompanying drawings are used to distinguish similar items and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, such that the embodiments of the present invention described herein can be implemented in sequences other than those illustrated or described herein. Furthermore, the terms "including," "having," and any variations thereof are intended to cover non-exclusive inclusions.

[0057] An embodiment of the present invention provides a method for driving a display panel. By adjusting the time phase of clock signals connected to different scanning circuits, the horizontal stripe problem in a partitioned multi-frequency display mode can be effectively improved. The method can be executed by a driving device of the display panel. The driving device of the display panel can be implemented in the form of hardware and / or software. The driving device of the display panel can be configured in a driver chip of the display device.

[0058] The structure and driving process of the display panel are first briefly described below. Figure 1 Schematic diagram of the structure of a display panel provided by an embodiment of the present invention. Figure 1 The display panel includes a first scanning circuit 11, a second scanning circuit 12, and a plurality of pixel circuits 20. The first scanning circuit 11 and the second scanning circuit 12 receive different clock signals. For example, the first scanning circuit 11 receives a first clock signal CK1 and a second clock signal CK2, while the second scanning circuit 12 receives a third clock signal CK3 and a fourth clock signal CK4. The second scanning circuit 12 also receives a partition enable signal VFE. The display panel also includes a plurality of light-emitting devices arranged in an array, and each pixel circuit 20 is connected to a light-emitting device in a one-to-one correspondence. Figure 1 For example, the pixel circuits 20 may be arranged in an array in the display area AA of the display panel 100 , and the first scanning circuit 11 and the second scanning circuit 12 are both disposed in the non-display area NAA of the display panel 100 .

[0059] The first scanning circuit 11 and the second scanning circuit 12 are both connected to each pixel circuit 20, and for the same pixel circuit 20, the first scanning circuit 11 and the second scanning circuit 12 are connected to different signal terminals of the pixel circuit 20. The first scanning circuit 11 is used to provide a first scanning signal S1 to each pixel circuit 20, and the second scanning circuit 12 is used to control the frequency of the second scanning signal S2 provided to each pixel circuit 20 according to the partition enable signal VFE, thereby controlling the position and refresh frequency of each display partition in the display panel 100. Specifically, the first scanning circuit 11 can receive a first start signal having a pulse with a certain frequency, and according to the control of the first clock signal CK1 and the second clock signal CK2, the pulse of the first start signal is shifted and output step by step, thereby obtaining a first scanning signal S1 having the same frequency as the first start signal at each stage. The second scanning circuit 12 can receive a second start signal having a pulse frequency (e.g., the same as the frequency of the first start signal), and control the step-by-step shift transmission of the pulses of the second start signal according to the third clock signal CK3 and the fourth clock signal CK4, thereby obtaining a level transmission signal having the same frequency as the second start signal at each level. Furthermore, the voltage of the output second scanning signal S2 at each level is controlled according to the partition enable signal VFE. The number of pulses in the second scanning signal S2 at any level is less than or equal to the number of pulses in the level transmission signal at the same level, so that the frequency of the second scanning signal S2 at that level is less than or equal to the frequency of the level transmission signal at the same level. The second scanning signal S2 is used to control whether a driving phase related to the gate voltage of the driving transistor in the pixel circuit is performed, such as whether a gate initialization phase and a data writing phase are performed. The frequency of the second scanning signal S2 received by the pixel circuit 20 in the same display partition is the refresh frequency of the display partition. Scanning signals are typically provided to each pixel circuit 20 via a scan line extending along the row direction X. Each pixel circuit 20 in the same row receives the same first scan signal S1 and the same second scan signal S2. The pixel circuit 20 is scanned row by row. Therefore, by controlling the frequency of each second scan signal S2, a partitioned multi-frequency display along the column direction Y can be achieved. The row direction X is perpendicular to the column direction Y. The frequency of any scan signal refers to the frequency of the on-pulse in the scan signal. The on-pulse is the pulse that controls the conduction of the transistor in the pixel circuit 20 that receives the scan signal.

[0060] The voltages of each clock signal and the partition enable signal VFE are provided by the same power supply. Specifically, each clock signal is a signal in which a first voltage and a second voltage alternate. In the partition multi-frequency display mode, the partition enable signal VFE is also a signal in which a first voltage and a second voltage alternate. The first voltage of each clock signal and the first voltage of the partition enable signal VFE are provided by, for example, the same first power supply, and the second voltage of each clock signal and the second voltage of the partition enable signal VFE are provided by, for example, the same second power supply.

[0061] The driving method of the display panel includes: when the display panel displays in at least two display partitions with different refresh frequencies, controlling the voltage jump edges in all clock signals connected to the first scanning circuit to not overlap in time with the voltage jump edges in the same voltage jump direction in all clock signals connected to the second scanning circuit.

[0062] The situation where the display panel performs display in at least two display partitions with different refresh frequencies is the situation where the display panel performs display in the partition multi-frequency display mode.

[0063] The two voltage transition edges having the same voltage transition direction means that both voltage transition edges are rising voltage edges or both voltage falling voltage edges. Therefore, the control step specifically includes: controlling the rising voltage edges of all clock signals connected to the first scanning circuit to be staggered in time with the rising voltage edges of all clock signals connected to the second scanning circuit; and controlling the falling voltage edges of all clock signals connected to the first scanning circuit to be staggered in time with the falling voltage edges of all clock signals connected to the second scanning circuit.

[0064] Because the voltages of the clock signals and the partition enable signal VFE are provided by the same power supply, the first scanning circuit 11 and the second scanning circuit 12 both act as loads for the power supplies. Large fluctuations in the loads can cause fluctuations in the voltages output by the power supplies. For example, fluctuations in the voltage output of the first power supply can cause fluctuations in the first voltage of the partition enable signal VFE, while fluctuations in the voltage output of the second power supply can cause fluctuations in the second voltage of the partition enable signal VFE. When the second scanning circuit 12 outputs the second scanning signal S2 for each stage, it outputs the voltage of the connected partition enable signal VFE as the second scanning signal S2 during the period when the stage pass signal of the same stage is outputting an on pulse. For example, the first voltage is the on-voltage of the transistor in the pixel circuit 20 connected to the second scanning signal S2, and the second voltage is the cut-off voltage of the transistor. Exemplarily, the level transfer signal is a high-frequency signal having an on-pulse in each display frame; then, corresponding to the time period in which the level transfer signal of the same level outputs an on-pulse in any display frame, if the partition enable signal VFE is the first voltage, the second scanning signal S2 has an on-pulse in the display frame, and the pixel circuit 20 connected to the second scanning signal S2 performs data refresh in the display frame; if the partition enable signal VFE is the second voltage, the second scanning signal S2 does not have an on-pulse in the display frame, and the pixel circuit 20 connected to the second scanning signal S2 maintains data in the display frame without refreshing data. In summary, the voltage of the partition enable signal VFE determines the on / off state of the transistor connected to the second scan signal S2 in the pixel circuit 20. When the first voltage on the partition enable signal VFE fluctuates, it affects the degree of conduction of the transistor connected to the second scan signal S2, thereby affecting the degree of data writing to the gate of the driver transistor in the pixel circuit 20. When the second voltage on the partition enable signal VFE fluctuates, it affects the degree of off-state of the transistor connected to the second scan signal S2, thereby affecting the degree of leakage of the gate of the driver transistor in the pixel circuit 20. The above-mentioned effects will cause the gate voltage of the driver transistor to deviate from the expected value, resulting in fluctuations in the drive current output by the driver transistor, and thus causing fluctuations in the brightness of the light-emitting device. Because the second scan signal S2 is provided row by row, when the voltage on the partition enable signal VFE fluctuates, the drive current output by an entire row of pixel circuits will fluctuate, resulting in fluctuations in the brightness of an entire row of light-emitting devices, manifesting as a horizontal stripe problem.

[0065] Each clock signal is used to control the on and off of multiple transistors in the corresponding scanning circuit. The load carried by each clock signal serves as an important load of the power supply. Figure 2In the related art, at least part of the voltage rising edge (or voltage falling edge) of each clock signal connected to the first scanning circuit 11 has a voltage rising edge (or voltage falling edge) occurring simultaneously in each clock signal connected to the second scanning circuit 12, resulting in large load fluctuations on the first power supply and the second power supply. Specifically, the pulses of the first clock signal CK1 and the second clock signal CK2 connected to the first scanning circuit 11 appear staggered; the pulses of the third clock signal CK3 and the fourth clock signal CK4 connected to the second scanning circuit 11 appear staggered. Taking the first voltage as a high voltage and the second voltage as a low voltage as an example, see Figure 2 The short dashed line in FIG1 indicates that the voltage rising edge of the first clock signal CK1 and the voltage rising edge of the fourth scanning signal CK4 occur simultaneously, and the voltage rising edge of the second clock signal CK2 and the voltage rising edge of the third scanning signal CK3 occur simultaneously. This will cause the load of the first power supply to increase suddenly and the load of the second power supply to decrease suddenly, thereby causing the first voltage and the second voltage to fluctuate. Figure 2 As shown by the dotted lines in the figure, the falling edge of the first clock signal CK1 coincides with the falling edge of the fourth scan signal CK4, and the falling edge of the second clock signal CK2 coincides with the falling edge of the third scan signal CK3. This causes a sudden drop in the load on the first power supply and a sudden increase in the load on the second power supply, similarly leading to fluctuations in the first and second voltages. In the partitioned multi-frequency display mode, the partition enable signal VFE itself transitions between the first and second voltages, causing load fluctuations on the two power supplies. Combined with the simultaneous voltage transitions in the same direction by different clock signals, the voltage fluctuations of the partition enable signal VFE are more pronounced, making horizontal streaks more likely to occur.

[0066] In this embodiment, see Figure 3 ,like Figure 3 As shown by the short and medium dashed lines, the voltage rising edge of the first clock signal CK1 and the voltage rising edge of the fourth scanning signal CK4 are staggered in time, and the voltage rising edge of the second clock signal CK2 and the voltage rising edge of the third scanning signal CK3 are staggered in time, which can make the load of the first power supply increase in stages and the load of the second power supply decrease in stages, thus achieving load distribution of the two power supplies. Figure 3As shown by the midpoint dashed line, the falling edges of the first clock signal CK1 and the fourth scan signal CK4 are staggered in time, and the falling edges of the second clock signal CK2 and the third scan signal CK3 are staggered in time. This allows the load on the first power supply to decrease in stages and the load on the second power supply to increase in stages, thus distributing the loads on the two power supplies. This arrangement distributes the loads carried by the clock signals, which are the primary loads, in time, reducing jitter in the output voltages of the two power supplies. In particular, corresponding to the display partition boundary position, the partition enable signal VFE itself jumps between the first voltage and the second voltage, which will cause the power supply output voltage to fluctuate and easily cause boundary horizontal stripe problems; but since the load carried by the clock signal is heavier than the load carried by the partition enable signal VFE, compared with the jitter of the power supply output voltage increased due to the load fluctuation carried by the partition enable signal VFE, the improvement effect of reducing the jitter of the power supply output voltage obtained by dispersing the load carried by the clock signal in time is more obvious. Therefore, the jitter of the power supply output voltage can still be reduced as a whole, thereby reducing the voltage jitter of the partition enable signal VFE, and then reducing the voltage jitter of the second scanning signal S2 connected to the pixel circuit 20 at the partition boundary position, which can effectively improve the horizontal stripe problem at the partition boundary.

[0067] In the driving method of the display panel provided by an embodiment of the present invention, by controlling the voltage transition edges in all clock signals connected to the first scanning circuit and the voltage transition edges in the same voltage transition direction in all clock signals connected to the second scanning circuit, so that they do not overlap in time, the load on the power supply used to provide voltage to the clock signals and partition enable signals can be effectively dispersed, avoiding sudden changes in the load that cause significant jitter in the voltage output of the power supply. In this way, the voltage jitter of the partition enable signal can be effectively reduced. In the partition multi-frequency display mode, the partition enable signal itself needs to undergo a voltage transition corresponding to the intersection position of adjacent display partitions. By reducing the voltage jitter on the partition enable signal, the voltage jitter of the second scanning signal can be reduced, thereby reducing the impact on the on-off state of the transistor connected to the second scanning signal in the pixel circuit, reducing the voltage fluctuation of the gate of the driving transistor in the pixel circuit, and effectively improving the horizontal stripe problem during partition multi-frequency display.

[0068] On the basis of the above-mentioned embodiments, optionally, different time alignment relationships can be adopted for each voltage transition edge in each clock signal connected to the first scanning circuit and each voltage transition edge in the opposite direction of the voltage transition in each clock signal connected to the second scanning circuit, which are explained below respectively.

[0069] In one embodiment, optionally, the driving method of the display panel further includes: controlling the voltage transition edges in all clock signals connected to the first scanning circuit to not overlap in time with the voltage transition edges in opposite directions of the voltage transitions in all clock signals connected to the second scanning circuit.

[0070] Among them, the opposite voltage jump directions of the two voltage jump edges means that one of the two voltage jump edges is a voltage rising edge and the other is a voltage falling edge. Then, the control step is specifically as follows: control the voltage rising edges in all clock signals connected to the first scanning circuit and the voltage falling edges in all clock signals connected to the second scanning circuit to be staggered in time; and control the voltage falling edges in all clock signals connected to the first scanning circuit and the voltage rising edges in all clock signals connected to the second scanning circuit to be staggered in time. In this way, all voltage jump edges in all clock signals connected to the first scanning circuit and all voltage jump edges in all clock signals connected to the second scanning circuit do not overlap in time. Exemplarily, the timing relationship diagram of each clock signal obtained by the control of this embodiment can be seen in Figure 3 All voltage transition edges in the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, and the fourth clock signal CK4 do not overlap in time and occur in a time-sharing manner. This arrangement in this embodiment can maximize the dispersion of the power supply load and avoid voltage fluctuations in the power supply output.

[0071] In another embodiment, optionally, the driving method of the display panel also includes: controlling at least part of the voltage jump edges in at least part of the clock signal connected to the first scanning circuit to overlap in time with at least part of the voltage jump edges in the opposite direction of the voltage jump of at least part of the clock signal connected to the second scanning circuit.

[0072] In this way, at least some of the voltage transition edges in the clock signal connected to the first scanning circuit can be matched with voltage transition edges in the clock signal connected to the second scanning circuit that occur simultaneously and in the opposite direction, thereby balancing the load on the power supply and further avoiding voltage jitter in the power supply output. For example, if a rising voltage edge in the clock signal connected to the first scanning circuit and a falling voltage edge in the clock signal connected to the second scanning circuit occur simultaneously, then the clock signal connected to the first scanning circuit will increase the load on the first power supply and reduce the load on the second power supply, while the clock signal connected to the second scanning circuit will reduce the load on the first power supply and increase the load on the second power supply. The effects of the two on the loads of the two power supplies can offset each other, and the loads of the two power supplies will both increase and decrease, achieving dynamic balance between the loads of the first power supply and the second power supply, thereby effectively avoiding voltage jitter in the power supply output.

[0073] Exemplarily, the above-mentioned control of at least some of the voltage transition edges in at least some of the clock signals connected to the first scanning circuit and at least some of the voltage transition edges in the opposite direction of the voltage transition in at least some of the clock signals connected to the second scanning circuit to overlap in time may specifically include: controlling at least some of the voltage rising edges in at least one clock signal connected to the first scanning circuit to overlap in time with at least some of the voltage falling edges in at least one clock signal connected to the second scanning circuit. For example Figure 4 As shown, the voltage rising edge of the first clock signal CK1 and the voltage falling edge of the third clock signal CK3 occur simultaneously, and the voltage rising edge of the second clock signal CK2 and the voltage falling edge of the fourth clock signal CK4 occur simultaneously.

[0074] Alternatively, the above-mentioned control of at least some of the voltage transition edges in at least some of the clock signals connected to the first scanning circuit to overlap in time with at least some of the voltage transition edges in the opposite direction of the voltage transition in at least some of the clock signals connected to the second scanning circuit may specifically include: controlling at least some of the voltage falling edges in at least one clock signal connected to the first scanning circuit to overlap in time with at least some of the voltage rising edges in at least one clock signal connected to the second scanning circuit. For example Figure 5 As shown, the voltage falling edge of the first clock signal CK1 and the voltage rising edge of the third clock signal CK3 occur simultaneously, and the voltage falling edge of the second clock signal CK2 and the voltage rising edge of the fourth clock signal CK4 occur simultaneously.

[0075] Based on the above embodiments, optionally, the frequencies and pulse widths of all clock signals connected to the first scanning circuit and the second scanning circuit are the same. Figure 4 When the voltage rising edge of at least one of the first clock signal CK1 and the second clock signal CK2 is controlled to occur simultaneously with the voltage falling edge of at least one of the third clock signal CK3 and the fourth clock signal CK4, the voltage falling edge of at least one of the first clock signal CK1 and the second clock signal CK2 does not overlap with the voltage rising edge of at least one of the third clock signal CK3 and the fourth clock signal CK4 in time. Figure 5 When the voltage falling edge of at least one of the first clock signal CK1 and the second clock signal CK2 is controlled to occur simultaneously with the voltage rising edge of at least one of the third clock signal CK3 and the fourth clock signal CK4, the voltage rising edge of at least one of the first clock signal CK1 and the second clock signal CK2 does not overlap in time with the voltage falling edge of at least one of the third clock signal CK3 and the fourth clock signal CK4.

[0076] Based on the above embodiments, optionally, the second scanning circuit may be connected to at least one partition enable signal. In other words, at least one partition enable signal line may be provided in the display panel to provide the partition enable signals required by the second scanning circuit.

[0077] The display panel driving method further includes: when the display panel needs to display in at least two display partitions with different refresh frequencies, controlling at least part of the partition enable signal to be a signal that alternates between a first voltage and a second voltage, so that the frequencies of the second scanning signals received by the at least two display partitions are different. The refresh frequency of any display partition is the frequency of the second scanning signal received by the display partition. In other words, by controlling the voltage variation of the partition enable signal, multi-frequency display of the display panel can be achieved.

[0078] The specific structure of the display panel and the specific implementation of the partitioned multi-frequency display are described below, but are not intended to limit the present invention.

[0079] Figure 6 FIG is a schematic diagram of the structure of another display panel provided by an embodiment of the present invention. Figure 6 , each pixel circuit 20 can be connected one-to-one to each light-emitting device (not shown in the figure) arranged in an array in the display area AA; Figure 6 For example, each pixel circuit 20 is also arranged in an array in the display area. The first scanning circuit 11 may include multiple first shift registers 110 connected in cascade. The input end of the first-stage first shift register 110 is connected to the first start signal SIN1, and the output end of each stage of the first shift register 110 is connected to the input end of the next stage of the first shift register 110; the first clock end and the second clock end of each stage of the first shift register 110 are alternately connected to the first clock signal CK1 and the second clock signal CK2; each stage of the first shift register 110 outputs a first scanning signal S1, and the first scanning signal S1 of each stage is a step-by-step shift output of the first start signal SIN1. For example, one first shift register 110 provides the first scanning signal S1 to each pixel circuit 20 connected to a row of light-emitting devices.

[0080] The second scanning circuit 12 may include a plurality of second shift registers 120 connected in cascade, the input end of the first-stage second shift register 120 is connected to the second start signal SIN2, the first output end of each stage of the second shift register 120 is connected to the input end of the next stage of the second shift register 120, and provides a stage transfer signal Carry to the input end of the next stage of the second shift register 120; the stage transfer signal Carry is a stage-by-stage shift output of the second start signal SIN2; the first clock end and the second clock end of each stage of the second shift register 120 are alternately connected to the third clock signal CK3 and the fourth clock signal CK4; each second shift register 120 is connected to the corresponding partition enable signal VFE, and the second output end of each stage of the second shift register 120 outputs a stage of the second scanning signal S2, and the partition enable signal VFE is used to control the voltage of the second scanning signal S2. Exemplarily, a second shift register 120 shifts at least one row ( Figure 6 The second scanning signal S2 is provided to each pixel circuit 20 connected during the light emitting period (two rows in the figure).

[0081] For any pixel circuit 20 , during the gate initialization phase and the data writing phase of any display frame, the second shift register 120 controls the output voltage of the second scanning signal S2 to be equal to the voltage of the input partition enable signal VFE.

[0082] Specifically, the structure of the second shift register 120 can be found in Figure 7The second shift register 120 may include a voltage control module 31, a level transfer output module 32, and a scan output module 33. The voltage control module 31 is configured to control the voltages of the first node N1 and the second node N2 based on the third clock signal CK3, the fourth clock signal CK4, and the input signal IN; the input signal IN is the second start signal SIN2 or the level transfer signal Carry output by the previous level second shift register 120; the voltage control module 31 may have any structure known in the related art and will not be described in detail here. The level transfer output module 32 may include a ninth transistor M9 and a tenth transistor M10. The ninth transistor M9 is configured to control whether the first voltage VGH is output as the level transfer signal Carry based on the voltage of the first node N1; the tenth transistor M10 is configured to control whether the second voltage VGL is output as the level transfer signal Carry based on the voltage of the second node N2; the level transfer output module 32 may further include a capacitor C2 for storing the voltage of the first node N1. The scan output module 33 may include an eleventh transistor M11 and a twelfth transistor M12. The eleventh transistor M11 is used to control whether the partition enable signal VFE is output as the second scan signal S2 based on the voltage of the first node N1, and the twelfth transistor M12 is used to control whether the second voltage VGL is output as the second scan signal S2 based on the voltage of the second node N2. The difference between the level transmission output module 32 and the scan output module 33 is that the level transmission output module 32 is directly connected to the first voltage. When the ninth transistor M9 is turned on, the voltage of the level transmission signal Carry is equal to the first voltage VGH. The scan output module 33 is connected to the partition enable signal VFE. When the eleventh transistor M11 is turned on, the voltage of the second scan signal S2 is equal to the voltage of the partition enable signal VFE. Since the voltage of the partition enable signal VFE is adjustable, it can be the first voltage VGH or the second voltage VGL, making the frequency of the second scan signal S2 adjustable.

[0083] Figure 8 Schematic diagram of a pixel circuit according to an embodiment of the present invention. Figure 8 The pixel circuit 20 includes: a driving transistor M1, a threshold compensation transistor M3, and a first initialization transistor M4; the threshold compensation transistor M3 is connected between the gate and the second electrode of the driving transistor M1, and the first initialization transistor M4 is connected to the second electrode of the driving transistor M1. The first scanning circuit is used to provide a first scanning signal S1 to the gate of each first initialization transistor M4, and the second scanning circuit is used to provide a second scanning signal S2 to the gate of each threshold compensation transistor M3. The threshold compensation transistor M3 and the first initialization transistor M4 have the same channel type, for example, both are N-type transistors. The first voltage is, for example, the on-state voltage of the threshold compensation transistor M3, specifically a high voltage, and the second voltage is, for example, the off-state voltage of the threshold compensation transistor M3, specifically a low voltage.

[0084] The pixel circuit may further include: a data write transistor M2, a first emission control transistor M5, a second emission control transistor M6, a second initialization transistor M7, a third initialization transistor M8, and a storage capacitor Cst. The first emission control transistor M5, the driving transistor M1, the second emission control transistor M6, and the light-emitting device OLED are sequentially connected in series, for example, between a first power line and a second power line, where the first power line is used to provide a first power signal VDD and the second power line is used to provide a second power signal VSS. The gates of the first emission control transistor M5 and the second emission control transistor M6 are both connected to the emission control signal EM. The data write transistor M2 is connected to the first electrode of the driving transistor M1 and is connected to the third scan signal S3 and the data voltage Vdata. The first initialization transistor M4 is also connected to the first initialization voltage Vrefn1. The second initialization transistor M8 is connected to the second electrode of the driving transistor M1 and is connected to the second initialization voltage Vrefp and the fourth scan signal S4. The third initialization transistor M7 is connected to the anode of the light-emitting device OLED and is connected to the third initialization voltage Vrefn2 and the fourth scan signal S4. The storage capacitor Cst is connected to the gate of the driving transistor M1 and is connected to the first power supply signal VDD. Except for the threshold compensation transistor M3 and the first initialization transistor M4, all other transistors in the pixel circuit 20 may be P-type transistors. The third scan signal S3 and the fourth scan signal S4 may be provided by a third scan circuit, and the light-emission control signal EM may be provided by the light-emission control circuit. The power supply for the clock signal connected to the third scan circuit and the light-emission control circuit is different from the power supply for the clock signal connected to the first scan circuit and the second scan circuit. That is, the operation of the third scan circuit and the light-emission control circuit does not affect the voltage on the partition enable signal VFE.

[0085] The driving timing of the pixel circuit 20 can be found in Figure 9 , combined with Figure 8 and Figure 9 , the driving process of the pixel circuit 20 may include:

[0086] In the gate initialization stage T11, the first scanning signal S1 and the second scanning signal S2 are both high voltages, the threshold compensation transistor M3 and the first initialization transistor M4 are both turned on, and the first initialization voltage Vrefn1 is transmitted to the gate of the driving transistor M1 through the threshold compensation transistor M3 and the first initialization transistor M4, thereby initializing the gate of the driving transistor M1.

[0087] In the data writing phase T12, the second scanning signal S2 is a high voltage, the third scanning signal S3 is a low voltage, the threshold compensation transistor M3 and the data writing transistor M2 are both turned on, and the data voltage Vdata is transmitted to the gate of the driving transistor M1 through the data writing transistor M2, the driving transistor M1 and the threshold compensation transistor M3 to charge the storage capacitor Cst.

[0088] In the anode initialization stage T13, the fourth scanning signal S4 is a low voltage, and the second initialization transistor M8 and the third initialization transistor M7 are both turned on; the second initialization voltage Vrefp is transmitted to the second electrode of the driving transistor M1 through the second initialization transistor M8 to initialize the second electrode of the driving transistor M1; the third initialization voltage Vrefn2 is transmitted to the anode of the light-emitting device OLED through the third initialization transistor M7 to initialize the anode of the light-emitting device OLED.

[0089] In the light emitting stage T14 , the light emitting control signal EM is at a low voltage, the first light emitting control transistor M5 and the second light emitting control transistor M6 are both turned on; the driving transistor M1 generates a driving current according to the voltage of its gate to drive the light emitting device OLED to emit light.

[0090] It can be understood that the driving process of the pixel circuit 20 described above is the driving process during the refresh frame. In the hold frame, the second scanning signal S2 maintains a low voltage, the threshold compensation transistor M3 remains off, the gate initialization phase T11 and the data writing phase T12 are not performed, and the gate voltage of the driving transistor M1 is maintained by the storage capacitor Cst. Therefore, by adjusting the voltage of the partition enable signal VFE, partition multi-frequency display can be achieved.

[0091] For details, see Figure 10 , with the display panel as Figure 1 The three upper, middle and lower partitions shown include the first display partition A1, the second display partition A2 and the third display partition A3 as an example, and the second scanning circuit 12 is connected to a partition enable signal VFE as an example, Figure 10 In the figure, hatched filling indicates that the display partition is performing data refresh, and blank filling indicates that the display partition is performing data retention. During the scan phase of any display partition in any display frame F, when the partition enable signal VFE maintains a first voltage (here, a high voltage), each second scanning signal S2 connected to the corresponding display partition includes an on-pulse, and the display frame is a refresh frame for each pixel circuit 20 in the display partition. When the partition enable signal VFE maintains a second voltage (here, a low voltage), each second scanning signal S2 connected to the corresponding display partition does not include an on-pulse in the display frame, and the display frame is a hold frame for each pixel circuit 20 in the display partition.

[0092] like Figure 10In the driving timing shown, the refresh frequency of the first display partition A1 is equal to the refresh frequency of the third display partition A3, and both are lower than the refresh frequency of the second display partition A2. The display process of the display panel may include multiple display cycles CYCLE, each display cycle CYCLE may include: from the beginning of a full refresh frame to the display frames before the next full refresh frame; the full refresh frame is a refresh frame for the pixel circuit 20 of each display partition.

[0093] On the basis of the above embodiments, optionally, the second scanning circuit 12 can be connected to multiple partition enable signals to make the control of partition multi-frequency more flexible. Figure 11 The second scanning circuit 12 may include a plurality of sequentially connected driving groups 121, each driving group 121 includes a plurality of sequentially connected second shift registers 120; the display panel further includes a plurality of partition enable signal lines, respectively used to transmit a plurality of partition enable signals; Figure 11 In the figure, four partition enable signal lines are exemplarily provided, which are used to transmit a first partition enable signal VFE1, a second partition enable signal VFE2, a third partition enable signal VFE3, and a fourth partition enable signal VFE4, respectively. The partition enable signal lines are alternately connected to the driver groups 121, and the second shift registers 120 in the same driver group 121 are connected to the same partition enable signal line.

[0094] Then, for the full refresh frame, each partition enable signal maintains the first voltage; Figure 10 In the display frame shown in F2, each partition enable signal maintains the second voltage; Figure 10 In the display frame shown in F3, each partition enable signal alternately appears as the first voltage and the second voltage. Figure 12 For example, the first display partition A1 receives the second scan signals output by the first four drive groups (121-1, 121-2, 121-3 and 121-4 respectively), the second display partition A2 receives the second scan signals output by the fifth to eighth drive groups (121-5, 121-6, 121-7 and 121-8 respectively), and the third display partition A3 receives the second scan signals output by the ninth to twelfth drive groups (121-9, 121-10, 121-11 and 121-12 respectively). Figure 10In the display frame shown in F3, the first partition enable signal VFE1 is at the second voltage during the output phase of the first driver group 121-1, causing the first driver group 121-1 to not output an on-pulse of the second scan signal during the display frame. It is at the first voltage during the output phase of the fifth driver group 121-5, causing the fifth driver group 121-5 to output an on-pulse of the second scan signal during the display frame. It is at the first voltage during the output phase of the ninth driver group 121-9, causing the ninth driver group 121-9 to not output an on-pulse of the second scan signal during the display frame. During the output phases of the other driver groups, the first partition enable signal VFE1 can maintain the voltage, for example, maintaining the voltage during the output phase of the previous driver group. Similarly, the second partition enable signal VFE2 is at the second voltage during the output phase of the second driver group 121-2, at the first voltage during the output phase of the sixth driver group 121-6, and at the first voltage during the output phase of the tenth driver group 121-10. Voltage maintenance is performed during the output phases of the other driver groups. The third partition enable signal VFE3 has a second voltage during the output phase of the third driver group 121-3, a first voltage during the output phase of the seventh driver group 121-7, and a first voltage during the output phase of the eleventh driver group 121-11, and maintains the voltage during the output phases of the other driver groups. The fourth partition enable signal VFE4 has a second voltage during the output phase of the fourth driver group 121-4, a first voltage during the output phase of the eighth driver group 121-8, and a first voltage during the output phase of the twelfth driver group 121-12, and maintains the voltage during the output phases of the other driver groups.

[0095] Exemplarily, each driving group 121 includes eight levels of second shift registers 120, and each level of second shift register 120 provides the same second scanning signal S2 to two rows of pixel circuits 20. Then, each partition enable signal line is equivalent to driving 16 rows of pixel circuits 20, and 64 rows of pixel circuits 20 form a cycle. The output of the partition enable signal directly acts on the gate of the threshold compensation transistor M3. If the power supply of the partition enable signal fluctuates, the gate voltage acting on the threshold compensation transistor M3 will jitter, thereby affecting the stability of the charging state of the storage capacitor Cst, resulting in the appearance of horizontal stripes. The driving method of the display panel provided in an embodiment of the present invention can effectively reduce the ripple jitter of the power supply output voltage of the partition enable signal by dispersing the changes in the load carried by the clock signal and reducing the coupling effect caused by the load jump, thereby improving the 16 rows of equally spaced horizontal stripes caused by the sudden change in the load.

[0096] On the basis of the above embodiments, optionally, see Figure 6The first scanning circuit 11 is also connected to the first start signal SIN1, and is used to generate each first scanning signal S1 according to the first start signal SIN1 and the connected clock signal; the second scanning circuit 12 is also connected to the second start signal SIN2, and is used to generate each second scanning signal S2 according to the second start signal SIN2, the partition enable signal VFE and the connected clock signal; the first start signal SIN1 and the second start signal SIN2 have the same frequency but different pulse widths. Figure 3 , the driving method of the display panel further includes: controlling the pulse width L1 of the first start signal SIN1 to be smaller than the pulse width L2 of the second start signal SIN2; and controlling each pulse of the second start signal SIN2 to temporally overlap each pulse of the first start signal SIN1. The pulses mentioned here are all conduction pulses, which are first voltage pulses (high voltage pulses) here. This setting allows the first scan signal S1 and the second scan signal S2 to have Figure 9 The corresponding relationship shown.

[0097] On the basis of the above embodiments, optionally, the display panel 100 further includes a third scanning circuit, the third scanning circuit is connected to the third start signal, and the third scanning circuit is used to provide a third scanning signal S3 to the gate of the data writing transistor M2 in each pixel circuit 10 according to the third start signal. The third start signal has the same frequency as the first start signal SIN1. The driving method of the display panel also includes: controlling the pulse width of the third start signal to be one line time; controlling the starting time of the first pulse of the third start signal to be later than or at the same time as the ending time of the first pulse of the first start signal; and controlling each pulse of the second start signal to temporally cover each pulse of the first start signal and each pulse of the third start signal. This setting allows the first scan signal S1, the second scan signal S2 and the third scan signal S3 to have in each refresh frame. Figure 9 The corresponding relationship shown in FIG. 2 shows that a pulse of the second scanning signal S2 includes the pulses of the first scanning signal S1 and the third scanning signal S3 that occurred successively. It can be understood that the line time is equal to 1 / base refresh rate / equivalent number of sub-pixel rows. The base refresh rate is the maximum refresh rate supported by each display partition of the display panel. The equivalent number of sub-pixel rows can be determined based on the resolution of the display panel.

[0098] On the basis of the above embodiments, optionally, see Figure 3-5 The first scanning circuit receives two clock signals. The pulse start time of the first start signal SIN1 overlaps with a voltage transition edge of one of the clock signals received by the first scanning circuit. For example, the pulse start time of the first start signal SIN1 overlaps with a voltage falling edge of the first clock signal CK1.

[0099] The second scanning circuit receives two clock signals. The pulse start time of the second start signal SIN2 overlaps with a voltage transition edge of one of the clock signals received by the second scanning circuit. For example, the pulse start time of the second start signal SIN2 overlaps with a voltage falling edge of the third clock signal CK3.

[0100] Therefore, when adjusting the corresponding timing of the clock signal, the start signal must also be adjusted according to the timing of the clock signal to ensure that the timing relationship between the start signal and the corresponding clock signal remains unchanged. Figure 2 In the related art, there is a dead time t1 between the voltage rising edge of the second clock signal CK2 and the voltage falling edge adjacent to the voltage rising edge in the first clock signal CK1, for example, 1.9 us. In one embodiment, when the clock signal is adjusted to Figure 5 When the timing relationship is shown, the first clock signal CK1, the second clock signal CK2, and the first start signal SIN1 can be collectively shifted forward by the dead time t1, that is, by 1.9 μs. The above shifting method is for illustrative purposes only and does not limit the present invention. In actual applications, the optimal shift amount can be selected and optimized based on the performance of different screens and driver chips.

[0101] On the basis of the above embodiments, optionally, considering the working characteristics of the first initialization transistor M4 and the threshold compensation transistor M3, the pulse widths of the first start signal SIN1 and the second start signal SIN2 can be appropriately adjusted, that is, the pulse widths of the first scan signal S1 and the second scan signal S2 are adjusted to reduce the characteristic differences between the first initialization transistor M4 and the threshold compensation transistor M3 at different refresh frequencies, thereby reducing the brightness differences between different display partitions.

[0102] Below, we first take the threshold compensation transistor M3 as an N-type transistor as an example to briefly explain the characteristics of the transistor: when the partition multi-frequency function is turned on, the different characteristic offsets of the threshold compensation transistor M3 at different refresh rates will cause brightness differences in different display partitions. Specifically, at a high refresh frequency, such as 120Hz, the transistor is in a positive bias (PBS) / negative bias (NBS) cycle state; at a low refresh frequency, such as 1Hz, the transistor is in a long-term NBS state. In the PBS state, the gate of the transistor has a positive voltage of about 6V, causing the electrons in the thin film to be attracted close to the interface between the active layer and the gate insulating layer, thereby being captured by defects at the interface, causing the transfer characteristic curve of the device to move toward the positive value of Vgs (gate-source voltage difference). In the NBS state, the holes in the thin film are attracted close to the interface and captured by defects at the interface, causing the device characteristics to drift toward the negative value of Vgs.

[0103] Specifically, at high refresh rates, the threshold compensation transistor M3 is turned on for a longer time, and the PBS effect causes the high refresh rate display partition to experience a higher voltage stress than the low refresh rate display partition. This results in a positive bias in the threshold voltage Vth of the threshold compensation transistor M3, weakening the degree to which the gate of the threshold compensation transistor M3 is pulled from a high voltage to a low voltage and coupled to the gate of the drive transistor M1, causing the high refresh rate display partition to be darker. On the other hand, at low refresh rates, the threshold compensation transistor M3 is turned off for a long time, experiencing the NBS effect, causing the low refresh rate display partition to experience a higher stress than the high refresh rate display partition. This results in a negative bias in the threshold voltage Vth of the threshold compensation transistor M3, weakening the degree to which the gate of the threshold compensation transistor M3 is pulled from a low voltage to a high voltage and coupled to the gate of the drive transistor M1, causing the low refresh rate display partition to be brighter.

[0104] In order to optimize the difference in characteristic offset of the threshold compensation transistor M3 in display partitions with different refresh frequencies, the timing corresponding to the first initialization transistor M4 / threshold compensation transistor M3 can be adjusted to reduce the high-level pulse width of the first start signal SIN1 / second start signal SIN2, thereby reducing the PBS time of the transistor in the high refresh frequency display partition as a whole, thereby reducing the threshold voltage offset caused by the PBS / NBS difference, resulting in the brightness difference problem of different display partitions under multi-frequency refresh of the partition.

[0105] Specifically, the pulse width of the first start signal SIN1 is: L1∈[2H, 10H], where L1 is the pulse width of the first start signal and H is the line time.

[0106] The display panel also includes a plurality of light-emitting devices arranged in an array, and each pixel circuit is connected to each light-emitting device in a one-to-one correspondence; each pixel circuit connected to each k rows of light-emitting devices is connected to the same second scanning signal; k is a positive integer; the pulse width of the second start signal SIN2 satisfies: L2 ≥ k * (L1 + H) to meet the driving timing requirements of the k-row gate initialization phase and the data writing phase. Wherein, L2 is the pulse width of the second start signal. For example, in the case where a set of driving groups includes eight second shift registers and drives 16 rows of pixel circuits, L2 ≥ 18H can be set to avoid the appearance of periodic horizontal stripes across the entire screen.

[0107] Specifically, k=2, L1=10H, L2=22H can be set, then the waveform correspondence of each scanning signal in the refresh frame can be seen in Figure 9 More preferably, L1=2H, L2=18H can be set, then the waveform correspondence of each scanning signal in the refresh frame can be seen in Figure 13By reducing the pulse width of the two start signals, the PBS difference between the threshold compensation transistor M3 and the first initialization transistor M4 at high refresh frequency and low refresh frequency can be effectively reduced, alleviating the brightness difference problem of different display partitions under multi-frequency refresh.

[0108] An embodiment of the present invention further provides a display panel driving device for executing the display panel driving method provided by any embodiment of the present invention, and having corresponding beneficial effects. The display panel driving device includes a time phase control module. The time phase control module is configured to control, when the display panel is displaying in at least two display partitions with different refresh rates, voltage transition edges in all clock signals connected to the first scanning circuit to ensure that they do not overlap in time with voltage transition edges with the same voltage transition direction in all clock signals connected to the second scanning circuit.

[0109] On the basis of the above embodiments, optionally, the driving device of the display panel further includes: a partition multi-frequency control module, which is used to control at least part of the partition enable signal to be a signal in which the first voltage and the second voltage alternately appear when the display panel needs to display in at least two display partitions with different refresh frequencies, so that the frequencies of the second scanning signals received by at least two display partitions are different; wherein the refresh frequency of any display partition is the frequency of the second scanning signal received by the display partition; the first voltage of each clock signal and each partition enable signal is provided by the same power supply, and the second voltage of each clock signal and each partition enable signal is provided by the same power supply.

[0110] Based on the above embodiments, optionally, the time phase control module is also used to: control at least part of the voltage jump edges in at least part of the clock signal connected to the first scanning circuit, and at least part of the voltage jump edges in the opposite direction of the voltage jump in at least part of the clock signal connected to the second scanning circuit, to overlap in time.

[0111] Based on the above embodiments, optionally, the time phase control module is specifically used to: control at least part of the voltage rising edge of at least one clock signal connected to the first scanning circuit to overlap in time with at least part of the voltage falling edge of at least one clock signal connected to the second scanning circuit; or, control at least part of the voltage falling edge of at least one clock signal connected to the first scanning circuit to overlap in time with at least part of the voltage rising edge of at least one clock signal connected to the second scanning circuit.

[0112] Based on the above embodiments, optionally, the time phase control module is also used to: control the voltage jump edges in all clock signals connected to the first scanning circuit, so that the voltage jump edges in the opposite direction of the voltage jump in all clock signals connected to the second scanning circuit do not overlap in time.

[0113] Based on the above embodiments, optionally, the driving device of the display panel also includes: a pulse width control module, which is used to control the pulse width of the first start signal to be smaller than the pulse width of the second start signal; and control each pulse of the second start signal to temporally overlap each pulse of the first start signal.

[0114] Based on the above embodiments, optionally, the pulse width control module is also used to: control the pulse width of the third start signal to be one line time; control the starting time of the first pulse of the third start signal to be later than or simultaneous with the ending time of the first pulse of the first start signal; and control the pulses of the second start signal to temporally overlap the pulses of the first start signal and the pulses of the third start signal.

[0115] An embodiment of the present invention further provides a display device, which can apply the display panel driving method provided by any embodiment of the present invention to drive the display panel, and has corresponding beneficial effects. Figure 14 Schematic diagram of a display device according to an embodiment of the present invention. Figure 14 The display device includes: a display panel 100 and a driver chip 200, wherein the driver chip 200 is used to execute the display panel driving method. Exemplarily, the display panel driving device provided by any embodiment of the present invention can be integrated into the driver chip 200.

[0116] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in the present invention can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. This is not limited herein.

[0117] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. A method for driving a display panel, characterized in that: The display panel includes: a first scanning circuit, a second scanning circuit, and a plurality of pixel circuits; the first scanning circuit and the second scanning circuit are connected to different clock signals, and the second scanning circuit is also connected to a partition enable signal; the voltages of the clock signals and the partition enable signal are provided by the same power supply; the first scanning circuit is used to provide a first scanning signal to each pixel circuit, and the second scanning circuit is used to control the frequency of a second scanning signal provided to each pixel circuit according to the partition enable signal; The display panel driving method includes: When the display panel displays in at least two display partitions with different refresh frequencies, the voltage jump edges in all clock signals connected to the first scanning circuit are controlled to not overlap in time with the voltage jump edges in the same voltage jump direction in all clock signals connected to the second scanning circuit.

2. The method for driving a display panel according to claim 1, wherein: Each of the clock signals is a pulse signal in which the first voltage and the second voltage appear alternately; The second scanning circuit is connected to at least one of the partition enable signals; The display panel driving method further includes: When the display panel needs to display in at least two display partitions with different refresh frequencies, at least part of the partition enable signal is controlled to be a signal in which the first voltage and the second voltage alternate, so that the frequencies of the second scanning signals received by at least two of the display partitions are different; wherein the refresh frequency of any one of the display partitions is the frequency of the second scanning signal received by the display partition; the first voltage of each of the clock signals and each of the partition enable signals is provided by the same power supply, and the second voltage of each of the clock signals and each of the partition enable signals is provided by the same power supply.

3. The method for driving a display panel according to claim 2, wherein: The display panel further includes a plurality of light-emitting devices arranged in an array, and each pixel circuit is connected to each light-emitting device in a one-to-one correspondence; the second scanning circuit includes a plurality of second shift registers connected in cascade, each second shift register is connected to a corresponding partition enable signal, and one second shift register provides the second scanning signal to each pixel circuit connected to at least one row of the light-emitting devices; For any pixel circuit, in the gate initialization phase and the data writing phase of any display frame, the second shift register controls the voltage of the second scanning signal output to be equal to the voltage of the input partition enable signal.

4. The method for driving a display panel according to any one of claims 1 to 3, wherein: Also includes: Control at least part of the voltage transition edges in at least part of the clock signal connected to the first scanning circuit to overlap in time with at least part of the voltage transition edges in opposite directions in at least part of the clock signal connected to the second scanning circuit.

5. The method for driving a display panel according to claim 4, wherein: Controlling at least a portion of voltage transition edges in at least a portion of the clock signal connected to the first scanning circuit to overlap in time with at least a portion of voltage transition edges in opposite directions of voltage transitions in at least a portion of the clock signal connected to the second scanning circuit, comprising: Controlling at least part of the voltage rising edges of at least one clock signal connected to the first scanning circuit to overlap in time with at least part of the voltage falling edges of at least one clock signal connected to the second scanning circuit; or, At least part of the voltage falling edges of at least one clock signal connected to the first scanning circuit and at least part of the voltage rising edges of at least one clock signal connected to the second scanning circuit are controlled to overlap in time.

6. The method for driving a display panel according to claim 5, wherein: The frequencies and pulse widths of all clock signals connected to the first scanning circuit and the second scanning circuit are the same.

7. The method for driving a display panel according to any one of claims 1 to 3, wherein: Also includes: The voltage transition edges in all the clock signals connected to the first scanning circuit are controlled so as not to overlap in time with the voltage transition edges in opposite directions in all the clock signals connected to the second scanning circuit.

8. The method for driving a display panel according to any one of claims 1 to 3, wherein: The pixel circuit includes: a driving transistor, a threshold compensation transistor and a first initialization transistor; the threshold compensation transistor is connected between the gate and the second electrode of the driving transistor, and the first initialization transistor is connected to the second electrode of the driving transistor; The first scanning circuit is used to provide the first scanning signal to the gate of each of the first initialization transistors, and the second scanning circuit is used to provide the second scanning signal to the gate of each of the threshold compensation transistors.

9. The method for driving a display panel according to claim 8, wherein: The threshold compensation transistor and the first initialization transistor have the same channel type.

10. The method for driving a display panel according to claim 8, wherein: The first scanning circuit is further connected to a first start signal, and is used to generate each first scanning signal according to the first start signal and the connected clock signal; the second scanning circuit is further connected to a second start signal, and is used to generate each second scanning signal according to the second start signal, the partition enable signal, and the connected clock signal; the first start signal and the second start signal have the same frequency but different pulse widths; The display panel driving method further includes: The pulse width of the first start signal is controlled to be smaller than the pulse width of the second start signal; and each pulse of the second start signal is controlled to temporally overlap each pulse of the first start signal.

11. The method for driving a display panel according to claim 10, wherein: The pixel circuit further includes a data writing transistor connected to the first electrode of the driving transistor; the display panel further includes a third scanning circuit, the third scanning circuit receiving a third start signal, the third scanning circuit being configured to provide a third scanning signal to the gate of the data writing transistor in each pixel circuit according to the third start signal; wherein the third start signal has the same frequency as the first start signal; The display panel driving method further includes: Control the pulse width of the third start signal to be one line time; control the starting time of the first pulse of the third start signal to be later than or simultaneous with the ending time of the first pulse of the first start signal; and control the pulses of the second start signal to temporally overlap the pulses of the first start signal and the pulses of the third start signal.

12. The method for driving a display panel according to claim 10, wherein: The first scanning circuit is connected to the two clock signals; the pulse start time of the first start signal overlaps with a voltage transition edge of one of the clock signals connected to the first scanning circuit; The second scanning circuit is connected to the two clock signals; the pulse start moment of the second start signal overlaps in time with a voltage jump edge of one of the clock signals connected to the second scanning circuit.

13. The method for driving a display panel according to claim 10, wherein: The pulse width of the first start signal is: L1∈[2H, 10H], where L1 is the pulse width of the first start signal and H is the line time.

14. The method for driving a display panel according to claim 13, wherein: The display panel further includes a plurality of light-emitting devices arranged in an array, each pixel circuit being connected to each light-emitting device in a one-to-one correspondence; each pixel circuit connected to each of the light-emitting devices in every k rows receives the same second scanning signal; k is a positive integer; The pulse width of the second start signal satisfies: L2≥k*(L1+H); wherein L2 is the pulse width of the second start signal.

15. The method for driving a display panel according to claim 14, wherein: L2≥18H.

16. The method for driving a display panel according to claim 14, wherein: k=2, L1=2H, L2=18H.

17. A driving device for a display panel, characterized in that: include: The time phase control module is used to control the voltage jump edges in all clock signals connected to the first scanning circuit to avoid temporal overlap with the voltage jump edges in the same voltage jump direction in all clock signals connected to the second scanning circuit when the display panel displays in at least two display partitions with different refresh frequencies.

18. A display device, characterized in that: include: A display panel and a driving chip, wherein the driving chip is used to execute the display panel driving method according to any one of claims 1 to 16.

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