Gate driving circuit and display device including the same

Abstract

A gate driving circuit and a display device including the same are provided. The gate driving circuit includes a plurality of stage circuits. Any one of the stage circuits may include a first clock signal input terminal, a second clock signal input terminal, an input terminal, an output terminal, a constant voltage terminal, and first to eighth transistors. The transistors may include both an N-type transistor and a P-type transistor, which may be fabricated in the same process of fabricating the transistors in the pixel circuit. Therefore, the structures of the gate driving circuit and the display device can be simplified.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and all benefits derived from Korean Patent Application No. 10-2023-0129682, filed on September 26, 2023, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] Embodiments of the present disclosure relate to a gate driving circuit and a display device including the gate driving circuit. Background Art

[0004] As information technology develops, display devices that provide a connection medium between users and information are becoming increasingly important. Therefore, the use of display devices such as liquid crystal display devices (LCDs) and organic light emitting display devices has increased.

[0005] The display device may include an array of sub-pixels for displaying an image, and each of the sub-pixels may include a pixel circuit. The pixel circuit may include one or more switching elements (e.g., transistors) and a storage element (e.g., capacitor). The display device may drive the switching element (e.g., transistor) of the pixel circuit by supplying a gate signal to the sub-pixel. The display device may include a gate drive circuit configured to output a gate signal. A gate drive circuit with a simplified structure would be desirable. Summary of the invention

[0006] An object of the present disclosure is to provide a gate driving circuit having a simplified structure, and to provide a display device including the gate driving circuit.

[0007] Embodiments of the present disclosure may include a gate drive circuit. The gate drive circuit may include a plurality of stage circuits, and any one of the plurality of stage circuits may include: a first clock signal input terminal for inputting a first clock signal, a second clock signal input terminal for inputting a second clock signal, an input terminal for inputting an input signal, an output terminal for outputting an output signal, a constant voltage terminal to which a constant voltage is applied, a first transistor electrically connected to the input terminal and controlled in response to the first clock signal, a second transistor electrically connected to the second clock input terminal and controlled in response to a voltage of a second node, a third transistor connected between the first transistor and the second node, a fourth transistor configured to switch an electrical connection between the constant voltage terminal and the output terminal in response to a voltage of the second node, a fifth transistor configured to switch an electrical connection between the first clock signal input terminal and the output terminal in response to a voltage of the first node, a sixth transistor configured to switch an electrical connection between the first node and the first clock signal input terminal in response to a voltage of the second node, a seventh transistor controlled in response to a voltage of the second node and electrically connected to the constant voltage terminal, and an eighth transistor configured to switch an electrical connection between the seventh transistor and the first node.

[0008] The seventh transistor may include an N-type semiconductor layer.

[0009] Any one of the stage circuits may further include a first capacitor configured to maintain a voltage difference between the first clock signal input terminal and the first node.

[0010] Any one of the stage circuits may further include a second capacitor configured to maintain a voltage difference between any one of a source electrode and a drain electrode of the second transistor and a gate electrode of the second transistor.

[0011] The plurality of stage circuits may include another stage circuit before any one of the stage circuits, and the input signal may be an output signal of the another stage circuit.

[0012] The any one stage circuit may be located before all other stage circuits among the plurality of stage circuits, and the input signal may be a start signal.

[0013] The output signal may have any one of a high level and a low level, and a length of a period in which the plurality of stage circuits output the output signal of the low level is longer than a length of a period in which the plurality of stage circuits output the output signal of the high level.

[0014] The first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the eighth transistor may include a P-type semiconductor layer.

[0015] Embodiments of the present disclosure may provide a display device. The display device may include a display panel, a gate driving circuit, and a timing controller, wherein a plurality of sub-pixels are arranged in the display panel, a plurality of gate lines extending in a first direction and electrically connected to the plurality of sub-pixels are arranged, and a plurality of data lines extending in a second direction and electrically connected to the plurality of sub-pixels are arranged, the gate driving circuit is configured to drive the plurality of gate lines and includes a plurality of stage circuits, and the timing controller is configured to output a first clock signal and a second clock signal. Any one of the multiple stage circuits may include: a first clock signal input terminal for inputting a first clock signal, a second clock signal input terminal for inputting a second clock signal, an input terminal for inputting an input signal, an output terminal for outputting an output signal, a constant voltage terminal to which a low-level voltage is applied, a first transistor electrically connected to the input terminal and controlled in response to the first clock signal, a second transistor electrically connected to the second clock signal input terminal and controlled in response to a voltage of a second node, a third transistor connected between the first transistor and the second node, a fourth transistor configured to switch the electrical connection between the constant voltage terminal and the output terminal in response to the voltage of the second node, a fifth transistor configured to switch the electrical connection between the first clock signal input terminal and the output terminal in response to the voltage of the first node, a sixth transistor configured to switch the electrical connection between the first node and the first clock signal input terminal in response to the voltage of the second node, a seventh transistor controlled in response to the voltage of the second node and electrically connected to the constant voltage terminal, and an eighth transistor configured to switch the electrical connection between the seventh transistor and the first node.

[0016] The seventh transistor may include an N-type semiconductor layer.

[0017] Each of the multiple sub-pixels may include a pixel circuit and a light-emitting element connected to the pixel circuit, the pixel circuit may include a first pixel transistor connected between a first pixel node and a second pixel node and including a gate electrode electrically connected to a third pixel node, a second pixel transistor connected between a corresponding data line among a plurality of data lines and the first pixel node and including a gate electrode connected to a first scan line, a third pixel transistor connected between the second pixel node and a third pixel node and including a gate electrode connected to the second scan line, and a fourth pixel transistor configured to switch the electrical connection between a power line to which a first initialization voltage is applied and the third pixel node and including a gate electrode connected to the third scan line, and the output terminal may be electrically connected to any one of the second scan line and the third scan line.

[0018] The light-emitting element may be connected between a fourth pixel node and a voltage line to which a low potential voltage is applied, and the pixel circuit may further include a fifth pixel transistor connected between the fourth pixel node and a power line to which a second initialization voltage is applied and including a gate electrode connected to a fourth scan line, a sixth pixel transistor connected between the second pixel node and the fourth pixel node and including a gate electrode connected to the emission line, a seventh pixel transistor connected between the first pixel node and a first power line to which a high potential voltage is applied and including a gate electrode connected to the emission line, and an eighth pixel transistor connected between the first pixel node and a power line to which a conduction bias voltage is applied and including a gate electrode connected to the fourth scan line.

[0019] The output terminal may be electrically connected to a fourth pixel transistor included in any one of the plurality of sub-pixels, and may be electrically connected to a third pixel transistor included in another one of the plurality of sub-pixels.

[0020] Any sub-pixel may be located in a different pixel row than another sub-pixel.

[0021] At least one of the third pixel transistor and the fourth pixel transistor may include an N-type semiconductor layer, and at least one of the first pixel transistor and the second pixel transistor may include a P-type semiconductor layer.

[0022] In the display panel, multiple sub-pixels can be arranged in the display area, in the display panel, multiple stage circuits can be arranged in the non-display area located around the display area, and the seventh transistor, the third pixel transistor and the fourth pixel transistor can be formed in the same process.

[0023] The first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the eighth transistor, the first pixel transistor, and the second pixel transistor may be formed in the same process.

[0024] Any one of the stage circuits may further include a first capacitor configured to maintain a voltage difference between the first clock signal input terminal and the first node.

[0025] Any one of the stage circuits may further include a second capacitor configured to maintain a voltage difference between any one of a source electrode and a drain electrode of the second transistor and a gate electrode of the second transistor.

[0026] The plurality of stage circuits may include another stage circuit before any one of the stage circuits, and the input signal may be an output signal of the another stage circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and other features of the present disclosure will become more apparent by describing the embodiments of the present disclosure in further detail with reference to the accompanying drawings.

[0028] Figure 1 is a system block diagram of a display device according to an embodiment of the present disclosure.

[0029] Figure 2 An example of a pixel array in a display device according to an embodiment of the present disclosure is shown.

[0030] Figure 3 An example of data lines and gate lines connected to sub-pixels according to an embodiment of the present disclosure is shown.

[0031] Figure 4 yes Figure 3 An equivalent circuit diagram of an example of a sub-pixel.

[0032] Figure 5A and Figure 5B shows the input to Figure 4 The waveform of the gate signal of the sub-pixel.

[0033] Figure 6 is used to input Figure 4 A timing diagram of an example of a gate signal of a sub-pixel.

[0034] Figure 7 yes Figure 1 A block diagram of an implementation of a gate drive circuit.

[0035] Figure 8 yes Figure 7 An equivalent circuit diagram of an example of a stage circuit included in a shift register.

[0036] Fig. 9 It shows the input to Figure 7 The shift register signals and the Figure 7 A timing diagram of an example of the shift register output signals.

[0037] Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15 , Fig.16 and Fig.17 An example of a method of driving a gate driving circuit according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0038] Hereinafter, various embodiments are described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement various aspects of the present disclosure. The embodiments of the present disclosure can be implemented in various forms and are not limited to the specific embodiments described herein.

[0039] In order to clearly describe certain features or aspects of the present disclosure, parts not related to those features or aspects may be omitted.

[0040] Throughout the specification, the same or similar elements in the various drawings may be represented by the same reference numerals. In addition, the size and thickness of each component shown in the drawings may be shown for the convenience of illustration or description, and therefore the present disclosure is not necessarily limited to the size or shape shown in the drawings. In the drawings, the thickness may be exaggerated to more clearly show the various layers and regions.

[0041] The expression "is the same" in the description may mean "is substantially the same". That is, reciting that an object is "the same" as another object means that the objects are similar enough for a person of ordinary skill to understand that the objects are the same. Other expressions may also be expressions in which "substantially" is omitted.

[0042] The terms "first", "second", etc. may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another component. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component without departing from the scope of the present disclosure. Unless the context clearly indicates otherwise, the singular expressions used herein should be interpreted as including the corresponding plural expressions.

[0043] The terms "lower", "below", "upper", and "above" may be used to describe the relationship as shown in the drawings. These terms describe relative concepts based on the directions indicated in the drawings.

[0044] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. In addition, terms, such as those defined in commonly used dictionaries, will be interpreted as having a meaning consistent with the meaning in the context of the relevant technology, and unless explicitly defined herein, should not be interpreted in an ideal or overly formal manner.

[0045] It should be understood that terms such as “including”, “having”, etc. are used to specify that the features, quantities, steps, operations, components, parts, or a combination thereof are included as described in the specification, but do not exclude the possibility of the existence or addition of one or more other features, quantities, steps, operations, components, parts, or a combination thereof.

[0046] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0047] Figure 1 is a system block diagram of a display device 100 according to an embodiment of the present disclosure.

[0048] Reference Figure 1 , the display device 100 may include a display panel 110 , a gate driving circuit 120 and a panel driving circuit 130 .

[0049] A plurality of sub-pixels SPX are arranged in the display panel 110. The display panel 110 may further include a plurality of data lines DL1, ..., and DLn (n is an integer greater than or equal to 2), a plurality of scan lines SL1, ..., and SLm (m is an integer greater than or equal to 2), a plurality of emission lines EL1, ..., and ELm, etc. electrically connected to the plurality of sub-pixels SPX. In the display panel 110, one or more power lines configured to apply a power supply voltage (e.g., a first power supply voltage ELVDD, a second power supply voltage VINT, a third power supply voltage VAR, a fourth power supply voltage VOBS, etc.) to the plurality of sub-pixels SPX may be arranged.

[0050] The display panel 110 may include a display area AA in which a plurality of sub-pixels SPX are arranged, and a non-display area NA positioned in a peripheral area of ​​the display area AA (eg, an edge area surrounding the display area AA).

[0051] The display panel 110 may have a flat (e.g., horizontal) surface, but the embodiments of the present disclosure are not limited thereto. For example, the display panel 110 may include a bending portion (not shown) formed at the left side or left end and the right side or right end. The bending surface of the bending portion may have a constant curvature or a varying curvature. In addition, the display panel 110 may be formed to be flexible so as to be bent, folded, or curled.

[0052] The plurality of scan lines SL1 to SLm may extend in a first direction DR1 and may be arranged in the display panel 110. For example, the first direction DR1 may be a direction from the left side to the right side of the display panel 110. However, embodiments of the present disclosure are not limited thereto.

[0053] The plurality of emission lines EL1 to ELm may extend in the first direction DR1 and may be arranged in the display panel 110. However, embodiments of the present disclosure are not limited thereto.

[0054] The plurality of data lines DL1 to DLn may extend in the second direction DR2 and may be arranged in the display panel 110. The second direction DR2 may be a direction different from the first direction DR1 (e.g., a direction crossing the first direction DR1). For example, the second direction DR2 may be a direction perpendicular to the first direction DR1. For example, the second direction DR2 may be a direction from the lower side to the upper side of the display panel 110.

[0055] The gate driving circuit 120 may include a scan driver 122 and an emission driver 124. The gate driving circuit 120 is configured to output a gate signal (e.g., a scan signal, an emission signal, etc.) having a high level voltage VGH or a low level voltage VGL to a gate line (e.g., a scan line SL, an emission line EL, etc.) in response to an input control signal.

[0056] The scan driver 122 may output a scan signal (e.g., a scan signal of an on level) to a plurality of scan lines SL1 to SLm in response to a scan driver control signal SCS. For example, the scan driver control signal SCS may include a start signal indicating the start of a frame, a horizontal synchronization signal for outputting a gate signal (e.g., a scan signal) according to a timing of applying a data voltage, a clock signal, and the like.

[0057] According to an embodiment, the scan driver 122 may be implemented as an integrated circuit (e.g., a gate driver integrated circuit (GDIC)) formed separately from the display panel 110. According to an embodiment, the scan driver 122 may be formed together with the display panel 110, and may be formed in at least a portion of the non-display area NA of the display panel 110. According to an embodiment, at least a portion of the scan driver 122 may overlap the display area AA.

[0058] The emission driver 124 may output an emission signal (e.g., an emission signal of an on level) to a plurality of emission lines EL1 to ELm in response to an emission driver control signal ECS. For example, the emission driver control signal ECS may include a start signal, a horizontal synchronization signal for outputting a gate signal (e.g., an emission signal), a clock signal, etc.

[0059] According to an embodiment, the emission driver 124 may be implemented as an integrated circuit formed separately from the display panel 110. According to an embodiment, the emission driver 124 may be formed together with the display panel 110, and may be formed in at least a portion of the non-display area NA of the display panel 110. According to an embodiment, at least a portion of the emission driver 124 may overlap the display area AA.

[0060] The panel driving circuit 130 may include a data driver 132, a timing controller 134, and a power generator 136. The panel driving circuit 130 may be implemented as one integrated circuit, or the panel driving circuit 130 may be divided into two or more integrated circuits. For example, the data driver 132, the timing controller 134, the power generator 136, etc. may be functional units within one integrated circuit. In another example, at least one of the data driver 132, the timing controller 134, and the power generator 136 may be implemented as an integrated circuit different from the integrated circuit containing any one or more of the remaining ones. For the convenience of description, an embodiment in which the panel driving circuit 130 including the data driver 132, the timing controller 134, and the power generator 136 is implemented as one integrated circuit is described below as an example, but the embodiments of the present disclosure are not limited thereto. The panel driving circuit 130 may be implemented as, for example, a timing controller embedded driver integrated circuit (TED-IC).

[0061] The data driver 132 may supply data voltages to a plurality of data lines DL1 to DLn. The data driver 132 may generate data voltages based on image data DATA, a data driver control signal DCS, and a gamma voltage Vgamma. The data driver 132 may output the generated data voltages to a plurality of data lines DL1 to DLn according to a timing sequence. The data driver control signal DCS may include, for example, a source start pulse (SSP), a source shift clock (SSC), a source output enable (SOE), and the like.

[0062] The timing controller 134 may be configured to control the data driver 132, the gate driving circuit 120, the power generator 136, etc. The timing controller 134 may receive a control signal CS (e.g., a synchronization signal, a data enable signal, a clock signal, etc.) from an external system or device (e.g., a host 140). The timing controller 134 may output control signals DCS, SCS, and ECS for controlling the data driver 132, the gate driving circuit 120, etc. based on the control signal CS.

[0063] The timing controller 134 may receive input image data IDATA from an external system or device (e.g., the host 140), and arrange the input image data IDATA in units corresponding to rows of pixels. The timing controller 134 may convert the input image data IDATA according to a preset interface (e.g., low voltage differential signaling (LVDS), display port (DP), embedded display port (eDP), etc.). The image data DATA output from the timing controller 134 to the data driver 132 may be converted inside the timing controller 134 according to the preset interface.

[0064] The timing controller 134 may receive input image data IDATA, a control signal CS, etc. from an external system or device (eg, the host 140 ) through an interface such as a serial programming interface (SPI), an inter-integrated circuit (I2C), or a mobile industry processor interface (MIPI).

[0065] The timing controller 134 may be arranged in a logic or processor type in the display device 100. The timing controller 134 may include one or more registers.

[0066] The timing controller 134 may receive power (e.g., interface driving power, logic driving power, etc.) from an external source (e.g., a power supply circuit). The timing controller 134 may convert the input image data IDATA according to a preset interface, or may arrange the input image data IDATA in pixel row units using the input power.

[0067] The power generator 136 may be configured to receive a voltage from an external source (e.g., a power supply circuit, etc.), and supply a voltage of an appropriate level to each component of the display device 100 by using the supplied voltage (e.g., reducing the voltage). According to an embodiment, the power generator 136 may include a resistor string for reducing the voltage level by distributing the driving power supplied from the power supply circuit. According to an embodiment, the power generator 136 may include a regulator for keeping the voltage level (e.g., the reduced voltage level) constant. For example, the regulator may be a low dropout (LDO) regulator.

[0068] The power generator 136 may supply a first power voltage ELVDD, a second power voltage VINT, a third power voltage VAR, a fourth power voltage VOBS, etc. to the display panel 110. The power generator 136 may supply a high level voltage VGH, a low level voltage VGL, etc. to the gate driving circuit 120. The power generator 136 may supply a gamma voltage Vgamma to the data driver 132.

[0069] The power supply circuit (not shown) may supply, for example, a logic driving power supply, an interface driving power supply, a regulator driving power supply, etc. The power supply circuit may supply a first power supply voltage ELVDD. However, according to an embodiment, the power generator 136 may generate the first power supply voltage ELVDD and supply the first power supply voltage ELVDD to the display panel 110. For example, the power supply circuit may be implemented as a power management integrated circuit (PMIC).

[0070] The host 140 may execute, for example, software (eg, a program) to control another component (eg, the display device 100) connected to the host 140, and may perform various data processing or calculations. The host 140 may include, for example, a set-top box, an application processor (AP), etc.

[0071] The display device 100 according to some embodiments of the present disclosure can be used as a display screen for various products such as televisions, notebook computers, monitors, billboards, Internet of Things (IoT) devices, and portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), smart watches, watch phones, mobile communication terminals, electronic notepads, electronic books, portable multimedia players (PMPs), navigation devices, and ultra mobile personal computers (UMPCs). The display device 100 according to some embodiments of the present disclosure can be used as a display screen for virtual reality (VR) devices, augmented reality (AR) devices, etc.

[0072] When the display device 100 is used as a display screen for a VR device, an AR device, etc., the display device 100 may be positioned very close to the user's eyes. When the display device 100 is used as a display screen for a VR device, an AR device, etc., the sub-pixel SPX may require high integration to provide high resolution. As a method for increasing the integration of the sub-pixel SPX, the sub-pixel SPX may be formed on a silicon substrate. The technology for forming a pixel circuit and a light-emitting element (e.g., an organic light-emitting diode (OLED)) connected thereto on a silicon substrate may be referred to as silicon-based OLED (OLEDoS).

[0073] Figure 2 An example of a pixel array in a display device according to an embodiment of the present disclosure is shown.

[0074] Reference Figure 2 , a plurality of sub-pixels SPX may be arranged in the display device 100 (refer to Figure 1 ) in the display area AA. For example, the plurality of sub-pixels SPX may include a first sub-pixel SPX1, a second sub-pixel SPX2, a third sub-pixel SPX3, and the like.

[0075] Each of the first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3 may be electrically connected to a corresponding one of a plurality of data lines. Each of the first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3 may be electrically connected to at least one of a plurality of scan lines. Each of the first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3 may be electrically connected to at least one of a plurality of emission lines.

[0076] Each sub-pixel SPX (e.g., the first sub-pixel SPX1, the second sub-pixel SPX2, or the third sub-pixel SPX3) or the emission area of ​​the sub-pixel SPX may have a planar shape of a rectangle, a square, a diamond, or a similar shape. However, the embodiments of the present disclosure are not limited thereto, and the sub-pixel SPX or the emission area of ​​the sub-pixel SPX may have other shapes such as a circle, other polygons, or a similar shape.

[0077] Figure 2 A pixel array structure in which a plurality of sub-pixels SPX are arranged in a plurality of rows is shown. For example, in the first row 1N, the first sub-pixel SPX1 and the third sub-pixel SPX3 may be arranged alternately. In the second row 2N, a plurality of second sub-pixels SPX2 may be arranged to be spaced apart (e.g., spaced apart at a predetermined distance). In the third row 3N, the third sub-pixel SPX3 and the first sub-pixel SPX1 may be arranged alternately. In the fourth row 4N, a plurality of second sub-pixels SPX2 may be arranged to be spaced apart (e.g., spaced apart at a predetermined distance). According to an embodiment, the size of the first sub-pixel SPX1 (or the size of the emission area of ​​the first sub-pixel SPX1) may be larger than the size of the second sub-pixel SPX2 (or the size of the emission area of ​​the second sub-pixel SPX2). According to an embodiment, the size of the third sub-pixel SPX3 (or the size of the emission area of ​​the third sub-pixel SPX3) may be larger than the size of the second sub-pixel SPX2 (or the size of the emission area of ​​the second sub-pixel SPX2). According to an embodiment, the size of the third subpixel SPX3 (or the size of the emission area of ​​the third subpixel SPX3) may be greater than the size of the first subpixel SPX1 (or the size of the emission area of ​​the first subpixel SPX1). The first row 1N and the second row 2N may be adjacent to each other in the second direction DR2. The second row 2N and the third row 3N may be adjacent to each other in the second direction DR2. The third row 3N and the fourth row 4N may be adjacent to each other in the second direction DR2.

[0078] Figure 2 Also shown is a pixel array structure in which a plurality of sub-pixels SPX are arranged in a plurality of columns. The first sub-pixel SPX1 and the third sub-pixel SPX3 may be offset from the second sub-pixel SPX2 in the first direction DR1, so that the column containing the second sub-pixel SPX2 may be different from the column containing the first sub-pixel SPX1 and the third sub-pixel SPX3. In the first column 1M, the first sub-pixel SPX1 and the third sub-pixel SPX3 may be arranged alternately. In the second column 2M, a plurality of second sub-pixels SPX2 may be arranged to be spaced apart (e.g., spaced apart at a predetermined distance). In the third column 3M, the third sub-pixel SPX3 and the first sub-pixel SPX1 may be arranged alternately. In the fourth column 4M, a plurality of second sub-pixels SPX2 may be arranged to be spaced apart (e.g., spaced apart at a predetermined distance). The first column 1M and the second column 2M may be adjacent to each other in the first direction DR1. The second column 2M and the third column 3M may be adjacent to each other in the first direction DR1. The third column 3M and the fourth column 4M may be adjacent to each other in the first direction DR1.

[0079] As described above, a pixel array structure in which a plurality of sub-pixels SPX are divided into a plurality of pixel rows and a plurality of pixel columns and arranged may be referred to as structure.

[0080] In the embodiment of the above-mentioned pixel array structure, a virtual quadrilateral VS may be defined, in which the center point of the second sub-pixel SPX2 is set as the center point of the virtual quadrilateral VS, and two first sub-pixels SPX1 and two third sub-pixels SPX3 are set as vertices. Among the vertices of the virtual quadrilateral VS, the first sub-pixel SPX1 may be arranged at the first vertex and the third vertex facing each other across the diagonal line, respectively. Among the vertices of the virtual quadrilateral VS, the third sub-pixel SPX3 may be arranged at the remaining second vertex and the fourth vertex facing each other across another diagonal line, respectively. Depending on the geometry of the pixel array structure, the virtual quadrilateral VS may have various shapes such as a rectangle, a rhombus, or a square.

[0081] The first sub-pixel SPX1 may emit light of a first wavelength band, the second sub-pixel SPX2 may emit light of a second wavelength band, and the third sub-pixel SPX3 may emit light of a third wavelength band. Here, the light of the first wavelength band may be light of a red wavelength band, the light of the second wavelength band may be light of a green wavelength band, and the light of the third wavelength band may be light of a blue wavelength band. The red wavelength band may be a wavelength band of about 600nm (nanometers) to 750nm, the green wavelength band may be a wavelength band of about 480nm to 560nm, and the blue wavelength band may be a wavelength band of about 370nm to 460nm. The embodiments of the present disclosure are not limited thereto.

[0082] Each of the first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3 may include a light emitting element for emitting light. For example, each of the first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3 may include an organic light emitting diode (OLED) as a light emitting element, but the embodiments of the present disclosure are not limited thereto.

[0083] Figure 3 An example of a data line and a gate line connected to a sub-pixel SPX according to an embodiment of the present disclosure is shown.

[0084] Reference Figure 3 , the sub-pixel SPX can be connected to the jth (j is an integer equal to or greater than 1 and equal to or less than n) data line DLj (hereinafter also referred to as data line DLj) among multiple data lines. The sub-pixel SPX can be connected to the ith (i is an integer equal to or greater than 1 and equal to or less than m) scan line SLi among multiple scan lines. The sub-pixel SPX can be connected to the i-th emission line ELi (hereinafter also referred to as emission line ELi) among multiple emission lines.

[0085] According to an embodiment, the i-th scan line SLi (hereinafter also referred to as the scan line SLi) may include the i-th first scan line S1i (hereinafter also referred to as the first scan line S1i), the i-th second scan line S2i (hereinafter also referred to as the second scan line S2i), the i-th third scan line S3i (hereinafter also referred to as the third scan line S3i) and the i-th fourth scan line S4i (hereinafter also referred to as the fourth scan line S4i).

[0086] In an embodiment of the present disclosure, the scan line SLi and the emission line ELi may be connected (eg, electrically connected) to a gate electrode of a transistor included in the subpixel SPX. Each of the scan line SLi and the emission line ELi may be referred to as a gate line.

[0087] Figure 4 yes Figure 3 An example of an equivalent circuit diagram of a sub-pixel SPX.

[0088] according to Figure 4 The sub-pixel SPX of the embodiment shown in FIG. 1 may include a pixel circuit PXC and a light emitting element LE. The pixel circuit PXC and the light emitting element LE may be connected (eg, electrically connected).

[0089] The pixel circuit PXC may include one or more switching elements (e.g., pixel transistors) and one or more storage elements (e.g., capacitors). Hereinafter, an embodiment in which the pixel circuit PXC includes eight pixel transistors and one capacitor is described as an example, but embodiments of the present disclosure are not limited thereto.

[0090] The first pixel transistor TR1 may be configured to generate or control a current (e.g., a driving current) flowing through the light emitting element LE. The first pixel transistor TR1 may be connected between the first pixel node PN1 and the second pixel node PN2. The gate electrode of the first pixel transistor TR1 may be electrically connected to the third pixel node PN3. One electrode (e.g., a source electrode) of the first pixel transistor TR1 may be connected to the first pixel node PN1. Another electrode (e.g., a drain electrode) of the first pixel transistor TR1 may be connected to the second pixel node PN2. The first pixel transistor TR1 may be referred to as a driving transistor.

[0091] The second pixel transistor TR2 may switch the electrical connection between the data line DLj and the first pixel node PN1 in response to the first scan signal GW[i]. The first scan signal GW[i] may be applied to the first scan line S1i connected to the gate electrode of the second pixel transistor TR2. The second pixel transistor TR2 may be turned on in response to the first scan signal GW[i] of the on level, and when the second pixel transistor TR2 is turned on, the data voltage Vdata (or a voltage corresponding to the data voltage Vdata) may be applied to the first pixel node PN1. The second pixel transistor TR2 may be referred to as a scan transistor.

[0092] The third pixel transistor TR3 may be configured to switch the electrical connection between the second pixel node PN2 and the third pixel node PN3. The third pixel transistor TR3 may switch the connection (e.g., electrical connection) between the second pixel node PN2 and the third pixel node PN3 in response to the second scan signal GC[i]. The second scan signal GC[i] may be applied to the second scan line S2i connected to the gate electrode of the third pixel transistor TR3. The third pixel transistor TR3 may electrically connect the second pixel node PN2 and the third pixel node PN3 in response to the second scan signal GC[i] of the on level. When the third pixel transistor TR3 is turned on, the first pixel transistor TR1 may be diode-connected. The third pixel transistor TR3 may be referred to as a compensation transistor.

[0093] The fourth pixel transistor TR4 may be configured to switch the electrical connection between the third pixel node PN3 and the third power line PL3. The fourth pixel transistor TR4 may switch the electrical connection between the third pixel node PN3 and the third power line PL3 in response to the third scan signal GI[i]. The third scan signal GI[i] may be applied to the third scan line S3i connected to the gate electrode of the fourth pixel transistor TR4. The second power supply voltage VINT may be applied to the third power line PL3. The fourth pixel transistor TR4 may electrically connect the third pixel node PN3 and the third power line PL3 in response to the third scan signal GI[i] of the on level. The second power supply voltage VINT may be referred to as the first initialization voltage VINT. The second power supply voltage VINT may have the on level of the first pixel transistor TR1. The fourth pixel transistor TR4 may be referred to as the first initialization transistor.

[0094] The fifth pixel transistor TR5 may be configured to switch the electrical connection between the fourth pixel node PN4 and the fourth power line PL4. The fifth pixel transistor TR5 may switch the electrical connection between the fourth pixel node PN4 and the fourth power line PL4 in response to the fourth scan signal GB[i]. The fourth scan signal GB[i] may be applied to the fourth scan line S4i connected to the gate electrode of the fifth pixel transistor TR5. The third power supply voltage VAR may be applied to the fourth power line PL4. The fifth pixel transistor TR5 may electrically connect the fourth pixel node PN4 and the fourth power line PL4 in response to the fourth scan signal GB[i] of the on level. The third power supply voltage VAR may be referred to as the second initialization voltage VAR or the anode reset voltage VAR. The fifth pixel transistor TR5 may be referred to as the second initialization transistor.

[0095] The sixth pixel transistor TR6 may be configured to switch the electrical connection between the second pixel node PN2 and the fourth pixel node PN4. The sixth pixel transistor TR6 may switch the electrical connection between the second pixel node PN2 and the fourth pixel node PN4 in response to the emission signal EM[i]. The emission signal EM[i] may be applied to the emission line ELi connected to the gate electrode of the sixth pixel transistor TR6. The sixth pixel transistor TR6 may electrically connect the second pixel node PN2 and the fourth pixel node PN4 in response to the emission signal EM[i] of the on level. The sixth pixel transistor TR6 may be referred to as a first emission control transistor.

[0096] The seventh pixel transistor TR7 may be configured to switch the electrical connection between the first power line PL1 and the first pixel transistor TR1. The seventh pixel transistor TR7 may switch the electrical connection between the first power line PL1 and the first pixel transistor TR1 in response to the emission signal EM[i]. The first power supply voltage ELVDD may be applied to the first power line PL1. The emission signal EM[i] is applied to the emission line ELi connected to the gate electrode of the seventh pixel transistor TR7. The seventh pixel transistor TR7 may electrically connect the first power line PL1 and the first pixel transistor TR1 in response to the emission signal EM[i] of the on level. The seventh pixel transistor TR7 may be referred to as a second emission control transistor.

[0097] The eighth pixel transistor TR8 may be configured to switch the electrical connection between the fifth power line PL5 and the first pixel node PN1. The eighth pixel transistor TR8 may switch the electrical connection between the fifth power line PL5 and the first pixel node PN1 in response to the fourth scan signal GB[i]. The fourth power supply voltage VOBS may be applied to the fifth power line PL5. The eighth pixel transistor TR8 may electrically connect the fifth power line PL5 and the first pixel node PN1 in response to the fourth scan signal GB[i] of the on level. The fourth power supply voltage VOBS may be referred to as a turn-on bias voltage VOBS. The eighth pixel transistor TR8 may be referred to as a bias control transistor. The fourth power supply voltage VOBS may be applied to the first pixel transistor TR1, and thus the threshold voltage or other characteristic value of the first pixel transistor TR1 may be maintained.

[0098] The storage capacitor Cstg may be configured and used to maintain a voltage applied to the third pixel node PN3. The storage capacitor Cstg may include one electrode E1 electrically connected to the first power line PL1 and another electrode E2 electrically connected to the third pixel node PN3.

[0099] The light emitting element LE may include a first electrode AE, a second electrode CE, and a light emitting layer EML. For example, the light emitting layer EML may be positioned between the first electrode AE ​​and the second electrode CE. The first electrode AE ​​may be any one of an anode and a cathode. The second electrode CE may be the other of the anode and the cathode. Hereinafter, for convenience, the following description assumes that the first electrode AE ​​is an anode and the second electrode CE is a cathode, but the embodiments of the present disclosure are not limited thereto.

[0100] The first electrode AE ​​of the light emitting element LE may be electrically connected to the fourth pixel node PN4, and the second electrode CE of the light emitting element LE may be electrically connected to the second power line PL2. The low potential power supply voltage ELVSS may be applied to the second power line PL2. A current (e.g., a driving current) having a magnitude corresponding to the voltage difference between the voltage applied to the fourth pixel node PN4 and the low potential power supply voltage ELVSS may flow through the light emitting element LE. The light emitting element LE may emit light having a brightness corresponding to the voltage difference between the voltage applied to the fourth pixel node PN4 and the low potential power supply voltage ELVSS.

[0101] The light emitting layer EML may include an organic light emitting material having a high molecular weight or a low molecular weight. The light emitting layer EML may include an inorganic light emitting material or a quantum dot. For example, the light emitting layer EML may include an organic light emitting material having a high molecular weight or a low molecular weight for emitting light of a predetermined wavelength band (e.g., a blue wavelength band, a green wavelength band, or a red wavelength band).

[0102] One or more transistors in the pixel circuit PXC may include a P-type semiconductor layer or an N-type semiconductor layer. For example, at least one of the first pixel transistor TR1 to the eighth pixel transistor TR8 may be implemented as a field effect transistor (FET) including a P-type semiconductor layer (e.g., a P-channel metal oxide semiconductor (PMOS)). For example, at least one of the first pixel transistor TR1 to the eighth pixel transistor TR8 may be implemented as a FET including an N-type semiconductor layer (e.g., an N-channel metal oxide semiconductor (NMOS)). Figure 4 An embodiment is shown in which the first pixel transistor TR1, the second pixel transistor TR2, and the fifth pixel transistor TR5 to the eighth pixel transistor TR8 are implemented as FETs including PMOS, and the third pixel transistor TR3 and the fourth pixel transistor TR4 are implemented as FETs including NMOS. However, the embodiments of the present disclosure are not limited thereto. For example, at least one of the first pixel transistor TR1, the second pixel transistor TR2, and the fifth pixel transistor TR5 to the eighth pixel transistor TR8 may be implemented as a FET including NMOS. For example, at least one of the third pixel transistor TR3 and the fourth pixel transistor TR4 may be implemented as a FET including PMOS.

[0103] The pixel transistors in the pixel circuit PXC may include amorphous silicon (a-Si) semiconductors, oxide semiconductors, low temperature polycrystalline silicon (LTPS) semiconductors, etc. For example, some of the eight pixel transistors in the pixel circuit PXC may include LTPS semiconductors, and the others may include oxide semiconductors. For example, the third pixel transistor TR3 and the fourth pixel transistor TR4 may include oxide semiconductors, and the remaining pixel transistors TR1, TR2, and TR5 to TR8 may include LTPS semiconductors. However, according to an embodiment, at least one of the third pixel transistor TR3 and the fourth pixel transistor TR4 may include an amorphous silicon semiconductor or an LTPS semiconductor. According to an embodiment, at least one of the remaining pixel transistors TR1, TR2, and TR5 to TR8 may include an oxide semiconductor.

[0104] The first scan signal GW[i], the second scan signal GC[i], the third scan signal GI[i], and the fourth scan signal GB[i] may be applied to different scan lines. For example, the first to fourth scan lines S1i to S4i may be separate scan lines different from each other.

[0105] According to an embodiment, at least two of the first scan signal GW[i], the second scan signal GC[i], the third scan signal GI[i], and the fourth scan signal GB[i] may be applied to the same scan line. For example, at least two of the first scan line S1i to the fourth scan line S4i may be implemented as one scan line. For example, the i-th second scan line S2i and the (i+2)-th third scan line may be implemented as one scan line. In the above embodiment, the second scan signal GC[i] applied to the i-th second scan line S2i may be the same (or substantially the same) as the third scan signal applied to the (i+2)-th third scan line. In this case, the scan driver 122 (refer to Figure 1 ) design and manufacture. However, the embodiments of the present disclosure are not limited thereto.

[0106] Figure 5A and Figure 5B shows the input to Figure 4 The gate signals EM, GW, GC, GI and GB of the sub-pixel SPX (for example, the gate signals EM[i], GW[i], GC[i], GI[i] and GB[i] (refer to Figure 4 ))'s waveform.

[0107] The gate signal may include a first scan signal GW, a second scan signal GC, a third scan signal GI, and a fourth scan signal GB and an emission signal EM. In an embodiment of the present disclosure, the gate signal may have a high logic level or a low logic level. In the following description, a signal of a high logic level is a high level voltage VGH as an example, and a signal of a low logic level is a low level voltage VGL as an example. However, embodiments of the present disclosure are not limited thereto.

[0108] The high level voltage VGH may be an off level voltage of a pixel transistor including a PMOS. The high level voltage VGH may be an on level voltage of a pixel transistor including an NMOS.

[0109] The low level voltage VGL may be a turn-on level voltage of a pixel transistor including a PMOS. The low level voltage VGL may be a turn-off level voltage of a pixel transistor including an NMOS.

[0110] Reference Figure 5A , in the first scan signal GW, the fourth scan signal GB, and the emission signal EM, the high level voltage VGH may be an off level voltage, and the low level voltage VGL may be an on level voltage.

[0111] Reference Figure 5B , in the second scan signal GC and the third scan signal GI, the high level voltage VGH may be an on-level voltage, and the low level voltage VGL may be an off-level voltage.

[0112] Figure 6 Is input to Figure 4 0 is an example of a timing diagram of gate signals EM[i], GW[i], GC[i], GI[i] and GB[i] of the sub-pixel SPX.

[0113] Reference Figure 6 , first to tenth periods H1 to H10 are shown, and the length or duration of each of the first to tenth periods H1 to H10 may correspond to one horizontal period 1H.

[0114] The length of one horizontal period 1H may correspond to the length of the period for transmitting the data voltage Vdata (refer to Figure 4 ) is written into the sub-pixel SPX (refer to Figure 4 ) (or the length of the period allocated for writing the data voltage Vdata). The corresponding length may correspond to the length of the period in which the horizontal synchronization signal Hsync switches once. In the following description, except for reference to Figure 6 In addition, refer to Figure 4 .

[0115] In the first period H1, the emission signal EM[i] of the on level, the third scan signal GI[i] of the off level, the second scan signal GC[i] of the off level, the first scan signal GW[i] of the off level, and the fourth scan signal GB[i] of the off level are applied to the sub-pixel SPX. The sixth pixel transistor TR6 and the seventh pixel transistor TR7 may be turned on. The fourth pixel transistor TR4 may be turned off. The third pixel transistor TR3 may be turned off. The second pixel transistor TR2 may be turned off. The fifth pixel transistor TR5 and the eighth pixel transistor TR8 may be turned off.

[0116] In the second period H2, an emission signal EM[i] of an off level, a third scan signal GI[i] of an off level, a second scan signal GC[i] of an off level, a first scan signal GW[i] of an off level, and a fourth scan signal GB[i] of an off level are applied to the subpixel SPX. From the first period H1 to the second period H2, the emission signal EM[i] is changed from an on level to an off level. The sixth pixel transistor TR6 and the seventh pixel transistor TR7 may be turned off. The fourth pixel transistor TR4 may be turned off. The second pixel transistor TR2 may be turned off. The fifth pixel transistor TR5 and the eighth pixel transistor TR8 may be turned off. The third pixel transistor TR3 may be turned off.

[0117] In the third period H3, the emission signal EM[i] of the off level, the third scan signal GI[i] of the off level, the second scan signal GC[i] of the off level, the first scan signal GW[i] of the off level, and the fourth scan signal GB[i] of the on level are applied to the sub-pixel SPX. The sixth pixel transistor TR6 and the seventh pixel transistor TR7 may be turned off. The fourth pixel transistor TR4 may be turned off. The third pixel transistor TR3 may be turned off. The second pixel transistor TR2 may be turned off. The fifth pixel transistor TR5 and the eighth pixel transistor TR8 may be turned on. During the third period H3, the third power supply voltage VAR may be applied to the fourth pixel node PN4, and the fourth power supply voltage VOBS may be applied to the first pixel node PN1.

[0118] In the fourth period H4, the emission signal EM[i] of the off level, the first scan signal GW[i] of the off level, the second scan signal GC[i] of the off level, and the fourth scan signal GB[i] of the off level are applied to the sub-pixel SPX. The third scan signal GI[i] is changed from the off level to the on level during the fourth period. The sixth pixel transistor TR6 and the seventh pixel transistor TR7 may be turned off. The second pixel transistor TR2 may be turned off. The fifth pixel transistor TR5 and the eighth pixel transistor TR8 may be turned off. The fourth pixel transistor TR4 may be turned on. The third pixel transistor TR3 may be turned off. The second power supply voltage VINT may be applied to the third pixel node PN3 during the fourth period H4. The second power supply voltage VINT may be the on-level voltage of the first pixel transistor TR1.

[0119] In the fifth period H5, the emission signal EM[i] of the off level, the third scan signal GI[i] of the on level, the second scan signal GC[i] of the off level, the first scan signal GW[i] of the off level, and the fourth scan signal GB[i] of the off level are applied to the sub-pixel SPX. The sixth pixel transistor TR6 and the seventh pixel transistor TR7 may be turned off. The fourth pixel transistor TR4 may be turned on. The third pixel transistor TR3 may be turned off. The second pixel transistor TR2 may be turned off. The fifth pixel transistor TR5 and the eighth pixel transistor TR8 may be turned off.

[0120] In the sixth period H6, the emission signal EM[i] of the off level, the first scan signal GW[i] of the off level, and the fourth scan signal GB[i] of the off level are applied to the sub-pixel SPX. The second scan signal GC[i] is changed from the off level to the on level, and the third scan signal GI[i] is changed from the on level to the off level. The sixth pixel transistor TR6 and the seventh pixel transistor TR7 may be turned off. The third pixel transistor TR3 may be turned on. The second pixel transistor TR2 may be turned off. The fifth pixel transistor TR5 and the eighth pixel transistor TR8 may be turned off.

[0121] In the seventh period H7, an emission signal EM[i] of an off level, a third scan signal GI[i] of an off level, a second scan signal GC[i] of an on level, a first scan signal GW[i] of an on level, and a fourth scan signal GB[i] of an off level are applied to the subpixel SPX. The sixth pixel transistor TR6 and the seventh pixel transistor TR7 may be turned off. The fourth pixel transistor TR4 may be turned off. The third pixel transistor TR3 may be turned on. The second pixel transistor TR2 may be turned on. The fifth pixel transistor TR5 and the eighth pixel transistor TR8 may be turned off. In the seventh period H7, the data voltage Vdata or a voltage corresponding thereto may be applied to the first pixel node PN1.

[0122] In the eighth period H8, the emission signal EM[i] of the off level, the third scan signal GI[i] of the off level, the second scan signal GC[i] of the off level, the first scan signal GW[i] of the off level, and the fourth scan signal GB[i] of the on level are applied to the sub-pixel SPX. The sixth pixel transistor TR6 and the seventh pixel transistor TR7 may be turned off. The fourth pixel transistor TR4 may be turned off. The third pixel transistor TR3 may be turned off. The second pixel transistor TR2 may be turned off. The fifth pixel transistor TR5 and the eighth pixel transistor TR8 may be turned on. During the eighth period H8, the third power supply voltage VAR may be applied to the fourth pixel node PN4, and the fourth power supply voltage VOBS may be applied to the first pixel node PN1.

[0123] In the ninth period H9, the emission signal EM[i] of the off level, the third scan signal GI[i] of the off level, the second scan signal GC[i] of the off level, the first scan signal GW[i] of the off level, and the fourth scan signal GB[i] of the off level are applied to the sub-pixel SPX. The sixth pixel transistor TR6 and the seventh pixel transistor TR7 may be turned off. The fourth pixel transistor TR4 may be turned off. The third pixel transistor TR3 may be turned off. The second pixel transistor TR2 may be turned off. The fifth pixel transistor TR5 and the eighth pixel transistor TR8 may be turned off.

[0124] In the tenth period H10, the emission signal EM[i] of the on level, the third scan signal GI[i] of the off level, the second scan signal GC[i] of the off level, the first scan signal GW[i] of the off level, and the fourth scan signal GB[i] of the off level are applied to the sub-pixel SPX. The sixth pixel transistor TR6 and the seventh pixel transistor TR7 may be turned on. The fourth pixel transistor TR4 may be turned off. The third pixel transistor TR3 may be turned off. The second pixel transistor TR2 may be turned off. The fifth pixel transistor TR5 and the eighth pixel transistor TR8 may be turned off. In the tenth period H10, the light emitting element LE of the sub-pixel SPX may emit light having a brightness corresponding to the written data voltage Vdata.

[0125] Figure 7 yes Figure 1 1 is a block diagram of an embodiment of a gate drive circuit 120.

[0126] Reference Figure 7 According to the gate drive circuit 120 of the embodiment shown (refer to Figure 1 ) may include a shift register 700. The shift register 700 may include a plurality of stage circuits 7101, ..., 710i, 710(i+1), 710(i+2), 710(i+3), .... The shift register 700 may be applied to the above reference Figure 1 The scan driver 122 and / or the emission driver 124.

[0127] Figure 7 An embodiment is shown in which one start signal VST and four clock signals (e.g., a first clock signal CLK1, a second clock signal CLK2, a third clock signal CLK3, and a fourth clock signal CLK4) are input to the shift register 700. However, depending on the embodiment, the number of clock signals input to the shift register 700 may be less than four or greater than four. Hereinafter, for convenience of description, an embodiment in which four clock signals are input to the shift register 700 is described as an example, but embodiments of the present disclosure are not limited thereto.

[0128] At least one of the plurality of stage circuits 7101, ..., 710i, 710(i+1), 710(i+2), 710(i+3), ... (e.g., each of the stage circuits) may include an input terminal IN, a first clock signal input terminal CLK_IN1, a second clock signal input terminal CLK_IN2, and an output terminal OUT. The shift register 700 may output output signals OUT[1], ..., OUT[i], OUT[i+1], OUT[i+2], OUT[i+3], ... from the output terminal OUT in response to signals input to the input terminal IN, the first clock signal input terminal CLK_IN1, and the second clock signal input terminal CLK_IN2 of the plurality of stage circuits 7101, ..., 710i, 710(i+1), 710(i+2), 710(i+3), ...

[0129] Each of the input terminals IN of the stage circuits 7101, ..., 710i, 710(i+1), 710(i+2), 710(i+3), ... receives a different input signal. For example, the start signal VST may be applied to the input terminal IN of the first stage circuit 7101 among the plurality of stage circuits 7101, ..., 710i, 710(i+1), 710(i+2), 710(i+3), ... As another example, at least one stage circuit other than the first stage circuit 7101 among the plurality of stage circuits 7101, ..., 710i, 710(i+1), 710(i+2), 710(i+3), ... may include an input terminal IN connected to the output terminal OUT of any one of the previous stage circuits. In the illustrated embodiment, the output signal of the previous stage circuit may be used as an input signal of the subsequent stage circuit.

[0130] Reference Figure 7 , the (i+1)th stage circuit 710(i+1) may include an input terminal IN connected to the output terminal OUT of any previous stage circuit (for example, the i-th stage circuit 710i (hereinafter, also referred to as the stage circuit 710i)). In the above embodiment, the previous stage circuit connected to the (i+1)th stage circuit 710(i+1) is the i-th stage circuit 710i as an example. However, the embodiments of the present disclosure are not limited to this. For example, the input terminal IN of the (i+1)th stage circuit 710(i+1) may be connected to the output terminal of the (i-1)th stage circuit, or may be connected to the output terminal of the (i-2)th stage circuit.

[0131] Each of the plurality of stage circuits 7101 , . . . , 710 i , 710 ( i+1 ), 710 ( i+2 ), 710 ( i+3 ), . . . may receive two clock signals selected from among the four clock signals CLK1 to CLK4 .

[0132] For example, the i-th stage circuit 710i may receive the first clock signal CLK1 at the first clock signal input terminal CLK_IN1, and receive the second clock signal CLK2 at the second clock signal input terminal CLK_IN2. For example, the (i+1)-th stage circuit 710(i+1) may receive the second clock signal CLK2 at the first clock signal input terminal CLK_IN1, and receive the third clock signal CLK3 at the second clock signal input terminal CLK_IN2. For example, the (i+2)-th stage circuit 710(i+2) may receive the third clock signal CLK3 at the first clock signal input terminal CLK_IN1, and receive the fourth clock signal CLK4 at the second clock signal input terminal CLK_IN2. For example, the (i+3)-th stage circuit 710(i+3) may receive the fourth clock signal CLK4 at the first clock signal input terminal CLK_IN1, and receive the first clock signal CLK1 at the second clock signal input terminal CLK_IN2.

[0133] Figure 8 yes Figure 7 An example of a stage circuit 710i included in the shift register 700.

[0134] Reference Figure 8 , the stage circuit 710i according to the embodiment of the present disclosure may include a first clock signal input terminal CLK_IN1, a second clock signal input terminal CLK_IN2, an input terminal IN, an output terminal OUT, and a constant voltage terminal L_IN. The stage circuit 710i may include at least one switching element (e.g., a transistor) and at least one storage element (e.g., a capacitor). For example, Figure 8 An embodiment in which the stage circuit 710i includes eight transistors and two capacitors is shown. However, the embodiments of the present disclosure are not limited thereto.

[0135] The first clock signal input terminal CLK_IN1 is configured to receive a clock signal. For example, the clock signal input to the first clock signal input terminal CLK_IN1 may be Figure 7 Any one of the first to fourth clock signals CLK1 to CLK4 described.

[0136] The second clock signal input terminal CLK_IN2 is configured to receive a clock signal. For example, the clock signal input to the second clock signal input terminal CLK_IN2 may be Figure 7 Another one of the first to fourth clock signals CLK1 to CLK4 described above. A clock signal (eg, the second clock signal CLK2 (refer to Figure 7)) may be a clock signal input to the first clock signal input terminal CLK_IN1 (for example, the first clock signal CLK1 (refer to Figure 7 )) is a clock signal whose phase is delayed compared to the clock signal of FIG. However, the embodiments of the present disclosure are not limited thereto.

[0137] Reference above Figure 7 The described start signal VST may be input to the input terminal IN. Alternatively, the input terminal IN may be connected (eg, electrically connected) to the output terminal OUT of the previous stage circuit. In the above-described embodiment, the output signal output from the output terminal OUT of the previous stage circuit may be input to the input terminal IN.

[0138] The output terminal OUT may be configured to output an output signal. The output signal may be a gate signal or a signal corresponding to a gate signal. For example, the output signal output from the output terminal OUT may correspond to the above reference Figure 4 In other examples, the output signal output from the output terminal OUT may correspond to the first scan signal GW[i], may correspond to the fourth scan signal GB[i], or may correspond to the emission signal EM[i], all of which are described above with reference to Figure 4 Hereinafter, for the convenience of description, an embodiment in which an output signal corresponds to the second scan signal GC[i] or the third scan signal GI[i] is described as an example. However, embodiments of the present disclosure are not limited thereto.

[0139] According to an embodiment, the output terminal OUT may be connected (eg, electrically connected) to a level shifter (not shown). According to an embodiment, the output terminal OUT or the level shifter may be connected (eg, electrically connected) to a gate line (eg, Figure 4 The output terminal OUT is directly connected to the second scan line S2i or the third scan line S3i (refer to Figure 4 ) are described as examples, but embodiments of the present disclosure are not limited thereto.

[0140] In an embodiment in which the level shifter as described above is omitted, a signal high level of the output signal output from the output terminal OUT may correspond to Figure 5B The high level voltage VGH. The low level signal can correspond to Figure 5B However, the embodiments of the present disclosure are not limited to the above structure.

[0141] The constant voltage may be applied to the constant voltage terminal L_IN. According to an embodiment, when the stage circuit 710i is configured to drive a transistor including an N-type semiconductor layer, the level of the constant voltage may be a low level. In the following, the stage circuit 710i is configured to drive a transistor including an N-type semiconductor layer (e.g., Figure 4 The embodiment of the third pixel transistor TR3 and the fourth pixel transistor TR4 is described as an example. However, the embodiments of the present disclosure are not limited thereto. In the above-mentioned embodiment, the level of the constant voltage applied to the constant voltage terminal L_IN may be, for example, a low level L. The low level L may correspond to the above-mentioned low level voltage VGL (refer to Figure 5B ).

[0142] The stage circuit 710i according to the illustrated embodiment may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8. The stage circuit 710i may also include a first capacitor C1 and a second capacitor C2.

[0143] The first transistor T1 may be configured to switch the electrical connection between the input terminal IN and the third transistor T3. The first transistor T1 may include a gate electrode connected (e.g., electrically connected) to the first clock signal input terminal CLK_IN1. The first transistor T1 may be driven by a clock signal (e.g., the first clock signal CLK1 (refer to Figure 7 When the first transistor T1 is turned on, the second node N2 and the input terminal IN may be electrically connected via the third transistor T3.

[0144] The second transistor T2 may be configured to switch the electrical connection between the second clock signal input terminal CLK_IN2 and the second capacitor C2. The second transistor T2 may include a side electrode (e.g., any one of the source electrode and the drain electrode) connected to (e.g., electrically connected) the second clock signal input terminal CLK_IN2 and another side electrode (e.g., the other of the source electrode and the drain electrode) connected (e.g., electrically connected) to the second capacitor C2 (e.g., one electrode of the second capacitor C2). The second transistor T2 may be controlled by the voltage of the second node N2. The second node N2 may be connected (e.g., electrically connected) to the other electrode of the second capacitor C2. When the second transistor T2 is turned on, the second capacitor C2 and the second clock signal input terminal CLK_IN2 may be electrically connected.

[0145] The third transistor T3 may be connected between the first transistor T1 and the second node N2. The third transistor T3 may include a gate electrode connected (eg, electrically connected) to the constant voltage terminal L_IN. When the third transistor T3 is turned on, the first transistor T1 and the second node N2 may be electrically connected.

[0146] The fourth transistor T4 may be configured to switch the electrical connection between the constant voltage terminal L_IN and the output terminal OUT. The fourth transistor T4 may be controlled by the voltage of the second node N2. When the fourth transistor T4 is turned on, the output terminal OUT may be electrically connected to the constant voltage terminal L_IN.

[0147] The fifth transistor T5 may be configured to switch the electrical connection between the first clock signal input terminal CLK_IN1 and the output terminal OUT. The fifth transistor T5 may be controlled by the voltage of the first node N1. When the fifth transistor T5 is turned on, the first clock signal input terminal CLK_IN1 and the output terminal OUT may be electrically connected. One side electrode (e.g., one of the source electrode and the drain electrode of the fifth transistor T5) may be connected (e.g., electrically connected) to the first capacitor C1 (e.g., one electrode of the first capacitor C1). The gate electrode of the fifth transistor T5 may be connected (e.g., electrically connected) to the first capacitor C1 (e.g., the other electrode of the first capacitor C1) at the first node N1.

[0148] The sixth transistor T6 may be configured to switch the electrical connection between the first clock signal input terminal CLK_IN1 and the first node N1. The sixth transistor T6 may be controlled by the voltage of the second node N2. When the sixth transistor T6 is turned on, the first clock signal input terminal CLK_IN1 may be electrically connected to the first node N1.

[0149] The seventh transistor T7 may be configured to switch the electrical connection between the constant voltage terminal L_IN and the eighth transistor T8. The seventh transistor T7 may be controlled by the voltage of the second node N2. When the seventh transistor T7 is turned on, the eighth transistor T8 and the constant voltage terminal L_IN may be electrically connected.

[0150] The eighth transistor T8 may be configured to switch the electrical connection between the seventh transistor T7 and the first node N1. The eighth transistor T8 may include a gate electrode connected (e.g., electrically connected) to the second clock signal input terminal CLK_IN2. The eighth transistor T8 may be input to the second clock signal input terminal CLK_IN2 by a clock signal (e.g., the second clock signal CLK2 (refer to Figure 7 When the eighth transistor T8 is turned on, the seventh transistor T7 and the first node N1 may be electrically connected.

[0151] The first capacitor C1 may include one electrode connected (eg, electrically connected) to the first clock signal input terminal CLK_IN1 and another electrode connected (eg, electrically connected) to the first node N1 .

[0152] The second capacitor C2 may include one electrode connected (eg, electrically connected) to the second transistor T2 and another electrode connected (eg, electrically connected) to the second node N2.

[0153] According to an embodiment, the stage circuit 710i can be the same as that described above with reference to Figure 4 According to an embodiment, the stage circuit 710i may be implemented as an integrated circuit and connected to the display panel 110 (refer to Figure 1 ).

[0154] The first transistor T1 to the eighth transistor T8 may be implemented as field effect transistors. At least one of the first transistor T1 to the eighth transistor T8 may be implemented as a field effect transistor including an N-type semiconductor layer, and the remaining transistors may be implemented as field effect transistors including a P-type semiconductor layer. For example, the seventh transistor T7 may be implemented as a field effect transistor including an N-type semiconductor layer, and the first transistor T1 to the sixth transistor T6 and the eighth transistor T8 may be implemented as field effect transistors including a P-type semiconductor layer.

[0155] Further references Figure 4 and Figure 8 In an embodiment, the seventh transistor T7 may be formed in the same process as the process of forming the third pixel transistor TR3 and / or the fourth pixel transistor TR4. For example, the third pixel transistor TR3, the fourth pixel transistor TR4, and the seventh transistor T7 may be formed together in a process including forming an oxide semiconductor.

[0156] Further references Figure 4 and Figure 8 In an embodiment, the first to sixth transistors T1 to T6 and the eighth transistor T8 may be formed together in a process of forming at least one of the first pixel transistor TR1, the second pixel transistor TR2, and the fifth pixel transistor TR5 to the eighth pixel transistor TR8. For example, the first to sixth transistors T1 to T6, the eighth transistor T8, the first pixel transistor TR1, the second pixel transistor TR2, and the fifth pixel transistor TR5 to the eighth pixel transistor TR8 may be formed together in a process including forming an LTPS semiconductor.

[0157] Fig. 9 Is input to Figure 7 The signals of the shift register 700 and from Figure 7 An example of a timing diagram of the signals output by the shift register 700.

[0158] Reference Fig. 9The timing diagram shows the horizontal synchronization signal Hsync, the start signal VST, the first clock signal CLK1 to the fourth clock signal CLK4, and the output signals OUT[1], OUT[2], etc. Fig. 9 The horizontal synchronization signal Hsync in the reference Figure 6 The horizontal synchronization signals Hsync are the same.

[0159] The horizontal synchronization signal Hsync can be switched. The length of a period in which the horizontal synchronization signal Hsync is switched once may correspond to one horizontal period 1H.

[0160] Reference Figure 7 , the i-th output signal OUT[i] may correspond to a signal output from the output terminal OUT of the stage circuit 710i, i being an integer ranging from 1 to the number of stages in the shift register 700. The first output signal OUT[1] (hereinafter, also simply referred to as the output signal OUT[1]) may correspond to a signal output from the output terminal OUT of the first stage circuit 7101. The second output signal OUT[2] may correspond to a signal output from the output terminal OUT of the second stage circuit.

[0161] Figures 10 to 17 An example of a method of driving a gate driving circuit according to an embodiment of the present disclosure is shown.

[0162] Reference Figures 10 to 17 ,like Figure 7 The first stage circuit 7101 (hereinafter referred to as the stage circuit 7101) connected as shown in FIG. 1 is described as an example. Figure 7 , the signal input to the first clock signal input terminal CLK_IN1 may correspond to the first clock signal CLK1. The signal input to the second clock signal input terminal CLK_IN2 may correspond to the second clock signal CLK2. However, the embodiments of the present disclosure are not limited thereto, and in another stage circuit (e.g., a second stage circuit, a third stage circuit, a fourth stage circuit, etc.) other than the first stage circuit 7101, the signal input to the first clock signal input terminal CLK_IN1 may be different from the first clock signal CLK1, and the signal input to the second clock signal input terminal CLK_IN2 may be different from the second clock signal CLK2.

[0163] Figures 10 to 17 The levels of the first node N1 and the second node N2 and the levels of the signals input to or output from the terminals are shown. "L" may indicate that the level of the corresponding node or the signal input to or output from the corresponding terminal is a low level. "H" may indicate that the level of the corresponding node or the signal input to or output from the corresponding terminal is a high level.

[0164] The level indicated by "L" may be a turn-on level of the first transistor T1 to the sixth transistor T6 and the eighth transistor T8. The level indicated by "L" may be a turn-off level of the seventh transistor T7. The level indicated by "H" may be a turn-off level of the first transistor T1 to the sixth transistor T6 and the eighth transistor T8. The level indicated by "H" may be a turn-on level of the seventh transistor T7.

[0165] Figures 10 to 17 The first to eighth periods PR1 to PR8 are shown respectively. The first to eighth periods PR1 to PR8 may be sequentially continuous. Each of the first to eighth periods PR1 to PR8 may be defined as a period between two timings.

[0166] Figures 10 to 17 It is also shown that each of the first period PR1 to the eighth period PR8 includes seven sub-periods SPR (refer to Fig. 9 However, the embodiments of the present disclosure are not limited thereto, and each of the time periods may include less than seven sub-time periods SPR (refer to Fig. 9 ) or more than seven sub-period SPRs (refer to Fig. 9 ).

[0167] In an embodiment, the total length of the first period PR1 to the eighth period PR8 may be five to six horizontal periods. In the above embodiment, the second clock signal CLK2 may be a clock signal whose phase is delayed by one horizontal period 1H compared with the first clock signal CLK1 (refer to Fig. 9 The third clock signal CLK3 may be a signal whose phase is delayed by one horizontal period 1H compared with the second clock signal CLK2 (refer to Fig. 9 The fourth clock signal CLK4 may be a signal whose phase is delayed by one horizontal period 1H compared with the third clock signal CLK3 (refer to Fig. 9 The first clock signal CLK1 may be a signal whose phase is delayed by one horizontal period 1H compared with the fourth clock signal CLK4 (refer to Fig. 9 However, the embodiments of the present disclosure are not limited thereto.

[0168] Hereinafter, a method of operating a gate driving circuit according to an embodiment of the present disclosure during the first to eighth periods PR1 to PR8 is described in detail with reference to a timing diagram and an equivalent circuit diagram of the stage circuit 7101 .

[0169] Reference Fig.10 , the first period PR1 may be a period between the first timing TM1 and the second timing TM2.

[0170] The first timing TM1 may be the time when the level of the signal input to the input terminal IN (e.g., the start signal VST) is at a low level L, the level of the signal input to the second clock signal input terminal CLK_IN2 (e.g., the second clock signal CLK2) is at a high level H, and the level of the signal input to the first clock signal input terminal CLK_IN1 (e.g., the first clock signal CLK1) changes from a high level H to a low level L.

[0171] The second timing TM2 may be a time when the level of the signal input to the input terminal IN changes from low level L to high level H, the level of the signal input to the first clock signal input terminal CLK_IN1 is low level L, and the level of the signal input to the second clock signal input terminal CLK_IN2 is high level H.

[0172] In the first period PR1, the first transistor T1 may be turned on. The third transistor T3 may be turned on. The second node N2 may be at a low level L. The second transistor T2 may be turned on. The fourth transistor T4 may be turned on. The sixth transistor T6 may be turned on. The first node N1 may be at a low level L. The fifth transistor T5 may be turned on. The seventh transistor T7 may be turned off. The eighth transistor T8 may be turned off. The output terminal OUT may be at a low level L. The output signal OUT[1] has a low level L.

[0173] Reference Fig.11 , the second period PR2 may be a period between the second timing TM2 and the third timing TM3.

[0174] Description and reference of the second timing TM2 Fig.10 Same as the one described.

[0175] The third timing TM3 may be a time when the level of the signal input to the input terminal IN is high level H, the level of the signal input to the first clock signal input terminal CLK_IN1 is low level L, and the level of the signal input to the second clock signal input terminal CLK_IN2 changes from high level H to low level L.

[0176] In the second period PR2, the first transistor T1 may be turned on. The third transistor T3 may be turned on, and the second node N2 may be at a high level H. The second transistor T2 may be turned off. The fourth transistor T4 may be turned off. The sixth transistor T6 may be turned off. The first node N1 may maintain a low level L. The fifth transistor T5 may be turned on. The seventh transistor T7 may be turned on. The eighth transistor T8 may be turned off. The output terminal OUT may be at a low level L. The output signal OUT[1] has a low level L.

[0177] Reference Fig.12 , the third period PR3 may be a period between the third timing TM3 and the fourth timing TM4.

[0178] Description and reference of the third timing TM3 Fig.11 Same as the one described.

[0179] The fourth timing TM4 may be a time when the level of the signal input to the input terminal IN is high level H, the level of the signal input to the first clock signal input terminal CLK_IN1 changes from low level L to high level H, and the level of the signal input to the second clock signal input terminal CLK_IN2 is low level L.

[0180] In the third period PR3, the first transistor T1 may be turned on. The third transistor T3 may be turned on. The second node N2 may be maintained at a high level H. The second transistor T2 may be turned off. The fourth transistor T4 may be turned off. The sixth transistor T6 may be turned off. The first node N1 may maintain a low level L. The fifth transistor T5 may be turned on. The seventh transistor T7 may be turned on. The eighth transistor T8 may be turned on. The first node N1 may be electrically connected to the constant voltage terminal L_IN. The output terminal OUT may be a low level L until the level of the signal input to the first clock signal input terminal CLK_IN1 changes from a low level L to a high level H. The output signal OUT[1] has a low level L during the third period PR3.

[0181] Reference Fig.13 , the fourth period PR4 may be a period between the fourth timing TM4 and the fifth timing TM5.

[0182] Description and reference of the fourth timing TM4 Fig.12 Same as the one described.

[0183] The fifth timing TM5 may be a time when the level of the signal input to the input terminal IN is high level H, the level of the signal input to the first clock signal input terminal CLK_IN1 is high level H, and the level of the signal input to the second clock signal input terminal CLK_IN2 changes from low level L to high level H.

[0184] In the fourth period PR4, the first transistor T1 may be turned off. The third transistor T3 may be turned on. The second node N2 may be maintained at a high level H. The second transistor T2 may be turned off. The fourth transistor T4 may be turned off. The sixth transistor T6 may be turned off. The seventh transistor T7 may be turned on. The eighth transistor T8 may be turned on. The first node N1 may be a low level L. The fifth transistor T5 may be turned on. The output terminal OUT may be a high level H, and thus the output signal OUT[1] has a high level H.

[0185] Reference Fig.14 , the fifth period PR5 may be a period between the fifth timing TM5 and the sixth timing TM6.

[0186] Description and reference of the fifth timing TM5 Fig.13 Same as the one described.

[0187] The sixth timing TM6 may be a time when the level of the signal input to the input terminal IN changes from high level H to low level L, the level of the signal input to the first clock signal input terminal CLK_IN1 is high level H, and the level of the signal input to the second clock signal input terminal CLK_IN2 is high level H.

[0188] In the fifth period PR5, the first transistor T1 may be turned off. The third transistor T3 may be turned on. The second node N2 may be maintained at a high level H. The second transistor T2 may be turned off. The fourth transistor T4 may be turned off. The sixth transistor T6 may be turned off. The seventh transistor T7 may be turned on. The eighth transistor T8 may be turned off. The voltage of the first node N1 may be maintained at a low level L. The fifth transistor T5 may be turned on. The output terminal OUT may be a high level H, and thus the output signal OUT[1] may have a high level H.

[0189] Reference Fig.15 , the sixth period PR6 may be a period between the sixth timing TM6 and the seventh timing TM7.

[0190] Description and reference of the sixth timing TM6 Fig.14 Same as the one described.

[0191] The seventh timing TM7 may be a time when the level of the signal input to the input terminal IN is low level L, the level of the signal input to the first clock signal input terminal CLK_IN1 changes from high level H to low level L, and the level of the signal input to the second clock signal input terminal CLK_IN2 is high level H.

[0192] In the sixth period PR6, the first transistor T1 may be turned off. The third transistor T3 may be turned on. The second node N2 may be maintained at a high level H. The second transistor T2 may be turned off. The fourth transistor T4 may be turned off. The sixth transistor T6 may be turned off. The seventh transistor T7 may be turned on. The eighth transistor T8 may be turned off. The first node N1 may be maintained at a low level L. The fifth transistor T5 may be turned on. The output terminal OUT may be a high level H, and thus the output signal OUT[1] has a high level H.

[0193] Reference Fig.16 , the seventh period PR7 may be a period between the seventh timing TM7 and the eighth timing TM8.

[0194] Description and reference of the seventh timing TM7 Fig.15 Same as the one described.

[0195] The eighth timing TM8 may be a time when the level of the signal input to the input terminal IN is low level L, the level of the signal input to the first clock signal input terminal CLK_IN1 is low level L, and the level of the signal input to the second clock signal input terminal CLK_IN2 changes from high level H to low level L.

[0196] In the seventh period PR7, the first transistor T1 may be turned on. The third transistor T3 may be turned on. The second node N2 may be at a low level L. The second transistor T2 may be turned on. The fourth transistor T4 may be turned on. The sixth transistor T6 may be turned on. The first node N1 may be at a low level L. The fifth transistor T5 may be turned on. The seventh transistor T7 may be turned off. The eighth transistor T8 may be turned off. The output terminal OUT may be at a low level L, and thus the output signal OUT[1] has a low level L.

[0197] Reference Fig.17 , the eighth period PR8 may be a period between the eighth timing TM8 and the ninth timing TM9.

[0198] Description and reference of the eighth timing TM8 Fig.16 Same as the one described.

[0199] The ninth timing TM9 may be a time when the level of the signal input to the input terminal IN is low level L, the level of the signal input to the first clock signal input terminal CLK_IN1 changes from low level L to high level H, and the level of the signal input to the second clock signal input terminal CLK_IN2 is low level L.

[0200] In the eighth period PR8, the first transistor T1 may be turned on. The third transistor T3 may be turned on. The second node N2 may be at a low level L. The second transistor T2 may be turned on. The fourth transistor T4 may be turned on. The sixth transistor T6 may be turned on. The first node N1 may be at a low level L. The fifth transistor T5 may be turned on. The seventh transistor T7 may be turned off. The eighth transistor T8 may be turned on. The output terminal OUT may be at a low level L, and thus the output signal OUT[1] has a high level H.

[0201] The output signal OUT[ 1 ] output from the first stage circuit 7101 through the first to eighth periods PR1 to PR8 may be input to an input terminal IN of a subsequent stage circuit (eg, a second stage circuit).

[0202] Through this, the output signals OUT[1], ..., OUT[i], OUT[i+1], OUT[i+2], OUT[i+3], ... can be output from the shift register 700 (for example, sequentially output) (refer to Figure 7 ).

[0203] According to the present disclosure, the structures of the gate driving circuit according to the embodiment of the present disclosure and the display device including the gate driving circuit can be simplified.

[0204] The drawings and detailed description herein are only examples of some specific embodiments, are only used to describe various aspects of the present disclosure, and are not intended to limit the meaning and scope of the claims to specific embodiments. Therefore, it will be understood by those skilled in the art that various modifications and other equivalent embodiments are possible. Therefore, the true scope of the present disclosure should be determined by the technical spirit of the attached claims.

Claims

1. A gate drive circuit, comprising: Multiple stage circuits, Wherein, any one of the plurality of stage circuits comprises: a first clock signal input terminal, into which a first clock signal is input; a second clock signal input terminal, to which a second clock signal is input; An input terminal to which an input signal is input; an output terminal from which an output signal is output; a constant voltage terminal to which a constant voltage is applied; a first transistor electrically connected to the input terminal and controlled in response to the first clock signal; a second transistor electrically connected to the second clock signal input terminal and controlled in response to a voltage of a second node; a third transistor connected between the first transistor and the second node; a fourth transistor configured to switch an electrical connection between the constant voltage terminal and the output terminal in response to the voltage of the second node; a fifth transistor configured to switch an electrical connection between the first clock signal input terminal and the output terminal in response to a voltage of the first node; a sixth transistor configured to switch an electrical connection between the first node and the first clock signal input terminal in response to the voltage of the second node; a seventh transistor controlled in response to the voltage of the second node and electrically connected to the constant voltage terminal; and An eighth transistor configured to switch an electrical connection between the seventh transistor and the first node.

2. The gate drive circuit according to claim 1, wherein: The seventh transistor includes an N-type semiconductor layer.

3. The gate driving circuit according to claim 1, wherein: The any one stage circuit further includes a first capacitor configured to maintain a voltage difference between the first clock signal input terminal and the first node.

4. The gate driving circuit according to claim 1, wherein: The any one stage circuit further includes a second capacitor configured to maintain a voltage difference between any one of a source electrode and a drain electrode of the second transistor and a gate electrode of the second transistor.

5. The gate driving circuit according to claim 1, wherein: The plurality of stage circuits include another stage circuit preceding any one of the stage circuits, and The input signal is the output signal of the another stage circuit.

6. The gate driving circuit according to claim 1, wherein: Any one of the stage circuits precedes all other stage circuits among the plurality of stage circuits, and The input signal is a start signal.

7. The gate driving circuit according to claim 1, wherein: The output signal has either a high level or a low level, and The length of a period during which the plurality of stage circuits output the output signal of the low level is longer than the length of a period during which the plurality of stage circuits output the output signal of the high level.

8. The gate driving circuit according to claim 1, wherein: The first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the eighth transistor include a P-type semiconductor layer.

9. A display device, comprising: a display panel in which a plurality of sub-pixels are arranged, a plurality of gate lines extending in a first direction and electrically connected to the plurality of sub-pixels are arranged, and a plurality of data lines extending in a second direction and electrically connected to the plurality of sub-pixels are arranged; a gate driving circuit configured to drive the plurality of gate lines and comprising a plurality of stage circuits; as well as a timing controller configured to output a first clock signal and a second clock signal, Wherein, any one of the plurality of stage circuits comprises: a first clock signal input terminal, to which the first clock signal is input; a second clock signal input terminal, to which the second clock signal is input; An input terminal to which an input signal is input; an output terminal from which an output signal is output; a constant voltage terminal to which a low-level voltage is applied; a first transistor electrically connected to the input terminal and controlled in response to the first clock signal; a second transistor electrically connected to the second clock signal input terminal and controlled in response to a voltage of a second node; a third transistor connected between the first transistor and the second node; a fourth transistor configured to switch an electrical connection between the constant voltage terminal and the output terminal in response to the voltage of the second node; a fifth transistor configured to switch an electrical connection between the first clock signal input terminal and the output terminal in response to a voltage of the first node; a sixth transistor configured to switch an electrical connection between the first node and the first clock signal input terminal in response to the voltage of the second node; a seventh transistor controlled in response to the voltage of the second node and electrically connected to the constant voltage terminal; and An eighth transistor configured to switch an electrical connection between the seventh transistor and the first node.

10. The display device according to claim 9, wherein: The seventh transistor includes an N-type semiconductor layer.

11. The display device according to claim 9, wherein: Each of the plurality of sub-pixels includes a pixel circuit and a light emitting element connected to the pixel circuit, The pixel circuit comprises: a first pixel transistor connected between the first pixel node and the second pixel node and including a gate electrode electrically connected to a third pixel node; a second pixel transistor connected between a corresponding data line among the plurality of data lines and the first pixel node and including a gate electrode connected to a first scan line; a third pixel transistor connected between the second pixel node and the third pixel node and including a gate electrode connected to a second scan line; and a fourth pixel transistor configured to switch electrical connection between a power line to which a first initialization voltage is applied and the third pixel node, and including a gate electrode connected to a third scan line, and The output terminal is electrically connected to any one of the second scan line and the third scan line.

12. The display device according to claim 11, wherein: The light emitting element is connected between the fourth pixel node and a voltage line to which a low potential voltage is applied, and The pixel circuit further includes: a fifth pixel transistor connected between the fourth pixel node and a power line to which a second initialization voltage is applied, and including a gate electrode connected to a fourth scan line; a sixth pixel transistor connected between the second pixel node and the fourth pixel node and including a gate electrode connected to an emission line; a seventh pixel transistor connected between the first pixel node and a first power supply line to which a high potential voltage is applied, and including a gate electrode connected to the emission line; and An eighth pixel transistor is connected between the first pixel node and a power line to which a conduction bias voltage is applied, and includes a gate electrode connected to the fourth scan line.

13. The display device according to claim 11, wherein: The output terminal is electrically connected to the fourth pixel transistor included in any one of the plurality of sub-pixels, and is electrically connected to the third pixel transistor included in another sub-pixel of the plurality of sub-pixels.

14. The display device according to claim 13, wherein: The any one sub-pixel and the another sub-pixel are positioned in different pixel rows.

15. The display device according to claim 11, wherein: At least one of the third pixel transistor and the fourth pixel transistor includes an N-type semiconductor layer, and At least one of the first pixel transistor and the second pixel transistor includes a P-type semiconductor layer.

16. The display device according to claim 11, wherein: In the display panel, the plurality of sub-pixels are arranged in a display area, In the display panel, the plurality of stage circuits are arranged in a non-display area located around the display area, and The seventh transistor, the third pixel transistor, and the fourth pixel transistor are formed in the same process.

17. The display device according to claim 16, wherein: The first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the eighth transistor, the first pixel transistor, and the second pixel transistor are formed in the same process.

18. The display device according to claim 9, wherein: The any one stage circuit further includes a first capacitor configured to maintain a voltage difference between the first clock signal input terminal and the first node.

19. The display device according to claim 9, wherein: The any one stage circuit further includes a second capacitor configured to maintain a voltage difference between any one of a source electrode and a drain electrode of the second transistor and a gate electrode of the second transistor.

20. The display device according to claim 9, wherein: The plurality of stage circuits include another stage circuit preceding any one of the stage circuits, and The input signal is the output signal of the another stage circuit.

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