Memory unit, memory device, memory unit, and operating method of

Abstract

The invention discloses a storage unit, a storage device, a storage unit and an operation method of the storage device, and the storage unit comprises a memory, a first end of the memory is suitable for being electrically connected with a word line driving circuit; the first end of the gate is suitable for being electrically connected with the bit line driving circuit, the second end of the gate is suitable for being electrically connected with the second end of the memory, and the gate has at least two different threshold voltages, so that the gate has different opening states under different threshold voltage conditions. Therefore, the gate has at least two different threshold voltages, the gate has different opening states under different threshold voltage conditions, and the different opening states of the gate can control the memory to execute different operations, so that misoperation of the memory under the different opening states of the gate can be avoided; therefore, the operation reliability of the storage unit can be ensured.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a storage unit, a storage device, and an operating method of the storage unit and the storage device. Background Art

[0002] Semiconductor memory cells usually include a switching device and a memory, wherein the switching device is used to control the selection and non-selection of the target memory. Existing semiconductor memory devices usually present a 1T1M, 1S1M or 1D1M array structure, wherein T is a transistor, S is a selector, D is a diode, and M is a memory. The target memory can be selected or non-selected by applying different voltages to the gate of the transistor, or by applying different voltages across the selector or diode.

[0003] In the related art, when the threshold voltage of the read operation is large, the memory has the risk of being written incorrectly. In addition, a large voltage will reduce the service life of the switching device, and a large current will cause the switching device to generate a large power consumption. Summary of the invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, one object of the present invention is to provide a storage unit that can ensure the reliability of operation.

[0005] The present invention further provides an operating method of a storage unit.

[0006] The present invention further provides a storage device.

[0007] The present invention further provides an operating method of a storage device.

[0008] A memory cell according to an embodiment of the present invention comprises: a memory, wherein a first end of the memory is adapted to be electrically connected to a word line driving circuit; a gate, wherein a first end of the gate is adapted to be electrically connected to a bit line driving circuit, a second end of the gate is adapted to be electrically connected to a second end of the memory, and the gate has at least two different threshold voltages so that the gate has different on states under different threshold voltage conditions.

[0009] Therefore, by setting the gate to have at least two different threshold voltages, and the gate to have different on states under different threshold voltage conditions, the different on states of the gate can control the memory to perform different operations, thereby avoiding the memory from erroneous operation under different on states of the gate, thereby ensuring the operational reliability of the storage unit.

[0010] According to some embodiments of the present invention, the gate includes at least a first gate tube and a second gate tube, and a threshold voltage of the first gate tube is different from a threshold voltage of the second gate tube.

[0011] According to some embodiments of the present invention, the threshold voltage of the first gate tube is set to V1th, and the threshold voltage of the second gate tube is set to V2th, and V1th and V2th satisfy the relationship: V1th<V2th.

[0012] According to some embodiments of the present invention, V1th and V2th satisfy the relationship: 0.2V≤V2th-V1th≤1V.

[0013] According to some embodiments of the present invention, V1th and V2th satisfy the relationship: 0.2V≤V1th≤1.0V, 0.6V≤V2th≤1.8V.

[0014] According to some embodiments of the present invention, the first gating tube and the second gating tube are arranged in series.

[0015] According to some embodiments of the present invention, the first gating tube and the second gating tube are arranged in parallel.

[0016] According to some embodiments of the present invention, the first end of the first gate tube and the first end of the second gate tube are electrically connected to two different bit lines respectively; or, the first end of the first gate tube and the first end of the second gate tube are both electrically connected to the same bit line, wherein the bit line is suitable for being electrically connected to the bit line driving circuit.

[0017] According to some embodiments of the present invention, the first gate transistor and / or the second gate transistor includes at least one of a bidirectional threshold switch, a diode, and a conversion device of a metal-insulator-metal structure.

[0018] According to some embodiments of the present invention, the switching layer material of the first gate tube and / or the second gate tube includes at least one of niobium oxide, vanadium oxide and hafnium oxide.

[0019] According to some embodiments of the present invention, when the switching layer material of the first gate tube and / or the second gate tube includes hafnium oxide, the upper motor layer or the lower electrode layer of the first gate tube and / or the second gate tube includes at least silver.

[0020] According to some embodiments of the present invention, the gate includes a first electrode, a second electrode and at least two gate layers with different threshold voltages, and the at least two gate layers with different threshold voltages are arranged between the first electrode and the second electrode.

[0021] According to some embodiments of the present invention, the memory includes at least one of a resistive memory, a phase change memory, a magnetic random access memory and a ferroelectric memory.

[0022] A method for operating a memory cell according to the present invention is suitable for the memory cell described above, comprising the following steps: setting the voltage difference between a word line driving circuit and a bit line driving circuit respectively connected to two ends of the memory cell to Vsel, setting the Vsel to satisfy the relationship: V1th≤Vsel, so as to control the gate of the memory cell to enter a first on state, and performing a read operation on the memory of the memory cell, wherein the threshold voltage of the first on state of the gate is V1th.

[0023] According to some embodiments of the present invention, the gate includes at least a first gate tube and a second gate tube, and the Vsel is set to satisfy the relationship: V1th≤Vsel<V2th, the first gate tube of the storage unit is controlled to be turned on, and the second gate tube of the storage unit is controlled to be turned off, and a read operation is performed on the memory of the storage unit; wherein the threshold voltage of the first gate tube of the storage unit is V1th, and the threshold voltage of the second gate tube of the storage unit is V2th.

[0024] A method for operating a memory cell according to the present invention is suitable for the memory cell described above, comprising the following steps: setting the voltage difference between the word line driving circuit and the bit line driving circuit respectively connected to the two ends of the memory cell to Vsel, setting the Vsel to satisfy the relationship: V2th≤Vsel, so as to control the gate of the memory cell to enter a second on state, and performing a write operation on the memory cell, wherein the threshold voltage of the second on state of the gate is V2th.

[0025] According to some embodiments of the present invention, the gate includes at least a first gate tube and a second gate tube, and the Vsel is set to satisfy the relationship: V1th≤Vsel and V2th≤Vsel, so as to control the first gate tube and the second gate tube of the storage unit to be turned on, and perform a write operation on the memory of the storage unit; wherein the threshold voltage of the first gate tube of the storage unit is V1th, the threshold voltage of the second gate tube of the storage unit is V2th, and V1th<V2th.

[0026] According to some embodiments of the present invention, the step of performing a write operation on the memory of the storage unit also includes: when a write 1 operation is performed on the memory, Vsel satisfies the relationship: Vsel=Vset, wherein the threshold voltage of the memory for writing 1 is Vset; when a write 0 operation is performed on the memory, Vsel satisfies the relationship: Vsel=Vreset, wherein the threshold voltage of the memory for writing 0 is Vreset.

[0027] A storage device according to an embodiment of the present invention includes: a front-end driving circuit, the front-end driving circuit includes a bit line driving circuit and a word line driving circuit; a storage array, the storage array includes the storage unit mentioned above, the first end of the memory of the storage unit is electrically connected to the word line driving circuit, the first end of the gate of the storage unit is electrically connected to the bit line driving circuit, and the second end of the gate is suitable for being electrically connected to the second end of the memory.

[0028] An operating method for a storage device according to the present invention is suitable for the storage device described above, comprising the following steps: the threshold voltage of the on state of the gate of the storage cell is V1th, the voltage difference between the word line driving circuit and the bit line driving circuit respectively connected to the two ends of the target storage cell in the storage device is set to Vsel, and the voltage difference between the word line driving circuit and the bit line driving circuit respectively connected to the two ends of the non-target storage cell in the storage device is set to Vunsel; Vsel is set to satisfy the relationship: V1th≤Vsel, the gate of the target storage cell is controlled to be turned on, and a read operation or a write operation is performed on the memory of the target storage cell; Vunsel is set to satisfy the relationship: Vunsel<V1th, and the gate of the non-target storage cell is controlled to be turned off.

[0029] According to some embodiments of the present invention, the gate includes at least a first gate tube and a second gate tube; Vsel is set to satisfy the relationship: V1th≤Vsel<V2th, the first gate tube of the target storage unit is controlled to be turned on, the second gate tube of the target storage unit is controlled to be turned off, and a read operation is performed on the memory of the target storage unit; or, Vsel is set to satisfy the relationship: V2th≤Vsel, the first gate tube and the second gate tube of the target storage unit are controlled to be turned on, and a write operation is performed on the memory of the target storage unit; Vunsel is set to satisfy the relationship: Vunsel<V1th, the first gate tube and the second gate tube of the non-target storage unit are controlled to be turned off; wherein the threshold voltage of the first gate tube of the storage unit is V1th, the threshold voltage of the second gate tube of the storage unit is V2th, and V1th and V2th satisfy the relationship: V1th<V2th.

[0030] According to some embodiments of the present invention, the step of performing a write operation on the memory of the target memory cell also includes: when a write 1 operation is performed on the target memory cell, Vsel satisfies the relationship: Vsel=Vset, wherein the threshold voltage of the target memory cell for performing write 1 is Vset; when a write 0 operation is performed on the target memory cell, Vsel satisfies the relationship: Vsel=reset, wherein the threshold voltage of the target memory cell for performing write 0 is Vreset.

[0031] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which: Figure 1 is a schematic diagram of a storage device according to an embodiment of the present invention; Figure 2 is a schematic diagram of a storage unit according to some embodiments of the present invention; Figure 3 is a schematic diagram of a storage unit according to some other embodiments of the present invention; Figure 4 is a schematic diagram of a storage unit according to some further embodiments of the present invention; Figure 5 is a schematic diagram of a gate according to some other embodiments of the present invention.

[0033] Reference numerals: 100. Storage device; 10. Front-end drive circuit; 11. Bit line drive circuit; 12. Word line drive circuit; 20. Storage array; 21. Storage unit; 211. Selector; 2111. First select tube; 2112. Second select tube; 2113. First electrode; 2114. Second electrode; 2115. Select layer; 213. Memory. DETAILED DESCRIPTION

[0034] Embodiments of the present invention are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. Embodiments of the present invention are described in detail below.

[0035] In the prior art, the semiconductor memory unit adopts the 1S1M (1-bit single-layer unit cross array) method, which includes a gate tube and a memory, and has the advantages of high density, low sneak current, low cost, and CMOS (complementary metal oxide semiconductor technology) compatibility. However, the gate tube in 1S1M requires a higher voltage for on switch operation each time reading and writing. This operation mode will cause the following problems in the array: a larger current is generated, thereby generating a larger power consumption; a larger voltage will reduce the service life of the memory; during the reading operation, if the gate tube is connected to a larger threshold voltage, the memory will be at risk of being written by mistake. To this end, an embodiment of the present invention proposes a storage device that can be turned on with multiple gradients, that is, the reading and writing of the storage device can be performed at different threshold voltages.

[0036] Reference below Figure 1-Figure 4 The storage unit 21 according to an embodiment of the present invention is described.

[0037] Combination Figure 1-Figure 4 As shown, the memory cell 21 according to the embodiment of the present invention may mainly include: a memory 213 and a gate 211, wherein the first end of the memory 213 is suitable for being electrically connected to the word line driving circuit 12, the first end of the gate 211 is suitable for being electrically connected to the bit line driving circuit 11, and the second end of the gate 211 is suitable for being electrically connected to the second end of the memory 213. In this way, the memory 213 and the gate 211 in the memory cell 21 can be connected between the word line driving circuit 12 and the bit line driving circuit 11 to apply a voltage to both ends of the memory cell 21, thereby ensuring the circuit connectivity inside the memory cell 21.

[0038] Furthermore, the gate 211 has at least two different threshold voltages, wherein the threshold voltage is the threshold voltage of the gate 211. Normally, when the voltage on the gate 211 is lower than its threshold voltage, the gate 211 remains in a closed state. Only when the voltage on the gate 211 is equal to or greater than its threshold voltage, the gate 211 will be converted from a closed state to an open state. The open state of the gate 211 can control the operation on the memory 213.

[0039] In the embodiment of the present invention, the gate 211 has at least two different threshold voltages, and the gate 211 has different open states under different threshold voltage conditions, so that different open states of the gate 211 can be set to control different operations on the memory 213. In this way, the operation independence of different operations on the memory 213 can be guaranteed, and the memory 213 can be prevented from erroneously operating in different open states of the gate 211, thereby ensuring the operational reliability of the storage unit 21.

[0040] Combination Figure 1 As shown, the gate 211 includes at least a first gate tube 2111 and a second gate tube 2112. The threshold voltage of the first gate tube 2111 and the threshold voltage of the second gate tube 2112 are different, so that the first gate tube 2111 and the second gate tube 2112 in the storage unit 21 can be turned on at different threshold voltages. When the first gate tube 2111 and the second gate tube 2112 respectively control the memory 213 to perform different operations, different voltages can be applied to the storage unit 21 to control the memory 213 to perform different operations, thereby enabling the storage unit 21 to perform different operations, and under the control of the first gate tube 2111 and the second gate tube 2112, the operation independence of different operations on the storage unit 21 can be guaranteed.

[0041] According to an embodiment of the present invention, the threshold voltage of the first gate tube 2111 is set to V1th, and the threshold voltage of the second gate tube 2112 is set to V2th, and V1th and V2th satisfy the relationship: V1th<V2th. Specifically, in an embodiment of the present invention, the threshold voltage of the first gate tube 2111 is set to be lower than the threshold voltage of the second gate tube 2112, so that the gate 211 of the storage unit 21 can have different threshold voltages. When the voltage on the storage unit 21 is lower than the threshold voltage of the first gate tube 2111, the first gate tube 2111 and the second gate tube 2112 are both kept in the closed state. When the voltage on the storage unit 21 is between the threshold voltage of the first gate tube 2111 and the threshold voltage of the second gate tube 2112, the open state of the memory 213 is that the first gate tube 2111 is in the open state and the second gate tube 2112 is in the closed state. When the voltage on the storage unit 21 exceeds the threshold voltage of the second gate tube 2112, the memory 213 is turned on when both the first gate tube 2111 and the second gate tube 2112 are turned on. In this way, the memory 213 of the storage unit 21 can have different turn-on states under different threshold voltage conditions.

[0042] According to an embodiment of the present invention, V1th and V2th satisfy the relationship: 0.2V≤V2th-V1th≤1V.

[0043] According to some embodiments of the present invention, the difference between the threshold voltage of the second gate tube 2112 and the threshold voltage of the first gate tube 2111 is set to be not less than the first parameter value. If the difference between the threshold voltage of the second gate tube 2112 and the threshold voltage of the first gate tube 2111 is less than the first parameter value, after the first gate tube 2111 is turned on, the second gate tube 2112 may be turned on by mistake, which may cause the memory 213 to malfunction. In order to ensure the operational reliability of the storage unit 21, it is necessary to set the difference between the threshold voltage of the second gate tube 2112 and the threshold voltage of the first gate tube 2111 to be not less than the first parameter value, wherein the first parameter value includes but is not limited to 0.2V, 0.3V and 0.4V.

[0044] According to some other embodiments of the present invention, the difference between the threshold voltage of the second gate tube 2112 and the threshold voltage of the first gate tube 2111 is set not to exceed the second parameter value. If the difference between the threshold voltage of the second gate tube 2112 and the threshold voltage of the first gate tube 2111 exceeds the second parameter value, the difference between the threshold voltage of the second gate tube 2112 and the threshold voltage of the first gate tube 2111 is too large, and the threshold voltage of the second gate tube 2112 is also too large, which will cause the current in the second gate tube 2112 to be too large, and the power consumption of the second gate tube 2112 will increase. In order to reduce the power consumption of the second gate tube 2112, it is necessary to set the difference between the threshold voltage of the second gate tube 2112 and the threshold voltage of the first gate tube 2111 not to exceed the second parameter value, wherein the second parameter value includes but is not limited to 0.8V, 0.9V and 1.0V.

[0045] Preferably, in the embodiment of the present invention, the difference between the threshold voltage of the second gate tube 2112 and the threshold voltage of the first gate tube 2111 is set to 0.7V.

[0046] According to the embodiment of the present invention, V1th and V2th satisfy the relationship: 0.2V≤V1th≤1.0V, 0.6V≤V2th≤1.8V. Specifically, because in the embodiment of the present invention, the first gate tube 2111 and the second gate tube 2112 are respectively responsible for opening different operation steps of the storage unit 21, the threshold voltage of the first gate tube 2111 is set to be different from the threshold voltage of the second gate tube 2112.

[0047] In the embodiment of the present invention, the threshold voltage of the first gate transistor 2111 is set between 0.2V and 1.0V.

[0048] According to some embodiments of the present invention, the threshold voltage of the first gate tube 2111 is set to be not less than the third parameter value. If the threshold voltage of the first gate tube 2111 is less than the third parameter value, the threshold voltage of the first gate tube 2111 is too small, which may easily cause the first gate tube 2111 to be short-circuited. To prevent the first gate tube 2111 from being short-circuited, the threshold voltage of the first gate tube 2111 needs to be set to be not less than the third parameter value, wherein the third parameter value includes but is not limited to 0.15V, 0.2V and 0.25V.

[0049] According to other embodiments of the present invention, the threshold voltage of the first gate tube 2111 is set not to exceed the fourth parameter value. If the threshold voltage of the first gate tube 2111 exceeds the fourth parameter value, the difference between the threshold voltage of the second gate tube 2112 and the threshold voltage of the first gate tube 2111 will be too small, and the memory 213 may be written by mistake. In order to ensure the operational reliability of the storage unit 21, it is necessary to set the threshold voltage of the first gate tube 2111 not to exceed the fourth parameter value, wherein the fourth parameter value includes but is not limited to 0.9V, 0.95V and 1.0V.

[0050] In the embodiment of the present invention, the threshold voltage of the second gate transistor 2112 is set between 0.6V and 1.8V.

[0051] According to some embodiments of the present invention, the threshold voltage of the second gate tube 2112 is set to be not less than the fifth parameter value. If the threshold voltage of the second gate tube 2112 is less than the fifth parameter value, the difference between the threshold voltage of the second gate tube 2112 and the threshold voltage of the second gate tube 2112 will be too small, and the memory 213 may be written by mistake. In order to ensure the operational reliability of the storage unit 21, it is necessary to set the threshold voltage of the second gate tube 2112 to be not less than the fifth parameter value, wherein the fifth parameter value includes but is not limited to 0.5V, 0.6V and 0.7V.

[0052] According to other embodiments of the present invention, the threshold voltage of the second gate tube 2112 is set not to exceed the sixth parameter value. If the threshold voltage of the second gate tube 2112 exceeds the sixth parameter value, the current in the second gate tube 2112 will be too large, which will increase the power consumption of the second gate tube 2112. In order to reduce the power consumption of the second gate tube 2112, it is necessary to set the threshold voltage of the second gate tube 2112 not to exceed the sixth parameter value, wherein the sixth parameter value includes but is not limited to 1.7V, 1.8V and 1.9V.

[0053] Preferably, the threshold voltage of the first gate tube 2111 in the embodiment of the present invention can be 0.3V, and the threshold voltage of the second gate tube 2112 in the embodiment of the present invention can be between 1.0V and 1.1V. In this way, the difference between the threshold voltage of the second gate tube 2112 and the threshold voltage of the first gate tube 2111 can be set to 0.7V.

[0054] According to some embodiments of the present invention, Figure 2 As shown, the first gate tube 2111 and the second gate tube 2112 are arranged in series. Specifically, when ensuring that the first ends of the first gate tube 2111 and the second gate tube 2112 are both connected to the bit line driving circuit 11, and the second ends of the first gate tube 2111 and the second gate tube 2112 are both connected to the word line driving circuit 12, the first gate tube 2111 and the second gate tube 2112 can be arranged in series, so that not only can the first ends of the first gate tube 2111 and the second gate tube 2112 be equal to the voltage of the bit line driving circuit 11, but also the second ends of the first gate tube 2111 and the second gate tube 2112 can be equal to the voltage of the word line driving circuit 12.

[0055] With such arrangement, when voltages are applied to the bit line driving circuit 11 and the word line driving circuit 12 respectively, the voltage difference between the first end and the second end of the first selection tube 2111 is equal to the voltage difference between the bit line driving circuit 11 and the word line driving circuit 12, and the voltage difference between the first end and the second end of the second selection tube 2112 is equal to the voltage difference between the bit line driving circuit 11 and the word line driving circuit 12. By changing the voltages of the bit line driving circuit 11 and the word line driving circuit 12, the first selection tube 2111 and the second selection tube 2112 can be selectively turned on, and thus the storage unit 21 can be selectively controlled to perform different operations.

[0056] According to other embodiments of the present invention, Figure 3 As shown, the first gate tube 2111 and the second gate tube 2112 are arranged in parallel. Specifically, when ensuring that the first ends of the first gate tube 2111 and the second gate tube 2112 are both connected to the bit line driving circuit 11, and the second ends of the first gate tube 2111 and the second gate tube 2112 are both connected to the word line driving circuit 12, the first gate tube 2111 and the second gate tube 2112 can be arranged in parallel, so that not only the first ends of the first gate tube 2111 and the second gate tube 2112 can be ensured to have the same voltage as the bit line driving circuit 11, but also the second ends of the first gate tube 2111 and the second gate tube 2112 can be ensured to have the same voltage as the word line driving circuit 12.

[0057] With such configuration, when voltages are applied to the bit line driving circuit 11 and the word line driving circuit 12, voltages can be applied to the first end and the second end of the first selection transistor 2111, and voltages can be applied to the first end and the second end of the second selection transistor 2112. By changing the voltages of the bit line driving circuit 11 and the word line driving circuit 12, the first selection transistor 2111 and the second selection transistor 2112 can be selectively turned on, and the storage unit 21 can be selectively controlled to perform different operations.

[0058] According to some embodiments of the present invention, Figure 1 As shown, the first end of the first gate tube 2111 and the first end of the second gate tube 2112 are electrically connected to two bit lines respectively. Specifically, in the embodiment of the present invention, the second ends of the first gate tube 2111 and the second gate tube 2112 are both connected to the same word line, wherein the word line is suitable for being electrically connected to the word line driving circuit 12, that is, the word line connected to the second ends of the first gate tube 2111 and the second gate tube 2112 is equal in voltage to the word line driving circuit 12. The first end of the first gate tube 2111 and the first end of the second gate tube 2112 are electrically connected to two bit lines respectively, wherein the bit line is suitable for being electrically connected to the bit line driving circuit 11, that is, the bit line connected to the first end of the first gate tube 2111 and the bit line connected to the first end of the second gate tube 2112 are equal in voltage to the bit line driving circuit 11.

[0059] In this embodiment, the first selection tube 2111 and the second selection tube 2112 are set to a Y-type circuit structure, and the two bit lines can be selectively opened and closed. When the bit line is opened, the circuit segment where the bit line is located is in an open state. Conversely, when the bit line is closed, the circuit segment where the bit line is located is in a connected state.

[0060] Furthermore, under this structure, the circuit where the first selection tube 2111 is located and the circuit where the second selection tube 2112 is located can be selectively turned on, so that when one of the first selection tube 2111 and the second selection tube 2112 is selected to be turned on, the other can be consistent with the voltage of the turned-on selection tube 211, or can be selected to be in an open circuit state.

[0061] According to some embodiments of the present invention, the voltage on the bit line driving circuit 11 connected to the first end of the first gate tube 2111 and the voltage on the bit line driving circuit 11 connected to the first end of the second gate tube 2112 may be the same.

[0062] In some embodiments of the present invention, the voltages on the two bit lines respectively connected to the first end of the first gate tube 2111 and the first end of the second gate tube 2112 can be set to be the same, and the voltage difference between the bit line driving circuit 11 and the word line driving circuit 12 is set to be at least the threshold voltage of the first gate tube 2111 and not more than the threshold voltage of the second gate tube 2112, so that the first gate tube 2111 can be turned on, the voltage on the second gate tube 2112 is consistent with the voltage of the first gate tube 2111, and the second gate tube 2112 is still in a closed state, so that it can be ensured that the storage unit 21 only performs the operation controlled by the first gate tube 2111, and no erroneous operation occurs.

[0063] Further, the voltages on the two bit lines respectively connected to the first end of the first gate tube 2111 and the first end of the second gate tube 2112 can be set to be the same, and the voltage difference between the bit line driving circuit 11 and the word line driving circuit 12 is set to be at least the threshold voltage of the second gate tube 2112, at which time the first gate tube 2111 and the second gate tube 2112 are both turned on. Normally, the first gate tube 2111 of the storage unit 21 controls the memory 213 to perform a read operation, and the second gate tube 2112 controls the memory 213 to perform a write operation. When the first gate tube 2111 and the second gate tube 2112 are both in the turned-on state, the read operation of the storage unit 21 will not affect its write operation, so when the voltages on the two bit lines are the same, the operation of the storage unit 21 is still reliable.

[0064] According to some other embodiments of the present invention, the voltage on the bit line driving circuit 11 connected to the first end of the first gate tube 2111 and the voltage on the bit line driving circuit 11 connected to the first end of the second gate tube 2112 may be different.

[0065] In some other embodiments of the present invention, if one of the two bit lines respectively connected to the first end of the first selection tube 2111 and the first end of the second selection tube 2112 has a voltage and the other is open, then one of the first selection tube 2111 and the second selection tube 2112 can be turned on and the other can be turned off, so that it can be ensured that there is no interference between the operation of the memory 213 controlled by the first selection tube 2111 and the operation of the memory 213 controlled by the second selection tube 2112, so that the operational reliability of the storage unit 21 can be guaranteed.

[0066] Furthermore, one of the two bit lines respectively connected to the first end of the first selection tube 2111 and the first end of the second selection tube 2112 is provided with voltage, and the other is open circuit, so that when one of the first selection tube 2111 and the second selection tube 2112 is turned on, no current flows through the circuit where the other one is located, which can not only reduce the power consumption of the storage unit 21, but also help to increase the service life of the selection device 211.

[0067] According to other embodiments of the present invention, the first end of the first gate tube 2111 and the first end of the second gate tube 2112 are both electrically connected to the same bit line. Specifically, in the embodiment of the present invention, the second ends of the first gate tube 2111 and the second gate tube 2112 are both connected to the same word line, wherein the word line is suitable for being electrically connected to the word line driving circuit 12, that is, the word line connected to the second ends of the first gate tube 2111 and the second gate tube 2112 has the same voltage as the word line driving circuit 12. The first end of the first gate tube 2111 and the first end of the second gate tube 2112 are electrically connected to the same bit line, wherein the bit line is suitable for being electrically connected to the bit line driving circuit 11, that is, the bit line connected to the first end of the first gate tube 2111 and the first end of the second gate tube 2112 has the same voltage as the bit line driving circuit 11.

[0068] In this embodiment, the first selection tube 2111 and the second selection tube 2112 are set to a Y-type circuit structure. When the first end of the first selection tube 2111 and the first end of the second selection tube 2112 are electrically connected to the same bit line, the Y-type circuit structure is equivalent to a circuit structure in which the first selection tube 2111 and the second selection tube 2112 are connected in parallel.

[0069] In an embodiment of the present invention, if the voltage difference between the bit line driving circuit 11 and the word line driving circuit 12 is set to be at least the threshold voltage of the first selection tube 2111 and not more than the threshold voltage of the second selection tube 2112, then the first selection tube 2111 is turned on and the second selection tube 2112 is turned off, and the second selection tube 2112 can be used as a resistor in a parallel circuit, which is beneficial to reduce the current in the storage unit 21, thereby helping to reduce the current in the circuit, so as to reduce the power consumption of the storage unit 21.

[0070] Further, if the voltage difference between the bit line driving circuit 11 and the word line driving circuit 12 is set to be at least the threshold voltage of the second gate tube 2112, the first gate tube 2111 and the second gate tube 2112 are both turned on. Normally, the first gate tube 2111 of the storage unit 21 controls the memory 213 to perform a read operation, and the second gate tube 2112 controls the memory 213 to perform a write operation. When the first gate tube 2111 and the second gate tube 2112 are both in the turned-on state, the read operation of the storage unit 21 will not affect its write operation, so when the voltages on the two bit lines are the same, the operation of the storage unit 21 is still reliable.

[0071] In an embodiment of the present invention, since the operations performed by the second gate tube 2112 to control the memory 213 are less used than the operations performed by the first gate tube 2111 to control the memory 213, the second gate tube 2112 can be protected, which is beneficial to extending the service life of the second gate tube 2112.

[0072] According to some embodiments of the present invention, the first gate tube 2111 includes but is not limited to any one of a bidirectional threshold switch, a diode, and a metal-insulator-metal structure converter. Specifically, the bidirectional threshold switch can determine whether to turn on or off according to the level of the input signal, and it has two different thresholds. The use of the bidirectional threshold switch in the present invention can accurately control the opening and closing of the first gate tube 2111, thereby facilitating the improvement of the reliability of the operation of the first gate tube 2111 controlling the memory 213. Furthermore, the diode has unidirectional conductivity and can be used as a switch. In addition, some metal-insulator-metal structure converters can also be used as switches.

[0073] According to some other embodiments of the present invention, the second gate tube 2112 includes but is not limited to any one of a bidirectional threshold switch, a diode, and a metal-insulator-metal structure converter. Specifically, the bidirectional threshold switch can determine whether to turn on or off according to the level of the input signal, and it has two different thresholds. The use of a bidirectional threshold switch in the present invention can accurately control the opening and closing of the second gate tube 2112, thereby facilitating the improvement of the reliability of the operation of the second gate tube 2112 controlling the memory 213. Furthermore, the diode has unidirectional conductivity and can be used as a switch. In addition, some metal-insulator-metal structure converters can also be used as switches.

[0074] According to some embodiments of the present invention, the structure of the first gate tube 2111 includes an upper electrode layer, a switching layer and a lower electrode layer, wherein the switching layer material of the first gate tube 2111 includes at least one of niobium oxide, vanadium oxide and hafnium oxide.

[0075] According to some other embodiments of the present invention, the structure of the second gate tube 2112 includes an upper electrode layer, a switching layer and a lower electrode layer, wherein the switching layer material of the second gate tube 2112 includes at least one of niobium oxide, vanadium oxide and hafnium oxide.

[0076] According to some further embodiments of the present invention, the structure of the first gate tube 2111 includes an upper electrode layer, a switching layer and a lower electrode layer, and the structure of the second gate tube 2112 includes an upper electrode layer, a switching layer and a lower electrode layer, wherein the switching layer material of the first gate tube 2111 includes at least one of niobium oxide, vanadium oxide and hafnium oxide, and the switching layer material of the second gate tube 2112 includes at least one of niobium oxide, vanadium oxide and hafnium oxide.

[0077] Specifically, niobium oxide, vanadium oxide, and hafnium oxide are excellent switching layer materials with advantages such as high on-off ratio, fast switching speed, good durability, low power consumption, easy integration, stable physical and chemical properties, and versatility.

[0078] According to some embodiments of the present invention, when the switching layer material of the first gate tube 2111 includes hafnium oxide, the upper electrode layer or the lower electrode layer of the first gate tube 2111 includes at least silver. According to other embodiments of the present invention, when the switching layer material of the second gate tube 2112 includes hafnium oxide, the upper electrode layer or the lower electrode layer of the second gate tube 2112 includes at least silver. According to still other embodiments of the present invention, when the switching layer materials of the first gate tube 2111 and the second gate tube 2112 both include hafnium oxide, the upper electrode layer or the lower electrode layer of the first gate tube 2111 and the second gate tube 2112 both include at least silver.

[0079] Specifically, hafnium oxide is used as the switching layer material, and the upper and lower electrode layers are both made of silver. This configuration has several significant advantages in memristors and other non-volatile memory 213 devices, including high conductivity, good thermal stability, chemical stability, low interface trap density, easy processing, high on-off ratio and low power consumption, reliable repeatability, and suitability for a variety of applications.

[0080] It should be noted that the constituent materials of the first gate tube 2111 and the constituent materials of the second gate tube 2112 may be the same or different.

[0081] According to other embodiments of the present invention, Figure 5 As shown, the gate 211 includes a first electrode 2113, a second electrode 2114 and at least two gate layers 2115 with different threshold voltages, and the at least two gate layers 2115 with different threshold voltages are arranged between the first electrode 2113 and the second electrode 2114. Specifically, in the embodiment of the present invention, the gate 211 may include at least two gate layers 2115, and the threshold voltages of the at least two gate layers 2115 are different, so that the at least two gate layers 2115 in the gate 211 can be selectively turned on at different threshold voltages, so that the at least two gate layers 2115 respectively control the memory 213 to perform different operations. Among them, the memory 213 in this embodiment can be subjected to read operations and write operations, and the read operations and the write operations are respectively controlled by different gate layers 2115.

[0082] Furthermore, at least two selection layers 2115 in the selector 211 are arranged on the first electrode 2113 and the second electrode 2114, and one of the first electrode 2113 and the second electrode 2114 is suitable for being electrically connected to the bit line driving circuit 11, and the other is suitable for being connected to the second end of the memory 213. With such a configuration, at least two selection layers 2115 can be connected between the bit line driving circuit 11 and the word line driving circuit 12, so that when a voltage is applied to the bit line driving circuit 11 and the word line driving circuit 12 connected to the two ends of the memory cell 21, a current can pass through the selection layer 2115, and then the selection layer 2115 can be selectively turned on and off when the memory cell 21 is powered on, so as to control the memory 213 of the memory cell 21 to perform different operations.

[0083] According to an embodiment of the present invention, the memory 213 includes at least one of a resistive memory, a phase change memory, a magnetic random access memory and a ferroelectric memory. That is to say, the storage unit 21 in the embodiment of the present invention is suitable for matching any one of the resistive memory, the phase change memory, the magnetic random access memory and the ferroelectric memory. The first gate tube 2111 and the second gate tube 2112 are respectively responsible for reading and writing operations. In this way, after setting the threshold voltages of the first gate tube 2111 and the second gate tube 2112 to be different, any one of the resistive memory, the phase change memory, the magnetic random access memory and the ferroelectric memory can perform different operations, thereby improving the operational reliability of any one of the resistive memory, the phase change memory, the magnetic random access memory and the ferroelectric memory.

[0084] According to an embodiment of the present invention, the storage unit 21 is configured with an operation method of the storage unit 21. The operation method of the storage unit 21 comprises the following steps: The voltage difference between the word line driving circuit 12 and the bit line driving circuit 11 respectively connected to the two ends of the storage unit 21 is set to Vsel, and Vsel is set to satisfy the relationship: V1th≤Vsel, so as to control the gate 211 of the storage unit 21 to enter the first turn-on state, and perform a read operation on the memory 213 of the storage unit 21; wherein the threshold voltage of the first turn-on state of the gate 211 is V1th.

[0085] Specifically, the voltage difference between the word line driving circuit 12 and the bit line driving circuit 11 respectively connected to the two ends of the storage unit 21 is set to be at least V1th, so that the gate 211 of the storage unit 21 can enter the first open state. When the gate 211 of the storage unit 21 enters the first open state, a read operation can be performed on the memory 213 of the storage unit 21, and V1th is the threshold voltage when the gate 211 enters the first open state.

[0086] Furthermore, the gate 211 includes at least a first gate tube 2111 and a second gate tube 2112, and Vsel is set to satisfy the relationship: V1th≤Vsel<V2th, the first gate tube 2111 of the storage unit 21 is controlled to be turned on, and the second gate tube 2112 of the storage unit 21 is controlled to be turned off, and a read operation is performed on the memory 213 of the storage unit 21; wherein the threshold voltage of the first gate tube 2111 of the storage unit 21 is V1th, and the threshold voltage of the second gate tube 2112 of the storage unit 21 is V2th.

[0087] Specifically, in the embodiment of the present invention, the gate 211 of the storage unit 21 at least includes a first gate tube 2111 and a second gate tube 2112, wherein the first gate tube 2111 performs a read operation on the memory 213 of the storage unit 21, and the second gate tube 2112 performs a write operation on the memory 213 of the storage unit 21. When the voltage difference between the word line driving circuit 12 and the bit line driving circuit 11 respectively connected to the two ends of the storage unit 21 is set to be at least the threshold voltage of the first gate tube 2111 and does not exceed the threshold voltage of the second gate tube 2112, the first gate tube 2111 is in an on state, and the second gate tube 2112 remains in an off state, so that the first gate tube 2111 controls the memory 213 of the storage unit 21 to perform a read operation, but does not perform a write operation.

[0088] In the embodiment of the present invention, the operation method of the storage unit 21 can not only ensure the reliability of the storage unit 21 in performing the read operation, but also ensure that the second selection tube 2112 will not be mistakenly turned on, which can reduce the power consumption of the storage unit 21 and is conducive to extending the service life of the second selection tube 2112.

[0089] According to an embodiment of the present invention, the storage unit 21 is configured with an operation method of the storage unit 21. The operation method of the storage unit 21 comprises the following steps: The voltage difference between the word line driving circuit 12 and the bit line driving circuit 11 respectively connected to the two ends of the storage unit 21 is set to Vsel, and Vsel is set to satisfy the relationship: V2th≤Vsel, so as to control the gate 211 of the storage unit 21 to enter the second turn-on state, and perform a write operation on the memory 213 of the storage unit 21; wherein the threshold voltage of the second turn-on state of the gate 211 is V2th.

[0090] Specifically, the voltage difference between the word line driving circuit 12 and the bit line driving circuit 11 respectively connected to the two ends of the memory cell 21 is set to be at least V2th, so that the gate 211 of the memory cell 21 can enter the second open state. When the gate 211 of the memory cell 21 enters the second open state, the memory cell 21 can perform a write operation, wherein V2th is a threshold voltage when the gate 211 enters the second open state.

[0091] Furthermore, the gate 211 includes at least a first gate tube 2111 and a second gate tube 2112, and Vsel is set to satisfy the relationship: V1th≤Vsel and V2th≤Vsel, so that the first gate tube 2111 and the second gate tube 2112 of the storage unit 21 can be controlled to be turned on to perform a write operation on the memory 213 of the storage unit 21; wherein the threshold voltage of the first gate tube 2111 of the storage unit 21 is V1th, the threshold voltage of the second gate tube 2112 of the storage unit 21 is V2th, and V1th<V2th.

[0092] Specifically, in the embodiment of the present invention, the gate 211 of the storage unit 21 includes at least a first gate tube 2111 and a second gate tube 2112, wherein the first gate tube 2111 controls the memory 213 of the storage unit 21 to perform a read operation, and the second gate tube 2112 controls the memory 213 of the storage unit 21 to perform a write operation. When the voltage difference between the word line driving circuit 12 and the bit line driving circuit 11 respectively connected to the two ends of the storage unit 21 is set to be at least the threshold voltage of the second gate tube 2112, at this time, the first gate tube 2111 and the second gate tube 2112 are both in the open state, so that the second gate tube 2112 can control the memory 213 of the storage unit 21 to perform a write operation. In this process, the opening of the first gate tube 2111 will not affect the write operation of the storage unit 21.

[0093] According to an embodiment of the present invention, the step of performing a write operation on the memory 213 of the storage unit 21 further includes: When a write 1 operation is performed on the memory 213, Vsel satisfies the relationship: Vsel=Vset, where the threshold voltage of the memory 213 for performing a write 1 is Vset; When a write-0 operation is performed on the memory 213 , Vsel satisfies the relationship: Vsel=Vreset, wherein the threshold voltage of the memory 213 for performing a write-0 operation is Vreset.

[0094] Specifically, in an embodiment of the present invention, the memory 213 of the storage unit 21 performs a write operation including performing a write 1 operation and performing a write 0 operation. The threshold voltage when the memory 213 performs a write 1 operation is different from the threshold voltage when the memory 213 performs a write 0 operation. Therefore, when different write operations are performed on the memory 213, different voltages need to be applied to both ends of the storage unit 21.

[0095] When the memory 213 performs writing 1, it is necessary to set the voltage difference between the word line driving circuit 12 and the bit line driving circuit 11 respectively connected to the two ends of the storage unit 21 as the threshold voltage for the memory 213 of the storage unit 21 to perform writing 1, wherein the threshold voltage for the memory 213 of the storage unit 21 to perform writing 1 operation is Vset. When the memory 213 performs writing 0, it is necessary to set the voltage difference between the word line driving circuit 12 and the bit line driving circuit 11 respectively connected to the two ends of the storage unit 21 as the threshold voltage for the memory 213 of the storage unit 21 to perform writing 0, wherein the threshold voltage for the memory 213 of the storage unit 21 to perform writing 0 operation is Vreset.

[0096] According to an embodiment of the present invention, the storage device 100 includes a front-end driving circuit 10 and a storage array 20, wherein the front-end driving circuit 10 includes a bit line driving circuit 11 and a word line driving circuit 12, and the word line driving circuit 12 and the bit line driving circuit 11 can be used to connect voltage to apply voltage to both ends of the storage device 100.

[0097] Furthermore, the memory array 20 includes a plurality of memory cells 21, a first end of a memory 213 of the memory cell 21 is connected to a word line driving circuit 12, a first end of a selector 211 of the memory cell 21 is electrically connected to a bit line driving circuit 11, and a second end of the selector 211 of the memory cell 21 is suitable for being electrically connected to a second end of the memory 213 of the memory cell 21.

[0098] Specifically, among the multiple memory cells 21 in the memory array 20, the first end of the memory 213 of each memory cell 21 is at the same voltage as the word line driving circuit 12, the first end of the selector 211 of each memory cell 21 is at the same voltage as the bit line driving circuit 11, and the second end of the selector 211 in each memory cell 21 is electrically connected to the second end of the memory 213. In this way, the memory 213 and the selector 211 of the multiple memory cells 21 in the memory array 20 can be connected between the word line driving circuit 12 and the bit line driving circuit 11, so that when voltage is applied to the word line driving circuit 12 and the bit line driving circuit 11 connected to the two ends of the memory device 100, the circuit connectivity of the multiple memory cells 21 in the memory device 100 can be guaranteed.

[0099] According to an embodiment of the present invention, the storage device 100 is provided with an operating method of the storage device 100. The operating method of the storage device 100 comprises the following steps: The threshold voltage of the on state of the gate 211 of the memory cell 21 is V1th, the voltage difference between the word line driving circuit 12 and the bit line driving circuit 11 respectively connected to the two ends of the target memory cell 21 in the memory device 100 is set to Vsel, and the voltage difference between the word line driving circuit 12 and the bit line driving circuit 11 respectively connected to the two ends of the non-target memory cell 21 in the memory device 100 is set to Vunsel; Vsel is set to satisfy the relationship: V1th≤Vsel, the gate 211 of the target storage unit 21 is controlled to be turned on, and a read operation or a write operation is performed on the memory 213 of the target storage unit 21; Vunsel is set to satisfy the relationship: Vunsel<V1th, and the gate 211 of the non-target memory cell 21 is controlled to be closed.

[0100] Specifically, there are multiple storage cells 21 in the storage array 20, wherein the target storage cell 21 is a cell to be operated in the storage array 20, that is, a storage cell 21 on which a read or write operation is to be performed, and the non-target storage cell 21 is a cell on which no operation is to be performed, that is, a storage cell 21 on which neither a read operation nor a write operation is to be performed.

[0101] In the embodiment of the present invention, the target storage unit 21 includes but is not limited to one or more storage units 21 in the storage array 20 at a time.

[0102] Furthermore, the voltage difference between the word line driving circuit 12 and the bit line driving circuit 11 respectively connected to the two ends of the target memory cell 21 in the memory device 100 is set to be at least the threshold voltage when the selector 211 of the memory cell 21 enters the on state, so that the target memory cell 21 in the memory device 100 can be controlled to perform a read or write operation, wherein the threshold voltage when the selector 211 of the memory cell 21 enters the on state is V1th.

[0103] Furthermore, the voltage between the word line driving circuit 12 and the bit line driving circuit 11 respectively connected to the two ends of the non-target memory cell 21 in the storage device 100 is set to be lower than the threshold voltage when the selector 211 of the memory cell 21 enters the on state, so that the non-target memory cell 21 in the storage device 100 can be controlled to remain in the off state.

[0104] With such a configuration, the target storage unit 21 in the storage device 100 can perform a read or write operation, while the non-target storage unit 21 in the storage device 100 does not perform the operation. This ensures that the storage device 100 only performs a read or write operation on the memory 213 of the target storage unit 21, thereby ensuring the accuracy and reliability of the operation performed by the storage device 100.

[0105] Further, the gate 211 includes at least a first gate tube 2111 and a second gate tube 2112, and Vsel is set to satisfy the relationship: V1th≤Vsel<V2th, the first gate tube 2111 of the target storage unit 21 is controlled to be turned on, and the second gate tube 2112 of the target storage unit 21 is controlled to be turned off, and a read operation is performed on the memory 213 of the target storage unit 21; or Vsel is set to satisfy the relationship: V2th≤Vsel, and the first gate tube 2111 and the second gate tube 2112 of the target storage unit 21 are controlled to be turned off. The second selection tube 2112 is turned on, and a write operation is performed on the memory 213 of the target storage unit 21; Vunsel is set to satisfy the relationship: Vunsel<V1th, and the first selection tube 2111 and the second selection tube 2112 of the non-target storage unit 21 are controlled to be turned off; wherein the threshold voltage of the first selection tube 2111 of the storage unit 21 is V1th, and the threshold voltage of the second selection tube 2112 of the storage unit 21 is V2th, and V1th and V2th satisfy the relationship: V1th<V2th.

[0106] Specifically, the gates 211 in the multiple storage units 21 of the storage device 100 each include at least a first gate tube 2111 and a second gate tube 2112, wherein the first gate tube 2111 controls the storage unit 21 to perform a read operation, and the second gate tube 2112 controls the storage unit 21 to perform a write operation.

[0107] When the target memory cell 21 performs a read operation, it is necessary to set the voltage difference between the word line driving circuit 12 and the bit line driving circuit 11 respectively connected to the two ends of the target memory cell 21 in the storage device 100 to be at least the threshold voltage of the first selection tube 2111 and less than the threshold voltage of the second selection tube 2112. In this way, the first selection tube 2111 in the target memory cell 21 can be controlled to be turned on, and the second selection tube 2112 in the target memory cell 21 can be controlled to be turned off, so as to control the memory 213 of the target memory cell 21 in the storage device 100 to perform a read operation.

[0108] Or the voltage difference between the word line driving circuit 12 and the bit line driving circuit 11 respectively connected to the two ends of the target memory cell 21 in the storage device 100 is set to be at least the threshold voltage of the second selection tube 2112, so that the first selection tube 2111 and the second selection tube 2112 of the target memory cell 21 can be turned on to perform a write operation on the memory 213 of the target memory cell 21.

[0109] During this process, the voltage difference between the word line driving circuit 12 and the bit line driving circuit 11 respectively connected to the two ends of the non-target memory cell 21 in the memory device 100 is set to be smaller than the threshold voltage of the first selection tube 2111, so that the first selection tube 2111 and the second selection tube 2112 of the non-target memory cell 21 in the memory device 100 can be turned off, which can prevent the memory device 100 from performing operations on the non-target memory cell 21, and ensure the operating reliability of the memory device 100.

[0110] According to an embodiment of the present invention, the step of performing a write operation on the memory 213 of the target storage unit 21 further includes: When a write 1 operation is performed on the target memory cell 21, Vsel satisfies the relationship: Vsel=Vset, wherein the threshold voltage of the target memory cell 21 for performing a write 1 operation is Vset; When a write-0 operation is performed on the target memory cell 21 , Vsel satisfies the relationship: Vsel=Vreset, wherein the threshold voltage of the target memory cell 21 for performing a write-0 operation is Vreset.

[0111] Specifically, in an embodiment of the present invention, the write operation of the target storage unit 21 includes a write 1 operation and a write 0 operation, and the threshold voltage of the memory 213 of the target storage unit 21 when performing the write 1 operation is different from the threshold voltage when performing the write 0 operation.

[0112] When a write 1 operation is performed on the memory 213 of the target memory cell 21, the voltage difference between the word line driving circuit 12 and the bit line driving circuit 11 respectively connected to the two ends of the target memory cell 21 needs to be set to the threshold voltage for the target memory cell 21 to perform write 1, that is, Vset. When a write 0 operation is performed on the memory 213 of the target memory cell 21, the voltage difference between the word line driving circuit 12 and the bit line driving circuit 11 respectively connected to the two ends of the target memory cell 21 needs to be set to the threshold voltage for the target memory cell 21 to perform write 0, that is, Vreset.

[0113] In the prior art, the storage device is mainly an array structure of a cell (storage unit) composed of a gate and a memory (1S1M). The gate has a fixed threshold voltage Vth. The threshold voltage of the write operation of the memory is set to Vwrite. Then Vth and Vwrite need to satisfy the relationship: the size of Vth needs to be greater than 1 / 3 Vwirte. For example, if the operating voltage of the memory is 3.6V, then the gate Vth needs to be set greater than 1.2V, otherwise it will cause errors in the array when selecting bits. And when Vth>1.2V, there is a large current in the gate, resulting in higher power consumption of the gate. In addition, frequent power-on exceeding 1.2V not only has an adverse effect on the life of the gate, but also at a read voltage exceeding 1.2V, the memory is at risk of erroneous write operations.

[0114] The following specifically describes the reading and writing operations performed by the storage device 100 according to the embodiment of the present invention under different connection modes of the first gate tube 2111 and the second gate tube 2112.

[0115] When the first end of the memory 213 is electrically connected to the word line driving circuit 12, and the first end of the selector 211 is electrically connected to the bit line driving circuit 11, the voltage of the word line driving circuit 12 connected to the target memory cell 21 is set to WL_sel, and the voltage of the bit line driving circuit 11 connected to the target memory cell 21 is set to BL_sel, then the difference between WL_sel and BL_sel is the voltage difference Vsel between the word line driving circuit 12 and the bit line driving circuit 11 respectively connected to the two ends of the target memory cell 21.

[0116] Correspondingly, the voltage of the word line driving circuit 12 connected to the non-target memory cell 21 is set to WL_unsel, and the voltage of the bit line driving circuit 11 connected to the non-target memory cell 21 is set to BL_unsel. The difference between WL_unsel and BL_unsel is the voltage difference Vunsel between the word line driving circuit 12 and the bit line driving circuit 11 respectively connected to the two ends of the non-target memory cell 21.

[0117] In the embodiment of the present invention, set represents a write 1 operation in a write operation, and reset represents a write 0 operation in a write operation. The write operation of the memory 213 includes a write 1 operation and a write 0 operation. It can be understood that Vset represents the threshold voltage of the memory device 100 performing a write 1 operation on the memory 213 of the memory cell 21, and Vreset represents the threshold voltage of the memory device 100 performing a write 0 operation on the memory 213 of the memory cell 21.

[0118] According to some embodiments of the present invention, when the first gate tube 2111 and the second gate tube 2112 are arranged in series, the first gate tube 2111 is responsible for controlling the read operation of the storage device 100, and the second gate tube 2112 is responsible for controlling the write operation of the storage device 100.

[0119] When the storage device 100 performs a read operation, WL_sel=0V, WL_unsel=0.25V, BL_sel=0.5V, and BL_unsel=0.25V are set, so that the voltage difference between the word line driving circuit 12 and the bit line driving circuit 11 respectively connected to the two ends of the non-target storage unit 21 is 0, and Vunsel satisfies the relationship: Vunsel<V1th. The voltage difference between the word line driving circuit 12 and the bit line driving circuit 11 respectively connected to the two ends of the target storage unit 21 is 0.5V, and Vsel satisfies the relationship: V1th≤Vsel.

[0120] At this time, the first gate tube 2111 in the target storage unit 21 is turned on, and the second gate tube 2112 remains turned off. Only the memory 213 of the target storage unit 21 in the storage device 100 performs a read operation, and the resistance state of the memory 213 in the target storage unit 21 can be read out. In the non-target storage unit 21, the first gate tube 2111 and the second gate tube 2112 are both in the turned-off state.

[0121] When the storage device 100 performs a write operation, Vset is set to satisfy the relationship: 1.5V≤Vset≤4.0V, and Vreset is set to satisfy the relationship: 1.5V≤Vreset≤3.5V.

[0122] When the storage device 100 performs a set operation, WL_sel=Vset, WL_unsel=1 / 3Vset, BL_sel=0V, BL_unsel=2 / 3Vset, so that the voltage difference between the word line driving circuit 12 and the bit line driving circuit 11 respectively connected at both ends of the non-target storage unit 21 can be guaranteed to be 1 / 3Vset, and Vunsel satisfies the relationship: V1th<Vunsel<V2th. In the target storage unit 21, the voltage difference Vset between the word line driving circuit 12 and the bit line driving circuit 11 respectively connected at both ends thereof, that is, Vsel satisfies the relationship: V2th≤Vsel.

[0123] In this way, when the storage device 100 executes write 1, the first selection tube 2111 and the second selection tube 2112 in the target storage unit 21 are both turned on, and at the same time, the voltage difference between the word line driving circuit 12 and the bit line driving circuit 11 respectively connected to the two ends of the target storage unit 21 is Vset, so the memory 213 of the target storage unit 21 executes the write 1 operation.

[0124] In the non-target storage unit 21, only the first gate tube 2111 is turned on, and the second gate tube 2112 remains turned off. In this way, the voltage division of the second gate tube 2112 in the non-target storage unit 21 is relatively large, and the voltage division on the memory 213 in the non-target storage unit 21 is relatively small, so that the memory 213 in the non-target storage unit 21 will not perform the write 1 operation, and the reliability of the storage device 100 performing the write 1 operation on the target storage unit 21 can be guaranteed.

[0125] Similarly, when the memory device 100 performs a write-0 operation, WL_sel=0, WL_unsel=2 / 3Vset, BL_sel=Vreset, and BL_unsel=1 / 3Vset are set, so that the voltage difference between the word line driving circuit 12 and the bit line driving circuit 11 respectively connected to the two ends of the non-target memory cell 21 can be ensured to be 1 / 3Vset, and Vunsel satisfies the relationship: V1th<Vunsel<V2th. In the target memory cell 21, the voltage difference between the word line driving circuit 12 and the bit line driving circuit 11 respectively connected to the two ends thereof is Vreset, and Vsel satisfies the relationship: V2th≤Vsel.

[0126] In this way, when the storage device 100 performs a write-0 operation, the first selection tube 2111 and the second selection tube 2112 in the target storage unit 21 are both turned on, and at the same time, the voltage difference between the word line driving circuit 12 and the bit line driving circuit 11 respectively connected to the two ends of the target storage unit 21 is Vreset, so that the memory 213 of the target storage unit 21 can perform a write-0 operation.

[0127] In the non-target storage unit 21, only the first gate tube 2111 is turned on, and the second gate tube 2112 remains turned off. In this way, the voltage division of the second gate tube 2112 in the non-target storage unit 21 is relatively large, while the voltage division on the memory 213 in the non-target storage unit 21 is relatively small, thereby ensuring that the memory 213 in the non-target storage unit 21 will not perform a write-0 operation, and ensuring the reliability of the storage device 100 performing a write-0 operation on the target storage unit 21.

[0128] According to other embodiments of the present invention, when the first gate tube 2111 and the second gate tube 2112 are arranged in parallel, the first gate tube 2111 is responsible for the read operation of the storage device 100 , and the second gate tube 2112 is responsible for the write operation of the storage device 100 .

[0129] When the storage device 100 performs a read operation, WL_sel=0V, WL_unsel=0.25V, BL_sel=0.5V, and BL_unsel=0.25V are set, so that the voltage difference between the word line driving circuit 12 and the bit line driving circuit 11 respectively connected to the two ends of the non-target storage unit 21 is 0, and Vunsel satisfies the relationship: Vunsel<V1th. The voltage difference between the word line driving circuit 12 and the bit line driving circuit 11 respectively connected to the two ends of the target storage unit 21 is 0.5V, and Vsel satisfies the relationship: V1th≤Vsel.

[0130] At this time, in the target storage unit 21, the first selection tube 2111 is turned on and the second selection tube 2112 remains turned off. The storage device 100 only performs a read operation on the memory 213 of the target storage unit 21, and the resistance state of the memory 213 in the target storage unit 21 can be read out. In the non-target storage unit 21, the first selection tube 2111 and the second selection tube 2112 are both in the turned-off state.

[0131] When the storage device 100 performs a write operation, Vset is set to satisfy the relationship: 1.5V≤Vset≤4.0V, and Vreset is set to satisfy the relationship: 1.5V≤Vreset≤3.5V.

[0132] When the storage device 100 performs a write 1 operation, WL_sel=Vset, WL_unsel=1 / 3Vset, BL_sel=0V, BL_unsel=2 / 3Vset are set, so that the voltage difference between the word line driving circuit 12 and the bit line driving circuit 11 respectively connected to the two ends of the non-target storage unit 21 can be guaranteed to be 1 / 3Vset, and Vunsel satisfies the relationship: V1th<Vunsel<V2th. It can be guaranteed that the voltage difference between the word line driving circuit 12 and the bit line driving circuit 11 respectively connected to the two ends of the target storage unit 21 is Vset, and Vsel satisfies the relationship: V2th≤Vsel.

[0133] In this way, when the storage device 100 performs a write 1 operation, the first select tube 2111 and the second select tube 2112 in the target storage unit 21 are both turned on, and at the same time, the voltage difference between the word line driving circuit 12 and the bit line driving circuit 11 respectively connected to the two ends of the target storage unit 21 is the threshold voltage Vset for the storage unit 21 to perform a write 1, and the memory 213 of the target storage unit 21 performs a write 1 operation, while in the non-target storage unit 21, only the first select tube 2111 is turned on, and the second select tube 2112 is not turned on.

[0134] In this way, in the non-target storage unit 21, the branch where the first selection tube 2111 is located will short-circuit the second selection tube 2112, thereby losing the function of the selection tube 211. This method will cause the current in the non-target storage unit 21 to be larger, but there is still a 1 / 3 bias method for the write 1 operation of the non-target memory 213. There is only 1 / 3Vset on the memory 213 in the non-target storage unit 21, so the memory 213 in the non-target storage unit 21 will not be misoperated, and this method can work normally.

[0135] Similarly, when the memory device 100 performs a reset operation, WL_sel=0, WL_unsel=2 / 3Vset, BL_sel=Vreset, BL_unsel=1 / 3Vset, so that the voltage difference between the word line driving circuit 12 and the bit line driving circuit 11 respectively connected to the two ends of the non-target memory cell 21 can be ensured to be 1 / 3Vset, and Vunsel satisfies the relationship: V1th<Vunsel<V2th. It can be ensured that the voltage difference between the word line driving circuit 12 and the bit line driving circuit 11 respectively connected to the two ends of the target memory cell 21 is Vreset, and Vsel satisfies the relationship: V2th≤Vsel.

[0136] Therefore, when the storage device 100 performs a write-0 operation, the first selection tube 2111 and the second selection tube 2112 in the target storage unit 21 are both turned on, and at the same time, the voltage difference between the word line driving circuit 12 and the bit line driving circuit 11 respectively connected to the two ends of the target storage unit 21 is the threshold voltage Vreset for the storage unit 21 to perform write-0, so that the memory 213 of the target storage unit 21 can perform write-0, and only the first selection tube 2111 in the non-target storage unit 21 is turned on, and the second selection tube 2112 is not turned on.

[0137] In this way, in the non-target storage unit 21, the first selection tube 2111 can short-circuit the second selection tube 2112, thereby losing the function of the selection tube 211. This method will cause a larger current in the non-target storage unit 21, but there is still a 1 / 3 bias method for executing the write 0 operation of the memory 213. There is only 1 / 3Vset on the memory 213 in the non-target storage unit 21, so the memory 213 in the non-target storage unit 21 will not be misoperated, and this method can work normally.

[0138] According to some further embodiments of the present invention, when the first selection tube 2111 and the second selection tube 2112 are set in a Y-shaped structure that can be selectively connected, the first selection tube 2111 is responsible for the read operation of the storage device 100, and the second selection tube 2112 is responsible for the write operation of the storage device 100, and the first bit line is set to be connected to the first end of the first selection tube 2111, and the second bit line is set to be connected to the first end of the second selection tube 2112.

[0139] In an embodiment of the present invention, the voltage of the driving circuit of the first bit line connected to the first selection tube 2111 of the target memory cell 21 is set to BL1_sel, the voltage of the driving circuit of the first bit line connected to the first selection tube 2111 of the non-target memory cell 21 is set to BL1_unsel, the voltage of the driving circuit of the second bit line connected to the second selection tube 2112 of the target memory cell 21 is set to BL2_sel, and the voltage of the driving circuit of the second bit line connected to the second selection tube 2112 of the non-target memory cell 21 is set to BL2_unsel.

[0140] When the storage device 100 performs a read operation, WL_sel=0V, WL_unsel=0.25V, BL1_sel=0.5V, and BL1_unsel=0.25V. In the embodiment of the present invention, the threshold voltage of the first selection tube 2111 can be 0.3V, and the voltage difference between the two ends of the word line driving circuit 12 and the bit line driving circuit 11 respectively connected to the two ends of the target storage unit 21 is 0.5V, so that Vsel can satisfy the relationship: V1th<Vsel, and then the first selection tube 2111 in the target storage unit 21 can be controlled to turn on.

[0141] For the branch where the second selection tube 2112 is located, the voltage difference between the two ends of the word line driving circuit 12 and the bit line driving circuit 11 respectively connected at both ends can be selected to be the same as the voltage difference between the two ends of the word line driving circuit 12 and the bit line driving circuit 11 respectively connected at both ends of the first selection tube 2111, or the first end of the second selection tube 2112 can be set to be open. In this way, the resistance state of the memory 213 in the target storage unit 21 can be read, while in the non-target storage unit 21, the first selection tube 2111 and the second selection tube 2112 are both in the closed state.

[0142] Furthermore, the storage device 100 includes two operating modes when performing a read operation, wherein one mode is that a voltage of the same magnitude can be selected to be loaded across the first bit line and the second bit line, so that the storage device 100 performs a read operation in the same manner as when the first selection tube 2111 and the second selection tube 2112 are arranged in parallel.

[0143] In another way, no voltage may be applied to the first bit line. In this case, the first end of the first selection tube 2111 is in an open circuit state, and the switch state of the first selection tube 2111 does not affect the use of the second selection tube 2112 and the memory 213 in the target storage unit 21.

[0144] In this manner, Vset is set to satisfy the relationship: 1.5V≤Vset≤4.0V, and Vreset is set to satisfy the relationship: 1.5V≤Vreset≤3.5V.

[0145] When the storage device 100 performs a write 1 operation, WL_sel=Vset, WL_unsel=1 / 3Vset, BL2_sel=0V, BL2_unsel=2 / 3Vset, so that the voltage difference between the word line and the second bit line respectively connected to the two ends of the second selection tube 2112 in the non-target storage unit 21 can be guaranteed to be 1 / 3Vset, so that Vunsel satisfies the relationship: V1th<Vunsel<V2th. It can be guaranteed that the voltage difference between the word line and the second bit line respectively connected to the two ends of the target storage unit 21 is Vset, so that Vsel satisfies the relationship: V2th≤Vsel.

[0146] In this way, on the target memory cell 21, the second selection tube 2112 is turned on, and the threshold voltage for executing write 1 for the memory 213 of the target memory cell 21 is set, so the memory 213 of the target memory cell 21 can execute the write 1 operation.

[0147] Similarly, when the memory device 100 performs a reset operation, WL_sel=0, WL_unsel=2 / 3Vset, BL2_sel=Vreset, BL2_unsel=1 / 3Vset, so that the voltage difference between the word line and the second bit line respectively connected to the two ends of the second gate tube 2112 in the non-target memory cell 21 can be guaranteed to be 1 / 3Vset, so that Vunsel satisfies the relationship: V1th<Vunsel<V2th. It can be guaranteed that the voltage difference between the word line and the second bit line respectively connected to the two ends of the target memory cell 21 is Vreset, and Vsel satisfies the relationship: V2th≤Vsel.

[0148] In this way, on the target memory cell 21, the second selection tube 2112 is turned on, and the threshold voltage for executing write-0 for the memory 213 of the target memory cell 21 is set, so the memory 213 of the target memory cell 21 can execute the write-0 operation.

[0149] According to an embodiment of the present invention, the storage device 100 uses two gates 211 and a memory 213 to form an array structure of the storage unit 21. When the storage device 100 performs a read operation, the voltage is low, and only the first gate tube 2111 responsible for the read operation is turned on, while the second gate tube 2112 responsible for writing is not turned on, thereby reducing the reading power consumption of the storage device 100. In addition, when the storage device 100 performs a write operation, the voltage is high, and the second gate tube 2112 is turned on. At this time, the first gate tube 2111 can also be turned on, but it does not affect the write operation, and when the first gate tube 2111 is turned on, it can be used as a small resistor in the circuit, which is conducive to reducing the circuit current. The storage device 100 in the embodiment of the present invention can also be used to solve the problem of large leakage of the gate 211.

[0150] In the description of the present invention, for the sake of ease of explanation and understanding, the selector 211 of the storage cell 21 is electrically connected to the bit line, and the memory 213 of the storage cell 21 is electrically connected to the word line, but the present invention does not specifically limit the electrical connection line of the selector 211 or the memory 213 of the storage cell 21, that is, the selector 211 of the storage cell 21 can be connected to the bit line, or the memory 213 of the storage cell 21 can be connected to the bit line, as long as the two ends of the storage cell 21 are electrically connected to the word line and the bit line, respectively.

[0151] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "circumferential", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0152] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example.

[0153] Although the embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A storage unit, characterized in that: include: A memory (213), wherein a first end of the memory (213) is suitable for being electrically connected to a word line driving circuit (12); A gate (211), wherein a first end of the gate (211) is suitable for being electrically connected to a bit line driving circuit (11), a second end of the gate (211) is suitable for being electrically connected to a second end of the memory (213), and the gate (211) has at least two different threshold voltages, so that the gate (211) has different open states under different threshold voltage conditions.

2. The storage unit according to claim 1, characterized in that The gate (211) comprises at least a first gate tube (2111) and a second gate tube (2112), wherein a threshold voltage of the first gate tube (2111) and a threshold voltage of the second gate tube (2112) are different.

3. The storage unit according to claim 2, characterized in that The threshold voltage of the first gate tube (2111) is set to V1th, and the threshold voltage of the second gate tube (2112) is set to V2th, and V1th and V2th satisfy the relationship: V1th<V2th.

4. The storage unit according to claim 3, characterized in that V1th and V2th satisfy the relationship: 0.2V≤V2th-V1th≤1V.

5. The storage unit according to claim 4, characterized in that V1th and V2th satisfy the relationship: 0.2V≤V1th≤1.0V, 0.6V≤V2th≤1.8V.

6. The storage unit according to claim 2, characterized in that: The first gating tube (2111) and the second gating tube (2112) are arranged in series.

7. The storage unit according to claim 2, characterized in that The first gating tube (2111) and the second gating tube (2112) are arranged in parallel.

8. The storage unit according to claim 7, characterized in that The first end of the first gate tube (2111) and the first end of the second gate tube (2112) are electrically connected to two different bit lines respectively; or, the first end of the first gate tube (2111) and the first end of the second gate tube (2112) are electrically connected to the same bit line; Wherein, the bit line is suitable for being electrically connected to the bit line driving circuit (11).

9. The storage unit according to claim 2, characterized in that: The first gating tube (2111) and / or the second gating tube (2112) comprises at least one of a bidirectional threshold switch, a diode and a conversion device of a metal-insulator-metal structure.

10. The storage unit according to claim 2, characterized in that: The switching layer material of the first gate tube (2111) and / or the second gate tube (2112) comprises at least one of niobium oxide, vanadium oxide and hafnium oxide.

11. The storage unit according to claim 2, characterized in that When the switching layer material of the first gate tube (2111) and / or the second gate tube (2112) includes hafnium oxide, the upper electrode layer or the lower electrode layer of the first gate tube (2111) and / or the second gate tube (2112) includes at least silver.

12. The storage unit according to claim 1, characterized in that The gate (211) comprises a first electrode (2113), a second electrode (2114) and at least two gate layers (2115) with different threshold voltages, wherein the at least two gate layers (2115) with different threshold voltages are arranged between the first electrode (2113) and the second electrode (2114).

13. The storage unit according to any one of claims 1 to 12, characterized in that: The memory (213) includes at least one of a resistive memory, a phase change memory, a magnetic random access memory and a ferroelectric memory.

14. A method for operating a storage unit, applicable to the storage unit (21) according to any one of claims 1 to 13, characterized in that: The following steps are involved: Setting the voltage difference between the word line driving circuit (12) and the bit line driving circuit (11) respectively connected to the two ends of the storage unit (21) to be Vsel, and setting Vsel to satisfy the relationship: V1th≤Vsel, so as to control the gate (211) of the storage unit (21) to enter a first open state, and perform a read operation on the memory (213) of the storage unit (21); The threshold voltage of the first on state of the gate (211) is V1th.

15. The method for operating a storage unit according to claim 14, characterized in that: The gate (211) comprises at least a first gate tube (2111) and a second gate tube (2112), and Vsel is set to satisfy the relationship: V1th≤Vsel<V2th, and the first gate tube (2111) of the storage unit (21) is controlled to be turned on, and the second gate tube (2112) of the storage unit (21) is controlled to be turned off, and a read operation is performed on the memory (213) of the storage unit (21); The threshold voltage of the first gate tube (2111) of the storage unit (21) is V1th, and the threshold voltage of the second gate tube (2112) of the storage unit (21) is V2th.

16. A method for operating a storage unit, applicable to the storage unit (21) according to any one of claims 1 to 15, characterized in that: The following steps are involved: Setting the voltage difference between the word line driving circuit (12) and the bit line driving circuit (11) respectively connected to the two ends of the storage unit (21) to be Vsel, and setting Vsel to satisfy the relationship: V2th≤Vsel, so as to control the gate (211) of the storage unit (21) to enter the second open state, and perform a write operation on the memory (213) of the storage unit (21); The threshold voltage of the second on state of the gate (211) is V2th.

17. The method for operating a storage unit according to claim 16, characterized in that: The gate (211) comprises at least a first gate tube (2111) and a second gate tube (2112), and Vsel is set to satisfy the relationship: V1th≤Vsel and V2th≤Vsel, so as to control the first gate tube (2111) and the second gate tube (2112) of the storage unit (21) to be turned on, and perform a write operation on the memory (213) of the storage unit (21); The threshold voltage of the first gate tube (2112) of the storage unit (21) is V1th, the threshold voltage of the second gate tube (2112) of the storage unit (21) is V2th, and V1th<V2th.

18. The method for operating a storage unit according to claim 17, characterized in that: The step of performing a write operation on the memory (213) of the storage unit (21) further comprises: When a write 1 operation is performed on the memory (213), Vsel satisfies the relationship: Vsel=Vset, wherein the threshold voltage of the memory (213) for performing a write 1 operation is Vset; When a write-0 operation is performed on the memory (213), Vsel satisfies the relationship: Vsel=Vreset, wherein the threshold voltage for the memory (213) to perform a write-0 operation is Vreset.

19. A storage device, characterized in that: include: A front-end driving circuit (10), the front-end driving circuit (10) comprising a bit line driving circuit (11) and a word line driving circuit (12); A memory array (20), the memory array (20) comprising a plurality of memory cells (21) according to any one of claims 1 to 12, the first end of the memory (213) of the memory cell (21) being electrically connected to the word line drive circuit (12), the first end of the gate (211) of the memory cell (21) being electrically connected to the bit line drive circuit (11), and the second end of the gate (211) being suitable for being electrically connected to the second end of the memory (213).

20. A method for operating a storage device, applicable to the storage device (100) according to claim 19, characterized in that: The following steps are involved: The threshold voltage of the on state of the selector (211) of the storage unit (21) is V1th, the voltage difference between the word line driving circuit (12) and the bit line driving circuit (11) respectively connected to the two ends of the target storage unit (21) in the storage device (100) is set to Vsel, and the voltage difference between the word line driving circuit (12) and the bit line driving circuit (11) respectively connected to the two ends of the non-target storage unit (21) in the storage device (100) is set to Vunsel; Vsel is set to satisfy the relationship: V1th≤Vsel, the gate (211) of the target storage unit (21) is controlled to be turned on, and a read operation or a write operation is performed on the memory (213) of the target storage unit (21); Vunsel is set to satisfy the relationship: Vunsel<V1th, and the gate (211) of the non-target storage unit (21) is controlled to be closed.

21. The method for operating a storage device according to claim 20, characterized in that: The gate (211) comprises at least a first gate tube (2111) and a second gate tube (2112); Vsel is set to satisfy the relationship: V1th≤Vsel<V2th, the first gate tube (2111) of the target storage unit (21) is controlled to be turned on, the second gate tube (2112) of the target storage unit (21) is controlled to be turned off, and a read operation is performed on the memory (213) of the target storage unit (21); or Vsel is set to satisfy the relationship: V2th≤Vsel, the first gate tube (2111) and the second gate tube (2112) of the target storage unit (21) are controlled to be turned on, and a write operation is performed on the memory (213) of the target storage unit (21); Vunsel is set to satisfy the relationship: Vunsel<V1th, and the first gate tube (2111) and the second gate tube (2112) of the non-target storage unit (21) are both turned off; The threshold voltage of the first gate tube (2111) of the storage unit (21) is V1th, the threshold voltage of the second gate tube (2112) of the storage unit (21) is V2th, and V1th and V2th satisfy the relationship: V1th<V2th.

22. The method for operating a storage device according to claim 21, characterized in that: The step of performing a write operation on the memory (213) of the target storage unit (21) further comprises: When a write-1 operation is performed on the target memory cell (21), Vsel satisfies the relationship: Vsel=Vset, wherein the threshold voltage of the target memory cell (21) for performing a write-1 operation is Vset; When a write-0 operation is performed on the target memory cell (21), Vsel satisfies the relationship: Vsel=reset, wherein the threshold voltage for performing a write-0 operation on the target memory cell (21) is Vreset.

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