Memory element and method for protecting a memory element

Abstract

The present disclosure provides a memory element and a protection method thereof. The memory element includes a controller configured to update at least one of the word lines during a first update period in response to an update signal; a digital adjuster configured to generate a modified first number according to a first number generated by a random number generator, wherein the modified first number is less than a first predetermined number. The memory element further includes a counter configured to receive the modified first number as an initial value and start in response to the update signal. The controller is configured to obtain an address of a first word line accessed when the counter counts to zero and update a second word line during a second update period, wherein an address of the second word line is adjacent to the address of the first word line.

Description

Technical Field

[0001] This application claims priority to U.S. Patent Application No. 18 / 374,151 (i.e., priority date "September 28, 2023"), the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to a memory element and a method for protecting the same. In particular, it relates to a memory element including protection circuitry for protecting word lines. Background Technology

[0003] Dynamic random access memory (DRAM) is a type of random access memory that stores each bit of data in a separate capacitor. The simplest DRAM cell consists of a single transistor and a single capacitor. If charge is stored in the capacitor, the cell is said to store a logic high level, depending on the protocol used. If no charge is present, the cell is said to store a logic low level. Because the charge in the capacitor dissipates over time, DRAM systems require additional update circuitry to periodically refresh the charge stored in the capacitor. Since a capacitor can only store a very limited amount of charge, two bit lines (BLs) are typically used for each bit to quickly distinguish between logic "1" and logic "0". The first bit in the bit line pair is called the bit line true (BLT), and the other is called the bit line complement (BLC). The gate of a single transistor is controlled by a word line (WL).

[0004] Row hammering is a security problem that exploits an unintended and unwanted side effect in DRAM, where memory cells electrically interact with each other by leaking their charge, potentially altering the contents of nearby memory rows (word lines) that were not addressed in the original memory access. Row hammering can be triggered by specific memory access patterns that rapidly activate the same memory rows (word lines) multiple times. As a result, memory cells connected to adjacent word lines will leak their charge and struggle to maintain their original contents in the next periodic update cycle. Attackers (or hackers) can exploit the row hammering effect to alter the contents of neighboring memory rows, causing memory element failure. Therefore, there is a need to develop a method to protect memory elements (especially word lines) and mitigate this problem.

[0005] The above description of "prior art" is merely to provide background information and does not constitute an admission that the above description of "prior art" reveals the subject matter of this disclosure. It does not constitute prior art of this disclosure, and no description of the above "prior art" should be considered part of this case. Summary of the Invention

[0006] One aspect of this disclosure provides a memory element. The memory element includes: a plurality of word lines; a controller configured to update at least one of the word lines during a first update cycle in response to an update signal; a random number generator configured to generate a first digit; and a digit adjuster connected to the random number generator. The digit adjuster is configured to generate a modified first digit based on the first digit, wherein the modified first digit is less than the first predetermined digit. The memory element further includes a counter electrically coupled to the random number generator and the digit adjuster, wherein the counter is configured to receive the modified first digit as an initial value and is configured to be turned on in response to the update signal. The controller is further configured to obtain an address of the accessed first word line when the counter counts to zero, and update a second word line during a second update cycle, wherein the address of the second word line is adjacent to the address of the first word line.

[0007] Another aspect of this disclosure provides a memory element. The memory element includes: a controller configured to update at least one of a plurality of word lines during a first update cycle in response to an update signal; a random number generator configured to generate a first number; and a number adjuster connected to the random number generator. The number adjuster is configured to modify the first number to a modified first number less than the first predetermined number. The memory element further includes a counter electrically coupled to the random number generator and configured to receive the modified first number as an initial value for the counter, and to count from the initial value in response to the update signal; and an address register electrically coupled to the counter and configured to store an address of a first word line activated when the counter decrements to zero. The counter is configured to access the address register to obtain the address of the first word line and to protect a second word line during a second update cycle, wherein an address of the second word line is adjacent to the address of the first word line.

[0008] Another aspect of this disclosure provides a method for protecting a memory element, wherein the memory element includes a plurality of word lines. The method includes: updating a first word line among the word lines during a first update cycle in response to an update signal; generating a first number using a random number generator; reducing the first number to a second number using a number adjuster when the first number is greater than a first predetermined number; counting down from the second number using a counter in response to the update signal; obtaining an address of a second word line being accessed using a controller when the counter counts to zero; and protecting a third word line during a second update cycle in response to the update signal, wherein an address of the third word line is adjacent to the address of the second word line.

[0009] This disclosure provides a memory element with protection circuitry for selecting and protecting bit lines that may be attacked. Specifically, the protection circuitry of the memory element can protect word lines (memory cells) from hammer attacks. To trigger a hammer attack, an attacker rapidly activates the same memory columns, causing inactive adjacent memory columns to potentially leak their charge. This protection circuitry provides a random number generator and a counter to randomly select and protect potential memory columns. The counter can be configured to count down from a random number generated by the random number generator. When the counter counts to zero, the address of the activated memory column is obtained. In other words, the memory columns are selected from those activated memory columns between update cycles. In this case, the selection pool includes memory columns activated between update cycles. Additionally, to prevent the random number generated by the random number generator from exceeding the maximum number of activations between two update cycles, a number adjuster is provided to modify the random number to a range of zero to a predetermined number (i.e., the maximum number of activations between update cycles). Since adjacent memory columns adjacent to those activated memory columns are more likely to experience a hammer attack, they will become the targets of protection in subsequent update cycles.

[0010] Typically, the activation amount that triggers a hammer attack cannot be completed within two update cycles. For example, a memory element with 8192 columns may have approximately 170 activations between two update cycles, and the activation amount for triggering a hammer attack for the same column could be 10,000 or more. Therefore, protecting additional memory columns that may trigger a hammer attack in each update cycle can eliminate the hammer attack problem. Furthermore, the memory element may include a digital adjuster to determine whether the random number used to select a specific column from the memory columns exceeds the maximum number of activations between two update cycles (i.e., 170 in this case), and then reduce the random number to the range of 0 to 170. This improves the security and performance of the memory element.

[0011] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, enabling a better understanding of the detailed description that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure through modifications or designs of other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined by the appended claims. Attached Figure Description

[0012] A more complete understanding of this disclosure can be obtained by referring to the detailed description and claims when considered in conjunction with the drawings, wherein similar reference numerals represent similar elements in the overall drawings, and:

[0013] Figure 1 A schematic diagram of a memory element is shown according to some embodiments of this disclosure.

[0014] Figure 2 A schematic diagram of a memory element is shown according to some embodiments of this disclosure.

[0015] Figure 3 A schematic diagram illustrating the activation of character lines along a timeline between update cycles is shown according to some embodiments of this disclosure.

[0016] Figure 3A A schematic diagram illustrating word line addresses accessed during each activation between update cycles along the timeline, according to some embodiments of this disclosure.

[0017] Figure 3B A schematic diagram illustrating word line addresses accessed during each activation between update cycles along the timeline, according to some embodiments of this disclosure.

[0018] Figure 3C A schematic diagram illustrating word line addresses accessed during each activation between update cycles along the timeline, according to some embodiments of this disclosure.

[0019] Figure 4 A schematic diagram of a shift register included in a memory element is shown according to some embodiments of the present disclosure.

[0020] Figure 5 A schematic diagram of a digital regulator included in a memory element is shown according to some embodiments of the present disclosure.

[0021] Figure 6 A schematic diagram of a digital adjuster included in a memory element is shown according to some embodiments of this disclosure.

[0022] Figure 7A flowchart of a method for protecting memory elements is shown according to some embodiments of this disclosure.

[0023] The reference numerals in the attached figures are explained as follows:

[0024] 1: Memory element

[0025] 2: Memory elements

[0026] 3: Schematic diagram

[0027] 3A: Schematic diagram

[0028] 3B: Schematic diagram

[0029] 3C: Illustration

[0030] 7: Method

[0031] 11: Memory Cell Array

[0032] 12: Sensing Amplifier

[0033] 21: Memory Cell Array

[0034] 22: Controller

[0035] 23: Random Number Generator

[0036] 23A: First digit

[0037] 23B: The modified first digit

[0038] 24: Counter

[0039] 25: Address Register

[0040] 26: Digital Adjuster

[0041] 26A: Digital Adjuster

[0042] 26B: Digital Adjuster

[0043] 71: Operation

[0044] 72: Operation

[0045] 73: Operation

[0046] 74: Operation

[0047] 75: Operation

[0048] 76: Operation

[0049] 111: Memory Column

[0050] 112: Memory Column

[0051] 113: Memory Column

[0052] 114: Memory Column

[0053] 131: Column Address Decoder

[0054] 132: Row Address Decoder

[0055] 211: Character Line

[0056] 212: Character Line

[0057] 213: Character Line

[0058] 214: Character Line

[0059] 231: Logic Gate

[0060] 232: Logic Gate

[0061] 233: Shift Register

[0062] 261: Judgment Unit

[0063] 262: and the door

[0064] 2330: Trigger

[0065] 2331: Trigger

[0066] 2332: Trigger

[0067] 2333: Trigger

[0068] 2334: Trigger

[0069] 2335: Trigger

[0070] 2336: Trigger

[0071] 2337: Trigger

[0072] 2610: Judgment Result

[0073] 2611: Part One

[0074] 2612: Part Two

[0075] 2620: with output

[0076] act_1: Activation

[0077] act_2: Activation

[0078] act_3: Activation

[0079] act_4: Activation

[0080] act_N-1: Activation

[0081] act_N: Activation

[0082] B0: Output terminal

[0083] B1: Output terminal

[0084] B5: Output terminal

[0085] B6: Output terminal

[0086] B7: Output terminal

[0087] Bit0: Bit value

[0088] Bit1: Bit value

[0089] Bit2: Bit value

[0090] Bit3: Bit value

[0091] Bit4: Bit value

[0092] Bit5: Bit value

[0093] Bit6: Bit value

[0094] Bit7: Bit value

[0095] CBR: First Update Cycle

[0096] CBR+1: Second Update Cycle

[0097] CLKA: Clock signal

[0098] CLKB: Clock signal

[0099] CLKC: Clock signal

[0100] CLKD: Clock signal

[0101] CLKE: Clock signal

[0102] D0: Data End

[0103] D1: Data Terminal

[0104] D5: Data Terminal

[0105] D6: Data Terminal

[0106] D7: Data Terminal

[0107] L1: AND gate

[0108] L2: AND gate

[0109] L3: OR gate

[0110] L4: AND gate

[0111] L5: AND gate

[0112] L6: AND gate

[0113] L7: AND gate

[0114] L8: Logic Gate

[0115] L10: Output

[0116] L20: Output

[0117] L30: Output

[0118] L40: Output

[0119] L50: Output

[0120] L60: Output

[0121] L70: Output

[0122] RS: Update signal

[0123] R / W: Read / Write signal

[0124] T act Time period

[0125] T CBR Time period

[0126] WL1: Word line address

[0127] WL2: Word line address

[0128] WL3: Wordline Address Detailed Implementation

[0129] The embodiments or examples of this disclosure shown in the drawings are described below using specific language. It should be understood that this is not intended to limit the scope of this disclosure. Any changes or modifications to the embodiments, and any further application of the principles set forth herein, are to be regarded as normal occurrences by those skilled in the art related to this disclosure. Reference numerals may be repeated in all embodiments, but this does not necessarily mean that a component of one embodiment is applicable to another embodiment, even if they use the same reference numerals.

[0130] It should be understood that although the terms first, second, third, etc., may be used herein to describe various elements, components, regions, layers, or parts, these elements, components, regions, layers, or parts are not limited to these terms. Rather, these terms are used only to distinguish one element, component, region, layer, or part from another. Therefore, without departing from the conceptual teachings of this disclosure, the first element, component, region, layer, or part discussed below may be referred to as a second element, component, region, layer, or part.

[0131] The terms used herein are for the purpose of describing particular example embodiments only and are not intended to limit the concepts of this disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms “a / an” and “the” also include the plural forms. It should be further understood that the terms “comprises” and “comprising” as used in this specification indicate the presence of said components, integers, steps, operations, elements, or components, but do not exclude the presence or addition of one or more components, integers, steps, operations, elements, components, or combinations thereof.

[0132] It should be noted that the use of the term "approximately" to modify the amounts of ingredients, components, or reactants used in this disclosure refers to numerical variations that may arise, for example, through typical measurement and liquid handling procedures used to prepare concentrates or solutions. Furthermore, variations may occur due to negligence or errors in measurement procedures, or differences in the manufacture, source, or purity of the ingredients used in the preparation of the composition or the implementation of the method. On one hand, the term "approximately" means within 10% of the reported value. On the other hand, the term "approximately" means within 5% of the reported value. Also, on another hand, the term "approximately" means within 10, 9, 8, 7, 6, 5, 4, 3, 2, or 1% of the reported value.

[0133] Figure 1 This is a schematic diagram of a memory element 1 according to some embodiments of the present disclosure. The memory element 1 may include a memory cell array 11, a sense amplifier 12, a column address decoder 131, and a row address decoder 132. In some embodiments, the memory element 1 may be DRAM.

[0134] like Figure 1 As shown, the memory cell array 11 may include multiple rows and columns. Each row of memory cells may share one bit line or a pair of bit lines. Each column of memory cells may share one word line. In some embodiments, a single memory cell may include a capacitor and a transistor, and is configured to store data bits therein. The charging state (charging or discharging) of the capacitor can determine whether the memory cell stores "1" or "0" as a binary bit value.

[0135] In some embodiments, the memory address applied to the memory cell array 11 can be represented as a column address and a row address, which are processed via a column address decoder 131 and a row address decoder 132. When the column address decoder 131 selects a specific column (e.g., memory column 114) for a read operation (this selection is also referred to as row activation), bits from all memory cells in that specific column can be transferred to a sense amplifier 12. In some embodiments, a sense amplifier 12 temporarily holds data for each row of memory cells. In some embodiments, the row address decoder 132 can select the exact bit from the sense amplifier 12. In some embodiments, the sense amplifier 12 can be configured to receive or transfer data in response to a read / write signal R / W. Write operations decode the address in a similar manner, but can rewrite the entire column to change the value of a single bit.

[0136] Because data bits are stored in capacitors with a natural discharge rate, the state stored in memory cell 11 may be lost over time. Therefore, all memory cells need to be periodically rewritten to preserve information; this is a known update process. Each memory update cycle can update one or more columns of memory cells, and all memory cells can be repeatedly updated in consecutive cycles. Memory updates can be performed in various ways. In some embodiments, memory updates can be performed using signals of different modes, such as row address strobe (RAS) updates, column-before-RAS (CAS-before-RAS) updates (also known as CBR updates), and hidden refreshes.

[0137] To trigger the hammer, the same memory column 111 can be activated at a high frequency and in large quantities. When the activation frequency and activation amount of memory column 111 are high enough, the unactivated neighboring memory columns 112 and 113 may leak their charge, which may cause the data / content stored therein to be lost.

[0138] This protection circuit provides a random number generator and a counter (details can be found in [reference]). Figure 2A counter is configured to randomly select and protect potential memory columns. This counter can be configured to count down from a random number generated by a random number generator. When the counter reaches zero, the address of the activated memory column (such as memory column 111) is obtained. In other words, the memory column is selected from those activated memory rows between update cycles. Because neighboring memory columns 112 and 113 adjacent to the activated memory column 111 are more likely to experience a hammering effect, they will be protected in subsequent update cycles. In some embodiments, memory columns 112 and 113, as well as the planned update memory column 114, can be updated in subsequent update cycles.

[0139] Figure 2 This is a schematic diagram of memory element 2 according to some embodiments of the present disclosure. (Refer to...) Figure 2 The memory element 2 may include a memory cell array 21, a controller 22, a random number generator 23, a counter 24, an address register 25, and a digital adjuster 26. In some embodiments, the memory element 2 may be a dynamic random access memory (DRAM).

[0140] In some embodiments, the memory cell array 21 may include a plurality of word lines. In some embodiments, the memory cell array 21 may include a potential target word line 211 to be accessed, two adjacent word lines 212 and 213 adjacent to the potential target word line 211, and a general word line 214. The general word line 214 may be located anywhere in the memory cell array 21. For example, the general word line 214 may be an edge word line or a word line sandwiched between two word lines. In one embodiment, the general word line 214 may be separate from the potential target word line 211. In another embodiment, the general word line 214 may be adjacent to the potential target word line 211 (not shown).

[0141] Controller 22 may be configured to update at least one word line during a first update cycle in response to an update signal RS. In some embodiments, the update signal RS may be a RAS update instruction or a CBR update instruction. Controller 22 may be configured to update one or more word lines during an update cycle. In some embodiments, controller 22 may be configured to update one, two, three, four, or more word lines simultaneously. In some embodiments, controller 22 may be configured to update all memory cell arrays 21 cycle-by-cycle.

[0142] A random number generator 23 can be configured to generate a first number 23A. The first number 23A can be a positive integer. In some embodiments, the first number 23A can be binary. The first number 23A can be represented by a binary sequence having more than 2 bits. For example, the first number 23A can be represented by a binary sequence having 8 bits. That is, the first number 23A can be a number in the range of 0 to 255.

[0143] Reference Figure 2 The random number generator may include logic gates 231 and 232 and shift register 233.

[0144] In some embodiments, logic gate 231 may have a first input terminal, a second input terminal, and an output terminal. In some embodiments, logic gate 231 may be configured to receive a first clock signal CLKA and a second clock signal CLKB through the first and second input terminals. In some embodiments, the frequency of the first clock signal CLKA is different from the frequency of the second clock signal CLKB. Logic gate 231 may be configured to generate a third clock signal CLKC in response to the first clock signal CLKA and the second clock signal CLKB. In some embodiments, logic gate 231 may output the third clock signal CLKC through its output terminal.

[0145] Logic gate 231 can be an OR gate, AND gate, XOR gate, XNOR gate, etc. In another embodiment, logic gates 231 and 232 can be other types of logic gates (not shown).

[0146] In some embodiments, the third clock signal CLKC can be unpredictable compared to the first clock signal CLKA and the second clock signal CLKB, because it is obtained based on a predetermined calculation in response to the first clock signal CLKA and the second clock signal CLKB. Taking logic gate 231 as an XOR gate as an example, in principle, regardless of its value, the output of the mutually exclusive OR (XOR) operation of the two inputs is true only when the two input values ​​are different; if the two input values ​​are equal, the output is false. Based on this calculation of the XOR gate, the third clock signal CLKC can have a non-uniform frequency.

[0147] In some embodiments, logic gate 232 may have a first input, a second input, and an output electrically connected to logic gate 231. Both the second input and the output of logic gate 232 may be electrically connected to shift register 233. Logic gate 232 may be configured to receive a third clock signal CLKC through its first input. In some embodiments, the second input of logic gate 232 may be configured to receive a bit value associated with a first digital number 23A output from shift register 233. Logic gate 232 may be configured to generate a fourth clock signal CLKD in response to the third clock signal CLKC and the bit value associated with the first digital number 23A. In some embodiments, logic gate 232 may output the fourth clock signal CLKD through its output.

[0148] Logic gate 232 can be an OR gate, AND gate, XOR gate, XNOR gate, etc. In some embodiments, logic gates 231 and 232 can be the same or different logic gates. For example, logic gates 231 and 232 can both be exclusive OR (XOR) gates. In another embodiment, logic gates 231 and 232 can be other types of logic gates (not shown).

[0149] In some embodiments, by feeding back the bit value associated with the first digit 23A to the logic gate 232, the fourth clock signal CLKD can be more unpredictable than the third clock signal CLKC.

[0150] Shift register 233 may include a first input electrically connected to the output of logic gate 232, a second input configured to receive a fifth clock signal CLKE, and an output connected to counter 24. In some embodiments, shift register 233 is an 8-bit shift register. Therefore, the output of shift register 233 may have 8 bits (e.g., ...). Figure 2 (As shown). In other embodiments, shift register 233 may have more or fewer than 8 bits.

[0151] In some embodiments, the first input of shift register 233 may be configured to receive a fourth clock signal CLKD. In some embodiments, the first input of shift register 233 may be a data input. In some embodiments, the second input of shift register 233 may be a clock input.

[0152] Shift register 233 can be configured to generate a first digital number 23A in response to a fourth clock signal CLKD and a fifth clock signal CLKE. In some embodiments, the output of shift register 233 can be configured to output the first digital number 23A in response to the fourth clock signal CLKD.

[0153] The output of shift register 233 can be connected to the second input of logic gate 232, such that the bit value associated with the first number 23A is fed back to logic gate 232. For example, three bits of the output of shift register 233 can be connected to the second input of logic gate 232. In some embodiments, logic gate 232 can be configured to generate a fourth clock signal CLKD in response to a third clock signal and a bit value (e.g., the bit value of the 3-bit output). The fourth clock signal CLKD can be associated with the current number output from shift register 233.

[0154] Shift register 233 can be configured to generate a random number (i.e., a first number 23A) in response to a fourth clock signal CLKD as a data input and a fifth clock signal CLKE as a clock input. By feeding the bit value associated with the first number 23A back to logic gate 232, the random number generator 23 can be non-pseudo. Therefore, the first number 23A can be more unpredictable. This improves the security of memory element 2.

[0155] A digit adjuster 26 may be connected to a random number generator 23 and configured to receive a first digit 23A. The digit adjuster 26 may be circuitry for reducing the first digit 23A to less than a threshold. In some embodiments, the digit adjuster 26 may be configured to generate a modified first digit 23B (or a second digit 23B) based on the first digit 23A. In some embodiments, when the first digit 23A is greater than a first predetermined number, the digit adjuster 26 may modify the first digit 23A to the modified first digit 23B. In some embodiments, the first predetermined number is the maximum number of accesses between update cycles (details of which can be found in [reference]). Figure 3 After modification, the modified first number 23B is less than the first predetermined number. The modified first number 23B can be less than the first number 23A.

[0156] The modified first digit 23B can be represented in the same form as the first digit 23A. In some embodiments, both the first digit and the modified digit can be binary. For example, if the first digit 23A is represented by a binary sequence with 8 bits, then the modified first digit 23B is also represented by a binary sequence with 8 bits. In some embodiments, the first digit 23A can be represented by a binary sequence having Bit7, Bit6, Bit5, Bit4, Bit3, Bit2, Bit1, and Bit0. The modified first digit 23B can be represented by a binary sequence having Bit7', Bit6', Bit5', Bit4', Bit3', Bit2', Bit1', and Bit0'.

[0157] The difference between the first digit 23A and the modified first digit 23B can be a single bit in the binary sequence. For example, the most significant bit (msb) of the first digit 23A can be different from the most significant bit of the modified first digit 23B. That is, Bit 7' of the modified first digit 23B is different from Bit 7 of the first digit 23A. In some embodiments, Bits 6' to 0' of the modified first digit 23B can be the same as Bits 6 to 0 of the first digit 23A. In another embodiment, the modified first digit 23B can be reset to zero by the digit adjuster 26. Therefore, Bits 7' to 0' of the modified first digit 23B are logic "0".

[0158] Conversely, when the first digit 23A is less than a first predetermined digit, the digit adjuster 26 will not take any action on the first digit 23A. In this case, the modified first digit 23B will be the same as the original first digit 23A.

[0159] Counter 24 may be electrically coupled to random number generator 23 and digital adjuster 26. In some embodiments, counter 24 may be electrically coupled to random number generator 23 via digital adjuster 26. Counter 24 may be configured to receive a modified first number 23B as the initial value of counter 24. In one embodiment, when the first number 23A is less than a first predetermined number, the modified first number 23B is the same as the first number 23A, and counter 24 decrements from the modified first number 23B (i.e., the first number 23A). In another embodiment, when the first number 23A is greater than a first predetermined number, the first number 23A is modified to a modified first number 23B that is less than the first predetermined number, and counter 24 decrements from the modified first number 23B, which is different from the first number 23A.

[0160] In some embodiments, counter 24 is configured to start in response to an update signal RS received from controller 22. In other words, counter 24 may be configured to begin counting down in response to the update signal RS. Counter 24 may be configured to decrement (count down) from an initial value (i.e., the modified first number 23B).

[0161] In some embodiments, counter 24 may be configured to decrement in response to an accessing signal indicating access to one of the character lines.

[0162] Address register 25 can be electrically coupled to counter 24. Address register 25 can be configured to obtain and store the address of the first word line 211 (or possibly the target word line 211) that is activated when counter 24 is decremented to zero.

[0163] Controller 22 may be configured to access address register 25 during a second update cycle to obtain the address of the first word line and protect the second word lines 212 / 213 (i.e., adjacent word lines 212 or 213). To protect the second word lines 212 / 213, the controller may be configured to update the second word lines 212 / 213 during the second update cycle in response to an update signal. In some embodiments, the second update cycle follows the first update cycle. For example, the second update cycle is the update cycle following the first update cycle. In some embodiments, the address of the second word line 212 / 213 is adjacent to the address of the first word line 211.

[0164] Controller 22 can be configured to update one or more character lines during an update cycle. In some embodiments, controller 22 can be configured to update one, two, three, four, or more character lines simultaneously. Controller 22 can be configured to update adjacent character lines 212 and 213 during the same update cycle. In some embodiments, in addition to the second character lines 212 / 213, controller 22 can also be configured to update a third character line 214 during a second update cycle in response to an update signal RS, wherein the address of the third character line 214 is separate from the address of the first character line 211.

[0165] In some embodiments, controller 22 may be configured to update a character line adjacent to a possible target character line 211 and another character line other than the possible target character line 211. For example, character lines 212 and 214 may be updated during a second update cycle. In some embodiments, in one update cycle, controller 22 may be configured to update two general character lines (such as character line 214) and two high-risk character lines (such as character lines 212 and 213), as determined by random number generator 23 and counter 24.

[0166] In this disclosure, the address of the first activated character line 211 (or a possible target character line 211) can be obtained when the counter 24 decrements to zero. In this case, the address of the character line to be protected can be randomly selected from those character lines activated during two update cycles. Furthermore, a digit adjuster 26 is provided to modify the first digit 23A to a range from 0 to a first predetermined digit, thereby preventing the first digit 23A from exceeding the maximum number of activations between two update cycles.

[0167] Figure 3This is a schematic diagram illustrating the activation of character lines along a timeline between update cycles, according to some embodiments of this disclosure. Figure 3 .

[0168] Reference Figure 3 Along the timeline (i.e., the x-axis), the time period T CBR Between the first update cycle CBR and the second update cycle CBR+1. In some embodiments, the second update cycle CBR+1 immediately follows the first update cycle CBR. In some embodiments, N activations (act_1, act_2, act_3, ..., act_N-1, act_N) occur between the first update cycle CBR and the second update cycle CBR+1. Each activation of act_1, act_2, act_3, act_N-1, and act_N represents an access to a character line. T act It is the time interval between two activations. For example, time interval T. act It can be between activating act_1 and act_2. In some embodiments, the time period T act It can be the minimum necessary time to access a word line (like the first active act_1).

[0169] To clearly illustrate this disclosure, a memory array with 8,000 character lines is used as an example. The memory array may include 8,192 character lines. In some embodiments, updating all character lines (i.e., all 8,192 character lines) can take 64 ms. In this case, the time period T... CBR The time required to update each character line can be calculated as 64ms / 8192. Therefore, the time period T... CBR The duration will be 7.8125 μs. In other words, for a total of 8k character lines, the time period T... CBR The sharing time between two update cycles can be 7.8125 μs. Assume the time period T... act If the time interval is 45.75 ns, then the maximum number of accesses N between two update cycles is... max According to formula N max =T CBR / T act The maximum number of accesses N is calculated. max It can be 7.8125μs / 45.75ns=170.765≈170, that is... Figure 3 The number N in the equation is 170. In this embodiment, 170 character lines can be accessed between two update cycles. Accordingly, the first number 23A received by the counter 24 can be modulated to be lower than a predetermined value (e.g., 170 in this embodiment).

[0170] In some embodiments, the first number 23A may be less than a predetermined number, which is related to the time period T used for accessing the character line. act and the time period T between the first update cycle CBR and the second update cycle CBR+1 CBR Relatedly, in some embodiments, counter 24 may be configured to reset its initial value when the first digit 23A is greater than a predetermined digit. For example, the initial value of counter 24 may be reset to zero or by subtracting a constant to make it less than the predetermined digit. Thus, counter 24 can count down from an initial value in the range of 0 to a predetermined digit (i.e., the maximum number of accesses between two update cycles), and when it decrements to zero, the character line to be protected during the next update cycle can be selected.

[0171] Figure 3A A schematic diagram of the word line addresses accessed during each activation along the timeline between update cycles CBR and CBR+1, according to some embodiments of this disclosure. Figure 3A .

[0172] Reference Figure 3A During each activation of act_1, act_2, act_3, act_4, ..., and act_N, word line address WL1 is accessed. In this case, regardless of the initial value of counter 24, address register 25 will store the most frequently accessed word line address WL1. In other words, word line address WL1 is most likely to become the target of an attacker. Therefore, selecting the word line adjacent to word line address WL1 for protection can effectively prevent the hammer attack.

[0173] Figure 3B Schematic diagram B2 shows, according to some embodiments of the present disclosure, the character line address accessed during each activation along the timeline between update cycles CBR and CBR+1.

[0174] Reference Figure 3B When act_1 is activated, word line address WL1 is accessed. When act_2 is activated, word line address WL2 is accessed. When act_3 is activated, word line address WL1 is accessed. When act_4 is activated, word line address WL2 is accessed. When act_N is activated, word line address WL2 is accessed. That is, only word line addresses WL1 and WL2 are accessed. In this case, regardless of the initial value of counter 24, address register 25 will store the most frequently accessed word line address WL1 or WL2. In some embodiments, word line addresses WL1 and WL2 are both 50% likely to be attacked. In other words, word line addresses WL1 and WL2 are most likely to be targets of attackers. Therefore, selecting the word line adjacent to word line addresses WL1 or WL2 for protection can effectively prevent the hammer effect.

[0175] Figure 3C A schematic diagram of the word line addresses accessed during each activation along the timeline between update cycles CBR and CBR+1, according to some embodiments of this disclosure. Figure 3C .

[0176] Reference Figure 3C When activating act_1, word line address WL1 is accessed. When activating act_2, word line address WL2 is accessed. When activating act_3, word line address WL3 is accessed. When activating act_4, word line address WL1 is accessed. When activating act_N-1, word line address WL2 is accessed. When activating act_N, word line address WL3 is accessed. In some embodiments, word line addresses WL1, WL2, and WL3 are accessed sequentially. That is, only word line addresses WL1, WL2, and WL3 are accessed between two update cycles. In this case, address register 25 will store one of word line addresses WL1, WL2, and WL3. In some embodiments, the probability that word line addresses WL1, WL2, and WL3 are attacked is approximately 33.33%. In other words, word line addresses WL1, WL2, and WL3 are most likely to be targeted by an attacker. Therefore, protecting the word lines adjacent to the word line addresses WL1, WL2, or WL3 can effectively prevent the hammer effect from occurring.

[0177] Figure 4 A schematic diagram of a shift register 233 included in a memory element is shown according to some embodiments of the present disclosure.

[0178] Reference Figure 4 The shift register 233 may include one or more flip-flops 2330, 2331, ..., 2335, 2336, and 2337. In some embodiments, the flip-flops 2330, 2331, ..., 2335, 2336, and 2337 may be any type of flip-flop, such as a D flip-flop. In some embodiments, the 8-bit shift register 233 may include eight flip-flops 2330, 2331, ..., 2335, 2336, and 2337. In some embodiments, the shift register 233 may be configured as serial-in parallel-out.

[0179] Each flip-flop 2330, 2331, ..., 2335, 2336, and 2337 may have a data input, a clock input, a reset input, and an output input. In some embodiments, the clock input of flip-flops 2330, 2331, ..., 2335, 2336, and 2337 is connected and configured to receive a clock signal CLKE (e.g., ...). Figure 2(As shown). That is, triggers 2330, 2331, ..., 2335, 2336, and 2337 can operate at a given clock frequency of the clock signal CLKE. The reset terminal of triggers 2330, 2331, ..., 2335, 2336, and 2337 is connected and configured to receive a reset signal. In some embodiments, triggers 2330, 2331, ..., 2335, 2336, and 2337 can be reset in response to a reset signal. In some embodiments, each trigger 2330, 2331, ..., 2335, 2336, and 2337 may have a set terminal (not shown).

[0180] In some embodiments, the data terminal D7 of the flip-flop 2337 can be configured to receive a clock signal CLKD (e.g., ...). Figure 2 (As shown). In response to clock signals CLKD and CLKE, the output B7 of flip-flop 2337 can be configured to output bit value Bit7, which is transmitted to the data terminal D6 of counter 24 and flip-flop 2336. In response to bit value Bit7 and clock signal CLKE, the output B6 of flip-flop 2336 can be configured to output bit value Bit6, which is transmitted to the data terminal D5 of counter 24 and flip-flop 2335. In response to bit value Bit6 and clock signal CLKE, the output B5 of flip-flop 2335 can be configured to output bit value Bit5, which is transmitted to the data terminal D4 (not shown) of counter 24 and flip-flop 2334. In some embodiments, the omitted flip-flops 2334, 2333, and 2332 can be configured between flip-flops 2335 and 2331 in a manner similar to that of flip-flops 2336 and 2335. In response to the bit value Bit2 received at the data terminal D1 of flip-flop 2331 and the clock signal CLKE, the output terminal B1 of flip-flop 2331 can be configured to output the bit value Bit1, which is transmitted to the counter 24 and the data terminal D0 of flip-flop 2330. In response to the bit value Bit1 and the clock signal CLKE, the output terminal B0 of flip-flop 2330 can be configured to output the bit value Bit0, which is transmitted to the counter 24.

[0181] The data input to shift register 233 is serial. Once data is input, it can be read off at each output simultaneously, or it can be shifted out. Each input bit moves down to the Nth output after N clock cycles, thus forming a parallel output. Bit values ​​Bit7, Bit6, Bit5, ..., Bit1, and Bit0 can form the first 8-bit number 23A. (Refer to previous section) Figure 2The output of shift register 233 can be connected to the second input of logic gate 232, so that the bit value associated with the first number 23A is fed back to logic gate 232. In some embodiments, the fed-back bit value can be... Figure 4 The bit value shown is one of Bit7, Bit6, Bit5, ..., Bit1, and Bit0.

[0182] Shift register 233 can be configured to generate random numbers (such as the first number 23A) in response to a data signal (i.e., clock signal CLKD) and a clock signal CLKE. An unpredictable clock signal CLKC is generated based on asynchronous clock signals CLKA and CLKB through logic gate 231. Furthermore, clock signal CLKD can be even more unpredictable because it is generated based on the unpredictable clock signal CLKC and the feedback bit value associated with the first number 23A. In this case, clock signal CLKD can be even more unpredictable. Without any pseudo-algorithm, random number generator 23 can be configured to generate even more unpredictable numbers. Therefore, a hammer attacker cannot predict or know the word line address that the memory element will protect.

[0183] Figure 5 A schematic diagram of a digital regulator 26A included in a memory element is shown according to some embodiments of this disclosure. The digital regulator 26A is... Figure 2 An embodiment of the number adjuster 26 is shown. The number adjuster 26A is configured to reset the most significant bit (msb) of the first number 23A when the first number 23A is greater than a first predetermined number.

[0184] Reference Figure 5 The digital adjuster 26A may include a judgment unit 261 and an AND gate 262. The judgment unit 261 may be configured to receive a first number 23A from the random number generator 23. In some embodiments, the judgment unit 261 may be configured to determine whether the first number 23A is greater than a first predetermined number and output a judgment result 2610.

[0185] AND gate 262 may have one input connected to random number generator 23, another input connected to decision unit 261, and an output connected to counter 24. In some embodiments, AND gate 262 may be configured to receive the most significant bit 7 of the first number 23A and decision result 2610, and generate an AND output 2620 in response to the most significant bit 7 of the first number 23A and decision result 2610. In some embodiments, AND gate 262 may be configured to transmit the AND output 2620 to counter 24 as the modified most significant bit 7' of the first number 23B.

[0186] In principle, the output of a two-input AND gate is true only when all input values ​​are logic "1". If not all inputs to the AND gate are logic "1", the output is false. Based on this calculation of AND gate 262, the AND output 2620 can be represented as truth table 1.

[0187] Truth Table 1

[0188] Bit 7 2610 2620 / Bit 7' 0 0 0 0 1 0 1 0 0 1 1 1

[0189] In some embodiments, when the judgment result 2610 is logic high, it indicates that the first number 23A is less than a predetermined number. Conversely, when the judgment result 2610 is logic low, it indicates that the first number 23A is greater than a predetermined number. Therefore, when the judgment result 2610 is logic low (logic "0") and Bit 7 of the first number 23A is logic high (logic "1"), the output 2620 will be logic low to reduce the first number 23A to the modified first number 23B. That is, the most significant bit (msb) of the first number 23A can be reset to logic "0". In some embodiments, when the first number 23A is greater than a first predetermined number, the digital adjuster 26A can be configured to subtract 128 (i.e., 2^34) from the first number 234. 7 This is used to obtain the modified first number 23B. For example, when the first number 23A is 171, which is greater than the first predetermined number 170, the number adjuster 26A can subtract 128 from the first number 23A to produce the modified first number 23B as 42.

[0190] The determination unit 261 may be a circuit including one or more logic gates. In some embodiments, the determination unit 261 may include a first portion 2611, a second portion 2612, and a logic gate L8.

[0191] In some embodiments, the first part 2611 may include two AND gates L6 and L7. AND gate L6 has two inputs connected to a shift register 233 of the random number generator 23, configured to receive Bit5 and Bit7 of the first number 23A, respectively. AND gate L6 is configured to generate an output L60 at its output in response to Bit5 and Bit7 of the first number 23A. AND gate L7 may have three inputs connected to the shift register 233 of the random number generator 23, configured to receive Bit4, Bit5, and Bit7 of the first number 23A, respectively. AND gate L7 is configured to generate an output L70 at its output in response to Bit4, Bit5, and Bit7 of the first number 23A.

[0192] The first portion 2611 can be configured to determine whether a first portion of the binary sequence of the first digit 23A is greater than a first threshold. In some embodiments, when the first digit 23A is represented by a binary sequence having 8 bits, the first portion of the binary sequence of the first digit 23A can be 4 bits (e.g., the first four digits). In some embodiments, the first threshold can be represented by a 4-bit binary sequence (e.g., the first four digits of a first predetermined digit). For example, if the first predetermined digit is 170, which can be represented in binary as 10101010, then the first threshold can be represented in binary as 1010.

[0193] In some embodiments, the second part 2612 includes AND gates L1, L2, L4, L5, and OR gate L3. AND gate L1 may have three inputs connected to shift register 233 of random number generator 23, configured to receive Bit0, Bit1, and Bit3 of the first number 23A, respectively. AND gate L1 is configured to generate output L10 at its output in response to Bit0, Bit1, and Bit3 of the first number 23A. AND gate L2 may have two inputs connected to shift register 233 of random number generator 23, configured to receive Bit2 and Bit3 of the first number 23A, respectively. AND gate L2 is configured to generate output L20 at its output in response to Bit2 and Bit3 of the first number 23A. The outputs of AND gates L1 and L2 are connected to OR gate L3 as inputs. OR gate L3 is configured to generate output L30 at its output in response to outputs L10 and L20.

[0194] AND gate L4 may have two inputs connected to shift register 233 of random number generator 23, configured to receive Bits 5 and 7 of the first digital number 23A, respectively. AND gate L4 is configured to generate output L40 at its output terminal in response to Bits 5 and 7 of the first digital number 23A. AND gate L5 may have two inputs connected to OR gate L3 and AND gate L4, configured to receive outputs L30 and L40, respectively. AND gate L5 is configured to generate output L50 at its output terminal in response to outputs L30 and L40.

[0195] The second part 2612 can be configured to determine whether the second part of the binary sequence of the first number 23A is greater than a second threshold if the first part of the binary sequence of the first number 23A is greater than or equal to a first threshold. In some embodiments, when the binary sequence of the first number 23A has 8 bits, the second part of the binary sequence of the first number 23A can be 4 bits (e.g., the last four digits). In some embodiments, the second threshold can be represented by a 4-bit binary sequence (e.g., the last four digits of a first predetermined number). For example, if the first predetermined number is 170, it can be represented in binary as 10101010, and the second threshold can be represented in binary as 1010. In some embodiments, the AND gate L4 is configured to determine whether the first part of the binary sequence of the first number 23A is greater than or equal to the first threshold.

[0196] In some embodiments, each of the first portion 2611 and the second portion 2612 can compare a portion of the first digit 23A with a corresponding portion of the first predetermined digit. Then, the logic gate L8 can combine the results of the first portion 2611 and the second portion 2612 and output the final judgment result (i.e., judgment result 2610).

[0197] In some embodiments, logic gate L8 may be a NOR gate. Logic gate L8 may be connected to the first portion 2611 and the second portion 2612. In some embodiments, logic gate L8 may have three inputs respectively connected to AND gates L5, L6, and L7, configured to receive outputs L50, L60, and L70 respectively. In some embodiments, logic gate L8 is configured to generate a decision result 2610 at the output in response to outputs L50, L60, and L70. Based on this calculation of logic gate L8, the decision result 2610 may be represented as truth table 2.

[0198] Truth Table 2

[0199] L50 L60 L70 2610 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 1 1 0 1 0 1 0 1 1 0 0 1 1 1 0

[0200] The logic gate L8 will only output a logic "1" when outputs L50, L60, and L70 are all logic "0". In some embodiments, a logic high level for the judgment result 2610 indicates that the first number 23A is less than a predetermined number. Conversely, a logic low level for the judgment result 2610 indicates that the first number 23A is greater than a predetermined number. In this case, when the judgment result 2610 is logic low and Bit 7 of the first number 23A is logic high, the most significant bit (msb) of the first number 23A can be reset to logic "0".

[0201] Taking the first predetermined number as 170 as an example, when the first number 23A is 127, 128, 170, 171, and 187, the logic gate output of the digital regulator 26A can be represented by Tables 1 to 5 respectively.

[0202] Table 1

[0203] 23A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 127 0 1 1 1 1 1 1 1 L10 L20 L30 L40 L50 L60 L70 2610 2620 1 1 1 0 0 0 0 1 0

[0204] Table 2

[0205] 23A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 128 1 0 0 0 0 0 0 0 L10 L20 L30 L40 L50 L60 L70 2610 2620 0 0 0 0 0 0 0 1 1

[0206] Table 3

[0207] 23A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 170 1 0 1 0 1 0 1 0 L10 L20 L30 L40 L50 L60 L70 2610 2620 0 0 0 1 0 0 0 1 1

[0208] Table 4

[0209] 23A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 171 1 0 1 0 1 0 1 1 L10 L20 L30 L40 L50 L60 L70 2610 2620 1 0 1 1 1 0 0 0 0

[0210] Table 5

[0211] 23A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 187 1 0 1 1 1 0 1 1 L10 L20 L30 L40 L50 L60 L70 2610 2620 1 0 1 1 1 0 1 0 0

[0212] Figure 5 The determination unit 261 shown is an exemplary circuit used to determine whether the first digit 23A is greater than a first predetermined digit. In some embodiments, the determination unit 261 can also be implemented by other configurations to determine whether the first digit 23A is greater than the same first predetermined digit. In other embodiments, in order to compare the first digit with different first predetermined digits, the determination unit 261 can be implemented by different configurations as needed.

[0213] A number adjuster 26A is provided to determine whether a random number (i.e., the first number 23A) exceeds a first predetermined number (i.e., the maximum number of activations between two update cycles), and then modifies the random number to a range from 0 to the first predetermined number. The number adjuster 26A modifies the most significant bit of the first number 23A so that the first number 23A can be slightly modified to maintain randomness. The operation of the number adjuster 26A is independent of the processing of the random number generator 23, and therefore does not affect the randomness of the first number 23A.

[0214] Figure 6 A schematic diagram of a digital regulator 26B included in a memory element is shown according to some embodiments of this disclosure. The digital regulator 26B is... Figure 2 An embodiment of the digital adjuster 26 is shown. The digital adjuster 26B is configured to reset the shift register 233 (i.e., the random number generator 23) when the first number 23A is greater than a first predetermined number, so that the modified first number 23B can be reset to zero.

[0215] Digital regulator 26B is similar to digital regulator 26A, except that... Figure 6 In this configuration, the output of logic gate L8 is directly connected to the reset terminal of shift register 233 to reset shift register 233. In some embodiments, the difference between digital adjuster 26A and digital adjuster 26B is that digital adjuster 26A includes AND gate 262.

[0216] As described above, the digital adjuster 26B is configured to determine whether the first digit 23A is greater than a first predetermined digit. When the first digit 23A is determined to be greater than the first predetermined digit (e.g., 170), the output of logic gate L8 (i.e., the determination result 2610) can be transmitted to shift register 233 to reset shift register 233. Therefore, the modified first digit 23B can be reset to zero.

[0217] A number adjuster 26B is provided to determine whether the random number (i.e., the first number 23A) exceeds a first predetermined number (i.e., the maximum number of activations between two update cycles), and then the random number generator 23 is reset so that the random number is zero, which is less than the first predetermined number. Therefore, using the number adjuster 26B, there is a higher probability of obtaining the first accessed character line after the previous update cycle.

[0218] Figure 7 A flowchart of a method 7 for protecting a memory element is shown according to some embodiments of the present disclosure. In some embodiments, method 7 is used to protect a word line included in a memory element. In some embodiments, the memory may include a plurality of word lines.

[0219] In operation 71, a first word line among a plurality of word lines can be updated during a first update cycle in response to an update signal. In some embodiments, the controller of the memory element (e.g., Figure 2 The controller 22 shown can update one or more character lines in each update cycle in response to an update signal. In some embodiments, it can be controlled by... Figure 2 The controller 22 shown is used to perform operation 71.

[0220] In operation 72, a first number can be generated using a random number generator. In some embodiments, the random number generator (e.g., Figure 2 The random number generator 23 shown can be configured to generate a random number based on different signals. In some embodiments, it can be generated by... Figure 2 The random number generator 23 shown is used to perform operation 72.

[0221] In operation 73, when the first number is greater than a first predetermined number, a number adjuster can be used to reduce the first number to a second number. In some embodiments, the second number can be a modified first number. In some embodiments, the first number and the second number can be binary. The difference between the first number and the second number can be a single bit of a binary sequence. For example, the most significant bit (msb) of the first number can be different from the most significant bit of the second number. In another embodiment, the second number can be zero. In some embodiments, it can be... Figure 2 The digital adjuster 26 shown is used to perform operation 73.

[0222] In operation 74, a counter can count down from a second number in response to an update signal. In some embodiments, the counter can be configured to start counting in response to the update signal. The counter can count down from a second number. In some embodiments, each countdown is triggered by an access signal indicating an access to a word line. In some embodiments, it can be... Figure 2 The counter 24 shown is used to perform operation 74.

[0223] In operation 75, when the counter counts to zero, the controller can obtain an address of the accessed second word line. In some embodiments, when the counter counts down to zero, the address of the second word line can be obtained and stored in an address register (e.g., Figure 2 In the address register 25 shown. The controller (e.g., Figure 2 The controller 22 shown can be configured to access the address register and obtain the address of the second word line. In some embodiments, the controller 22 can be configured to have / not have Figure 2 Operation 75 is performed in the case of address register 25 shown.

[0224] In operation 76, in response to an update signal, the third word line can be updated to protect the third word line during the second update cycle, wherein the address of the third word line is adjacent to the address of the second word line. In some embodiments, this can be achieved by... Figure 2 The controller 22 shown performs operation 76.

[0225] To achieve a hammer effect, memory attackers tend to access one or more target word lines at high frequencies. Frequent accesses to the target word line can cause a hammer effect on adjacent word lines. That is, under a hammer effect, even if neighboring word lines are not accessed, their contents may be altered by leaking their charge.

[0226] This disclosure provides a memory element that can identify potentially attacked target word lines and then protect word lines adjacent to the potential target word lines. A random number generator can generate a random number as the initial value of a counter. When the counter reaches zero, the address of the accessed target word line is obtained. Furthermore, to prevent the random number generated by the random number generator from exceeding the maximum number of activations between two update cycles, a number adjuster is provided to modify the random number to within a predetermined range (i.e., the maximum number of activations between two update cycles). Therefore, word lines adjacent to frequently accessed target word lines can be updated to maintain the same content.

[0227] One aspect of this disclosure provides a memory element. The memory element includes: a plurality of word lines; a controller configured to update at least one of the word lines during a first update cycle in response to an update signal; a random number generator configured to generate a first digit; and a digit adjuster connected to the random number generator. The digit adjuster is configured to generate a modified first digit based on the first digit, wherein the modified first digit is less than the first predetermined digit. The memory element further includes a counter electrically coupled to the random number generator and the digit adjuster, wherein the counter is configured to receive the modified first digit as an initial value and is configured to be turned on in response to the update signal. The controller is further configured to obtain an address of the accessed first word line when the counter counts to zero, and update a second word line during a second update cycle, wherein the address of the second word line is adjacent to the address of the first word line.

[0228] Another aspect of this disclosure provides a memory element. The memory element includes: a controller configured to update at least one of a plurality of word lines during a first update cycle in response to an update signal; a random number generator configured to generate a first number; and a number adjuster connected to the random number generator. The number adjuster is configured to modify the first number to a modified first number less than the first predetermined number. The memory element further includes a counter electrically coupled to the random number generator and configured to receive the modified first number as an initial value for the counter and to count from the initial value in response to the update signal; and an address register electrically coupled to the counter and configured to store an address of a first word line activated when the counter decrements to zero. The counter is configured to access the address register to obtain the address of the first word line and to protect a second word line during a second update cycle, wherein an address of the second word line is adjacent to the address of the first word line.

[0229] Another aspect of this disclosure provides a method for protecting a memory element, wherein the memory element includes a plurality of word lines. The method includes: updating a first word line among the word lines during a first update cycle in response to an update signal; generating a first number using a random number generator; reducing the first number to a second number using a number adjuster when the first number is greater than a first predetermined number; counting down from the second number using a counter in response to the update signal; obtaining an address of a second word line being accessed using a controller when the counter counts to zero; and protecting a third word line during a second update cycle in response to the update signal, wherein an address of the third word line is adjacent to the address of the second word line.

[0230] This disclosure provides a memory element with protection circuitry for selecting and protecting bit lines that may be attacked. Specifically, the protection circuitry of the memory element can protect word lines (memory cells) from hammer attacks. To trigger a hammer attack, an attacker rapidly activates the same memory columns, causing inactive adjacent memory columns to potentially leak their charge. This protection circuitry provides a random number generator and a counter to randomly select and protect potential memory columns. The counter can be configured to count down from a random number generated by the random number generator. When the counter counts to zero, the address of the activated memory column is obtained. In other words, the memory columns are selected from those activated memory columns between update cycles. In this case, the selection pool includes memory columns activated between update cycles. Additionally, to prevent the random number generated by the random number generator from exceeding the maximum number of activations between two update cycles, a number adjuster is provided to modify the random number to a range of zero to a predetermined number (i.e., the maximum number of activations between update cycles). Since adjacent memory columns adjacent to those activated memory columns are more likely to experience a hammer attack, they will become the targets of protection in subsequent update cycles.

[0231] Typically, the activation amount that triggers a hammer attack cannot be completed within two update cycles. For example, a memory element with 8192 columns may have approximately 170 activations between two update cycles, and the activation amount for triggering a hammer attack for the same column could be 10,000 or more. Therefore, protecting additional memory columns that may trigger a hammer attack in each update cycle can eliminate the hammer attack problem. Furthermore, the memory element may include a digital adjuster to determine whether the random number used to select a specific column from the memory columns exceeds the maximum number of activations between two update cycles (i.e., 170 in this case), and then reduce the random number to the range of 0 to 170. This improves the security and performance of the memory element.

[0232] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives may be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above may be implemented using different methods, and other processes or combinations thereof may be substituted for many of the processes described above.

[0233] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this publication that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used according to this disclosure. Therefore, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of the claims of this application.

Claims

1. A memory element, comprising: Multiple character lines; A controller is configured to update at least one of the plurality of character lines during a first update cycle in response to an update signal; A random number generator is configured to generate a first number; A number adjuster is connected to the random number generator, wherein the number adjuster is configured to generate a modified first number based on the first number, wherein the modified first number is less than a first predetermined number; as well as A counter, electrically coupled to the random number generator and the digital adjuster, wherein the counter is configured to receive the modified first number as an initial value for the counter and is configured to turn on in response to the update signal. The controller is further configured to obtain an address of a first word line being accessed when the counter counts to zero, and to update a second word line during a second update cycle, wherein the address of the second word line is adjacent to the address of the first word line.

2. The memory element of claim 1, wherein the digital adjuster is configured to reset the random number generator such that the modified first number is reset to zero.

3. The memory element of claim 1, wherein the first number is a positive integer.

4. The memory element of claim 1, wherein the first number is represented by a binary sequence having more than 2 bits.

5. The memory element of claim 4, wherein the first number is represented by an 8-bit binary sequence.

6. The memory element of claim 4, wherein when the first number is greater than the first predetermined number, the number adjuster is configured to reset a most significant bit of the first number.

7. The memory element of claim 6, wherein the digital adjuster comprises: A judgment unit is configured to receive the first number, determine whether the first number is greater than the first predetermined number, and output a judgment result; as well as An AND gate is configured to receive the most significant bit of the first number and the judgment result, and to generate an AND output in response to the most significant bit of the first number and the judgment result. The AND gate is configured to transmit the AND output to the counter as the most significant bit of the modified first digit.

8. The memory element of claim 7, wherein the determining unit comprises: A first part is configured to determine whether a first part of the binary sequence of the first number is greater than a first threshold; A second part is configured to determine whether a second part of the binary sequence of the first number is greater than a second threshold if a first part of the binary sequence of the first number is greater than or equal to a first threshold. as well as A first logic gate is connected to the first portion and the second portion, wherein the first logic gate is configured to generate the determination result.

9. The memory element of claim 1, wherein the digital adjuster includes one or more logic gates.

10. The memory element of claim 1, wherein the first predetermined number is associated with a first time period for accessing a word line and a second time period between the first update cycle and the second update cycle.

11. A memory element, comprising: A controller is configured to update at least one of a plurality of character lines in response to an update signal during a first update cycle; A random number generator is configured to generate a first number; A number adjuster is connected to the random number generator, wherein the number adjuster is configured to modify the first number to a modified first number, wherein the modified first number is less than a first predetermined number; as well as A counter, electrically coupled to the random number generator and configured to receive the modified first number as an initial value for the counter, and to start counting in response to the update signal; as well as An address register, electrically coupled to the counter and configured to store an address of a first word line that is activated when the counter decrements to zero. The counter is configured to access the address register to obtain the address of the first word line and to protect a second word line during a second update cycle, wherein an address of the second word line is adjacent to the address of the first word line.

12. The memory element of claim 11, wherein the digital adjuster is configured to reset the random number generator such that the modified first number is reset to zero.

13. The memory element of claim 11, wherein the first number is a positive integer.

14. The memory element of claim 11, wherein the first number is binary and greater than 2 bits.

15. The memory element of claim 14, wherein the first number is 8 bits.

16. The memory element of claim 14, wherein when the first number is greater than the first predetermined number, the number adjuster is configured to reset a most significant bit of the first number.

17. The memory element of claim 16, wherein the digital adjuster comprises: A judgment unit is configured to receive the first number and determine whether the first number is greater than the first predetermined number, and output a judgment result; as well as An AND gate is configured to receive the most significant bit of the first number and the judgment result, and to generate an AND output in response to the most significant bit of the first number and the judgment result. The AND gate is configured to transmit the AND output to the counter as the most significant bit of the modified first digit.

18. The memory element of claim 17, wherein the determining unit comprises: A first part is configured to determine whether a first part of the binary sequence of the first number is greater than a first threshold; A second part is configured to determine whether a second part of the binary sequence of the first number is greater than a second threshold if a first part of the binary sequence of the first number is greater than or equal to a first threshold. as well as A first logic gate is connected to the first portion and the second portion, wherein the first logic gate is configured to generate the determination result.

19. The memory element of claim 11, wherein the digital adjuster includes one or more logic gates.

20. The memory element of claim 11, wherein the first predetermined number is associated with a first time period for accessing a word line and a second time period between the first update cycle and the second update cycle.

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