Flash memory interference test method, controller and computer readable storage medium

Abstract

The embodiment of the invention provides a flash memory interference test method, a controller and a computer readable storage medium, and the flash memory interference test method simulates different target application scenes such as a mobile equipment application scene, an automobile electronic application scene or an industrial equipment application scene. In addition, the preset interference curve is adopted to perform interference operation on the to-be-tested flash memory, and the interference amplitude parameter is changed along with time in the interference test, so that different application scenes and changed interference degrees can be set to perform interference test on the flash memory product, and the test efficiency is improved. The interference test is more suitable for a complex actual use environment; and secondly, the read-write performance parameter curve of the to-be-tested flash memory is compared with the standard performance parameter curve of the qualified sample flash memory, so that the read-write interference resistance of the to-be-tested flash memory under the target application scene and the preset interference curve is determined, and the read-write interference resistance is more accurate.

Description

Technical Field

[0001] The present application relates to the field of chip testing technology, and in particular to a flash memory interference testing method, a controller and a computer-readable storage medium. Background Art

[0002] In the related art, during the production and development of flash memory products, it is necessary to test the anti-interference ability of the product in order to evaluate its read and write performance and service life. However, the existing interference test methods are often tested in the same application scenario, and the interference level set during the test is often unchanged. Therefore, the existing interference test methods are relatively simple and cannot cope with complex actual use environments. Summary of the invention

[0003] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application proposes a flash memory interference test method, a controller and a computer-readable storage medium, which are intended to set different application scenarios and varying interference levels to perform interference tests on flash memory products, so that the interference test is more suitable for complex actual use environments.

[0004] In a first aspect, an embodiment of the present application provides a flash memory interference test method, comprising: Obtaining a preset interference curve, and performing an interference operation on the flash memory to be tested according to the preset interference curve, wherein the preset interference curve is a variation curve between an interference amplitude parameter and a time parameter; In a target application scenario and during an interference operation on the flash memory to be tested, read and write operations are sequentially performed on each storage page of the flash memory to be tested, wherein the target application scenario includes a mobile device application scenario, an automotive electronics application scenario, or an industrial equipment application scenario; Acquire the read / write performance parameters of the flash memory to be tested under the read / write operation, and generate a read / write performance parameter curve according to the read / write performance parameters, wherein the read / write performance parameter curve is a change curve between the read / write performance parameters and the time parameter; Determine a standard performance parameter curve of a qualified sample flash memory under the target application scenario and the preset interference curve; The read / write performance parameter curve is compared with the standard performance parameter curve, and the read / write interference resistance capability of the flash memory to be tested under the target application scenario and the preset interference curve is determined according to the comparison result.

[0005] According to some embodiments of the present application, determining the anti-read / write disturb capability of the flash memory to be tested under the target application scenario and the preset interference curve according to the comparison result includes: Obtaining a parameter deviation value of the read / write performance parameter curve and the standard performance parameter curve within the same preset time interval; The read / write disturbance resistance capability of the flash memory to be tested under the target application scenario and the preset interference curve is determined according to the parameter deviation value.

[0006] According to some embodiments of the present application, determining the anti-read / write disturb capability of the flash memory to be tested under the target application scenario and the preset interference curve according to the parameter deviation value includes one of the following: When the parameter deviation value of the read / write performance parameter curve and the standard performance parameter curve in the same preset time interval is greater than the preset deviation value, it is determined that the anti-read / write disturb capability of the flash memory to be tested does not meet the requirements; When the parameter deviation value of the read / write performance parameter curve and the standard performance parameter curve within the same preset time interval is less than or equal to the preset deviation value, it is determined that the read / write disturbance resistance capability of the flash memory to be tested meets the requirements.

[0007] According to some embodiments of the present application, determining the anti-read / write disturb capability of the flash memory to be tested under the target application scenario and the preset interference curve according to the comparison result includes: When the read / write performance parameter curve is above the standard performance parameter curve, obtaining the number of curve intersections between the read / write performance parameter curve and the standard performance parameter curve during the entire read / write operation process; The read / write disturbance resistance capability of the flash memory to be tested under the target application scenario and the preset disturbance curve is determined according to the number of curve intersections.

[0008] According to some embodiments of the present application, determining the anti-read / write disturb capability of the flash memory to be tested under the target application scenario and the preset interference curve according to the number of curve intersections includes one of the following: When the number of curve intersections between the read / write performance parameter curve and the standard performance parameter curve during the entire read / write operation is greater than a preset number, it is determined that the read / write interference resistance capability of the flash memory to be tested does not meet the requirements; When the number of curve intersections between the read / write performance parameter curve and the standard performance parameter curve during the entire read / write operation is less than or equal to a preset number, it is determined that the read / write disturbance resistance capability of the flash memory to be tested meets the requirements.

[0009] According to some embodiments of the present application, after determining that the read / write disturbance resistance capability of the flash memory to be tested meets the requirement, the method further includes: Determining a target time interval corresponding to at least one rising curve segment in the preset interference curve; Calculating the rising slope of the preset interference curve in the target time interval; Calculating the descending slope of the read / write performance parameter curve in the target time interval; The anti-interference level of the flash memory to be tested is determined according to the absolute value of the falling slope and the rising slope.

[0010] According to some embodiments of the present application, determining the anti-interference level of the flash memory to be tested according to the absolute value of the falling slope and the rising slope includes: Calculating the absolute value of the descending slope and the slope difference of the ascending slope; The anti-interference level of the flash memory to be tested is determined according to the slope difference, wherein there is a negative correlation between the anti-interference level and the slope difference.

[0011] According to some embodiments of the present application, determining a standard performance parameter curve of a qualified sample flash memory under the target application scenario and the preset interference curve includes: In the case where there are multiple qualified sample flash memories, obtaining sample performance parameter curves of the multiple qualified sample flash memories under the target application scenario and the preset interference curve, and extracting data points of the multiple sample performance parameter curves; generating a curve fitting model, and estimating parameters of the curve fitting model according to a target statistical method; The estimated parameters and all of the data points are input into the curve fitting model to generate a standard performance parameter curve that approximates all of the data points.

[0012] In a second aspect, an embodiment of the present application provides a controller comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the flash memory interference test method of the first aspect when running the computer program.

[0013] In a third aspect, an embodiment of the present application provides a computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions are used to execute the flash memory interference test method as described in the first aspect above.

[0014] In a fourth aspect, an embodiment of the present application provides a computer program product, comprising a computer program or computer instructions, characterized in that the computer program or the computer instructions are stored in a computer-readable storage medium, a processor of a computer device reads the computer program or the computer instructions from the computer-readable storage medium, and the processor executes the computer program or the computer instructions, so that the computer device performs the flash memory interference test method as described in the first aspect above.

[0015] According to the technical solution of the embodiment of the present application, at least the following beneficial effects are achieved: the embodiment of the present application simulates different target application scenarios such as mobile device application scenarios, automotive electronics application scenarios or industrial equipment application scenarios, and also adopts a preset interference curve to perform interference operations on the flash memory to be tested, and realizes the interference amplitude parameter changing over time in the interference test. Therefore, the embodiment of the present application can set different application scenarios and changing interference levels to perform interference tests on flash memory products, making the interference test more in line with the complex actual use environment; secondly, the embodiment of the present application will also compare the read and write performance parameter curve of the flash memory to be tested with the standard performance parameter curve of the qualified sample flash memory, so as to determine the read and write interference resistance of the flash memory to be tested under the target application scenario and the preset interference curve, so that the read and write interference resistance is more accurate.

[0016] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings are used to provide further understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0018] Figure 1 is a flow chart of a flash memory interference testing method provided by an embodiment of the present application; Figure 2 yes Figure 1 A flow chart of sub-steps of an embodiment of step S150; Figure 3 yes Figure 2 Flow chart of sub-steps of step S220; Figure 4 It is a schematic diagram of parameter deviation values ​​of the read / write performance parameter curve and the standard performance parameter curve within the same preset time interval; Figure 5 yes Figure 1 A flowchart of sub-steps of another embodiment of step S150; Figure 6 yes Figure 5 Flow chart of sub-steps of step S520; Figure 7 It is a schematic diagram showing that there is an intersection between the read-write performance parameter curve and the standard performance parameter curve; Figure 8 is a flow chart of an embodiment of the present application for determining the anti-interference level of a flash memory to be tested that meets the anti-interference requirements; Fig. 9 yes Figure 8 Flow chart of sub-steps of step S840; Fig.10 yes Figure 1 A flowchart of sub-steps of an embodiment of step S140; Fig.11 It is a schematic diagram of a controller for executing a flash memory interference test method provided by an embodiment of the present application. DETAILED DESCRIPTION

[0019] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0020] In the description of the present application, it should be understood that descriptions involving orientation, such as up, down, front, back, left, right, etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0021] In the description of this application, "several" means one or more, "more" means more than two, "greater than", "less than", "exceed", etc. are understood to exclude the number itself, and "above", "below", "within", etc. are understood to include the number itself. If there is a description of "first" or "second", it is only used for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0022] In the description of this application, unless otherwise clearly defined, terms such as setting, installing, connecting, etc. should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in this application based on the specific content of the technical solution.

[0023] In some cases, during the production and development of flash memory products, it is necessary to test the anti-interference ability of the product in order to evaluate its read and write performance and service life. However, the existing interference test methods are often tested in the same application scenario, and the interference level set during the test is often unchanged. Therefore, the existing interference test methods are relatively simple and cannot cope with complex actual use environments.

[0024] Based on the above situation, the embodiments of the present application propose a flash memory interference test method, controller and computer-readable storage medium, which aim to set different application scenarios and varying interference levels to perform interference tests on flash memory products, so that the interference test can better fit the complex actual usage environment.

[0025] The following further describes various embodiments of the flash memory interference test method of the present application in conjunction with the accompanying drawings.

[0026] like Figure 1 As shown, Figure 1 1 is a flow chart of a flash memory interference test method provided by an embodiment of the present application. The flash memory interference test method includes but is not limited to step S110, step S120, step S130, step S140 and step S150.

[0027] Step S110, obtaining a preset interference curve, and performing an interference operation on the flash memory to be tested according to the preset interference curve, wherein the preset interference curve is a variation curve between an interference amplitude parameter and a time parameter; Step S120, in the target application scenario and during the interference operation on the flash memory to be tested, read and write operations are performed on each storage page of the flash memory to be tested in sequence, wherein the target application scenario includes a mobile device application scenario, an automotive electronics application scenario, or an industrial equipment application scenario; Step S130, obtaining the read / write performance parameters of the flash memory to be tested under the read / write operation, and generating a read / write performance parameter curve according to the read / write performance parameters, wherein the read / write performance parameter curve is a variation curve between the read / write performance parameters and the time parameter; Step S140, determining a standard performance parameter curve of a qualified sample flash memory under a target application scenario and a preset interference curve; Step S150: compare the read / write performance parameter curve with the standard performance parameter curve, and determine the read / write disturbance resistance capability of the flash memory to be tested under the target application scenario and the preset disturbance curve according to the comparison result.

[0028] In one embodiment, first, the embodiment of the present application will perform read and write operations and interference operations on the flash memory to be tested in the target application scenario and using a preset interference curve, wherein during the read and write operations, the interference amplitude will change with time, and at the same time, the embodiment of the present application will record the read and write performance parameters of the flash memory to be tested under the read and write operations, and generate a read and write performance parameter curve of the flash memory to be tested in response; in addition, the embodiment of the present application will also obtain a standard performance parameter curve of a qualified sample flash memory under the target application scenario and the preset interference curve, and then compare the read and write performance parameter curve of the flash memory to be tested with the standard performance parameter curve of the qualified sample flash memory, so as to determine the read and write interference resistance of the flash memory to be tested under the target application scenario and the preset interference curve.

[0029] In one embodiment, the read / write speed requirement and the random read / write performance requirement are determined according to the scenario type of the target application scenario; and the target test performance parameters are determined according to the read / write speed requirement and the random read / write performance requirement.

[0030] In one embodiment, since the read and write speed requirements and random read and write performance requirements corresponding to target application scenarios of different scenario types are different, the embodiment of the present application needs to first determine the read and write speed requirements and random read and write performance requirements according to the scenario type of the target application scenario, and then determine the target test performance parameters, such as read and write efficiency, error rate, etc., based on the read and write speed requirements and random read and write performance requirements.

[0031] It should be noted that for mobile device test scenarios, the read and write speed requirements, random read and write performance requirements, and application scenarios are as follows: Read and write speed requirements: Mobile devices (such as smartphones and tablets) usually have high requirements for eMMC read and write speeds, especially in scenarios such as launching applications, loading games, and playing high-definition videos. The continuous read speed of eMMC version 5.1 can reach 400MB / s, and the continuous write speed can reach 250MB / s.

[0032] Random read and write performance: In mobile devices, random read and write performance is also very important, especially when processing a large number of small files. The random read IOPS of eMMC 5.1 version can reach 8K, and the random write IOPS can reach 6K.

[0033] Application scenario: Mobile devices focus more on user experience, so low latency and high IOPS are key indicators.

[0034] In addition, it should be noted that for automotive electronics testing scenarios, the read and write speed requirements, random read and write performance requirements, and application scenarios are as follows: Read and write speed requirements: Automotive electronic systems have relatively low requirements for eMMC read and write speeds, but they focus more on reliability and durability. For example, vehicle infotainment systems and instrument panel systems usually do not require extremely high read and write speeds, but need to operate stably in extreme environments.

[0035] Random read and write performance: Automotive electronic systems have moderate requirements for random read and write performance, focusing mainly on data integrity and reliability.

[0036] Application scenarios: Automotive electronic systems focus more on long-term stability and safety rather than extreme performance.

[0037] In addition, it should be noted that for industrial equipment testing scenarios, the read and write speed requirements, random read and write performance requirements, and application scenarios are as follows: Read and write speed requirements: The read and write speed requirements of industrial equipment for eMMC vary depending on the specific application. Some industrial automation equipment may require higher read and write speeds to process large amounts of data, but they are generally not as strict as mobile devices.

[0038] Random read and write performance: Industrial equipment pays more attention to data integrity and low latency, especially in scenarios that require real-time data processing.

[0039] Application scenarios: Industrial equipment usually operates in harsh environments, so high durability and reliability requirements are placed on eMMC.

[0040] In one embodiment, the read / write performance parameters in the read / write performance parameter curve and the standard performance parameter curve may be read / write speed, number of input / output operations per second, or other parameters.

[0041] In one embodiment, if the interference amplitude parameter is larger, the read / write performance parameter is lower; if the interference amplitude parameter is smaller, the read / write performance parameter is higher.

[0042] It is worth noting that the embodiments of the present application simulate different target application scenarios such as mobile device application scenarios, automotive electronics application scenarios, or industrial equipment application scenarios, and also use a preset interference curve to perform interference operations on the flash memory to be tested, and realize the interference amplitude parameter changing over time in the interference test. Therefore, the embodiments of the present application can set different application scenarios and changing interference levels to perform interference tests on flash memory products, making the interference test more in line with the complex actual use environment; secondly, the embodiments of the present application will also compare the read and write performance parameter curve of the flash memory to be tested with the standard performance parameter curve of the qualified sample flash memory, so as to determine the read and write interference resistance of the flash memory to be tested under the target application scenario and the preset interference curve, so that the read and write interference resistance is more accurate.

[0043] In addition, if Figure 2 As shown, Figure 2 yes Figure 1 Sub-step flow chart of an embodiment of step S150 in the above step S150. Determining the anti-read and write disturb capability of the flash memory to be tested under the target application scenario and the preset disturbance curve according to the comparison result may include but is not limited to step S210 and step S220.

[0044] Step S210, obtaining a parameter deviation value of a read / write performance parameter curve and a standard performance parameter curve within the same preset time interval; Step S220: Determine the read / write disturbance resistance capability of the flash memory to be tested under the target application scenario and the preset disturbance curve according to the parameter deviation value.

[0045] In one embodiment, under the same target application scenario and preset interference curve, the embodiment of the present application can compare the read and write performance parameter curve of the flash memory to be tested with the standard performance parameter curve of a qualified sample flash memory. Specifically, part of the read and write performance parameter curve and part of the standard performance parameter curve within a preset time interval can be selected for comparison, and the difference between the part of the read and write performance parameter curve and part of the standard performance parameter curve within the preset time interval, that is, the parameter deviation value, is calculated. Finally, according to the size of the parameter deviation value, it is determined whether the read and write interference resistance capability of the flash memory to be tested under the target application scenario and the preset interference curve meets the requirements.

[0046] In addition, if Figure 3 As shown, Figure 3 yes Figure 2 The above-mentioned step S220 may include but is not limited to step S310 or step S320.

[0047] Step S310: When the parameter deviation value of the read / write performance parameter curve and the standard performance parameter curve within the same preset time interval is greater than the preset deviation value, it is determined that the anti-read / write disturb capability of the flash memory to be tested meets the requirements; Step S320: When the parameter deviation value of the read / write performance parameter curve and the standard performance parameter curve within the same preset time interval is less than or equal to the preset deviation value, it is determined that the read / write disturbance resistance capability of the flash memory to be tested does not meet the requirement.

[0048] In one embodiment, if Figure 4 As shown, Figure 4 It is a schematic diagram of the parameter deviation values ​​of the read-write performance parameter curve B and the standard performance parameter curve A within the same preset time interval. It can be seen that the parameter deviation value within the preset time interval T1 is H1, and H1 is a negative number. If the parameter deviation value H1 is greater than the preset deviation value, it means that the read-write performance parameter curve B within the preset time interval does not deviate far downward from the standard performance parameter curve A. At this time, it can be confirmed that the read-write interference resistance of the flash memory to be tested meets the requirements.

[0049] In one embodiment, if Figure 4 As shown, if the parameter deviation value H1 is less than or equal to the preset deviation value, it means that the read / write performance parameter curve within the preset time interval has deviated far downward from the standard performance parameter curve. At this time, it can be confirmed that the read / write interference resistance capability of the flash memory to be tested does not meet the requirements.

[0050] In addition, if Figure 5 As shown, Figure 5 yes Figure 1The sub-step flow chart of another embodiment of step S150 in the above step S150 may include but is not limited to step S510 and step S520, in terms of determining the anti-read / write disturb capability of the flash memory to be tested under the target application scenario and the preset disturbance curve according to the comparison result.

[0051] Step S510: when the read / write performance parameter curve is above the standard performance parameter curve, obtaining the number of curve intersections between the read / write performance parameter curve and the standard performance parameter curve during the entire read / write operation process; Step S520: Determine the read / write disturbance resistance capability of the flash memory to be tested under the target application scenario and the preset disturbance curve according to the number of curve crossings.

[0052] In one embodiment, under the same target application scenario and preset interference curve, if all the read-write performance parameter curves are above the standard performance parameter curve, it can be confirmed that the read-write interference resistance capability of the flash memory to be tested meets the requirements; if more than a preset proportion of the read-write performance parameter curves are above the standard performance parameter curve, then it is necessary to obtain the intersection of the read-write performance parameter curve of the flash memory to be tested and the standard performance parameter curve of the qualified sample flash memory, such as the number of curve intersections, and finally determine whether the read-write interference resistance capability of the flash memory to be tested under the target application scenario and the preset interference curve meets the requirements based on the number of curve intersections.

[0053] In addition, if Figure 6 As shown, Figure 6 yes Figure 5 The above-mentioned step S520 may include but is not limited to step S610 or step S620.

[0054] Step S610: When the number of curve intersections between the read / write performance parameter curve and the standard performance parameter curve during the entire read / write operation is greater than a preset number, it is determined that the read / write interference resistance capability of the flash memory to be tested does not meet the requirements; Step S620: When the number of curve intersections between the read / write performance parameter curve and the standard performance parameter curve during the entire read / write operation is less than or equal to a preset number, it is determined that the read / write disturbance resistance capability of the flash memory to be tested meets the requirements.

[0055] In one embodiment, if Figure 7 As shown, Figure 7It is a schematic diagram showing that there is an intersection between the read-write performance parameter curve B and the standard performance parameter curve A. There are multiple curve intersection points C between the read-write performance parameter curve B and the standard performance parameter curve A. If the number of curve intersection points C, that is, the number of curve intersections, is greater than the preset number, it indicates that the read-write performance parameter curve B is relatively unstable, that is, the read-write interference resistance capability of the flash memory to be tested is relatively unstable under the target application scenario and the preset interference curve, thereby confirming that the read-write interference resistance capability of the flash memory to be tested does not meet the requirements.

[0056] In one embodiment, if Figure 7 As shown, if the number of curve intersection points C, that is, the number of curve intersections, is less than or equal to the preset number, it indicates that the read-write performance parameter curve B is relatively stable, that is, the read-write interference resistance capability of the flash memory to be tested is relatively stable under the target application scenario and the preset interference curve, thereby confirming that the read-write interference resistance capability of the flash memory to be tested meets the requirements.

[0057] In addition, if Figure 8 As shown, Figure 8 This is a flowchart of an embodiment of the present application for determining the anti-interference level of a flash memory under test that meets the anti-interference requirements; the method also includes but is not limited to step S810, step S820, step S830 and step S840.

[0058] Step S810: after determining that the read / write disturbance resistance capability of the flash memory to be tested meets the requirements, determining a target time interval corresponding to at least one rising curve segment in a preset interference curve; Step S820, calculating the rising slope of the preset interference curve in the target time interval; Step S830, calculating the descending slope of the read / write performance parameter curve in the target time interval; Step S840: Determine the anti-interference level of the flash memory to be tested according to the absolute value of the falling slope and the rising slope.

[0059] In one embodiment, after determining that the read and write interference resistance of the flash memory to be tested meets the requirements, the embodiment of the present application can also grade the anti-interference level of the flash memory to be tested that meets the requirements, as follows: select a target time interval in which the preset interference curve is in an upward trend, wherein, since the preset interference curve is in an upward trend, the read and write performance parameter curve will be in a corresponding downward trend, then calculate the rising slope of the preset interference curve in the target time interval and the falling slope of the read and write performance parameter curve in the target time interval, and finally, compare the absolute value of the falling slope with the rising slope to determine the anti-interference level of the flash memory to be tested.

[0060] In addition, if Fig. 9 As shown, Fig. 9 yes Figure 8The above-mentioned step S840 may include but is not limited to step S910 or step S920.

[0061] Step S910, calculating the absolute value of the descending slope and the slope difference of the ascending slope; Step S920: determining the anti-interference level of the flash memory to be tested according to the slope difference, wherein the anti-interference level and the slope difference are negatively correlated.

[0062] In one embodiment, the embodiment of the present application can calculate the absolute value of the falling slope and the slope difference of the rising slope, and the slope difference can characterize the degree of decline in the read and write performance parameters of the flash memory to be tested during the period of enhanced interference amplitude; the anti-interference level of the flash memory to be tested can be determined based on the slope difference.

[0063] If the absolute value of the falling slope and the slope difference of the rising slope are larger, it indicates that the read and write performance parameters of the flash memory to be tested are less affected by the interference, and the anti-interference level of the flash memory to be tested can be set to the first anti-interference level. If the absolute value of the falling slope and the slope difference of the rising slope are smaller, it indicates that the read and write performance parameters of the flash memory to be tested are more affected by the interference, and the anti-interference level of the flash memory to be tested can be set to the second anti-interference level. The anti-interference ability of the first anti-interference level is higher than the anti-interference ability of the second anti-interference level.

[0064] In addition, if Fig.10 As shown, Fig.10 yes Figure 1 The sub-step flow chart of an embodiment of step S140 in the above step S140 may include but is not limited to step S1010, step S1020 and step S1030, in terms of determining the standard performance parameter curve of the qualified sample flash memory under the target application scenario and the preset interference curve.

[0065] Step S1010: when there are multiple qualified sample flash memories, obtain sample performance parameter curves of the multiple qualified sample flash memories under the target application scenario and the preset interference curve, and extract data points of the multiple sample performance parameter curves; Step S1020, generating a curve fitting model, and estimating parameters of the curve fitting model according to a target statistical method; Step S1030: input the estimated parameters and all data points into a curve fitting model to generate a standard performance parameter curve for approximating all data points.

[0066] In one embodiment, the present application embodiment can generate a standard performance parameter curve through multiple steps such as data collection, selection of fitting model, parameter estimation and curve fitting, which are as follows: Data collection: First, you need to collect data points for multiple curves; these data points can be experimental data, observational data, or simulation data.

[0067] Select a fitting model: Select a suitable mathematical model based on the characteristics of the data and the purpose of fitting; common models include linear models, polynomial models, exponential models, logarithmic models, etc.

[0068] Parameter estimation: Use least squares, maximum likelihood, or other statistical techniques to estimate the parameters of the model; these parameters are what give the model the best fit to all the curve's data points.

[0069] Curve fitting: Substitute the estimated parameters into the model to obtain a standard curve that should pass through or be close to all data points as closely as possible.

[0070] Based on the flash memory interference test methods of the above-mentioned embodiments, various embodiments of the controller, computer-readable storage medium and computer program product of the present application are respectively proposed below.

[0071] like Fig.11 As shown, Fig.11 1 is a schematic diagram of a controller for executing a flash memory interference test method provided by an embodiment of the present application. The controller 100 implemented in the present application includes: a processor 110, a memory 120, and a computer program stored in the memory 120 and executable on the processor 110, wherein: Fig.11 In the figure, a processor 110 and a memory 120 are taken as an example.

[0072] The processor 110 and the memory 120 may be connected via a bus or other means. Fig.11 The example of connecting through bus is taken in the following.

[0073] The memory 120, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer executable programs. In addition, the memory 120 may include a high-speed random access memory, and may also include a non-transitory memory, such as at least one disk storage device, a flash memory device, or other non-transitory solid-state storage device. In some embodiments, the memory 120 may optionally include a memory 120 remotely arranged relative to the processor 110, and these remote memories 120 may be connected to the controller 100 via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0074] Those skilled in the art will understand that Fig.11 The device structure shown in the figure does not constitute a limitation on the controller 100, and may include more or less components than shown in the figure, or combine certain components, or arrange the components differently.

[0075] exist Fig.11 In the controller 100 shown, the processor 110 can be used to call the control program stored in the memory 120, so as to implement the above-mentioned flash memory interference test method. Specifically, the non-transient software program and instructions required to implement the flash memory interference test method of the above-mentioned embodiment are stored in the memory 120, and when executed by the processor 110, the flash memory interference test method of the above-mentioned embodiment is executed.

[0076] It is worth noting that since the controller 100 of the embodiment of the present application can execute the flash memory interference test method of any of the above-mentioned embodiments, the specific implementation manner and technical effects of the controller 100 of the embodiment of the present application can refer to the specific implementation manner and technical effects of the flash memory interference test method of any of the above-mentioned embodiments.

[0077] In addition, an embodiment of the present application further provides a computer-readable storage medium, which stores computer-executable instructions, and the computer-executable instructions are used to execute the above-mentioned flash memory interference test method. Figures 1 to 3 , Figures 5 and 6 , Figures 8 to 10 The method steps in .

[0078] It is worth noting that since the computer-readable storage medium of the embodiments of the present application can execute the flash memory interference test method of any of the above-mentioned embodiments, the specific implementation methods and technical effects of the computer-readable storage medium of the embodiments of the present application can refer to the specific implementation methods and technical effects of the flash memory interference test method of any of the above-mentioned embodiments.

[0079] In addition, an embodiment of the present application further provides a computer program product, including a computer program or a computer instruction, the computer program or the computer instruction is stored in a computer-readable storage medium, the processor of the computer device reads the computer program or the computer instruction from the computer-readable storage medium, and the processor executes the computer program or the computer instruction, so that the computer device executes the above-described flash memory interference test method. Exemplarily, the execution of the above-described Figures 1 to 3 , Figures 5 and 6 , Figures 8 to 10 The method steps in .

[0080] It is worth noting that since the computer program product of the embodiments of the present application can execute the flash memory interference test method of any of the above-mentioned embodiments, the specific implementation methods and technical effects of the computer program product of the embodiments of the present application can refer to the specific implementation methods and technical effects of the flash memory interference test method of any of the above-mentioned embodiments.

[0081] It will be appreciated by those skilled in the art that all or some of the steps and systems in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or transient medium). As known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically include computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0082] It should be understood that in the present application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0083] In several embodiments provided in the present application, it should be understood that the disclosed systems, apparatuses and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely schematic, for example, the division of units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of apparatuses or units, which can be electrical, mechanical or other forms. The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the scheme of this embodiment.

[0084] It should also be understood that the various implementations provided in the embodiments of the present application can be combined arbitrarily to achieve different technical effects.

[0085] The above is a specific description of the preferred implementation of the present application, but the present application is not limited to the above implementation mode. Technical personnel familiar with the field can also make various equivalent modifications or substitutions under the shared conditions without violating the spirit of the present application. These equivalent modifications or substitutions are all included in the scope defined by the claims of the present application.

Claims

1. A flash memory interference test method, characterized in that: include: Obtaining a preset interference curve, and performing an interference operation on the flash memory to be tested according to the preset interference curve, wherein the preset interference curve is a variation curve between an interference amplitude parameter and a time parameter; In a target application scenario and during an interference operation on the flash memory to be tested, read and write operations are sequentially performed on each storage page of the flash memory to be tested, wherein the target application scenario includes a mobile device application scenario, an automotive electronics application scenario, or an industrial equipment application scenario; Acquire the read / write performance parameters of the flash memory to be tested under the read / write operation, and generate a read / write performance parameter curve according to the read / write performance parameters, wherein the read / write performance parameter curve is a change curve between the read / write performance parameters and the time parameter; Determine a standard performance parameter curve of a qualified sample flash memory under the target application scenario and the preset interference curve; The read / write performance parameter curve is compared with the standard performance parameter curve, and the read / write interference resistance capability of the flash memory to be tested under the target application scenario and the preset interference curve is determined according to the comparison result.

2. The method according to claim 1, characterized in that The step of determining the anti-read / write disturb capability of the flash memory to be tested under the target application scenario and the preset disturbance curve according to the comparison result includes: Obtaining a parameter deviation value of the read / write performance parameter curve and the standard performance parameter curve within the same preset time interval; The read / write disturbance resistance capability of the flash memory to be tested under the target application scenario and the preset interference curve is determined according to the parameter deviation value.

3. The method according to claim 2, characterized in that The step of determining the anti-read / write disturb capability of the flash memory to be tested under the target application scenario and the preset disturbance curve according to the parameter deviation value includes one of the following: When the parameter deviation value of the read / write performance parameter curve and the standard performance parameter curve within the same preset time interval is greater than the preset deviation value, it is determined that the anti-read / write disturb capability of the flash memory to be tested meets the requirements; When the parameter deviation value of the read / write performance parameter curve and the standard performance parameter curve within the same preset time interval is less than or equal to the preset deviation value, it is determined that the read / write disturbance resistance capability of the flash memory to be tested does not meet the requirements.

4. The method according to claim 1, characterized in that: The step of determining the anti-read / write disturb capability of the flash memory to be tested under the target application scenario and the preset disturbance curve according to the comparison result includes: When the read / write performance parameter curve is above the standard performance parameter curve, obtaining the number of curve intersections between the read / write performance parameter curve and the standard performance parameter curve during the entire read / write operation process; The read / write disturbance resistance capability of the flash memory to be tested under the target application scenario and the preset disturbance curve is determined according to the number of curve intersections.

5. The method according to claim 4, characterized in that Determining the anti-read / write disturb capability of the flash memory to be tested under the target application scenario and the preset disturbance curve according to the number of curve intersections includes one of the following: When the number of curve intersections between the read / write performance parameter curve and the standard performance parameter curve during the entire read / write operation is greater than a preset number, it is determined that the read / write interference resistance capability of the flash memory to be tested does not meet the requirements; When the number of curve intersections between the read / write performance parameter curve and the standard performance parameter curve during the entire read / write operation is less than or equal to a preset number, it is determined that the read / write disturbance resistance capability of the flash memory to be tested meets the requirements.

6. The method according to claim 3 or 5, characterized in that: After determining that the read / write disturbance resistance capability of the flash memory to be tested meets the requirement, the method further includes: Determining a target time interval corresponding to at least one rising curve segment in the preset interference curve; Calculating the rising slope of the preset interference curve in the target time interval; Calculating the descending slope of the read / write performance parameter curve in the target time interval; The anti-interference level of the flash memory to be tested is determined according to the absolute value of the falling slope and the rising slope.

7. The method according to claim 6, characterized in that The step of determining the anti-interference level of the flash memory to be tested according to the absolute value of the falling slope and the rising slope comprises: Calculating the absolute value of the descending slope and the slope difference of the ascending slope; The anti-interference level of the flash memory to be tested is determined according to the slope difference, wherein there is a negative correlation between the anti-interference level and the slope difference.

8. The method according to claim 1, characterized in that The step of determining a standard performance parameter curve of a qualified sample flash memory under the target application scenario and the preset interference curve includes: In the case where there are multiple qualified sample flash memories, obtaining sample performance parameter curves of the multiple qualified sample flash memories under the target application scenario and the preset interference curve, and extracting data points of the multiple sample performance parameter curves; generating a curve fitting model, and estimating parameters of the curve fitting model according to a target statistical method; The estimated parameters and all of the data points are input into the curve fitting model to generate a standard performance parameter curve that approximates all of the data points.

9. A controller, characterized in that: include: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the flash memory interference test method according to any one of claims 1 to 8 when executing the computer program.

10. A computer-readable storage medium, characterized in that: Computer executable instructions are stored, and the computer executable instructions are used to execute the flash memory interference test method as described in any one of claims 1 to 8.

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