Semiconductor packaging structure

Abstract

A semiconductor package structure includes a package substrate and a semiconductor chip. The package substrate includes a core structure, a heat sink, and a redistribution layer. The heat sink is embedded in the core structure. The redistribution layer includes a thermal via disposed on the heat sink. The semiconductor chip is disposed on the package substrate and is thermally coupled with the heat sink through the thermal through-hole.

Description

Technical Field

[0001] The present invention relates to semiconductor technology, and in particular to a semiconductor packaging structure including a heat sink. Background Art

[0002] In addition to protecting semiconductor chips from environmental pollutants, semiconductor packaging structures can also provide electrical connections between the semiconductor chips packaged therein and substrates such as printed circuit boards (PCBs).

[0003] Although existing semiconductor packaging structures generally meet the requirements, they are not satisfactory in various aspects. For example, if the heat generated during the operation of the semiconductor chip is not fully dissipated, the temperature increase may cause damage to the semiconductor components and may cause thermal stress and warping of the semiconductor packaging structure. However, some semiconductor components are not made of materials with good thermal conductivity, which leads to low heat dissipation efficiency. Therefore, further improvements are needed to the semiconductor packaging structure. Summary of the invention

[0004] A semiconductor package structure is provided. An exemplary embodiment of a semiconductor package structure includes a package substrate and a semiconductor chip. The package substrate includes a core structure, a heat sink and a redistribution layer. The heat sink is embedded in the core structure. The redistribution layer includes a thermal via arranged on the heat sink. The semiconductor chip is arranged on the package substrate and is thermally coupled to the heat sink through the thermal via.

[0005] Another embodiment of a semiconductor packaging structure includes a first redistribution layer, a heat sink, a second redistribution layer and a first semiconductor chip. The heat sink is arranged on the first redistribution layer. The second redistribution layer is arranged on the heat sink and includes a thermal via. The first semiconductor chip is arranged on the second redistribution layer and is thermally coupled to the heat sink through the first thermal via. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present invention may be more fully understood by reading the following detailed description and referring to the accompanying drawings, in which:

[0007] Figures 1A to 1G are cross-sectional views of various stages of manufacturing an exemplary semiconductor package structure according to some embodiments of the present disclosure;

[0008] Figure 2 is a cross-sectional view of an exemplary semiconductor package structure according to some embodiments of the present disclosure;

[0009] Figure 3 is a cross-sectional view of an exemplary semiconductor package structure according to some embodiments of the present disclosure;

[0010] Figure 4 is a top view of an exemplary semiconductor package structure according to some embodiments of the present disclosure;

[0011] FIG. 5A to FIG. 5E are cross-sectional views of various stages of manufacturing an exemplary semiconductor package structure according to some embodiments of the present disclosure;

[0012] Figure 6 is a cross-sectional view of an exemplary semiconductor package structure according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0013] The following description is intended to illustrate the general principles of the invention and should not be considered limiting. The scope of the invention is best determined by the appended claims.

[0014] The present disclosure will be described in conjunction with specific embodiments and certain illustrations, but the present disclosure is not limited thereto and is limited only by the claims. The illustrations described are only illustrative and not restrictive. In the illustrations, the sizes of certain elements may be exaggerated and not drawn to scale for illustrative purposes. The sizes and relative sizes may not be consistent with the descriptions in the present disclosure in actual applications.

[0015] Additional elements may be added based on the embodiments described below. For example, the description of "a first element is on / on a second element" may include an embodiment in which the first element is in direct contact with the second element, or an embodiment in which an additional element is arranged between the first element and the second element so that the first element and the second element are not in direct contact.

[0016] In addition, the description of "a first element extends through a second element" may include embodiments in which the first element is arranged in the second element and extends from one side of the second element to the other side, wherein a surface of the first element may be substantially flush with a surface of the second element, or a surface of the first element may be outside a surface of the second element.

[0017] The spatial relative description of the first element and the second element may change as the structure is operated or used in different directions. In addition, the present disclosure may reuse reference numbers and / or letters in various embodiments. This repetition is for simplicity and clarity and does not itself determine the relationship between the various embodiments discussed.

[0018] A semiconductor package structure including a heat sink is described according to some embodiments of the present disclosure. The heat sink is used to replace semiconductor components that do not have good thermal conductive materials, including the core structure of the package substrate, molding materials, etc. Therefore, the heat dissipation efficiency can be improved.

[0019] Figures 1A to 1G1 is a cross-sectional view of various stages of manufacturing a semiconductor package structure 100 according to some embodiments of the present disclosure. Additional features may be added to the semiconductor package structure 100. Some of the features described below may be replaced or omitted in different embodiments. To simplify the illustration, only a portion of the semiconductor package structure 100 is shown.

[0020] like Figure 1A As shown, according to some embodiments, a core structure 102 is provided. The core structure 102 may be formed of an organic material, a glass material, a ceramic material, a semiconductor material, or the like, or a combination thereof. The organic material may include a glass fiber resin (e.g., FR4), a bismaleimide triazine (BT) resin, or the like, or a combination thereof. The semiconductor material may include silicon, germanium, or a compound material, including silicon germanium, silicon carbide, gallium arsenide, silicon germanium carbon, or the like, or a combination thereof.

[0021] Then, according to some embodiments, a plurality of openings 104 are formed in the core structure 102. The openings 104 may be formed through the core structure 102 by laser drilling or any suitable method. Thereafter, a plurality of vias 106 may be formed by plating metal (e.g., copper, silver, gold, etc., or alloys or combinations thereof) on at least the sidewalls of the openings 104.

[0022] Then, if Figure 1B As shown, according to some embodiments, a plurality of insulating plugs 108 are formed in each through hole 106. The insulating plugs 108 may be formed by filling an insulating material (such as a resin) in a space surrounded by the through hole 106 and then polishing to form a flat surface.

[0023] Afterwards, if Figure 1C As shown, according to some embodiments, a metal layer is formed on the opposite surface of the insulating plug 108 by metallization or any suitable method. The metal layer can be formed of a material similar to that of the via 106, including copper, silver, gold, etc. or alloys or combinations thereof.

[0024] Then, if Figure 1D As shown, a cavity 103 can be formed in the core structure 102 by laser drilling or any suitable method. Afterwards, according to some embodiments, a heat sink 110 is arranged in the cavity 103. The heat sink 110 can be embedded in the core structure 102, and thus can be referred to as an embedded heat sink. The heat sink 110 can be formed of a material with high thermal conductivity and specific heat capacity to provide more thermal capacity. For example, the heat sink 110 can be formed of a metal, including copper, silver, gold, etc., or alloys or combinations thereof.

[0025] like Figure 1DAs shown, the bottom surface of the core structure 102 can be substantially aligned with the bottom surface of the heat sink 110. The top surface of the core structure 102 can be substantially aligned with the top surface of the heat sink 110. The thickness D1 of the core structure 102 can be substantially equal to the thickness D2 of the heat sink 110. This allows subsequent layers (such as redistribution layers) to be formed on a flat surface.

[0026] Similarly, one or more active and passive devices (not shown) may be arranged in the core structure 102 according to the structural and functional requirements of the design. For example, the active and passive devices may include transistors, capacitors, resistors, etc. or a combination thereof.

[0027] Then, according to some embodiments, a dielectric layer 112 is formed on the opposite surface of the core structure 102 and fills the remaining space in the cavity 103. The dielectric layer 112 may extend between the core structure 102 and the heat sink 110 to separate them. The dielectric layer 112 may be a laminated film and may be formed of a polymer or any suitable material.

[0028] Afterwards, if Figure 1E As shown, more dielectric layers 112 can be formed and patterned to form openings (not shown). These openings can be through holes or trenches. Then, wiring layers 114 can be formed in the openings. Wiring layers 114 can include horizontal interconnects, such as conductive layers or conductive pads, and vertical interconnects, such as conductive vias. Conductive vias can electrically couple conductive layers and conductive pads of different levels. Wiring layers 114 can be formed by electroplating or any suitable method. Wiring layers 114 can be made of materials similar to through holes 106, including copper, silver, gold, etc. or their alloys or combinations.

[0029] Afterwards, according to some embodiments, a plurality of thermal vias 116 are formed and contact the heat sink 110. Then, a plurality of heat dissipation pads 118 may be formed on the thermal vias 116. The thermal vias 116 and the heat dissipation pads 118 may be formed by electroplating or any suitable method when forming the wiring layer 114. The thermal vias 116 and the heat dissipation pads 118 may be made of metal, including copper, silver, gold, etc. or alloys or combinations thereof. The dielectric layer 112, the wiring layer 114, the thermal vias 116, and the heat dissipation pads 118 may be referred to as redistribution layers. The thermal vias 116 and the heat dissipation pads 118 may be thermally coupled to the heat sink 110. The thermal vias 116 and the heat dissipation pads 118 may be connected to ground without an electrical signal passing therethrough.

[0030] Afterwards, if Figure 1F As shown, according to some embodiments, a solder resist layer 120 is formed on the dielectric layer 112 to protect the redistribution layer from external damage. A plurality of openings can be formed in the solder resist layer 120 by photolithography or any suitable method to expose the heat dissipation pad 118 and the conductive pad of the wiring layer 114.

[0031] Then, a plurality of solder connectors 122 may be formed in the openings and contact the heat dissipation pad 118 and the conductive pads of the wiring layer 114. The solder connectors 122 may include solder balls or other conductive connectors. The solder connectors 122 may be placed in a row and column grid array by a printing process or any suitable method to form a package substrate 101.

[0032] Afterwards, if Figure 1G As shown, according to some embodiments, a semiconductor chip 126 is arranged on the package substrate 101. In some embodiments, the semiconductor chip 126 includes a system-on-chip (SoC) chip, a logic device, a memory device, a radio frequency (RF) device, the like, or any combination thereof. For example, the semiconductor chip 126 may include a micro control unit (MCU) chip, a microprocessor unit (MPU) chip, a power management integrated circuit (PMIC) chip, a radio frequency front end (RFFE) chip, an accelerated processing unit (APU) chip, a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, an input-output (IO) chip, a dynamic random access memory (DRAM) controller, a static random access memory (SRAM), a high bandwidth memory (HBM), an application processor (AP) chip, an application specific integrated circuit (ASIC) chip, the like, or any combination thereof.

[0033] It should be noted that one semiconductor chip 126 is only used for illustration purposes, and two or more semiconductor chips may be arranged on the package substrate 101. In addition, one or more passive components (such as resistors, capacitors, or inductors) may also be arranged on the package substrate 101.

[0034] A plurality of conductive connectors 124 may be formed under the semiconductor chip 126 to connect the solder connectors 122. The conductive connectors 124 may include micro flip-chips, controlled collapse chip connections (C4) flip-chips, conductive pillars, the like, or any combination thereof. The conductive connectors 124 may be made of metals such as tungsten, titanium, tantalum, ruthenium, cobalt, copper, aluminum, platinum, tin, silver, gold, the like, alloys thereof, or any combination thereof.

[0035] A plurality of conductive terminals 128 may be arranged on a surface of the package substrate 101 opposite to the semiconductor chip 126. A semiconductor package structure 100 is formed. The conductive terminals 128 may include micro flip-chip, controlled collapse chip connection (C4) flip-chip, solder balls, ball grid array (BGA) balls, the like, or any combination thereof. The conductive terminals 128 may be made of metal, such as tungsten, titanium, tantalum, ruthenium, cobalt, copper, aluminum, platinum, tin, silver, gold, the like, alloys thereof, or any combination thereof.

[0036] Therefore, as shown by arrow 130, heat from semiconductor chip 126 can be transferred to heat sink 110 through thermal pad 118 and thermal via 116, and can be further transferred to conductive terminal 128. Since heat sink 110 is made of a material with higher thermal conductivity than core structure 102, the system thermal budget of package substrate 101 can be increased. In addition, a fast heat dissipation path can be provided.

[0037] Figure 2 is a cross-sectional view of a semiconductor package structure 200 according to some embodiments of the present disclosure. It should be noted that the semiconductor package structure 200 may include Figure 1G For the sake of simplicity, the components of the semiconductor package structure 100 shown are the same or similar, and these components will not be discussed in detail. In the following embodiments, the thickness of the heat sink is greater than the thickness of the core structure.

[0038] like Figure 2 As shown, according to some embodiments, the heat sink 202 is embedded in the core structure 102. The thickness D3 of the heat sink 202 may be greater than the thickness D1 of the core structure 102 to improve heat dissipation efficiency. Due to the process of forming the heat sink 202, the bottom surface of the heat sink 202 may be substantially aligned with the bottom surface of the core structure 102. The top surface of the heat sink 202 may be higher than the top surface of the core structure 102. The thickness D3 of the heat sink 202 may be substantially equal to the sum of the thickness D1 of the core structure 102 and the thickness of at least one wiring layer 114. The top surface of the heat sink 202 may be substantially aligned with the upper layer of the wiring layer 114, which helps the subsequent process of forming the redistribution layer.

[0039] Figure 3 is a cross-sectional view of a semiconductor package structure 300 according to some embodiments of the present disclosure. It should be noted that the semiconductor package structure 300 may include Figure 1G For simplicity, the components of the semiconductor package structure 100 shown are the same or similar, and will not be discussed in detail. In the following embodiments, the thickness of the heat sink is less than the thickness of the core structure.

[0040] like Figure 3 As shown, according to some embodiments, heat sink 302 is embedded in core structure 102. Thickness D4 of heat sink 302 may be less than thickness D1 of core structure 102. Due to the process of forming heat sink 302, the bottom surface of heat sink 302 may be substantially aligned with the bottom surface of core structure 102. The top surface of heat sink 302 may be lower than the top surface of core structure 102.

[0041] Thermal vias 116 that contact heat sink 302 may extend into core structure 102. In some embodiments, Figure 3 As shown, the thickness of the bottommost thermal via 116 is greater than the thickness of the other thermal vias 116. Alternatively, in some other embodiments, additional thermal vias 116 (not shown) are embedded in the core structure 102, and the thickness of the bottommost thermal via 116 is substantially equal to the thickness of the other thermal vias 116.

[0042] Figure 4 is a top view of a semiconductor package structure 400 according to some embodiments of the present disclosure. It should be noted that the semiconductor package structure 400 may include Figure 1G For simplicity, the components of the semiconductor package structure 100 are the same or similar, and will not be discussed in detail. The description of the semiconductor package structure 400 can be applied to any semiconductor package structure of the present disclosure.

[0043] like Figure 4 As shown, semiconductor package structure 400 may include heat sinks 110a and 110b vertically overlapped by semiconductor chip 126. Semiconductor chip 126 may include hot spots 130 and 132, which may be central processing unit (CPU) cores or similar structures. Heat sinks 110a and 110b may be arranged below hot spots 130 and 132, respectively. Heat sinks 110a and 110b may be arranged to vertically overlap by hot spots 130 and 132 to improve heat dissipation efficiency.

[0044] In some embodiments, the area of ​​the heat sink 110a is smaller than the area of ​​the hot spot 130, so that the heat dissipation efficiency can be improved while the package substrate (such as Figure 1G More wiring layers (such as Figure 1GIn some embodiments, the area of ​​the heat sink 110b is larger than the area of ​​the hot spot 132, so that the heat dissipation efficiency can be further improved.

[0045] Figures 5A to 5E 5 is a cross-sectional view of various stages of manufacturing a semiconductor package structure 500 according to some embodiments of the present disclosure. It should be noted that the semiconductor package structure 500 may include Figure 1G For simplicity, the components of the semiconductor package structure 100 shown are the same or similar, and will not be discussed in detail. In the following embodiments, the heat sink is used to partially replace the molding material.

[0046] like Figure 5A As shown, according to some embodiments, a first redistribution layer 506 is formed on a carrier substrate 502 by a glue layer 504. The carrier substrate 502 may be made of silicon, glass, ceramic, or any suitable material. The glue layer 504 may be made of a polymer-based material and may be removed from the first redistribution layer 506 together with the carrier substrate 502. For example, the glue layer 504 may be made of a material that loses adhesion when heated or exposed to ultraviolet light.

[0047] The first redistribution layer 506 may include a wiring layer 506M arranged in a dielectric layer 506D. The dielectric layer 506D may be made of a polymer, including polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), epoxy resin, the like, or a combination thereof. Alternatively, the dielectric layer 506D may be made of silicon oxide, silicon nitride, silicon oxynitride, the like, or a combination thereof. The dielectric layer 506D may be formed by spin coating, chemical vapor deposition (CVD), or other suitable deposition methods. Then, the dielectric layer 506D may be patterned.

[0048] Then, wiring layer 506M can be formed in dielectric layer 506D by electroplating, chemical vapor deposition (CVD), physical vapor deposition (PVD), or other suitable deposition methods. Wiring layer 506M can include horizontal interconnects, such as conductive layers or conductive pads, and vertical interconnects, such as conductive vias. Conductive vias can electrically couple different levels of conductive layers and conductive pads. Wiring layer 506M can be made of metal, including tungsten, titanium, tantalum, ruthenium, cobalt, copper, aluminum, platinum, tin, silver, gold, the like, alloys thereof, or any combination thereof.

[0049] The first redistribution layer 506 may include a plurality of thermal vias 508. The thermal vias 508 may be formed during the process of forming the wiring layer 506M. The thermal vias 508 may be made of the same or similar material as the wiring layer 506M, such as metal. The thermal vias 508 may be connected to the ground without an electrical signal passing therethrough.

[0050] Then, if Figure 5BAs shown, a plurality of conductive pillars 512 are formed on the first redistribution layer 506 and electrically coupled to the conductive pads of the wiring layer 506M according to some embodiments. The conductive pillars 512 can be made of metal, such as tungsten, titanium, tantalum, ruthenium, cobalt, copper, aluminum, platinum, tin, silver, gold, the like, alloys thereof, or any combination thereof. The conductive pillars 512 can be formed by electroplating, CVD, PVD, or other suitable deposition methods.

[0051] According to some embodiments, the heat sink 514 is arranged on the first redistribution layer 506 and is thermally coupled to the thermal vias 508. The heat sink 514 can be made of a metal, such as tungsten, titanium, tantalum, ruthenium, cobalt, copper, aluminum, platinum, tin, silver, gold, the like, alloys thereof, or any combination thereof. In some embodiments, the heat sink 514 is a preformed metal block that is then attached to the first redistribution layer 506 via an adhesive layer, comprising a thermal interface material (TIM), Tin (Sn), or any suitable material. In some other embodiments, the heat sink 514 is formed by electroplating, CVD, PVD, or other suitable deposition methods, and is formed during the formation of the conductive pillar 512.

[0052] Then, according to some embodiments, a bridge structure 516 is formed on the first redistribution layer 506. The bridge structure 516 may be a bridge chip and may include a silicon body and a redistribution layer (not shown) formed on the silicon body. The redistribution layer may include a connection structure in one or more dielectric layers to electrically couple two semiconductor chips.

[0053] The bridge structure 516 may include an interconnect structure, such as a plurality of vias 518. The interconnect structure in the bridge structure 516 may have other configurations. The vias 518 may be made of a metal including tungsten, titanium, tantalum, ruthenium, cobalt, copper, aluminum, platinum, tin, silver, gold, the like, alloys thereof, or any combination thereof.

[0054] A plurality of conductive pads 520 may be formed on the front side surface of the bridge structure 516 and may be electrically coupled to the vias 518. The conductive pads 520 may be made of a metal such as tungsten, titanium, tantalum, ruthenium, cobalt, copper, aluminum, platinum, tin, silver, gold, the like, alloys thereof, or any combination thereof.

[0055] According to some embodiments, a passivation layer 522 is formed on the front side surface of the bridge structure 516. The passivation layer 522 may cover the edge portion of the conductive pad 520 and may partially expose the conductive pad 520. In some embodiments, the passivation layer 522 may include a polymer layer, which may be made of polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), epoxy resin, the like, or a combination thereof. Alternatively, the passivation layer 522 may include a dielectric layer, which may be made of silicon oxide, silicon nitride, silicon oxynitride, the like, or a combination thereof.

[0056] The bridging structure 516 can be electrically coupled to the wiring layer 506M through a conductive pad 520, a plurality of conductive connectors 524, and a plurality of solder connectors 526. The solder connector 526 can include a solder ball. The conductive connector 524 can include a microbump, a controlled collapse chip connection (C4) bump, a solder ball, a ball grid array (BGA) ball, the like, or a combination thereof. The conductive connector 524 can be made of a metal including tungsten, titanium, tantalum, ruthenium, cobalt, copper, aluminum, platinum, tin, silver, gold, the like, an alloy thereof, or any combination thereof. The conductive connector 524 can be partially surrounded by a passivation layer 522.

[0057] According to some embodiments, an underfill material 528 may be formed between the bridging structure 516 and the first redistribution layer 506. The underfill material 528 may surround each conductive connector 524 and the solder connector 526 to provide structural support. The underfill material 528 may be made of a polymer, including epoxy, polyimide, polybenzoxazole (PBO), the like, or a combination thereof. The underfill material 528 may be dispensed by capillary force and then may be cured by any suitable curing process.

[0058] Then, if Figure 5C As shown, according to some embodiments, a molding material 530 is formed on the first redistribution layer 506. The molding material 530 can surround each conductive pillar 512, the bridge structure 516, and the heat sink 514. The molding material 530 can protect these components from environmental influences, thereby protecting them from damage by stress, chemicals, and moisture. The molding material 530 can be made of a non-conductive material, including a moldable polymer, an epoxy resin, a resin, a similar material, or a combination thereof.

[0059] Afterwards, according to some embodiments, the molding material 530 is planarized until the top surfaces of the conductive pillar 512, the heat sink 514, and the through hole 518 are exposed. The planarization process may include a chemical mechanical polishing (CMP) process, a mechanical polishing process, a similar process, or a combination thereof. The top surface of the conductive pillar 512, the top surface of the heat sink 514, the top surface of the bridge structure 516, and the top surface of the through hole 518 may be substantially coplanar.

[0060] like Figure 5C As shown, in a direction perpendicular to the top surface of the first redistribution layer 506, the heat sink 514 may have a thickness T1, one conductive pillar 512 may have a thickness T2, and the bridge structure 516 may have a thickness T3. The thickness T1 of the heat sink 514 may be substantially equal to the thickness T2 of one conductive pillar 512. The thickness T1 of the heat sink 514 may be greater than the thickness T3 of the bridge structure 516. The thickness T2 of one conductive pillar 512 may be greater than the thickness T3 of the bridge structure 516.

[0061] Then, according to some embodiments, a second redistribution layer 532 is formed on the bridge structure 516. The second redistribution layer 532 may include a wiring layer 532M arranged in a dielectric layer 532D. The dielectric layer 532D and the wiring layer 532M may be similar to the dielectric layer 506D and the wiring layer 506M, respectively, and will not be described in detail here. The wiring layer 532M may be electrically coupled to the wiring layer 506M through the conductive pillar 512 and the through hole 518.

[0062] The second redistribution layer 532 may include a plurality of thermal vias 534 and a heat dissipation pad 536. The thermal vias 534 and the heat dissipation pad 536 may be formed during the formation of the wiring layer 532M. The thermal vias 534 and the heat dissipation pad 536 may be made of the same or similar material as the wiring layer 532M, such as metal. The thermal vias 534 and the heat dissipation pad 536 may be connected to the ground without an electrical signal passing therethrough.

[0063] Then, if Figure 5DAs shown, according to some embodiments, semiconductor chips 538 and 540 are formed on the second redistribution layer 532. In some embodiments, each of the semiconductor chips 538 and 540 independently includes a system-on-chip (SoC) chip, a logic device, a memory device, a radio frequency (RF) device, the like, or any combination thereof. For example, each of the semiconductor chips 538 and 540 may include a micro control unit (MCU) chip, a microprocessor unit (MPU) chip, a power management integrated circuit (PMIC) chip, a radio frequency front end (RFFE) chip, an accelerated processing unit (APU) chip, a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, an input-output (IO) chip, a dynamic random access memory (DRAM) controller, a static random access memory (SRAM), a high bandwidth memory (HBM), an application processor (AP) chip, an application specific integrated circuit (ASIC) chip, the like, or any combination thereof. The semiconductor chips 538 and 540 may include the same or different devices.

[0064] It should be noted that the two semiconductor chips 538 and 540 are only used for illustration purposes, and more than two semiconductor chips and / or one or more passive components (eg, resistors, capacitors, or inductors) may be arranged on the second redistribution layer 532 .

[0065] A plurality of conductive pads 542 may be formed on the front side of the semiconductor chips 538 and 540. A passivation layer 544 may be formed on the front side of the semiconductor chips 538 and 540. The passivation layer 544 may cover edge portions of the conductive pads 542 and partially expose the conductive pads 542. The conductive pads 542 and the passivation layer 544 may be similar to the conductive pads 520 and the passivation layer 522, respectively, and will not be described in detail herein.

[0066] The semiconductor chips 538 and 540 can be electrically coupled to the wiring layer 532M through a plurality of conductive connectors 546. The conductive connectors 546 can include micro flip-chips, controlled collapse chip connections (controlled collapse chip connections, referred to as C4) flip-chips, solder balls, ball grid arrays (BGA) balls, the like, or any combination thereof. The conductive connectors 546 can be made of metal. The conductive connectors 546 can be partially surrounded by the passivation layer 544.

[0067] Semiconductor chips 538 and 540 may be arranged on opposite sides of the bridge structure 516. The semiconductor chips 538 and 540 may respectively partially overlap the bridge structure 516 and may be electrically coupled to each other through the conductive pad 542, the conductive connector 546, the wiring layer 532M, and the bridge structure 516.

[0068] An underfill material 550 is formed between the semiconductor chips 538, 540 and the second redistribution layer 532 according to some embodiments. The underfill material 550 can surround each conductive connector 546 to provide structural support. In some embodiments, the underfill material 550 includes a non-conductive film. An underfill material 550 can be arranged under the semiconductor chips 538, 540 as shown. Alternatively, two independent underfill materials 550 can be arranged under each semiconductor chip 538, 540.

[0069] Then, if Figure 5E As shown, according to some embodiments, a molding material 552 is formed on the second redistribution layer 532. The molding material 552 can surround the underfill material 550 and the semiconductor chips 538 and 540. The molding material 552 can protect these components from environmental influences, thereby preventing damage caused by stress, chemicals, and moisture. The molding material 552 can be made of a non-conductive material, including a moldable polymer, an epoxy resin, a resin, a similar material, or a combination thereof.

[0070] Then, the molding material 552 may be planarized until the top surfaces of the semiconductor chips 538 and 540 are exposed. The planarization process may include a CMP process, a mechanical polishing process, the like, or a combination thereof.

[0071] Afterwards, carrier substrate 502 and glue layer 504 may be removed by a debonding process. In some embodiments, debonding is performed by projecting UV light onto glue layer 504 or heating glue layer 504, which causes glue layer 504 to decompose, thereby separating carrier substrate 502 from first redistribution layer 506.

[0072] Then, according to some embodiments, a plurality of conductive terminals 554 are formed under the first redistribution layer 506 and electrically coupled to the wiring layer 506M. The conductive terminals 554 may include micro flip-chip, controlled collapse chip connection (C4) flip-chip, solder balls, ball grid array (BGA) balls, the like, or any combination thereof. The conductive terminals 554 may be made of metal, such as tungsten, titanium, tantalum, ruthenium, cobalt, copper, aluminum, platinum, tin, silver, gold, the like, alloys thereof, or any combination thereof. A semiconductor package structure 500 is formed.

[0073] The semiconductor chip 538 can be arranged to vertically overlap the heat sink 514. In particular, the hot spots of the semiconductor chip 538 can be arranged to vertically overlap the heat sink 514 to improve heat dissipation efficiency. The heat from the semiconductor chip 538 can be transferred to the heat sink 514 through the thermal pad 536 and the thermal vias 534 and 508, and can be further transferred to the conductive terminal 554. Since the heat sink 514 is made of a material with higher thermal conductivity than the molding material 530, the system thermal budget of the semiconductor package structure 500 can be increased. In addition, a fast heat dissipation path can be provided.

[0074] although Figure 5E 5. Although one heat sink 514 is shown in FIG. 5, the present disclosure is not limited thereto. For example, an additional heat sink may be arranged below the semiconductor chip 538 and adjacent to the heat sink 514. Alternatively, an additional heat sink may be arranged below the semiconductor chip 540 and vertically overlapped by the semiconductor chip 540.

[0075] Figure 6 is a cross-sectional view of a semiconductor package structure 600 according to some embodiments of the present disclosure. It should be noted that the semiconductor package structure 600 may include Figure 5E For simplicity, the components of the semiconductor package structure 500 shown in FIG. 5 are the same or similar, and will not be discussed in detail. In the following embodiments, the heat sink is formed by a plurality of metal pillars.

[0076] like Figure 6As shown, according to some embodiments, the semiconductor package structure 600 includes a heat sink 602, which includes a plurality of metal pillars. The heat sink 602 can be arranged between the first redistribution layer 506 and the second redistribution layer 532. The heat sink 602 can be made of metal, such as tungsten, titanium, tantalum, ruthenium, cobalt, copper, aluminum, platinum, tin, silver, gold, the like, alloys thereof, or any combination thereof.

[0077] The heat sink 602 may be thermally coupled with the thermal vias 508 and 534 and the thermal pad 536 so that heat from the semiconductor chip 538 may be transferred to the heat sink 602 through the thermal pad 536 and the thermal vias 508 and 534, and may be further transferred to the conductive terminal 554. The heat sink 602 may be formed by electroplating, CVD, PVD, or other suitable deposition methods, and may be formed during the formation of the conductive pillar 512.

[0078] In summary, the semiconductor package structure according to the present disclosure includes a heat sink to replace the semiconductor component that is not made of a good thermal conductive material, thereby improving the heat dissipation efficiency, thereby providing more system thermal budget and a fast heat dissipation path.

[0079] Although the present invention has been described by way of examples and preferred embodiments, it should be understood that the present invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as will be apparent to those skilled in the art). Therefore, the scope of the appended claims should be given the broadest interpretation to cover all such modifications and similar arrangements.

Claims

1. A semiconductor packaging structure, comprising: A package substrate, comprising: A core structure; a heat sink embedded in the core structure; a redistribution layer including a thermal via disposed on the heat sink; A semiconductor chip is arranged on the package substrate and thermally coupled to the heat sink through the thermal via.

2. The semiconductor package structure as claimed in claim 1, wherein the package substrate further comprises: A dielectric layer surrounds the thermal via and extends between the heat sink and the core structure. 3 . The semiconductor package structure as claimed in claim 1 , wherein a bottom surface of the heat sink is aligned with a bottom surface of the core structure. The semiconductor package structure as claimed in claim 3 , wherein a top surface of the heat sink is aligned with a top surface of the core structure. The semiconductor package structure as claimed in claim 3 , wherein a top surface of the heat sink is higher than a top surface of the core structure. The semiconductor package structure as claimed in claim 3 , wherein a top surface of the heat sink is lower than a top surface of the core structure.

7. The semiconductor package structure as claimed in claim 1, wherein the package substrate further comprises: A via is embedded in the core structure and electrically coupled to the wiring layer of the redistribution layer.

8. The semiconductor package structure as claimed in claim 1, wherein the heat sink is made of metal. 9 . The semiconductor package structure as claimed in claim 1 , wherein a hot spot of the semiconductor chip vertically overlaps the heat sink. 10 . The semiconductor package structure as claimed in claim 9 , wherein an area of ​​the heat sink is smaller than an area of ​​the hot spot in a top view. 11 . The semiconductor package structure as claimed in claim 9 , wherein an area of ​​the heat sink is larger than an area of ​​the hot spot in a top view.

12. A semiconductor packaging structure, comprising: a first weight layer; a heat sink disposed on the first redistribution layer; a second redistribution layer disposed on the heat sink and comprising a first thermal via; A first semiconductor chip is disposed on the second redistribution layer and thermally coupled to the heat sink through the first thermal via.

13. The semiconductor package structure according to claim 12, further comprising: a bridging structure disposed between the first redistribution layer and the second redistribution layer; A second semiconductor chip is disposed on the second redistribution layer and electrically coupled to the first semiconductor chip through the bridge structure.

14. The semiconductor package structure according to claim 13, further comprising: A plurality of conductive pillars electrically coupling the first redistribution layer and the second redistribution layer; A molding material surrounds the heat sink, the bridge structure, and the plurality of conductive pillars. 15 . The semiconductor package structure as claimed in claim 14 , wherein a thickness of the heat sink in a direction perpendicular to the first redistribution layer is equal to a thickness of the plurality of conductive pillars. 16 . The semiconductor package structure as claimed in claim 14 , wherein a thickness of the heat sink in a direction perpendicular to the first redistribution layer is greater than a thickness of the bridge structure. 17 . The semiconductor package structure as claimed in claim 12 , wherein a hot spot of the first semiconductor chip vertically overlaps the heat sink.

18. The semiconductor package structure as claimed in claim 12, wherein the heat sink comprises a metal block.

19. The semiconductor package structure as claimed in claim 12, wherein the heat sink comprises a plurality of metal pillars.

20. The semiconductor package structure according to claim 12, further comprising: A conductive terminal is disposed below the first redistribution layer, wherein the first redistribution layer includes a second thermal via that thermally couples the heat sink to the conductive terminal.

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