Semiconductor package and manufacturing method thereof

Abstract

A semiconductor package may include a semiconductor chip, a redistribution layer on the semiconductor chip, a protection pattern covering the redistribution layer, and a connection terminal on the redistribution layer. The redistribution layer may include a redistribution pad on a top surface of the redistribution layer, and the redistribution pad may include a first pad and a second pad on the first pad. The second pad may have a side surface inclined and extending to a top surface of the first pad, and the protection pattern may be spaced apart from the side surface of the second pad and may have a side surface inclined and extending to the top surface of the first pad.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0129039 filed in the Korean Intellectual Property Office on September 26, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to semiconductor packages, and in particular, to semiconductor packages having improved electrical and reliability characteristics. Background Art

[0004] In the semiconductor industry, various packaging technologies have been developed in response to the increased demand for high-capacity, thin and small semiconductor devices and / or the resulting electronic products. Semiconductor packaging is configured to easily use an integrated circuit chip as a part of an electronic product. Typically, a semiconductor package includes a printed circuit board (PCB) and a semiconductor chip, which is mounted on the PCB and electrically connected to the PCB using bonding wiring or solder bumps. The development of the electronics industry has led to an increasing demand for high functionality, high speed and miniaturization of semiconductor packaging. Summary of the invention

[0005] Some example embodiments of the inventive concepts provide a semiconductor package having improved electrical characteristics and structural stability.

[0006] Some example embodiments of the inventive concepts provide methods of manufacturing a semiconductor package having improved electrical characteristics and structural stability.

[0007] According to an example embodiment of the inventive concept, a semiconductor package may include: a semiconductor chip; a redistribution layer on the semiconductor chip; a protection pattern covering the redistribution layer; and a connection terminal on the redistribution layer. The redistribution layer includes a redistribution pad on a top surface of the redistribution layer, the redistribution pad including a first pad and a second pad on the first pad. The second pad has a side surface that is inclined and extends to the top surface of the first pad. The protection pattern is spaced apart from the side surface of the second pad and has a side surface that is inclined and extends to the top surface of the first pad.

[0008] According to an example embodiment of the present invention, a semiconductor package may include: a lower redistribution layer; a first semiconductor chip on the lower redistribution layer; an upper redistribution layer on the first semiconductor chip, the upper redistribution layer including a redistribution pad on a top surface of the upper redistribution layer; a second semiconductor chip on the upper redistribution layer; a connection terminal electrically connecting the second semiconductor chip to the upper redistribution layer; and a protection pattern on the upper redistribution layer. The redistribution pad includes a first pad and a second pad on the first pad, the protection pattern has a side surface on the first pad, and the side surface of the protection pattern is spaced apart from the side surface of the second pad. The connection terminal includes a first portion on a top surface of the second pad, and a second portion between the side surface of the second pad and the side surface of the protection pattern.

[0009] According to an example embodiment of the present invention, a semiconductor package may include: a lower redistribution layer; a logic chip on the lower redistribution layer; a connection substrate on the lower redistribution layer, surrounding the logic chip in a plan view; a molding layer covering the logic chip and the connection substrate; an upper redistribution layer on the molding layer, the upper redistribution layer including a redistribution pad; a protection pattern covering the upper redistribution layer; a memory chip on the upper redistribution layer; and a connection terminal on a corresponding redistribution pad of the redistribution pad, the connection terminal being between the upper redistribution layer and the memory chip. Each of the redistribution pads includes a first pad and a second pad on the first pad. The protection pattern covers the first pad and is horizontally spaced apart from the second pad. Each connection terminal includes a first portion on the second pad, and a second portion extending between the second pad and the protection pattern. The second pad and the protection pattern have side surfaces that are inclined and extend to the top surface of the first pad.

[0010] According to an example embodiment of the inventive concept, a method for manufacturing a semiconductor package may include: forming a second pad on a first pad; forming a protection pattern to cover the first pad and expose the second pad; placing a connection terminal on the second pad; and bonding the connection terminal to the second pad. The second pad and the protection pattern have side surfaces that are inclined and extend from a top surface of the first pad. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 are cross-sectional views illustrating semiconductor packages according to some example embodiments of the inventive concepts.

[0012] FIG. 2A to FIG. 2D FIG. 1 is a diagram showing a portion of a semiconductor package according to some example embodiments of the inventive concept (eg, Figure 1 An enlarged cross-sectional view of P1).

[0013] Figure 3 and Figure 4are cross-sectional views illustrating semiconductor packages according to some example embodiments of the inventive concepts.

[0014] Figure 5 , Figure 6 , Figure 7 , Fig. 8A , Fig. 9A and Fig. 10A are cross-sectional views illustrating a method of manufacturing a semiconductor package according to some example embodiments of the inventive concepts.

[0015] Figure 8B yes Fig. 8A An enlarged cross-sectional view of portion P1.

[0016] Fig. 9B and Fig. 9C It shows Fig. 9A An enlarged cross-sectional view of portion P1.

[0017] Fig. 10B yes Fig. 10A An enlarged cross-sectional view of portion P1. DETAILED DESCRIPTION

[0018] Example embodiments of the inventive concept will now be described more fully with reference to the accompanying drawings, in which example embodiments are shown. Like reference numerals in the drawings represent like elements, and thus, description thereof will be omitted.

[0019] When the terms "about" or "substantially" are used in conjunction with a numerical value in this specification, it is intended that the associated numerical value includes a manufacturing or operating tolerance (e.g., ±10%) around the numerical value. In addition, when the words "about" and "substantially" are used in conjunction with a geometric shape, it is intended that the accuracy of the geometric shape is not required, but the tolerance for the shape is within the scope of the present disclosure. In addition, regardless of whether a numerical value or shape is modified to "about" or "substantially", it will be understood that these values ​​or shapes should be interpreted as including manufacturing or operating tolerances (e.g., ±10%) around the numerical value or shape. When a range is specified, the range includes all values ​​therebetween (e.g., increments of 0.1%).

[0020] Figure 1 are cross-sectional views illustrating semiconductor packages according to some example embodiments of the inventive concepts.

[0021] refer to Figure 1 , the semiconductor package may include a first semiconductor chip 300 , a second semiconductor chip 700 , and several elements electrically connecting the first semiconductor chip 300 to the second semiconductor chip 700 .

[0022] A lower redistribution layer 100 may be provided. The lower redistribution layer 100 may include a first insulating layer 110, a first conductive pattern 120, a passivation layer 130, and an external terminal pad 140. The lower redistribution layer 100 may have a top surface 100a and a bottom surface 100b opposite to each other. The top surface 100a of the lower redistribution layer 100 may be located at a higher level than the bottom surface 100b of the lower redistribution layer 100.

[0023] The first insulating layers 110 may be stacked in a vertical direction (e.g., a third direction D3). The thickness of the uppermost first insulating layer 110 among the first insulating layers 110 may be less than the thickness of the remaining first insulating layers 110 among the first insulating layers 110, but the inventive concept is not limited to this example embodiment. In other words, the first insulating layers 110 may have substantially the same thickness. The top surface of the uppermost first insulating layer 110 may correspond to the top surface 100a of the lower redistribution layer 100.

[0024] The first insulating layer 110 may include a polymer. For example, the first insulating layer 110 may be formed of an insulating polymer or a photo-imaging dielectric (PID) material, or include an insulating polymer or a photo-imaging dielectric (PID) material. For example, the PID material may be formed of at least one of a photo-imaging polyimide, a polybenzoxazole (PBO), a phenol-based polymer, or a benzocyclobutene-based polymer, or include at least one of a photo-imaging polyimide, a polybenzoxazole (PBO), a phenol-based polymer, or a benzocyclobutene-based polymer. Alternatively, the first insulating layer 110 may include an insulating material. For example, the first insulating layer 110 may be formed of at least one of silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), or an insulating polymer, or include at least one of silicon oxide (SiO), silicon nitride (SiN), or an insulating polymer.

[0025] The first conductive pattern 120 may be disposed in the first insulating layer 110. The first conductive pattern 120 may be configured to electrically connect elements placed on the top surface 100a and the bottom surface 100b of the lower redistribution layer 100 to each other. For example, the first conductive pattern 120 may be an element for horizontal redistribution in the lower redistribution layer 100. The first conductive pattern 120 may include a conductive material. For example, the first conductive pattern 120 may be formed of a metal material (e.g., copper (Cu)) or include a metal material (e.g., copper (Cu)).

[0026] The first conductive pattern 120 may have a mosaic structure. In detail, each first conductive pattern 120 may include a wiring line placed on the bottom surface of the first insulating layer 110, and a via extending from the wiring line to protrude in the third direction D3. For example, each first conductive pattern 120 may have an inverted letter "T" shape. The wiring line of the first conductive pattern 120 may extend in a horizontal direction (e.g., the first direction D1 or the second direction D2) on the bottom surface of the first insulating layer 110. The via of the first conductive pattern 120 may be arranged to penetrate a portion of the first insulating layer 110.

[0027] The via holes of the first conductive pattern 120 may be used to connect the wiring lines of the first conductive pattern 120 adjacent to each other in the third direction D3 to each other. In addition, the via holes of the first conductive pattern 120 may be used to electrically connect the connection substrate 200 (to be described below) and the first semiconductor chip 300 to the lower redistribution layer 100. As the distance from the bottom surface 100b of the lower redistribution layer 100 increases in a direction toward the top surface 100a of the lower redistribution layer 100, the via holes of the first conductive pattern 120 may have a decreasing width.

[0028] The external terminal pad 140 may be disposed on the bottom surface of the lowermost first insulating layer 110 among the first insulating layers 110. The external terminal pad 140 may be connected to a via of the lowermost first conductive pattern 120 among the first conductive patterns 120. The external terminal pad 140 may be connected to an external terminal 150 (to be described below).

[0029] The passivation layer 130 may be disposed on the bottom surface of the lowest first insulating layer 110 among the first insulating layers 110. The passivation layer 130 may cover the external terminal pads 140. Alternatively, the passivation layer 130 may be disposed to expose the external terminal pads 140 to the outside. In this case, the passivation layer 130 may cover the bottom surface of the lowest first insulating layer 110 among the first insulating layers 110, but not cover the bottom surface of the external terminal pads 140. For example, the passivation layer 130 may include an insulating polymer and / or a photo-imaging dielectric (PID) material.

[0030] The external terminals 150 may be respectively disposed on the bottom surface of the external terminal pads 140. The external terminals 150 may be disposed to penetrate a portion of the passivation layer 130 and may be connected to the external terminal pads 140. For example, the external terminals 150 may be formed of an alloy containing at least one of tin (Sn), silver (Ag), copper (Cu), nickel (Ni), bismuth (Bi), indium (In), antimony (Sb), or cerium (Ce), or include an alloy containing at least one of tin (Sn), silver (Ag), copper (Cu), nickel (Ni), bismuth (Bi), indium (In), antimony (Sb), or cerium (Ce). The semiconductor package may have a ball grid array (BGA) structure, a fine ball grid array (FBGA) structure, or a land grid array (LGA) structure according to the type or arrangement of the external terminals 150.

[0031] The connection substrate 200 may be disposed on the lower redistribution layer 100. The connection substrate 200 may have an opening OP therein. For example, the opening OP may have an opening formed to connect the top surface 200a and the bottom surface 200b of the connection substrate 200 to each other. The bottom surface 200b of the connection substrate 200 may be in contact with the top surface 100a of the lower redistribution layer 100. The opening OP may be defined as a space in which the first semiconductor chip 300 is placed. In other words, the first semiconductor chip 300 may be provided in the form of a fan-out panel level package (FO-PLP).

[0032] The connection substrate 200 may include a base layer 210, and a conductive portion 220 disposed in the base layer 210. The base layers 210 may be stacked in the third direction D3. For example, the top surface of the uppermost base layer 210 in the base layers 210 may correspond to the top surface 200a of the connection substrate 200, and the bottom surface of the lowermost base layer 210 in the base layers 210 may correspond to the bottom surface 200b of the connection substrate 200.

[0033] The conductive portion 220 may be disposed between the opening OP and the outer side surface of the connection substrate 200. The conductive portion 220 may include an upper pad 221, a lower pad 223, and a connection via 225. The upper pad 221 may be disposed on the top surface of the uppermost substrate layer 210 of the substrate layer 210, but the inventive concept is not limited to this example embodiment. Therefore, the upper pad 221 may be buried in the uppermost substrate layer 210 among the substrate layers 210, and the top surface of the upper pad 221 may be coplanar with the top surface 200a of the connection substrate 200. The lower pad 223 may be disposed on the bottom surface of the lowermost substrate layer 210 among the substrate layers 210. The lower pad 223 may be buried in the lowermost substrate layer 210 among the substrate layers 210, and the bottom surface of the lower pad 223 may be coplanar with the bottom surface 200b of the connection substrate 200.

[0034] The connection via 225 may be provided to penetrate the base layer 210 and electrically connect the upper pad 221 to the lower pad 223. The widths on the top and bottom surfaces of each connection via 225 may be different from each other. For example, the width of the connection via 225 in the first direction D1 and the second direction D2 may increase as the distance from the bottom surface 200b of the connection substrate 200 increases in the direction toward the top surface 200a of the connection substrate 200. In other words, the width of each connection via 225 may increase as the height in the third direction D3 increases.

[0035] In some example embodiments, the base layer 210 may be formed of or include at least one of an insulating polymer, a photo-imaging dielectric (PID) material, and / or an insulating material. The upper pad 221, the lower pad 223, and the connecting via 225 may be formed of or include at least one of a metal or a conductive material (e.g., copper (Cu)).

[0036] The connection substrate 200 may be mounted on the lower redistribution layer 100. In other words, the connection substrate 200 may be in contact with the lower redistribution layer 100 and electrically connected to the lower redistribution layer 100. The via hole of the uppermost first conductive pattern 120 among the first conductive patterns 120 may be provided to penetrate the uppermost first insulating layer 110 among the first insulating layers 110 and may be connected to the lower pad 223 of the connection substrate 200. Accordingly, the connection substrate 200 may be electrically connected to the external terminal 150 through the lower redistribution layer 100.

[0037] The first semiconductor chip 300 may be disposed on the lower redistribution layer 100 and may be placed in the opening OP of the connection substrate 200. The first semiconductor chip 300 may fill a portion of the opening OP. The first semiconductor chip 300 may be in contact with the top surface 100a of the lower redistribution layer 100 exposed through the opening OP. The bottom surface 300b of the first semiconductor chip 300 may be coplanar with the bottom surface 200b of the connection substrate 200 and the top surface 100a of the lower redistribution layer 100. The top surface 300a of the first semiconductor chip 300 may be located at a level lower than the top surface 200a of the connection substrate 200. In other words, the height of the first semiconductor chip 300 may be less than the height of the connection substrate 200. However, example embodiments are not limited thereto.

[0038] The first semiconductor chip 300 may include a circuit layer 310 and a semiconductor layer 320. The semiconductor layer 320 may be placed on the circuit layer 310, and the circuit layer 310 and the semiconductor layer 320 may contact each other. The bottom surface of the circuit layer 310 may correspond to the bottom surface 300b of the first semiconductor chip 300, and the top surface of the semiconductor layer 320 may correspond to the top surface 300a of the first semiconductor chip 300.

[0039] The circuit layer 310 may include a first chip pad 330, an integrated circuit, and an insulating pattern. The first chip pad 330 may be placed on the bottom surface of the circuit layer 310. For example, the integrated circuit may be a logic circuit and may be composed of at least one transistor, etc. Here, the insulating pattern may cover the integrated circuit, but the first chip pad 330 may be exposed to the area below the bottom surface of the circuit layer 310. In other words, the first chip pad 330 may be provided with a bottom surface coplanar with the bottom surface 300b of the first semiconductor chip 300. In some example embodiments, the first chip pad 330 may be formed of various metal materials (e.g., copper (Cu), aluminum (Al), and / or nickel (Ni)), or include various metal materials (e.g., copper (Cu), aluminum (Al), and / or nickel (Ni)).

[0040] In the first semiconductor chip 300, the bottom surface of the circuit layer 310 including the integrated circuit may be the active surface of the first semiconductor chip 300. The top surface of the semiconductor layer 320 not including the integrated circuit may be the inactive surface of the first semiconductor chip 300. In other words, the bottom surface 300b of the first semiconductor chip 300 may correspond to the active surface, and the top surface 300a of the first semiconductor chip 300 may correspond to the inactive surface. Since the active surface of the first semiconductor chip 300 is located at a lower level than the inactive surface thereof, the first semiconductor chip 300 may be mounted on the lower redistribution layer 100 in a face-down manner.

[0041] In some example embodiments, the first semiconductor chip 300 may be mounted on the top surface 100a of the lower redistribution layer 100 in a direct bonding manner. For example, the bottom surface 300b of the first semiconductor chip 300 may be in contact with the top surface 100a of the lower redistribution layer 100. The first chip pad 330 may be connected to the uppermost first conductive pattern 120 among the first conductive patterns 120. Accordingly, the first semiconductor chip 300 may be electrically connected to the lower redistribution layer 100. The first semiconductor chip 300 may be electrically connected to the external terminal 150 through the lower redistribution layer 100. Since solder balls or solder bumps are omitted from the area between the first semiconductor chip 300 and the lower redistribution layer 100, the size of the semiconductor package may be reduced.

[0042] For example, the first semiconductor chip 300 may be a logic chip. The logic chip may include an application specific integrated circuit (ASIC) chip, an application processor (AP) chip, a central processing unit (CPU), and / or a graphic processing unit (GPU).

[0043] The first mold layer 400 may be disposed on the connection substrate 200. The first mold layer 400 may cover the connection substrate 200 and the first semiconductor chip 300. The first mold layer 400 may fill the remaining portion of the opening OP. The first mold layer 400 may extend into the gap region between the connection substrate 200 and the first semiconductor chip 300, and may contact a portion of the lower redistribution layer 100. A portion of the first mold layer 400 may be placed between the connection substrate 200 and the first semiconductor chip 300. Since the first mold layer 400 covers the top surface 200a of the connection substrate 200 and the top surface 300a of the first semiconductor chip 300, the top surface of the first mold layer 400 may be placed at a level higher than the top surface 200a of the connection substrate 200. For example, the first mold layer 400 may be formed of, or include, an epoxy molding compound (EMC).

[0044] Since the first semiconductor chip 300 is covered by the first mold layer 400 and the connection substrate 200, the first semiconductor chip 300 can be protected from external influences. Accordingly, the first semiconductor chip 300 may not be exposed to external impacts. Therefore, the reliability and structural stability of the semiconductor package can be improved.

[0045] The upper redistribution layer 500 may be disposed on the first mold layer 400. The upper redistribution layer 500 may include a second insulating layer 510, a second conductive pattern 520, and a redistribution pad 540. The upper redistribution layer 500 may have a bottom surface 500b and a top surface 500a opposite to each other. The top surface 500a of the upper redistribution layer 500 may be located at a higher level than the bottom surface 500b of the upper redistribution layer 500.

[0046] The second insulating layers 510 may be stacked in a vertical direction (e.g., a third direction D3). In some example embodiments, the second insulating layers 510 may have substantially the same thickness. A top surface of an uppermost second insulating layer 510 among the second insulating layers 510 may correspond to a top surface 500a of an upper redistribution layer 500. A bottom surface of a lowermost second insulating layer 510 among the second insulating layers 510 may correspond to a bottom surface 500b of an upper redistribution layer 500. The second insulating layers 510 may include a photo-imaging polymer material or an insulating material.

[0047] The second conductive pattern 520 may be disposed within the second insulating layer 510. The second conductive pattern 520 may be configured to electrically connect elements respectively disposed on the top surface 500a and the bottom surface 500b of the upper redistribution layer 500 to each other. For example, the second conductive pattern 520 may be an element for horizontal redistribution in the upper redistribution layer 500. In some example embodiments, the second conductive pattern 520 may be formed of or include at least one of metal materials (e.g., copper (Cu)).

[0048] Similar to the first conductive pattern 120, the second conductive pattern 520 may have a mosaic structure. In detail, each second conductive pattern 520 may include a wiring line disposed on the top surface of the second insulating layer 510 and the first mold layer 400, and a via extending from the wiring line to protrude in the opposite direction to the third direction D3. In other words, each second conductive pattern 520 may have the shape of the letter "T". The wiring line of the second conductive pattern 520 may extend in a horizontal direction (e.g., the first direction D1 or the second direction D2) on the top surface of the second insulating layer 510 and the first mold layer 400. The via of the second conductive pattern 520 may be arranged to penetrate a portion of the second insulating layer 510.

[0049] The via holes of the second conductive pattern 520 may be configured to connect the wiring lines of the second conductive pattern 520 adjacent to each other in the third direction D3 to each other. In addition, the via holes of the second conductive pattern 520 may be configured to electrically connect the connection substrate 200 to the upper redistribution layer 500. The via holes of the second conductive pattern 520 may have a width that increases as the distance from the bottom surface 500b of the upper redistribution layer 500 increases in a direction toward the top surface 500a of the upper redistribution layer 500.

[0050] The redistribution pads 540 may be located on the top surface of the uppermost second insulating layer 510 in the second insulating layer 510. In other words, the redistribution pads 540 may be placed on the top surface 500a of the upper redistribution layer 500 and may be connected to the uppermost second conductive pattern 520 in the second conductive pattern 520. The top surface of the redistribution pads 540 may be located at a level higher than the top surface 500a of the upper redistribution layer 500. In other words, the redistribution pads 540 may not be buried in the upper redistribution layer 500, but the inventive concept is not limited to this example. The redistribution pads 540 may be arranged two-dimensionally in a plan view. In other words, the redistribution pads 540 may be spaced apart from each other in a horizontal direction (e.g., the first direction D1 or the second direction D2).

[0051] The protection pattern 550 may be disposed on the upper redistribution layer 500. For example, the protection pattern 550 may include at least one of an inorganic filler (e.g., a prepreg, an Ajinomoto built-in film (ABF), FR-4, and / or bismaleimide triazine (BT)), and / or a resin containing glass fiber. The protection pattern 550 may cover a portion of the top surface 500a of the upper redistribution layer 500 and the redistribution pad 540. For example, the protection pattern 550 may cover a portion of the redistribution pad 540 that is not in contact with the connection terminal 650 (to be described below). In this case, the possibility of the redistribution pad 540 being exposed to the outside and being oxidized can be prevented or reduced. As a result, the reliability of the semiconductor package can be improved.

[0052] The connection terminals 650 may be disposed on the upper redistribution layer 500 , the interposer substrate 600 may be disposed on the connection terminals 650 , and the second semiconductor chip 700 may be mounted on the interposer substrate 600 .

[0053] Each connection terminal 650 may be placed on a corresponding redistribution pad 540 among the redistribution pads 540. The connection terminal 650 may be placed between the redistribution pad 540 and a lower pad 630 (to be described below) of the interposer substrate 600. The connection terminal 650 may be formed of an alloy containing at least one of tin (Sn), silver (Ag), copper (Cu), nickel (Ni), bismuth (Bi), indium (In), antimony (Sb), or cerium (Ce), or includes an alloy containing at least one of tin (Sn), silver (Ag), copper (Cu), nickel (Ni), bismuth (Bi), indium (In), antimony (Sb), or cerium (Ce). Reference will be made to FIG. 2A to FIG. 2D The connection terminals 650 and the redistribution pads 540 are described in more detail.

[0054] The interposer substrate 600 may include an upper pad 610, a lower pad 630, and an interconnection pattern. The upper pad 610 may be placed on the top surface of the interposer substrate 600 and may be exposed by the top surface of the interposer substrate 600. The lower pad 630 may be placed on the bottom surface of the interposer substrate 600 and may be exposed by the bottom surface of the interposer substrate 600. In some example embodiments, the top surface of the upper pad 610 may be coplanar with the top surface of the interposer substrate 600, and the bottom surface of the lower pad 630 may be coplanar with the bottom surface of the interposer substrate 600. The upper pad 610 and the lower pad 630 may be spaced apart from each other in the third direction D3. The interconnection pattern may be placed in the interposer substrate 600 and may be configured to electrically connect the upper pad 610 to the lower pad 630. For example, the upper pad 610, the lower pad 630, and the interconnection pattern may be formed of or include at least one of a metal or a conductive material, such as copper (Cu).

[0055] The second semiconductor chip 700 may be located on the interposer substrate 600. The second semiconductor chip 700 may include a second chip pad 710. The second chip pad 710 may be placed in a lower portion of the second semiconductor chip 700 and may be exposed by the bottom surface of the second semiconductor chip 700. The second chip pads 710 may be horizontally spaced apart from each other. The second semiconductor chip 700 may be a semiconductor chip of a different type from the first semiconductor chip 300. For example, the second semiconductor chip 700 may be a memory chip. The memory chip may include a dynamic random access memory (DRAM) chip.

[0056] The chip terminal 750 may be disposed between the second semiconductor chip 700 and the interposer substrate 600. The chip terminal 750 may be placed between the second chip pad 710 of the second semiconductor chip 700 and the upper pad 610 of the interposer substrate 600, and may electrically connect the second semiconductor chip 700 to the interposer substrate 600. The chip terminal 750 may be formed of an alloy containing at least one of tin (Sn), silver (Ag), copper (Cu), nickel (Ni), bismuth (Bi), indium (In), antimony (Sb), or cerium (Ce).

[0057] The bottom filling layer 760 may be disposed between the second semiconductor chip 700 and the interposer substrate 600 to surround the chip terminal 750. The bottom filling layer 760 may cover the side surface of the chip terminal 750. The bottom filling layer 760 may have an inclined side surface, but the inventive concept is not limited to this example embodiment. Since the chip terminal 750 is not exposed to the outside through the bottom filling layer 760, the durability of the chip terminal 750 can be improved.

[0058] The second mold layer 800 may be disposed on the interposer substrate 600 to surround the second semiconductor chip 700. The second mold layer 800 may cover the side surfaces of the second semiconductor chip 700 and the side surfaces of the underfill layer 760. The side surfaces of the second mold layer 800 may be aligned with the side surfaces of the interposer substrate 600. The top surface of the second mold layer 800 may be coplanar with the top surface of the second semiconductor chip 700, but the inventive concept is not limited to this example embodiment.

[0059] FIG. 2A to FIG. 2D FIG. 1 is a diagram showing a portion of a semiconductor package according to some example embodiments of the inventive concept (eg, Figure 1 An enlarged cross-sectional view of P1).

[0060] refer to Figure 2A, the redistribution pad 540 may include a first pad PAD1 and a second pad PAD2. For example, the first pad PAD1 may be formed of copper (Cu), or include copper (Cu). The top surface P1t of the first pad PAD1 may be parallel to the first direction D1 and the second direction D2 that are not parallel to each other. The third direction D3 that is not parallel to the first direction D1 and the second direction D2 may be perpendicular to the top surface P1t of the first pad PAD1. For example, the first direction D1, the second direction D2, and the third direction D3 may be orthogonal to each other.

[0061] The second pad PAD2 may be placed on the top surface P1t of the first pad PAD1 and may be in contact with the first pad PAD1. The second pad PAD2 may be formed of a different metal material from the first pad PAD1, or include a different metal material from the first pad PAD1. Accordingly, a visible interface may exist between the first pad PAD1 and the second pad PAD2. For example, the second pad PAD2 may include nickel (Ni) and / or gold (Au).

[0062] The second pad PAD2 may have a top surface P2t, a bottom surface P2b, and a side surface P2s between the top surface P2t and the bottom surface P2b. The top surface P2t and the bottom surface P2b of the second pad PAD2 may be parallel to the top surface P1t of the first pad PAD1. The second pad PAD2 may have a first thickness T1 in the third direction D3. When measured in the first direction D1 at the top surface P2t of the second pad PAD2, the second pad PAD2 may have a first width W1. When measured in the first direction D1 at the bottom surface P2b of the second pad PAD2, the second pad PAD2 may have a second width W2. The first width W1 may be greater than the second width W2, and therefore, the second pad PAD2 may have a side surface P2s inclined at a certain angle relative to the top surface P1t of the first pad PAD1. For example, the side surface P2s of the second pad PAD2 may be inclined at a constant angle θ with respect to a direction (eg, the third direction D3) perpendicular to the top surface P1t of the first pad PAD1.

[0063] The width of the first pad PAD1 may be greater than the first width W1 and the second width W2 of the second pad PAD2. The second pad PAD2 may be placed to overlap with the center of the first pad PAD1 in a horizontal direction (e.g., the first direction D1 and the second direction D2). Accordingly, the second pad PAD2 may overlap with the first pad PAD1 vertically. When viewed in a plan view, the area of ​​the first pad PAD1 may be greater than the area of ​​the second pad PAD2.

[0064] When viewed in a plan view, the first pad PAD1 and the second pad PAD2 may have a circular shape, but the inventive concept is not limited to this example. For example, the first pad PAD1 and the second pad PAD2 may have a polygonal shape (e.g., an elliptical, triangular, and rectangular shape), and in some example embodiments, the first pad PAD1 and the second pad PAD2 may have shapes different from each other.

[0065] The protection pattern 550 may be placed on the first pad PAD1. The protection pattern 550 may cover the side surface of the first pad PAD1, and a portion of the top surface P1t, and may expose the second pad PAD2. The side surface 550s of the protection pattern 550 may be spaced apart from the side surface P2s of the second pad PAD2. In other words, the protection pattern 550 may cover the first pad PAD1, and may be spaced apart horizontally from the second pad PAD2. At the top surface P2t of the second pad PAD2, the distance between the side surface P2s of the second pad PAD2 and the side surface 550s of the protection pattern 550 may be a third width W3. At the bottom surface P2b of the second pad PAD2, the distance between the side surface P2s of the second pad PAD2 and the side surface 550s of the protection pattern 550 may be a fourth width W4. The third width W3 and the fourth width W4 may be substantially equal to each other. Since the side surface P2s of the second pad PAD2 is spaced a constant distance from the side surface 550s of the protection pattern 550, the protection pattern 550 may have a side surface 550s located on the top surface P1t of the first pad PAD1 and inclined relative to the top surface P1t of the first pad PAD1. For example, the side surface 550s may extend from the top surface P1t of the first pad PAD1, or extend to the top surface P1t of the first pad PAD1. For example, the side surface 550s may form an oblique angle with the top surface P1t of the first pad PAD1.

[0066] The protection pattern 550 may have a second thickness T2 in the third direction D3. The second thickness T2 of the protection pattern 550 may be greater than the first thickness T1 of the second pad PAD2. Since the bottom surface of the protection pattern 550 is coplanar with the bottom surface P2b of the second pad PAD2, the top surface 550t of the protection pattern 550 may be located at a higher level than the top surface P2t of the second pad PAD2.

[0067] The protection pattern 550 may include a resin 550b and a filler 550a placed in the resin 550b. The filler 550a may be surrounded by the resin 550b. In other words, the protection pattern 550 may be a resin 550b containing a filler 550a. For example, the filler 550a may include an inorganic filler (e.g., silicon oxide or aluminum oxide). The size of each filler 550a may be in the range of about 1 μm to about 5 μm. For example, the resin 550b may be formed of a thermosetting resin material (e.g., epoxy resin) or a thermoplastic resin material (e.g., polyimide), or include a thermosetting resin material (e.g., epoxy resin) or a thermoplastic resin material (e.g., polyimide).

[0068] The void 550v may be formed at the side surface 550s of the protection pattern 550. When the filler 550a near the side surface 550s of the protection pattern 550 is removed, the void 550v may be formed. Due to the presence of the void 550v, the roughness of the side surface 550s of the protection pattern 550 may be greater than the roughness of the side surface P2s of the second pad PAD2. In some example embodiments, at least a portion of the void 550v may be filled with the connection terminal 650. The friction between the protection pattern 550 and the connection terminal 650 may be increased. This may make it possible to prevent or reduce the possibility of the connection terminal 650 being separated from the redistribution pad 540.

[0069] The connection terminal 650 may include a first portion P1 and a second portion P2 protruding from the first portion P1. The first portion P1 may be disposed between the second pad PAD2 and the lower pad 630 of the interposer substrate 600. The first portion P1 may be in contact with the top surface P2t of the second pad PAD2. The second portion P2 may extend into a space between the side surface 550s of the protection pattern 550 and the side surface P2s of the second pad PAD2. In other words, the second portion P2 may be in contact with the side surface 550s of the protection pattern 550 and the side surface P2s of the second pad PAD2. In addition, the second portion P2 may be in contact with a portion of the top surface P1t of the first pad PAD 1. In some example embodiments, the first portion P1 and the second portion P2 may be disposed to form a single object. In this case, there may be no visible interface between the first portion P1 and the second portion P2.

[0070] Since the side surface 550s of the protection pattern 550 and the side surface P2s of the second pad PAD2 are spaced apart from each other by a constant distance, the upper width and the lower width of the second portion P2 may be substantially equal to each other. For example, the upper width of the second portion P2 may be the third width W3, and the lower width of the second portion P2 may be the fourth width W4 substantially equal to the third width W3. In other words, the width of the second portion P2 may be constant regardless of the distance from the top surface P2t of the second pad PAD2. In addition, since the protection pattern 550 and the second pad PAD2 have side surfaces 550s and P2s inclined at a certain angle relative to the top surface P1t of the first pad PAD1, the second portion P2 may extend in a direction inclined relative to the top surface P1t of the first pad PAD1.

[0071] In other words, the connection terminal 650 may be arranged to cover the top surface P2t and the side surface P2s of the second pad PAD2, and the second portion P2 of the connection terminal 650 located on the side surface P2s of the second pad PAD2 may have a shape extending in a direction inclined relative to the top surface P1t of the first pad PAD1. Accordingly, the second portion P2 of the connection terminal 650 may be engaged with the second pad PAD2 and may not be movable in a vertical direction (e.g., a third direction D3). In other words, the connection terminal 650 may have a clamp shape fixed to the second pad PAD2, and this may make it possible to prevent or reduce the possibility of the connection terminal 650 being detached from the second pad PAD2.

[0072] refer to Figure 2B , a portion of the protection pattern 550 on the first pad PAD1 may be spaced apart from the top surface P1t of the first pad PAD1 in the third direction D3. In other words, a portion of the bottom surface of the protection pattern 550 may be separated from the top surface P1t of the first pad PAD1. Accordingly, a space may be formed between the protection pattern 550 and the first pad PAD1.

[0073] The connection terminal 650 may further include a third portion P3. The third portion P3 may extend horizontally from the second portion P2 and may be placed on the top surface P1t of the first pad PAD1. The third portion P3 may fill the space formed between the protection pattern 550 and the first pad PAD1. The third portion P3 may be placed between the bottom surface of the protection pattern 550 and the top surface P1t of the first pad PAD1. In other words, the third portion P3 may adhere between the protection pattern 550 and the first pad PAD1, and therefore, the connection terminal 650 may be securely fastened to the redistribution pad 540. In this case, the possibility of the connection terminal 650 being detached from the redistribution pad 540 can be prevented or reduced.

[0074] refer to Figure 2C , the side surface 550s of the protection pattern 550 may be horizontally spaced apart from the side surface P2s of the second pad PAD2. The side surface 550s of the protection pattern 550 may have a slope different from the side surface P2s of the second pad PAD2. Accordingly, the horizontal distance between the side surface 550s of the protection pattern 550 and the side surface P2s of the second pad PAD2 may be changed according to the height in the third direction D3. For example, at the top surface P2t of the second pad PAD2, the distance between the side surface P2s of the second pad PAD2 and the side surface 550s of the protection pattern 550 may be the third width W3. At the bottom surface P2b of the second pad PAD2, the distance between the side surface P2s of the second pad PAD2 and the side surface 550s of the protection pattern 550 may be the fourth width W4. Here, the third width W3 may be greater than the fourth width W4. In other words, a horizontal distance between the side surface P2s of the second pad PAD2 and the side surface 550s of the protection pattern 550 may decrease as a distance from the top surface P1t of the first pad PAD1 decreases.

[0075] Since the horizontal distance between the side surface 550s of the protection pattern 550 and the side surface P2s of the second pad PAD2 depends on the height in the third direction D3, the upper width and the lower width of the second portion P2 may be different from each other. For example, the upper width of the second portion P2 may be the third width W3, and the lower width of the second portion P2 may be the fourth width W4. The upper width of the second portion P2 may be greater than the lower width. In other words, the second portion P2 may have a width that decreases as the distance from the top surface P1t of the first pad PAD1 decreases.

[0076] refer to Figure 2D , the second pad PAD2 may have a first width W1 in the first direction D1 at its top surface P2t. The second pad PAD2 may have a second width W2 in the first direction D1 at its bottom surface P2b. In some example embodiments, the first width W1 may be smaller than the second width W2. In other words, the second pad PAD2 may have a width that decreases as the distance from the top surface P1t of the first pad PAD1 increases. Accordingly, the side surface P2s of the second pad PAD2 may be inclined at a certain angle relative to the top surface P1t of the first pad PAD1, but the angle may be different from the side surface P2s of the second pad PAD2. FIG. 2A to FIG. 2C For example, the side surface P2s of the second pad PAD2 may be inclined at a constant angle θ with respect to a direction (eg, the third direction D3) perpendicular to the top surface P1t of the first pad PAD1.

[0077] and FIG. 2A to FIG. 2CUnlike the example embodiment of the present invention, the second portion P2 of the connection terminal 650 may be fastened to the protection pattern 550. For example, the connection terminal 650 may include two wing-shaped portions, the distance between which increases as the distance from the top surface P1t of the first pad PAD1 decreases, and due to this structure, the connection terminal 650 may be securely fastened to the protection pattern 550. Therefore, the possibility of the connection terminal 650 being separated from the protection pattern 550 can be prevented or reduced.

[0078] Return to reference FIG. 2A to FIG. 2D , the first portion P1 of the connection terminal 650 may contact the top surface P2t of the second pad PAD2. The second portion P2 of the connection terminal 650 may contact the side surface P2s of the second pad PAD2. Accordingly, the contact area between the connection terminal 650 and the second pad PAD2 may be increased. This makes it possible to improve the electrical characteristics of the semiconductor package.

[0079] In addition, the second portion P2 of the connection terminal 650 may be arranged to have a shape that is inclined relative to the top surface P1t of the first pad PAD1 between the protection pattern 550 and the second pad PAD2. In other words, the second portion P2 of the connection terminal 650 may have an anchoring structure between the protection pattern 550 and the second pad PAD2. Accordingly, the connection terminal 650 may be fastened to the second pad PAD2 and the protection pattern 550. In this case, since the connection terminal 650 is immovable in the vertical direction, the possibility of the detachment problem of the connection terminal 650 can be prevented or reduced. In addition, the second portion P2 of the connection terminal 650 can be used to disperse the pressure applied from the upper element (e.g., the interposer substrate 600 and the second semiconductor chip 700) of the semiconductor package. Therefore, the reliability of the semiconductor package can be improved.

[0080] However, if the angle between the side surface P2s of the second pad PAD2 and the normal direction of the top surface P1t of the first pad PAD1 (e.g., the third direction D3) is too small, the connection terminal 650 may not be fastened to the second pad PAD2 and the protection pattern 550. If the angle between the side surface P2s of the second pad PAD2 and the third direction D3 is too large, it may be difficult to stably form the second portion P2. In this case, an air gap may be formed between the protection pattern 550 and the second pad PAD2. This may indicate that the angle needs to be controlled within a specific range. For example, the angle between the side surface P2s of the second pad PAD2 and the third direction D3 may be in the range of about 3° to about 20°.

[0081] In addition, if the second portion P2 of the connection terminal 650 is formed to have a smaller vertical length and a smaller horizontal width, the connection terminal 650 may not be fastened to the second pad PAD2 and the protection pattern 550. On the contrary, if the second portion P2 of the connection terminal 650 is formed to have a larger vertical length and a larger horizontal width, it may be difficult to reduce the size of the semiconductor package. This may mean that the size of the second portion P2 of the connection terminal 650 needs to be controlled within a specific range. In some example embodiments, the vertical length of the second portion P2 of the connection terminal 650 may be in the range of about 3 μm to about 5 μm, and the horizontal width may be in the range of about 1 μm to about 4 μm.

[0082] Figure 3 and Figure 4 are cross-sectional views illustrating semiconductor packages according to some example embodiments of the inventive concepts.

[0083] In the following description, for the sake of simplicity, the previous reference Figure 1 Described elements may be identified by the same reference numerals without repeating their overlapping descriptions.

[0084] refer to Figure 3 , the semiconductor package may include a lower redistribution layer 100, a connection substrate 200, a first semiconductor chip 300, a first mold layer 400, an upper redistribution layer 500, an interposer substrate 600, a second semiconductor chip 700, and a second mold layer 800. The lower redistribution layer 100, the connection substrate 200, the first semiconductor chip 300, the first mold layer 400, and the upper redistribution layer 500 may be configured to have Figure 1 The features in the exemplary embodiments are substantially the same features.

[0085] The second semiconductor chip 700 may be located on the interposer substrate 600. The second semiconductor chip 700 may be in direct contact with the interposer substrate 600. The bottom surface of the second semiconductor chip 700 may be located at the same level as the top surface of the interposer substrate 600. In other words, the second semiconductor chip 700 may be omitted. Figure 1 The chip terminals 750 and the bottom filling layer 760 are formed.

[0086] The second semiconductor chip 700 may include a second chip pad 710. The second chip pad 710 may be placed on the top surface of the second semiconductor chip 700 and may be exposed by the top surface of the second semiconductor chip 700. In other words, the top surface of the second chip pad 710 may be coplanar with the top surface of the second semiconductor chip 700.

[0087] The bonding wire 751 may be disposed on the second semiconductor chip 700 . The bonding wire 751 may be connected to the second chip pad 710 of the second semiconductor chip 700 and the upper pad 610 of the interposer substrate 600 . The bonding wire 751 may electrically connect the second semiconductor chip 700 to the interposer substrate 600 .

[0088] The second mold layer 800 may be disposed on the interposer substrate 600 to cover the second semiconductor chip 700 and the bonding wires 751. Since the second mold layer 800 covers the bonding wires 751 on the second semiconductor chip 700, the second mold layer 800 may have a top surface located at a higher level than that of the second semiconductor chip 700.

[0089] refer to Figure 4 , the semiconductor package may include a lower redistribution layer 100, a connection substrate 200, a first semiconductor chip 300, a first molding layer 400, an upper redistribution layer 500, an interposer substrate 600, a second semiconductor chip 700, and a second molding layer 800. The interposer substrate 600, the second semiconductor chip 700, and the second molding layer 800 may be configured to have Figure 1 The features in the exemplary embodiments are substantially the same features.

[0090] The first insulating layer 110 of the lower redistribution layer 100 may be stacked in a vertical direction (e.g., a third direction D3), and the first conductive pattern 120 may be placed in the first insulating layer 110. In detail, each first conductive pattern 120 may include a wiring line placed on the top surface of the first insulating layer 110, and a via extending from the wiring line to protrude in the opposite direction of the third direction D3. For example, each first conductive pattern 120 may have a shape of a letter "T". The wiring line of the first conductive pattern 120 may extend in a horizontal direction (e.g., the first direction D1 or the second direction D2) on the top surface of the first insulating layer 110. The via of the first conductive pattern 120 may be arranged to penetrate a portion of the first insulating layer 110. As the distance from the bottom surface 100b of the lower redistribution layer 100 increases in the direction toward the top surface 100a of the lower redistribution layer 100, the via of the first conductive pattern 120 may have an increasing width.

[0091] The external terminal pad 140 may be placed on the bottom surface of the lowermost first insulating layer 110 among the first insulating layers 110, and may be exposed by the lowermost first insulating layer 110 among the first insulating layers 110. For example, the bottom surface of the external terminal pad 140 may be coplanar with the bottom surface of the lowermost first insulating layer 110 among the first insulating layers 110. The external terminal pad 140 may be connected to the lowermost first conductive pattern 120 among the first conductive patterns 120.

[0092] The first semiconductor chip 300 may be placed on the lower redistribution layer 100, and may be placed in a central region of the lower redistribution layer 100 when viewed in a plan view. The first semiconductor chip 300 may be configured to have Figure 1 The bump 350 may be provided between the first semiconductor chip 300 and the lower redistribution layer 100. Accordingly, the bottom surface 300b of the first semiconductor chip 300 may be spaced apart from the top surface 100a of the lower redistribution layer 100 in the third direction D3. Each bump 350 may be placed between the corresponding uppermost first conductive pattern 120 in the first conductive pattern 120 and the first chip pad 330. In other words, the first semiconductor chip 300 and the lower redistribution layer 100 may be electrically connected to each other through the bump 350. For example, the bump 350 may be formed of an alloy containing at least one of tin (Sn), silver (Ag), copper (Cu), nickel (Ni), bismuth (Bi), indium (In), antimony (Sb), or cerium (Ce), or include an alloy containing at least one of tin (Sn), silver (Ag), copper (Cu), nickel (Ni), bismuth (Bi), indium (In), antimony (Sb), or cerium (Ce).

[0093] The through via 250 may be disposed on the top surface 100a of the lower redistribution layer 100. The through via 250 may be horizontally spaced apart from the first semiconductor chip 300. For example, the through via 250 may be placed on an edge region of the lower redistribution layer 100, and here, the edge region of the lower redistribution layer 100 may surround a central region of the lower redistribution layer 100 in which the first semiconductor chip 300 is disposed. In other words, the through via 250 may be disposed to surround the first semiconductor chip 300 when viewed in a plan view.

[0094] The through vias 250 may be placed on the uppermost first conductive pattern 120 of the first conductive patterns 120. The through vias 250 may be horizontally spaced apart from each other. Each through via 250 may have a shape extending in the third direction D3, for example, each through via 250 may have a maximum size in the third direction D3. The through via 250 may be configured to electrically connect the lower redistribution layer 100 to the upper redistribution layer 500. For example, the through via 250 may be formed of or include at least one of a metal or a conductive material (e.g., copper (Cu)).

[0095] The first mold layer 400 may be disposed on the lower redistribution layer 100. The first mold layer 400 may cover the top surface 300a, the bottom surface 300b, and the side surface of the first semiconductor chip 300, and the side surface of the through via 250. The first mold layer 400 may be placed between the through vias 250, and between the through via 250 and the first semiconductor chip 300. In other words, the first mold layer 400 may surround the first semiconductor chip 300 and the through via 250. The side surface of the first mold layer 400 may be aligned with the side surface of the lower redistribution layer 100.

[0096] The first mold layer 400 may have a top surface parallel to the first direction D1 and the second direction D2. The top surface of the first mold layer 400 may be located at a level higher than the top surface 300a of the first semiconductor chip 300. The top surface of the first mold layer 400 may be located at a level higher than the top surface of the through-hole 250, but the inventive concept is not limited to this example. In other words, the top surface of the first mold layer 400 may be coplanar with the top surface of the through-hole 250. In example embodiments, the first mold layer 400 may include an insulating polymer (e.g., epoxy molding compound (EMC)).

[0097] The upper redistribution layer 500 may be disposed on the first mold layer 400. The upper redistribution layer 500 may include a second insulating layer 510, a second conductive pattern 520, and a redistribution pad 540. The upper redistribution layer 500 may be configured to have Figure 1 However, the lowermost second conductive patterns 520 among the second conductive patterns 520 may be respectively placed on the penetration vias 250 and connected to the penetration vias 250. In this case, the upper redistribution layer 500 and the lower redistribution layer 100 may be electrically connected to each other through the penetration vias 250.

[0098] The redistribution pads 540, the protection pattern 550, and the connection terminals 650 may be disposed on the top surface of the uppermost second insulation layer 510 among the second insulation layers 510. The redistribution pads 540, the protection pattern 550, and the connection terminals 650 may be configured to have a Figure 1 and FIG. 2A to FIG. 2D The features in the described example embodiments are substantially the same features.

[0099] Figure 5 , Figure 6 , Figure 7 , Fig. 8A , Fig. 9A and Fig. 10A is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to an example embodiment of the inventive concept. Figure 8B yes Fig. 8A An enlarged cross-sectional view of portion P1. Fig. 9Band Fig. 9C It shows Fig. 9A An enlarged cross-sectional view of portion P1. Fig. 10B yes Fig. 10A An enlarged cross-sectional view of portion P1.

[0100] refer to Figure 5 , a connection substrate 200 may be formed. The connection substrate 200 may include a base layer 210 and a conductive portion 220. The conductive portion 220 may include an upper pad 221, a lower pad 223, and a connection via 225. A lower base layer 210 and the conductive portion 220 therein may be formed in the base layer 210, and then, an upper base layer 210 and the conductive portion 220 therein may be formed in the base layer 210.

[0101] Thereafter, an opening OP may be formed in the connection substrate 200. The opening OP may be formed by removing a portion of the connection substrate 200. The opening OP may be formed to penetrate the connection substrate 200 from the top surface 200a to the bottom surface 200b. In some example embodiments, the opening OP may be formed by an etching process, a drilling process, a laser ablation process, or a laser cutting process.

[0102] After forming the opening OP, a first carrier substrate 810 may be formed on the bottom surface 200b of the connection substrate 200. The first carrier substrate 810 may cover the bottom surface 200b of the connection substrate 200 and may close the opening OP. In some example embodiments, the first carrier substrate 810 may be an insulating substrate including glass or polymer, or a conductive substrate including a metal material.

[0103] The first semiconductor chip 300 may be placed on the first carrier substrate 810 and in the opening OP of the connection substrate 200. The first semiconductor chip 300 may fill a portion of the opening OP. The first semiconductor chip 300 may include a circuit layer 310, a semiconductor layer 320 on the circuit layer 310, and a first chip pad 330 in the circuit layer 310. The first semiconductor chip 300 may be attached to the first carrier substrate 810. In other words, the bottom surface 300b of the first semiconductor chip 300 may be coplanar with the bottom surface 200b of the connection substrate 200, and the circuit layer 310 of the first semiconductor chip 300 may contact the first carrier substrate 810.

[0104] Next, a first mold layer 400 may be formed to cover the connection substrate 200 and the first semiconductor chip 300. The top surface of the first mold layer 400 may be located at a level higher than the top surface 300a of the first semiconductor chip 300 and the top surface 200a of the connection substrate 200. The first mold layer 400 may fill the remaining portion of the opening OP. The first mold layer 400 may extend into the gap region between the connection substrate 200 and the first semiconductor chip 300. For example, a portion of the first mold layer 400 may be formed between the connection substrate 200 and the first semiconductor chip 300. The formation of the first mold layer 400 may include: injecting a molding member into the gap region between the connection substrate 200 and the first semiconductor chip 300, and curing the molding member.

[0105] refer to Figure 6 , a second carrier substrate 820 may be formed on the first mold layer 400. The second carrier substrate 820 may cover a top surface of the first mold layer 400. In some example embodiments, an adhesive member may be disposed between the second carrier substrate 820 and the first mold layer 400.

[0106] Thereafter, the second carrier substrate 820 may be inverted. In other words, the second carrier substrate 820 may be placed below the first carrier substrate 810, and the connection substrate 200 may be placed between the second carrier substrate 820 and the first carrier substrate 810. Accordingly, the bottom surface 200b of the connection substrate 200 may be placed at a higher level than the top surface 200a.

[0107] After inverting the second carrier substrate 820, the first carrier substrate 810 may be removed. Accordingly, the bottom surface 200b of the connection substrate 200, the bottom surface 300b of the first semiconductor chip 300, and a portion of the first mold layer 400 disposed between the first semiconductor chip 300 and the connection substrate 200 may be exposed to the outside.

[0108] After removing the first carrier substrate 810, a lower redistribution layer 100 may be formed on the bottom surface 200b of the connection substrate 200. The formation of the lower redistribution layer 100 may include forming a first insulating layer 110 on the connection substrate 200 and the first semiconductor chip 300, patterning the first insulating layer 110 using photolithography and etching processes, forming a conductive layer on the patterned first insulating layer 110, and patterning the conductive layer to form a first conductive pattern 120. The first conductive pattern 120 may be connected to the first chip pad 330 of the first semiconductor chip 300 and the lower pad 223 of the connection substrate 200, respectively.

[0109] The process of forming the lower redistribution layer 100 may be repeatedly performed to form vertically stacked first insulating layers 110 , and first conductive patterns 120 respectively formed in the first insulating layers 110 .

[0110] Next, the external terminal pad 140 and the passivation layer 130 may be formed on the first insulating layer 110. The passivation layer 130 may cover the external terminal pad 140 and the first insulating layer 110. Accordingly, the external terminal pad 140 and the first insulating layer 110 may be protected from subsequent processes.

[0111] refer to Figure 7 , the second carrier substrate 820 may be inverted again. Therefore, the second carrier substrate 820 may be placed on the upper portion. The top surface 200a of the connection substrate 200 may be placed at a higher level than the bottom surface 200b. Thereafter, the second carrier substrate 820 may be removed. As a result of removing the second carrier substrate 820, the first mold layer 400 may be exposed to the outside.

[0112] Next, an upper redistribution layer 500 may be formed on the first mold layer 400. The formation of the upper redistribution layer 500 may include: forming a second insulating layer 510 on the first mold layer 400, patterning the second insulating layer 510 using a photolithography and etching process, forming a conductive layer on the patterned second insulating layer 510, and patterning the conductive layer to form a second conductive pattern 520. The process of forming the upper redistribution layer 500 may be repeatedly performed to form vertically stacked second insulating layers 510 and second conductive patterns 520 respectively formed in the second insulating layers 510.

[0113] The formation of the upper redistribution layer 500 may be substantially the same process as the formation of the lower redistribution layer 100. Each of the second conductive patterns 520 may be connected to a corresponding upper pad 221 of the upper pads 221 of the connection substrate 200.

[0114] The preliminary redistribution pads 540a may be formed on the uppermost second insulating layer 510 in the second insulating layers 510. The preliminary redistribution pads 540a may be located at the same level and may be horizontally spaced apart from each other. Each preliminary redistribution pad 540a may be connected to a corresponding second conductive pattern 520 in the uppermost second conductive pattern 520 of the second conductive patterns 520. For example, the preliminary redistribution pads 540a may be formed of a metal material (e.g., copper (Cu)), or include a metal material (e.g., copper (Cu)).

[0115] refer to Fig. 8A and Figure 8B , the redistribution pads 540 each including the first pad PAD1 and the second pad PAD2 may be formed from the preliminary redistribution pads 540a. For example, the preliminary redistribution pads 540a may correspond to the first pads PAD1 of each redistribution pad 540. The redistribution pads 540 may be a structure including the preliminary redistribution pads 540a and the second pads PAD2 formed thereon.

[0116] The formation of the redistribution pads 540 may include forming a mask pattern MP on the first pads PAD1 to expose a portion of a top surface P1t of the first pads PAD1 , and forming a second pad PAD2 on the exposed portion of the top surface P1t of the first pads PAD1 .

[0117] The formation of the mask pattern MP may include: forming a mask layer to completely cover the first pad PAD1, and removing a portion of the mask layer by an exposure process performed on the mask layer. The mask pattern MP may have a pad opening POP. The pad opening POP may be formed on the top surface P1t of the first pad PAD1 to expose a portion of the top surface P1t of the first pad PAD1. The pad opening POP may have a side surface inclined at a certain angle relative to the top surface P1t of the first pad PAD1. For example, the pad opening POP may have a width that increases as the distance from the top surface P1t of the first pad PAD1 increases, but the inventive concept is not limited to this example.

[0118] The formation of the second pad PAD2 may be performed by an electroplating process. In some example embodiments, the electroplating process may include a nickel (Ni) electroplating process and / or a gold (Au) electroplating process, and in this case, the second pad PAD2 may contain nickel (Ni) and / or gold (Au). The electroplating process may be performed until the thickness of the second pad PAD2 from the top surface P1t of the first pad PAD1 has a first thickness T1. For example, the second pad PAD2 may fill the lower portion of the pad opening POP of the mask pattern MP.

[0119] Since the side surface of the mask pattern MP is inclined relative to the top surface P1t of the first pad PAD1, the side surface P2s of the second pad PAD2 may also be inclined relative to the top surface P1t of the first pad PAD1. For example, the second pad PAD2 may have a width that increases as the distance from the top surface P1t of the first pad PAD1 increases. The second pad PAD2 may have a first width W1 at its top surface P2t. The second pad PAD2 may have a second width W2 that is less than the first width W1 at its bottom surface P2b. The side surface P2s of the second pad PAD2 may be inclined at a constant angle θ relative to a direction perpendicular to the top surface P1t of the first pad PAD1. For example, the angle θ may be in the range of about 3° to about 20°.

[0120] refer to Fig. 9A , Fig. 9B and Fig. 9C, a protection pattern 550 may be formed on the upper redistribution layer 500. The formation of the protection pattern 550 may include: forming a protection layer to cover the redistribution pad 540, and removing a portion of the protection layer to expose the second pad PAD2. For example, the partial removal of the protection layer may be performed by an etching process, a drilling process, a laser ablation process, or a laser cutting process.

[0121] The protection pattern 550 may have a thickness greater than that of the second pad PAD2. In other words, the protection pattern 550 may have a second thickness T2 in the vertical direction, and here, the second thickness T2 may be greater than the first thickness T1 of the second pad PAD2. Accordingly, the top surface 550t of the protection pattern 550 may be located at a level higher than the top surface P2t of the second pad PAD2.

[0122] The protection pattern 550 may cover the side surface and the top surface P1t of the first pad PAD1, and may expose the top surface P2t of the second pad PAD2. The bottom surface of the protection pattern 550 may contact the top surface P1t of the first pad PAD1, and the side surface 550s of the protection pattern 550 may contact the side surface P2s of the second pad PAD2. Accordingly, the protection pattern 550 may have a side surface 550s inclined at a certain angle relative to the top surface P1t of the first pad PAD1.

[0123] The protection pattern 550 may include a resin 550b and a filler 550a placed in the resin 550b. The filler 550a may be surrounded by the resin 550b. For example, the protection pattern 550 may include at least one of an inorganic filler (e.g., prepreg, Ajinomoto built-in film (ABF), FR-4, and / or bismaleimide triazine (BT)), and / or a resin containing glass fiber.

[0124] Thereafter, a curing process may be performed on the protection pattern 550. The protection pattern 550 may be shrunk by the curing process. In addition, the bonding strength between the protection pattern 550 and the first pad PAD1 may be greater than the bonding strength between the protection pattern 550 and the second pad PAD2. Accordingly, the protection pattern 550 may be easily detached from the second pad PAD2. Since the side surface 550s of the protection pattern 550 is horizontally spaced apart from the side surface P2s of the second pad PAD2, a gap GAP may be formed between the protection pattern 550 and the second pad PAD2.

[0125] The shrinkage of the protection pattern 550 may depend on the process time and / or the process temperature in the curing process. For example, as the process time and / or the process temperature in the curing process increases, the shrinkage of the protection pattern 550 may increase. This may mean that by adjusting the process time and / or the process temperature in the curing process, the shape and size of the gap area between the protection pattern 550 and the second pad PAD2 can be controlled differently. For example, the protection pattern 550 may be spaced a constant distance from the second pad PAD2. When measured at the top surface P2t of the second pad PAD2, the distance between the side surface P2s of the second pad PAD2 and the side surface 550s of the protection pattern 550 may be a third width W3. When measured at the bottom surface P2b of the second pad PAD2, the distance between the side surface P2s of the second pad PAD2 and the side surface 550s of the protection pattern 550 may be a fourth width W4. In some example embodiments, the third width W3 may be substantially equal to the fourth width W4, such as Figure 2A shown.

[0126] In some example embodiments, the protection pattern 550 may be detached from the first pad PAD1. Figure 2B As shown, a portion of the bottom surface of the protection pattern 550 may be spaced apart from the top surface P1t of the first pad PAD1 in the vertical direction. A space may be formed between the protection pattern 550 and the first pad PAD1. For example, Figure 2B The process time and / or process temperature in the curing process may be greater than Figure 2A The process time and / or process temperature in the curing process.

[0127] In some example embodiments, the distance from the protection pattern 550 to the second pad PAD2 may not be constant. Figure 2C As shown, the third width W3 may be greater than the fourth width W4. In other words, the gap GAP between the protection pattern 550 and the second pad PAD2 may become narrower as the distance from the top surface P1t of the first pad PAD1 decreases. For example, Figure 2C The process time and / or process temperature in the curing process may be less than Figure 2A The process time and / or process temperature in the curing process.

[0128] refer to Fig. 10A , Fig. 10B and Figure 2A, the interposer substrate 600 on which the second semiconductor chip 700 is mounted may be mounted on the upper redistribution layer 500. The connection terminals 650 may be respectively provided on the lower pads 630 of the interposer substrate 600. The mounting of the interposer substrate 600 may include placing each connection terminal 650 on a corresponding redistribution pad 540 among the redistribution pads 540, and bonding each connection terminal 650 to the second pad PAD2 of the redistribution pad 540.

[0129] The placement of the connection terminal 650 may include placing the connection terminal 650 between the side surfaces 550s of the protection pattern 550. The top surface 550t of the protection pattern 550 may be located at a level higher than the top surface P2t of the second pad PAD2. Accordingly, the connection terminal 650 may be easily placed between the side surfaces 550s of the protection pattern 550. In other words, the protection pattern 550 may be used as a guide for accurately placing the connection terminal 650. Since the connection terminal 650 is placed between the side surfaces 550s of the protection pattern 550, the connection terminal 650 may contact the top surface P2t of the second pad PAD2.

[0130] The bonding of the connection terminal 650 and the second pad PAD2 may be performed by a reflow process. In this case, the connection terminal 650 may be melted by the reflow process, and the fluidity of the connection terminal 650 may be increased. In addition, the reactivity between the connection terminal 650 and the second pad PAD2 may be greater than the reactivity between the connection terminal 650 and the protection pattern 550. Accordingly, the melted portion of the connection terminal 650 may flow to the area on the side surface P2s of the second pad PAD2, rather than flowing to the area on the top surface 550t of the protection pattern 550. Therefore, the connection terminal 650 may be formed to fill the gap GAP between the second pad PAD2 and the protection pattern 550.

[0131] In other words, the connection terminal 650 may be formed to include a first portion P1 placed on the second pad PAD2, and a second portion P2 extending from the first portion P1 into the gap GAP. In other words, the joining of the connection terminal 650 and the second pad PAD2 may include: forming the first portion P1 of the connection terminal 650, and forming the second portion P2 of the connection terminal 650. Since the second portion P2 of the connection terminal 650 has an anchoring structure between the protection pattern 550 and the second pad PAD2, the possibility of a detachment problem of the connection terminal 650 can be prevented or reduced. Therefore, the reliability of the semiconductor package can be improved.

[0132] According to some example embodiments of the inventive concept, a semiconductor package may include a connection terminal in contact with a top surface and a side surface of a pad. In this case, the contact area between the connection terminal and the pad may be increased. Therefore, the electrical characteristics of the semiconductor package may be improved.

[0133] In addition, the connecting terminal may include a first portion disposed on the pad, and a second portion extending in an oblique direction between the protection pattern and the pad. The second portion of the connecting terminal may have an anchoring structure between the protection pattern and the pad. Therefore, the possibility of the connecting terminal being detached from the pad can be prevented or reduced. In addition, the second portion of the connecting terminal may be configured to release the pressure applied downward from the outside of the semiconductor package. Therefore, the reliability of the semiconductor package can be improved.

[0134] While example embodiments of the inventive concepts have been particularly shown and described, it will be understood by those skilled in the art that changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor package, comprising: Semiconductor chips; a redistribution layer on the semiconductor chip; a protection pattern covering the redistribution layer; as well as connecting terminals, on the redistribution layer, wherein the redistribution layer comprises redistribution pads on a top surface of the redistribution layer, The redistribution pad includes a first pad and a second pad on the first pad, The second pad has a side surface that is inclined and extends to a top surface of the first pad, and The protection pattern is spaced apart from the side surface of the second pad, and has a side surface that is inclined and extends to the top surface of the first pad.

2. The semiconductor package according to claim 1, wherein The connection terminal includes a first portion on the second pad, and a second portion extending between the side surface of the second pad and the side surface of the protection pattern.

3. The semiconductor package according to claim 2, wherein: The second portion contacts the top surface of the first pad.

4. The semiconductor package according to claim 2, wherein: The second portion has a width that decreases as a distance from the first pad decreases.

5. The semiconductor package according to claim 2, wherein: The connection terminal further includes a third portion extending from the second portion to a region between a bottom surface of the protection pattern and the top surface of the first pad.

6. The semiconductor package according to claim 1, wherein A width of the second pad increases as a distance from the top surface of the first pad increases.

7. The semiconductor package according to claim 1, wherein: A width of the second pad decreases as a distance from the top surface of the first pad increases.

8. The semiconductor package according to claim 1, wherein A top surface of the protection pattern is higher than a top surface of the second pad.

9. The semiconductor package according to claim 1, wherein: The protection pattern covers a side surface of the first pad and a portion of the top surface of the first pad, and the protection pattern exposes the second pad.

10. The semiconductor package according to claim 1, wherein The second pad vertically overlaps the first pad.

11. The semiconductor package according to claim 1, wherein The width of the first pad is greater than the width of the second pad.

12. The semiconductor package according to claim 1, wherein A roughness of the side surface of the protection pattern is greater than a roughness of the side surface of the second pad.

13. The semiconductor package according to claim 1, wherein The first pad and the second pad include metal materials different from each other.

14. The semiconductor package according to claim 1, wherein: The side surface of the second pad is inclined at an angle of 3° to 20° with respect to a direction perpendicular to the top surface of the first pad.

15. A semiconductor package, comprising: Lower redistribution layer; a first semiconductor chip on the lower redistribution layer; an upper redistribution layer on the first semiconductor chip, the upper redistribution layer comprising redistribution pads on a top surface of the upper redistribution layer; a second semiconductor chip on the upper redistribution layer; connecting terminals to electrically connect the second semiconductor chip to the upper redistribution layer; as well as a protection pattern, on the upper redistribution layer, The redistribution pad includes a first pad and a second pad on the first pad. The protection pattern has a side surface on the first pad, and the side surface of the protection pattern is spaced apart from a side surface of the second pad, and The connection terminal includes a first portion on a top surface of the second pad, and a second portion between a side surface of the second pad and a side surface of the protection pattern.

16. The semiconductor package according to claim 15, wherein: The width of the first pad is greater than the width of the second pad, and The first pad and the second pad vertically overlap each other.

17. The semiconductor package according to claim 15, wherein: The second portion extends to a top surface of the first pad in an oblique direction, and the second portion contacts the top surface of the first pad.

18. The semiconductor package according to claim 15, wherein: The vertical length of the second portion ranges from 3 μm to 5 μm, and The horizontal width of the second portion ranges from 1 μm to 4 μm.

19. The semiconductor package according to claim 15, wherein: The first pad comprises copper Cu, and The second pad includes nickel (Ni) or gold (Au).

20. A semiconductor package, comprising: Lower redistribution layer; a logic chip on the lower redistribution layer; a connection substrate, on the lower redistribution layer, surrounding the logic chip in a plan view; A molding layer covering the logic chip and the connection substrate; an upper redistribution layer, on the molding layer, the upper redistribution layer comprising redistribution pads; a protection pattern covering the upper redistribution layer; a memory chip on the upper redistribution layer; as well as a connecting terminal on a corresponding one of the redistribution pads, the connecting terminal being between the upper redistribution layer and the memory chip, Each of the redistribution pads includes a first pad and a second pad on the first pad, The protection pattern covers the first pad and is horizontally spaced apart from the second pad, Each of the connection terminals includes a first portion on the second pad and a second portion extending between the second pad and the protection pattern, and The second pad and the protection pattern have side surfaces that are inclined and extend to a top surface of the first pad.

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