A method for high-frequency current harmonic suppression of a modular dual-winding permanent magnet synchronous motor

Abstract

The application discloses a high-frequency current harmonic suppression method for a modular double-winding permanent magnet synchronous motor and relates to the field of double-winding permanent magnet synchronous motor control. The method solves the problems of cost increase caused by multiple inverters and energy conversion not considered in the prior control strategy. The method comprises the following steps: constructing a double-winding permanent magnet synchronous motor control system, wherein the power supply topology of the control system is an isolated interleaved parallel topology; obtaining a motor rotor position angle and a rotating speed signal, calculating the difference between a rotating speed given value and a rotating speed feedback signal, and obtaining two sets of d-axis and q-axis current given values; obtaining 6-phase current values, obtaining actual values of the d-axis and q-axis currents of the two sets of windings according to a coordinate transformation matrix, and solving the difference between the d-axis and q-axis currents as the input of a current loop PI controller; performing coordinate transformation on the output of the current loop PI controller, calculating a voltage modulation ratio, selecting a proper voltage modulation strategy and a carrier phase shift angle, and performing high-frequency current harmonic suppression. The application is applied to the field of high-frequency current harmonic suppression.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of double-winding permanent magnet synchronous motor control, and particularly relates to a high-frequency current harmonic suppression method for a modular double-winding permanent magnet synchronous motor. BACKGROUND

[0002] The double-winding permanent magnet synchronous motor has the advantages of low-voltage large-capacity operation and high reliability, but when the inductance of the motor is small, the high-frequency current harmonic content caused by the voltage modulation process is large. At the same time, in some high-power application occasions, the switching frequency of the power switching device is limited, which will further increase the high-frequency harmonic current content in the system. The existence of high-frequency harmonic current will increase the high-frequency loss of the system and cause a large high-frequency noise in the system.

[0003] In order to suppress the high-frequency harmonic current, some scholars have proposed a control strategy using an isolated interleaved parallel topology combined with a carrier phase-shifted technology. In order to suppress the high-frequency current harmonics near 1 times and 2 times the switching frequency as much as possible, three three-phase inverters are needed. Therefore, the technology has the following defects:

[0004] Only the power supply topology is improved, such as adding more inverters, which can improve the current harmonics to a certain extent, but cannot fundamentally solve the complexity of the control system and the problem of hardware cost. Since multiple inverters (for example, three three-phase inverters) are used, the hardware requirements of the control system increase significantly, which will lead to an increase in system cost.

[0005] At the same time, the improvement of the power supply topology only enhances the hardware structure, but does not effectively consider the problem of energy conversion efficiency. Although the introduction of multiple inverters may help to suppress some harmonics, the increased number and complexity of inverters may lead to a decrease in the energy conversion efficiency of the system. Especially in a multi-inverter system, the loss, heat dissipation problem and frequency control problem in the power conversion process may affect the overall efficiency, especially under high load or long time operation. SUMMARY

[0006] The present application proposes a high-frequency current harmonic suppression method for a modular double-winding permanent magnet synchronous motor to solve the problems of cost increase and energy conversion efficiency affected by the use of multiple inverters in the existing control strategy using an isolated interleaved parallel topology combined with a carrier phase-shifted technology, and the method comprises:

[0007] S1: constructing a double-winding permanent magnet synchronous motor control system, wherein the power supply topology of the double-winding permanent magnet synchronous motor control system is an isolated interleaved parallel topology, including two sets of three-phase inverters and three common-mode inductors;

[0008] S2: According to the resolver, the motor rotor position angle and the rotating speed signal are obtained, the difference between the rotating speed given value and the rotating speed feedback signal is calculated as the input of the speed loop PI controller, and the d-axis and q-axis current given values of the two sets of windings are obtained;

[0009] S3: The 6-phase current values are obtained through the current sensor, the actual values of the d-axis and q-axis currents of the two sets of windings are obtained according to the coordinate transformation matrix, and the difference between the given values and the actual values of the d-axis and q-axis currents is solved as the input of the current loop PI controller;

[0010] S4: The output of the current loop PI controller is coordinate-transformed to obtain the given voltage value in the α-β coordinate system, and the voltage modulation ratio M is calculated according to the control system;

[0011] S5: According to the voltage modulation ratio M, the appropriate voltage modulation strategy and carrier phase shift angle are selected for high-frequency current harmonic suppression of the double-winding permanent magnet synchronous motor.

[0012] Further, an optimal mode is also proposed, and step S4 comprises:

[0013]

[0014] Wherein, M is the voltage modulation ratio, V dc is the bus voltage, u d1 is the d-axis current inner loop output, u q1 is the q-axis current inner loop output.

[0015] Further, an optimal mode is also proposed, and the voltage modulation strategy in step S5 comprises a space vector voltage modulation strategy SVPWM and a double-switch sequence voltage modulation strategy DSPWM.

[0016] Further, an optimal mode is also proposed, and the matching principle between the voltage modulation ratio M, the voltage modulation strategy and the carrier phase shift angle is:

[0017] The relationship between the high-frequency voltage harmonic content and the voltage modulation ratio M is calculated;

[0018] The relationship between the current harmonic content and the voltage modulation ratio M is calculated;

[0019] An isolated interleaved parallel topology based on two three-phase inverters is adopted for harmonic analysis;

[0020] According to the high-frequency current harmonic distribution characteristics when the space vector voltage modulation strategy SVPWM and the double-switch sequence voltage modulation strategy DSPWM are adopted, the carrier phase shift angle size and the voltage modulation strategy are selected.

[0021] Further, an optimal mode is also proposed, and the calculation of the relationship between the high-frequency voltage harmonic content and the voltage modulation ratio M comprises:

[0022]

[0023] where A mn represents the real part of the harmonic voltage amplitude, B mn represents the imaginary part of the harmonic voltage amplitude, j represents the imaginary unit, m represents the harmonic order of the carrier, n represents the harmonic order of the fundamental, i represents the number of sectors, y s (i) represents the lower limit of the interval of the i-th sector, y e (i) represents the upper limit of the interval of the i-th sector; x r (i) represents the carrier phase corresponding to the rising edge in the voltage waveform in the i-th sector, x f (i) represents the carrier phase corresponding to the falling edge in the voltage waveform in the i-th sector, V dc represents the bus voltage.

[0024] Further, a preferred mode is also proposed, which calculates the relationship between the current harmonic content and the voltage modulation ratio M, comprising:

[0025]

[0026] where I m-rms represents the m times switching frequency harmonic current distortion value, L is the motor phase inductance; h = 0, 1, 2, 3…, f c represents the carrier frequency, f0 represents the motor operating fundamental frequency.

[0027] Further, a preferred mode is also proposed, which uses an isolated interleaved parallel topology based on two three-phase inverters for harmonic analysis, comprising:

[0028] Obtain the motor phase voltage u ao1 :

[0029]

[0030] where Z0(ω0) represents the coupling inductance impedance; Z A1 (ω0) represents the A1 phase winding impedance; u ag1 , u bg1 and u cg1 represent the output voltage of the first set of three-phase inverters, u ag2 , u bg2 and u cg2 represent the three-phase output voltage of the second set of three-phase inverters;

[0031] According to the double Fourier decomposition formula, the output voltage of each bridge arm of the inverter is calculated;

[0032] According to the output voltage of each bridge arm of the inverter, the harmonic voltage content influencing factors are analyzed.

[0033] Further, a preferred mode is also proposed, and the specific matching principle of the mixed modulation strategy and the voltage modulation ratio M is:

[0034] When M<0.41, the space vector voltage modulation strategy SVPWM is adopted and the carrier phase shift angle is set to π / 2;

[0035] When 0.41<M<0.84, the double-switch sequence voltage modulation strategy DSPWM is adopted and the carrier phase shift angle is set to π;

[0036] When 0.84<M<0.98, the space vector voltage modulation strategy SVPWM is adopted and the carrier phase shift angle is set to π;

[0037] When M>0.98, the space vector voltage modulation strategy DSPWM is adopted and the carrier phase shift angle is set to π / 2.

[0038] Based on the same inventive concept, the application also proposes a computer device comprising a memory and a processor, the memory storing a computer program, when the processor runs the computer program stored in the memory, the processor executes the modular double-winding permanent magnet synchronous motor high-frequency current harmonic suppression method according to any one of the above.

[0039] Based on the same inventive concept, the application also proposes a computer readable storage medium, the computer readable storage medium storing a computer program, when the computer program is run by a processor, the steps of the modular double-winding permanent magnet synchronous motor high-frequency current harmonic suppression method according to any one of the above are executed.

[0040] The application has the advantages of:

[0041] In the traditional isolated interleaved parallel topology, multiple inverters are used to realize the suppression of high-frequency current harmonics, which usually leads to a significant increase in hardware cost and requires a complex control system for coordination. The introduction of multiple inverters increases the hardware cost, and increases the complexity of system debugging, maintenance and troubleshooting. The application adopts a double-winding permanent magnet synchronous motor combined with two sets of three-phase inverter power supply topology, and suppresses high-frequency harmonics through an optimized control strategy, avoids the use of too many inverters, effectively controls the complexity of the overall system, and relatively reduces the hardware cost.

[0042] In the traditional method, although the harmonics are reduced by increasing the inverter, the efficiency of energy conversion is not specially considered, which may cause the overall energy conversion efficiency of the system to be reduced due to the increase in the number of hardware, the increase in control difficulty and other factors. The application can maintain a high energy conversion efficiency while reducing harmonics through optimization of the control system and voltage modulation strategy. For example, the current control of the motor is optimized through the precise current loop PI controller and the coordinate transformation matrix, so that the system operates at a high efficiency, thereby reducing energy loss.

[0043] The harmonic suppression measures in the traditional scheme are often only for certain specific frequency range, and the harmonic control problem of the system under different loads and operating conditions is not considered from a global perspective. Some schemes may only rely on the improvement of the hardware topology, and are not optimized for specific working environment. The application realizes high-frequency current harmonic suppression in a wider frequency spectrum through carrier phase-shift technology and voltage modulation ratio selection, can dynamically select the most suitable modulation strategy according to the real-time operation of the motor, and can flexibly adapt to changes under different loads and working conditions, achieving a more comprehensive harmonic suppression effect.

[0044] The application is applied to the field of high-frequency current harmonic suppression. BRIEF DESCRIPTION OF DRAWINGS

[0045] Figure 1 The double-winding permanent magnet synchronous motor control system schematic diagram of the embodiment one is shown in the figure.

[0046] Figure 2 The isolation type interleaved parallel topology structure diagram of the embodiment one is shown in the figure.

[0047] Figure 3 The I sector SVPWM and DSPWM modulation strategy switch sequence diagram of the embodiment eleven is shown in the figure.

[0048] Figure 4 The sector division schematic diagram of the embodiment eleven is shown in the figure.

[0049] Figure 5 The theoretical calculation and simulation result schematic diagram of the harmonic voltage amplitude under the DSPWM modulation of the embodiment eleven is shown in the figure.

[0050] Figure 6 The theoretical calculation and simulation result schematic diagram of the harmonic voltage amplitude under the SVPWM modulation of the embodiment eleven is shown in the figure.

[0051] Figure 7 The high-order harmonic current distortion value under the SVPWM modulation and the DSPWM modulation of the embodiment eleven is shown in the figure.

[0052] Figure 8 The motor system circuit network schematic diagram of the embodiment eleven is shown in the figure.

[0053] Figure 9 is a schematic diagram of the minimum high-order current harmonic content under different modulation strategies according to embodiment eleven;

[0054] Figure 10 is a schematic diagram of the pre-suppression current waveform according to embodiment eleven;

[0055] Figure 11 is a schematic diagram of the pre-suppression current FFT analysis according to embodiment eleven;

[0056] Figure 12 is a schematic diagram of the post-suppression current waveform according to embodiment eleven;

[0057] Figure 13 is a schematic diagram of the post-suppression current waveform FFT analysis according to embodiment eleven. DETAILED DESCRIPTION

[0058] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application.

[0059] Embodiment one, see Figure 1 and Figure 2 This embodiment describes a high-frequency current harmonic suppression method for a modular dual-winding permanent magnet synchronous motor. The method comprises:

[0060] S1: Construct a dual-winding permanent magnet synchronous motor control system, wherein the power supply topology of the dual-winding permanent magnet synchronous motor control system is an isolated interleaved topology, including two sets of three-phase inverters and three common-mode inductors;

[0061] S2: Obtain the motor rotor position angle and speed signal according to the resolver, calculate the difference between the speed given and the speed feedback signal as the input of the speed loop PI controller, and obtain the d-axis and q-axis current given values of the two sets of windings;

[0062] S3: Obtain the 6-phase current value through the current sensor, obtain the actual value of the d-axis and q-axis currents of the two sets of windings according to the coordinate transformation matrix, and solve the difference between the given value and the actual value of the d-axis and q-axis currents as the input of the current loop PI controller;

[0063] S4: Perform coordinate transformation on the output of the current loop PI controller to obtain the given voltage value in the α-β coordinate system, and calculate the voltage modulation ratio according to the control system;

[0064] S5: Selecting appropriate voltage modulation strategy and carrier phase shift angle according to voltage modulation ratio M to suppress high-frequency current harmonics of double-winding permanent magnet synchronous motor.

[0065] In traditional isolated interleaved parallel topologies, multiple inverters are used to suppress high-frequency current harmonics, which often leads to a significant increase in hardware cost and the need for complex control systems for coordination. The introduction of multiple inverters increases hardware costs and increases the complexity of system debugging, maintenance, and troubleshooting. In this embodiment, by using a double-winding permanent magnet synchronous motor combined with a power supply topology of two sets of three-phase inverters, and through an optimized control strategy to suppress high-frequency harmonics, the use of excessive inverters is avoided, effectively controlling the overall system complexity and reducing hardware costs.

[0066] In traditional methods, although the number of inverters is increased to reduce harmonics, the efficiency of energy conversion is not specifically considered, which may lead to a decrease in overall energy conversion efficiency due to an increase in the number of hardware and an increase in control difficulty. In this embodiment, by optimizing the control system and voltage modulation strategy, high energy conversion efficiency can be maintained while reducing harmonics. For example, by using precise current loop PI controllers and coordinate transformation matrices to optimize motor current control, the system can operate at high efficiency, thereby reducing energy loss.

[0067] The harmonic suppression measures in traditional solutions often only target certain specific frequency ranges and do not consider the harmonic control problem of the system under different loads and operating conditions from a global perspective. Some solutions may rely solely on hardware topology improvements without optimizing for specific operating environments. In this embodiment, by using carrier phase shift technology and selecting voltage modulation ratio, high-frequency current harmonic suppression is achieved over a wider frequency spectrum, allowing dynamic selection of the most suitable modulation strategy based on real-time motor operating conditions and flexible adaptation to changes under different loads and operating conditions, achieving more comprehensive harmonic suppression effects.

[0068] The method proposed in this embodiment can reduce the number of hardware inverters by using modular design and optimized double-winding permanent magnet synchronous motor power supply topology, and suppress harmonics through a relatively simple and efficient control system, thereby reducing the overall system cost and complexity.

[0069] In this embodiment, precise current regulation is achieved through precise current loop PI controllers and coordinate transformation technology, ensuring that the motor maintains high energy conversion efficiency at different operating points. Energy loss due to hardware redundancy or inaccurate control is avoided.

[0070] The carrier phase-shift technology and adaptive adjustment of the voltage modulation ratio are adopted in the embodiment, so that the suppression effect of the high-frequency current harmonics can be flexibly adjusted to adapt to the requirements under different loads and operating conditions. This enables the system to provide stable and efficient harmonic control in a wider range of application scenarios.

[0071] Further, since the double-winding design and voltage modulation strategy adopted in the embodiment can optimize control under different motor operating conditions, the sensitivity of the system to external disturbances and load changes is reduced, thereby improving the robustness of the system. The design of multiple sets of inverters and current control loops also ensures that the entire system remains highly stable and reliable when a component malfunctions.

[0072] Embodiment two, the embodiment is a further limitation of the modular double-winding permanent magnet synchronous motor high-frequency current harmonic suppression method of embodiment one, step S4 comprises:

[0073]

[0074] Wherein, M is the voltage modulation ratio, V dc is the bus voltage, u d1 is the d-axis current inner loop output, u q1 is the q-axis current inner loop output.

[0075] Embodiment three, the embodiment is a further limitation of the modular double-winding permanent magnet synchronous motor high-frequency current harmonic suppression method of embodiment one, the voltage modulation strategy in step S5 comprises space vector voltage modulation strategy SVPWM and double-switch sequence voltage modulation strategy DSPWM.

[0076] The combination of the two modulation strategies in the embodiment makes the motor control system highly flexible, enabling it to automatically select the optimal voltage modulation method according to different loads, speeds and operating states, thereby adapting to various working environments and different operating conditions. In scenarios with large load changes, the use of SVPWM and DSPWM strategies can automatically adjust the voltage and current waveforms, effectively avoiding an increase in high-frequency harmonics caused by load fluctuations.

[0077] Embodiment four, the embodiment is a further limitation of the modular double-winding permanent magnet synchronous motor high-frequency current harmonic suppression method of embodiment three, the matching principle between the voltage modulation ratio M, the voltage modulation strategy and the carrier phase-shift angle is:

[0078] Calculate the relationship between the high-frequency voltage harmonic content and the voltage modulation ratio M;

[0079] Calculate the relationship between the current harmonic content and the voltage modulation ratio M;

[0080] Harmonic analysis is performed on an isolated interleaved parallel topology based on two three-phase inverters.

[0081] According to the high-frequency current harmonic distribution characteristics when using the space vector voltage modulation strategy SVPWM and the double-switch sequence voltage modulation strategy DSPWM, the carrier phase shift angle size and voltage modulation strategy are selected.

[0082] In this embodiment, by calculating the relationship between the high-frequency voltage harmonic content and the voltage modulation ratio (M), and the relationship between the current harmonic content and the voltage modulation ratio (M), the distribution and amplitude of the harmonics can be accurately evaluated. In this way, targeted parameter optimization can be carried out to effectively reduce high-frequency harmonics. Combined with harmonic content analysis, by comparing the high-frequency current harmonic distribution characteristics under different modulation strategies (such as the space vector voltage modulation strategy SVPWM and the double-switch sequence voltage modulation strategy DSPWM), appropriate modulation strategies and carrier phase shift angles are selected to further reduce harmonics.

[0083] The isolated interleaved parallel topology using two three-phase inverters can reduce the generation of harmonics through current distribution and timing control. An important advantage of the interleaved topology is that the current waveforms of each inverter are interleaved with each other, effectively balancing the current waveform and reducing the impact of high-frequency harmonics. This topology not only reduces the harmonic interference of the motor drive system, but also improves the reliability and efficiency of the system, as it achieves smooth and balanced inverter output.

[0084] Using precise voltage modulation ratio and carrier phase shift angle configuration, the generation of high-frequency harmonics can be actively suppressed. This modulation strategy precisely controls the current waveform of the motor, keeping the amplitude of the harmonics at the lowest level in the system, thereby reducing electromagnetic interference (EMI) and energy loss during motor operation. Further, according to the characteristics of different modulation strategies (such as SVPWM and DSPWM), the carrier phase shift angle can be flexibly selected to effectively avoid harmonic overlap by adjusting the phase relationship of the carrier frequency, making the output waveform closer to a sine wave and reducing the negative impact of harmonics on motor performance.

[0085] In this embodiment, by reducing the content of high-frequency current harmonics, the additional loss of the motor can be reduced, the heating of the motor winding can be reduced, and the efficiency of the motor can be improved.

[0086] Embodiment five, this embodiment is a further limitation of the modular dual-winding permanent magnet synchronous motor high-frequency current harmonic suppression method of embodiment four, the calculation of the relationship between the high-frequency voltage harmonic content and the voltage modulation ratio M includes:

[0087]

[0088] wherein A mnRepresents the real part of the harmonic voltage amplitude, B mn Represents the imaginary part of the harmonic voltage amplitude, j represents the imaginary unit, m represents the harmonic order of the carrier; n represents the harmonic order of the fundamental wave; i represents the sector number; y s (i) represents the lower limit of the interval of the i-th sector, y e (i) represents the upper limit of the interval of the i-th sector; x r (i) represents the carrier phase corresponding to the rising edge of the voltage waveform in the i-th sector, x f (i) represents the carrier phase corresponding to the falling edge of the voltage waveform in the i-th sector, V dc Indicates the bus voltage.

[0089] Embodiment 6: This embodiment further limits the method for suppressing high-frequency current harmonics of a modular dual-winding permanent magnet synchronous motor described in Embodiment 5. The calculation of the relationship between the current harmonic content and the voltage modulation ratio M includes:

[0090]

[0091] Among them, I m-rms Indicates the harmonic current distortion value of m times the switching frequency, L is the motor phase inductance; h=0,1,2,3…, f c Indicates the carrier frequency, f0 indicates the fundamental frequency of the motor.

[0092] Embodiment 7: This embodiment further limits the method for suppressing high-frequency current harmonics of a modular dual-winding permanent magnet synchronous motor described in Embodiment 4. The harmonic analysis is performed using an isolated interleaved parallel topology based on two three-phase inverters, including:

[0093] Get the motor phase voltage u represented by the inverter output voltage ao1 :

[0094]

[0095] Where Z0(ω0) represents the coupled inductor impedance; Z A1 (ω0) represents the impedance of the A1 phase winding; u ag1 、u bg1 and u cg1 Indicates the output voltage of the first three-phase inverter, u ag2 、u bg2 and u cg2 Indicates the three-phase output voltage of the second three-phase inverter;

[0096] The output voltage of each bridge arm of the inverter is calculated according to the double Fourier decomposition formula;

[0097] Analyze the factors affecting the harmonic voltage content based on the output voltage of each bridge arm of the inverter.

[0098] In this embodiment, the frequency spectrum of the inverter output voltage can be accurately analyzed through the double Fourier decomposition formula, and the content of voltage harmonics can be identified and quantified. This method not only identifies high-frequency harmonic components, but also obtains the source and influencing factors of harmonics, which is crucial for designing more effective harmonic suppression strategies and helps to achieve precise current regulation, thereby reducing harmonic-induced losses and motor vibration. The staggered parallel topology of two three-phase inverters makes the operating currents of the two inverters phase-shifted. In this way, the harmonic interference generated by the simultaneous operation of the two inverters can be effectively reduced. The staggered parallel topology allows the harmonic phases between the two inverters to cancel each other out, effectively reducing the harmonic current in the motor windings. This topology improves the system's harmonic suppression capability and improves the motor's running stability and efficiency.

[0099] During the operation of the permanent magnet synchronous motor, especially at high speed or high load, high-frequency harmonic currents may cause the motor to heat up, increase noise, and reduce efficiency. Through this method, the impact of high-frequency current harmonics can be accurately identified and reduced. Combined with the staggered parallel topology and accurate control of the inverter output voltage, these high-frequency current harmonics can be suppressed at the source, thereby improving the reliability and stability of the system.

[0100] Furthermore, by analyzing the harmonics of the output voltage of each bridge arm of the inverter, the operating mode of the inverter can be optimized to operate efficiently with lower harmonics. Effective harmonic suppression not only reduces energy loss due to harmonics, but also reduces electromagnetic interference inside and outside the motor, thereby improving the energy efficiency and stability of the entire drive system.

[0101] Embodiment Eight, this embodiment is a further limitation of the modular dual-winding permanent magnet synchronous motor high-frequency current harmonic suppression method of Embodiment Four, the specific matching principle of the hybrid modulation strategy and the voltage modulation ratio M is:

[0102] When M < 0.41, use the space vector voltage modulation strategy SVPWM and set the carrier phase shift angle to π / 2;

[0103] When 0.41 < M < 0.84, use the double-switch sequence voltage modulation strategy DSPWM and set the carrier phase shift angle to π;

[0104] When 0.84 < M < 0.98, use the space vector voltage modulation strategy SVPWM and set the carrier phase shift angle to π;

[0105] When M > 0.98, use the space vector voltage modulation strategy DSPWM and set the carrier phase shift angle to π / 2.

[0106] Embodiment nine, the computer device of the embodiment, comprising a memory and a processor, the memory has stored therein a computer program, when the processor runs the computer program stored in the memory, the processor executes a modular dual-winding permanent magnet synchronous motor high-frequency current harmonic suppression method according to any one of embodiments one to seven.

[0107] Embodiment ten, a computer readable storage medium of the embodiment, the computer readable storage medium has stored thereon a computer program, the computer program is run by the processor to execute the steps of a modular dual-winding permanent magnet synchronous motor high-frequency current harmonic suppression method as claimed in any one of embodiments one to seven.

[0108] Embodiment eleven, see Figures 3 to 12 This embodiment is described. This embodiment is a specific embodiment of the modular dual-winding permanent magnet synchronous motor high-frequency current harmonic suppression method of embodiment one, and is also used to explain embodiments two to eight, specifically:

[0109] Step one: according to Figure 1 The control system block diagram shown in is used to build a dual-winding permanent magnet synchronous motor control system, and the power supply topology is an isolated interleaved topology, which includes two sets of three-phase inverters and three common-mode inductors, and the topology structure is shown in Figure 2 ;

[0110] Step two: according to the resolver, the motor rotor position angle and the speed signal are obtained, the difference between the speed given value and the speed feedback signal is calculated, and then the difference is taken as the input of the speed loop PI controller, and the d, q axis current given values of the two sets of windings are obtained;

[0111] Step three: the 6-phase current values are obtained through the current sensor, and then the actual values of the d, q axis currents of the two sets of windings are obtained through the coordinate transformation matrix, and then the difference between the given values and the actual values of the d, q axis currents is solved and taken as the input of the current loop PI controller;

[0112] Step four: the output of the current loop PI controller is subjected to coordinate transformation to obtain the given voltage value in the α-β coordinate system, and the voltage modulation ratio M is calculated according to the bus voltage V dc , the current inner loop output u d1 and u q1 ; the calculation formula is:

[0113]

[0114] Step five: select a proper voltage modulation strategy and carrier phase shift angle τ according to the voltage modulation ratio M, wherein the voltage modulation strategy includes space vector voltage modulation strategy (SVPWM) and double-switch sequence voltage modulation strategy (DSPWM), and the switch sequence of the two voltage modulation strategies is as shown in Figure 3 .

[0115] The calculation process of the matching principle between voltage modulation ratio M, carrier phase shift angle τ and voltage modulation strategy in step five is as follows:

[0116] (1) Calculate the relationship between high-frequency voltage harmonic content and voltage modulation ratio M

[0117] The theoretical calculation of the harmonic voltage content of each multiple of the switching frequency and the frequency near the frequency under different M. Taking the double-switch sequence voltage modulation strategy as an example, the fundamental voltage and each harmonic voltage component in the modulation voltage can be calculated by the following formula:

[0118]

[0119] In the formula, A mn and B mn respectively represent the real part and the imaginary part of the harmonic voltage amplitude; m represents the harmonic number of the carrier; n represents the harmonic number of the fundamental; i represents the sector number; y s (i) and y e (i) respectively represent the lower limit and the upper limit of the interval in the i-th sector; x r (i) and x f (i) respectively represent the rising edge and the falling edge of the voltage waveform in the i-th sector corresponding to the carrier phase.

[0120] When the double-switch sequence modulation strategy is adopted, the number of switches in sectors II and V is 2, so the integral interval of the formula in sectors II and V has two segments; the number of switches in sectors III and IV is 0, so the integral result of the formula in sectors III and IV is 0, and the sector division is as shown in Figure 4 . The intersection of the voltage average in the sector and the carrier can be obtained by calculating the integral interval of each sector, as shown in the following table:

[0121] The integral interval in the table is substituted into the high-frequency voltage harmonic component calculation formula to calculate the amplitude of each high-frequency harmonic voltage under different voltage modulation ratios, and the calculation formula is:

[0122]

[0123] Under the working conditions of V dc = 200 V, f c = 20000π, f0= 500π, the frequency f c+f0 and 2f c The harmonic voltage amplitude of +f0 varies with M value as shown in Figure 5 The triangle in the figure represents the simulation result obtained by simulation software at corresponding M. It can be seen from the figure that the theoretical calculation result of the harmonic voltage amplitude is basically the same as the simulation result, and thus the harmonic voltage amplitude of each frequency can be calculated more accurately by using the above formula.

[0124] Similarly, the harmonic voltage amplitude of +f0 and 2f obtained by using SVPWM voltage modulation can be calculated as dc = 200V, f c = 20000π, f0= 500π, the harmonic voltage amplitude of +f0 and 2f obtained by using SVPWM voltage modulation can be calculated as c +f0 and 2f c The harmonic voltage amplitude of +f0 varies with M value as shown in Figure 6

[0125] (2) Calculation of the relationship between current harmonic content and voltage modulation ratio M

[0126] In order to more clearly see which voltage modulation strategy is used and what size of carrier phase shift angle is set under different modulation ratios M to make the high-order harmonic current content in the system smaller, the high-order current harmonic distortion of the phase winding under high-order harmonic voltage excitation is defined in the embodiment, and the calculation formula is:

[0127]

[0128] In the formula, L is the phase inductance of the motor; h = 0, 1, 2, 3…

[0129] The distribution of the high-frequency current harmonic content near 1 times the switching frequency and near 2 times the switching frequency when SVPWM and DSPWM are used is calculated by using the above formula, and the calculation result is shown in Figure 7 In the present application, the calculation result is standardized, and the reference value is V dc / L.

[0130] (3) Harmonic analysis of the system when the isolation type interleaved parallel topology based on two three-phase inverters is used

[0131] The motor system network is shown in Figure 8 Taking the A1 phase winding as an example, the motor phase voltage u ao1 represented by the output voltage of the inverter can be obtained according to the motor system network diagram.

[0132]

[0133] In the formula, Z0(ω0) represents the coupling inductance impedance; Z A1 (ω0) represents the A1 phase winding impedance; u ag1 , u​bg1 and u cg1 respectively represent the three-phase bridge arm output voltages of the first set of three-phase inverters; u ag2 , u bg2 and u cg2 respectively represent the three-phase output voltages of the second set of three-phase inverters.

[0134] According to the double Fourier decomposition formula, the specific expression of the bridge arm output voltage of the inverter can be calculated, taking the A1 phase bridge arm as an example:

[0135]

[0136] In the formula, A 1-00 = V dc , a is a modulation coefficient, ω0 is a motor fundamental angular frequency, and ω c is a carrier angular frequency.

[0137] Suppose that the initial phase angle of the carrier in the first set of inverters is 0, and the initial phase angle of the carrier in the second set of inverters is τ, and the phase difference of the carriers of the two sets of three-phase inverters is τ.

[0138] When the phase difference of the carriers is τ, the phase voltage of the A1 winding can be further derived as:

[0139]

[0140] When n = ±3p, p = 0, 1, 2, 3L, the harmonic voltage content of m ≠ 0 in the A1 phase voltage u ao1 can be 0; when n ≠ ±3p, p = 0, 1, 2, 3L, the A1 phase voltage can be simplified as

[0141]

[0142] From the above formula, it can be seen that the harmonic voltage content in the A1 phase voltage is not only related to the phase difference τ of the carriers, but also related to the impedance value of the coupling inductance and the motor impedance value. By reasonably designing the initial phase angle τ of the carrier of the second set of inverters, the suppression effect on the high-order voltage harmonics in the A1 phase voltage can be achieved.

[0143] In order to suppress the high-frequency current harmonics near 1 times the switching frequency, the carrier phase shift angle τ can be changed so that the value of Z0(ω0)(3+3cos(τ))+Z A1 (ω0) is minimum, and at the same time, 3Z0(ω0)sin(τ) = 0, at this time, τ = π can be solved. In order to suppress the high-order current harmonics near 2 times the switching frequency, the carrier phase shift angle τ can be changed so that the value of Z0(ω0)(3+3cos(2τ))+Z A1The value of (ω0) is minimum, while 3Z0(ω0)sin(mτ) = 0, at this time, τ = 0.5π can be solved.

[0144] (4): Optimal matching of voltage modulation ratio, carrier phase shift angle and voltage modulation strategy

[0145] When the isolated interleaved parallel topology is used to supply power to the double-winding permanent magnet synchronous motor, the high-order current harmonics of specific frequencies can be suppressed by reasonably setting the phase shift angle between the two sets of inverters. The high-order harmonic components of the motor phase current are mainly concentrated near the switching frequency and its multiple frequencies. When the carrier phase shift angle is set to π, the current harmonics near the 1 times switching frequency can be suppressed. When the carrier phase shift angle is set to π / 2, the current harmonics near the 2 times switching frequency can be suppressed. For the SVPWM voltage modulation strategy and the DSPWM voltage modulation strategy, the high-order harmonic voltage content at different frequencies will change with the change of M, thereby causing the change of the high-order current harmonic content at different frequencies. When the SVPWM voltage modulation strategy is used, the current harmonic content near the 2 times switching frequency is larger when the value of M is smaller, and the current harmonic content near the 1 times switching frequency is smaller when the value of M is larger. Therefore, when M changes, the carrier phase shift angle needs to be reasonably set to ensure that the high-order harmonic components in the current are always small. At the same time, when different voltage modulation strategies are used, the distribution of current harmonic content at each frequency is also different. Since only two sets of three-phase inverters are used in the present application, changing the carrier phase shift angle can only suppress the current harmonics near the 1 times switching frequency or the current harmonics near the 2 times switching frequency. In order to suppress the high-frequency current harmonics as much as possible, the carrier phase shift angle and the voltage modulation strategy need to be reasonably selected according to the distribution characteristics of the high-frequency current harmonics when SVPWM and DSPWM are used, so as to realize the minimum high-frequency current harmonic content under different voltage modulation ratios M.

[0146] According to the calculation results of (2), the optimal voltage modulation strategy and the size of the carrier phase shift angle under different voltage modulation ratios M can be obtained. Figure 9 The minimum high-order current harmonic content of the system under different voltage modulation ratios M when SVPWM, DSPWM and hybrid modulation are used is shown. As can be seen from the figure, when hybrid modulation is used, the advantages of the two voltage modulation strategies can be fully utilized, thereby ensuring the minimum high-order current harmonic content in the system under different voltage modulation ratios M. The specific matching principle of the hybrid modulation strategy and the voltage modulation ratio M is as follows: when M < 0.41, the SVPWM modulation strategy is used and the carrier phase shift angle is set to π / 2; when 0.41 < M < 0.84, the DSPWM modulation strategy is used and the carrier phase shift angle is set to π; when 0.84 < M < 0.98, the SVPWM modulation strategy is used and the carrier phase shift angle is set to π; when M > 0.98, the DSPWM modulation strategy is used and the carrier phase shift angle is set to π / 2.

[0147] The calculation result is stored into a microprocessor, in this example, a signal processing chip of TI company model TMS320F28377D.

[0148] Step six: after selecting the appropriate voltage modulation strategy and carrier phase shift angle according to the voltage modulation ratio M, the PWM wave sending logic in the master control chip needs to be modified in real time (selecting SVPWM or DSPWM). At the same time, the initial phase angle of the second carrier needs to be changed in real time, in this example, the TBPHS register of the PWM unit of the master control chip needs to be changed.

[0149] The effectiveness of the present application is verified by experiments as follows:

[0150] The method is verified on a double-winding permanent magnet synchronous motor drag test platform. The direct-axis inductance of the motor is 0.36 mH, the quadrature-axis inductance is 0.56 mH, the stator resistance is 0.034 Ω, the bus voltage is set to 100 V, the switching frequency is 10 kHz, the rotating speed is set to 300 r / min, and the torque is 20. Under this working condition, the voltage modulation ratio is 0.4, according to the calculation result of step two, the SVPWM voltage modulation strategy should be selected and the carrier phase shift angle is set to π / 2. The experimental results are shown in Figs. Figure 10 、 11 、12 and 13. As can be seen from the results, when the method of the present application is not used, the current harmonic content near the one-time switching frequency is smaller than that near the two-time switching frequency when the SVPWM voltage modulation is used. Since two three-phase inverters are used, the current harmonics near the one-time switching frequency and the two-time switching frequency cannot be suppressed at the same time. Under this working condition, the current near the two-time switching frequency is suppressed to ensure that the high-frequency current harmonic content is the smallest.

[0151] From the above, it can be seen that the present application only uses two three-phase inverters to realize the suppression of the high-frequency current harmonics near the one-time switching frequency or the two-time switching frequency under different voltage modulation ratios M, and ensures that the high-frequency current harmonic content is smaller under different voltage modulation ratios;

[0152] Since the present application only uses two three-phase inverters, the system cost is lower;

[0153] The present application fully utilizes the distribution characteristics of the high-frequency current harmonics when the SVPWM and DSPWM modulation strategies are used, and realizes smaller high-frequency current harmonics under different voltage modulation ratios M through hybrid modulation.

[0154] Those skilled in the art will appreciate that embodiments of the disclosure can be supplied as a method, a system, or a computer program product. Thus, the disclosure can take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the disclosure can take the form of a computer program product on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROMs, optical storage devices, etc.) embodying computer-readable program code.

[0155] The disclosure is described in reference to the flowchart and / or block diagrams of the method, apparatus (system) and computer program product according to embodiments of the disclosure. It should be understood that each flow and / or block in the flowchart and / or block diagram and a combination of flows and / or blocks in the flowchart and / or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing apparatus to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing apparatus produce a device that implements the flow Figure 1 one or more flows and / or blocks Figure 1 one or more flows and / or blocks Figure 1 one or more flows and / or blocks Figure 1 one or more flows and / or blocks

[0156] These computer program instructions can also be loaded into a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable data processing apparatus to produce a computer-implemented process, so that the instructions executed by the computer or other programmable data processing apparatus provide a process for implementing the flow Figure 1 one or more flows and / or blocks Figure 1 one or more flows and / or blocks

[0157] Finally, it should be noted that the above embodiments are merely used to illustrate the technical solutions of the present disclosure, but not to limit the protection scope of the present disclosure. Although the present disclosure is described in detail with reference to the above embodiments, those skilled in the art should understand that after reading the present disclosure, they can make various changes, modifications or equivalent replacements to the specific embodiments. However, these changes, modifications or equivalent replacements should be within the scope of the disclosure.

Claims

1. A method for suppressing high-frequency current harmonics in a modular dual-winding permanent magnet synchronous motor, characterized in that: The method comprises: S1: Build a dual-winding permanent magnet synchronous motor control system, where the power supply topology of the dual-winding permanent magnet synchronous motor control system is an isolated interleaved parallel topology, including two sets of three-phase inverters and three common-mode inductors; S2: Obtain the motor rotor position angle and speed signal from the resolver, calculate the difference between the speed reference and speed feedback signals as the input of the speed loop PI controller, and obtain the d-axis and q-axis current reference values ​​of the two sets of windings; S3: Obtain the 6-phase current values ​​through the current sensor, obtain the actual values ​​of the d-axis and q-axis currents of the two sets of windings according to the coordinate transformation matrix, and solve the difference between the set value and the actual value of the d-axis and q-axis currents as the input of the current loop PI controller; S4: Perform coordinate transformation on the output of the current loop PI controller to obtain a given voltage value in the α-β coordinate system, and calculate the voltage modulation ratio according to the control system. M ; S5: According to the voltage modulation ratio M Select appropriate voltage modulation strategy and carrier phase shift angle to suppress high-frequency current harmonics in dual-winding permanent magnet synchronous motors; In step S5, the voltage modulation strategy includes a space vector voltage modulation strategy SVPWM and a dual switch sequence voltage modulation strategy DSPWM; Voltage modulation ratio M , the matching principle between the voltage modulation strategy and the carrier phase shift angle is: Calculate high-frequency voltage harmonic content and voltage modulation ratio M relationship; Calculate current harmonic content and voltage modulation ratio M relationship; Harmonic analysis is performed using an isolated interleaved parallel topology based on two three-phase inverters; According to the high-frequency current harmonic distribution characteristics when using space vector voltage modulation strategy SVPWM and dual-switch sequence voltage modulation strategy DSPWM, the carrier phase shift angle and voltage modulation strategy are selected.

2. A method for suppressing high-frequency current harmonics of a modular dual-winding permanent magnet synchronous motor according to claim 1, characterized in that: Step S4 includes: in, M is the voltage modulation ratio, is the bus voltage, is the inner loop output of the first winding d-axis current, It is the inner loop output of the q-axis current of the first winding.

3. The method for suppressing high-frequency current harmonics of a modular dual-winding permanent magnet synchronous motor according to claim 1, characterized in that: The calculation of high-frequency voltage harmonic content and voltage modulation ratio M relationships, including: in, A mn represents the real part of the harmonic voltage amplitude, B mn Represents the imaginary part of the harmonic voltage amplitude, j represents the imaginary unit, m Indicates the harmonic order of the carrier; n Indicates the harmonic order of the fundamental wave; i Indicates the number of sectors; Indicates the i The lower limit of the sector interval, Indicates the i The upper limit of the sector range; Indicates the i The carrier phase corresponding to the rising edge of the voltage waveform in the sector, Indicates the i The carrier phase corresponding to the falling edge of the voltage waveform in the sector, V dc Indicates the bus voltage.

4. A method for suppressing high-frequency current harmonics of a modular dual-winding permanent magnet synchronous motor according to claim 3, characterized in that: The calculation of the relationship between the current harmonic content and the voltage modulation ratio M includes: in, Indicates the harmonic distortion value of the harmonic current at m times the switching frequency, L is the motor phase inductance; h =0,1,2,3…, Indicates the carrier frequency, f 0 indicates the motor's fundamental frequency.

5. The method for suppressing high-frequency current harmonics of a modular dual-winding permanent magnet synchronous motor according to claim 1, characterized in that: The harmonic analysis is performed using an isolated interleaved parallel topology based on two three-phase inverters, including: Get the motor phase voltage represented by the inverter output voltage : in, represents the coupled inductor impedance; Indicates the A1 phase winding impedance; 、 and Represents the output voltage of the first three-phase inverter, 、 and Indicates the three-phase output voltage of the second three-phase inverter; The output voltage of each bridge arm of the inverter is calculated according to the double Fourier decomposition formula; Analyze the factors affecting the harmonic voltage content based on the output voltage of each bridge arm of the inverter.

6. The method for suppressing high-frequency current harmonics of a modular dual-winding permanent magnet synchronous motor according to claim 1, characterized in that: The specific matching principle between the hybrid modulation strategy and the voltage modulation ratio M is: when When the space vector voltage modulation strategy SVPWM is used and the carrier phase shift angle is set to ; when When , the dual switch sequence voltage modulation strategy DSPWM is adopted and the carrier phase shift angle is set to π; when When , the space vector voltage modulation strategy SVPWM is adopted and the carrier phase shift angle is set to π; when When the space vector voltage modulation strategy DSPWM is used and the carrier phase shift angle is set to .

7. A computer device, characterized in that: The method comprises a memory and a processor, wherein a computer program is stored in the memory. When the processor runs the computer program stored in the memory, the processor executes a method for suppressing high-frequency current harmonics of a modular dual-winding permanent magnet synchronous motor according to any one of claims 1 to 6.

8. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, which, when executed by a processor, executes the steps of a method for suppressing high-frequency current harmonics of a modular dual-winding permanent magnet synchronous motor according to any one of claims 1 to 6.

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