Coding and decoding method and device, and storage medium

Abstract

The invention provides a coding and decoding method, equipment and a storage medium. The coding method comprises the following steps: coding a first bit sequence according to a preset pre-ordered polarization sequence and a polarization permutation table to obtain a second bit sequence; wherein the first bit sequence is a sequence of which the number of input coding bits is K; the pre-sorted polarization sequence is used for indicating the reliability arrangement sequence of the polarization sub-channel indexes of the polarization code with the maximum code length of Nmax, and has the characteristic that the code length nesting is the same as the reliability arrangement sequence of the polarization sub-channel indexes of all the sub-codes; the polarization permutation table is used for indicating sub-block indexes needing rate adjustment when the number of input coding bits is K; the code length of the second bit sequence is N; and sending the second bit sequence to a receiving end.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a coding and decoding method, device and storage medium. Background Art

[0002] The Fast Successive Cancellation (Fast-SC) algorithm is a commonly used fast decoding algorithm for polar codes. The basic idea of ​​the algorithm is that the decoding problem of a polar code with a length of N can be regarded as the decoding of two subcodes with a length of N / 2, and there is a fast decoding method for a specific type of subcode. The decoding of polar codes can be regarded as a process of depth-first traversal on a binary tree, and the number of nodes that need to be traversed determines the decoding delay. The fast decoding of a specific type of subcode in the Fast-SC algorithm can effectively reduce the number of nodes that need to be traversed, thereby reducing the decoding delay of the polar code. In the prior art, fast decoding methods for various types of subcodes are proposed, such as Rate-0, REP (Repetition), REP-2, PCR (Parity checked repetition), RPC (Repeated parity check), SPC-2, SPC (Single-Parity-Check) and Rate-1 nodes. However, there are still many types of subcodes that cannot be decoded quickly, which has become a bottleneck for further reducing the decoding complexity and delay of polar codes. Another existing method is to use a rate adjustment algorithm to adjust the code rate of polar code subcodes to eliminate the subcodes in polar codes that cannot be decoded quickly. This method requires running the rate adjustment algorithm once for each code length and code rate configuration, resulting in higher complexity. Summary of the invention

[0003] In view of this, the embodiments of the present application provide an encoding and decoding method, device and storage medium, which effectively reduce the number of nodes that need to be processed during the decoding process and improve the decoding parallelism.

[0004] The embodiment of the present application provides an encoding method, which is applied to a transmitting end, including:

[0005] The first bit sequence is encoded according to a preset pre-ordered polarization sequence and a polarization permutation table to obtain a second bit sequence; wherein the first bit sequence is a sequence with an input coding bit number of K; the pre-ordered polarization sequence is used to indicate that the maximum code length is N maxThe polarization permutation table is used to indicate the sub-block indexes that need to be rate adjusted when the number of input coded bits is K; the code length of the second bit sequence is N;

[0006] The second bit sequence is sent to the receiving end.

[0007] The present application provides a decoding method, which is applied to a receiving end and includes:

[0008] Receive a second bit sequence sent by a transmitting end; wherein the code length of the second bit sequence is N;

[0009] The second bit sequence is decoded to obtain a codeword estimation value.

[0010] An embodiment of the present application provides a communication device, including: a memory, and one or more processors;

[0011] The memory is configured to store one or more programs;

[0012] When the one or more programs are executed by the one or more processors, the one or more processors implement the method described in any of the above embodiments.

[0013] An embodiment of the present application provides a storage medium, wherein the storage medium stores a computer program, and when the computer program is executed by a processor, the method described in any of the above embodiments is implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a flowchart of an encoding method provided in an embodiment of the present application;

[0015] Figure 2 is a flowchart of a decoding method provided in an embodiment of the present application;

[0016] Figure 3 2. This is a schematic diagram showing a performance comparison of a polar code in different coding schemes provided in an embodiment of the present application;

[0017] Figure 4 is a schematic diagram of performance comparison of another polar code provided in an embodiment of the present application in different coding schemes;

[0018] Figure 5 is a structural block diagram of a coding device provided in an embodiment of the present application;

[0019] Figure 6 is a structural block diagram of a decoding device provided in an embodiment of the present application;

[0020] Figure 7 It is a structural diagram of a communication device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0021] The following will describe the embodiments of the present application in conjunction with the accompanying drawings. The following will describe the present application in conjunction with the accompanying drawings of the embodiments, and the examples cited are only used to explain the present application and are not used to limit the scope of the present application.

[0022] The fast polar code construction method in the existing scheme includes the following steps: segmenting the (N, K) polar code constructed by the traditional polar code construction method according to the length of 16; all frozen bit positions are initialized to active state, and the active bit positions can be converted to information bit positions; judging whether each segment belongs to the fast decodable mode set, if it does not belong to the fast decodable mode set, converting the most unreliable information position of the current segment to a frozen bit position, and converting the frozen bit position in an active state in a subsequent segment to an information bit position; the segment where the frozen bit position converted to the information bit position is located should still belong to the fast decodable mode set after the conversion, if not, the position is changed to an inactive state, and then the position is reselected. However, the existing scheme needs to run a rate adjustment algorithm for each code length and code rate configuration, resulting in high complexity.

[0023] In view of this, an embodiment of the present application proposes a fast polar code encoding and decoding method, which can perform fast polar code encoding and fast decoding of multiple nodes based on a pre-ordered polarization sequence and a polarization permutation table, thereby reducing the number of subcodes required to be processed during the decoding process and improving the decoding parallelism.

[0024] In one embodiment, Figure 1 It is a flowchart of a coding method provided by an embodiment of the present application. This embodiment is applied to the case of fast polar code coding. This embodiment can be executed by a transmitting end. Among them, the transmitting end can also be understood as an encoding end, and can include a first communication node, and can also include a second communication node. Among them, the first communication node can be a base station side, and the second communication node can be a terminal side. It should be noted that a communication node can also be called a communication device.

[0025] like Figure 1 As shown, this embodiment includes: S110-S120.

[0026] S110. Encode the first bit sequence according to a preset pre-ordered polarization sequence and a polarization permutation table to obtain a second bit sequence.

[0027] The first bit sequence is a sequence with K input coding bits; the pre-ordered polarization sequence is used to indicate that the maximum code length is N. maxThe polarization permutation table is used to indicate the sub-block indexes that need to be rate adjusted when the number of input coded bits is K; the code length of the second bit sequence is N.

[0028] The first bit sequence refers to the input bit sequence; the second bit sequence refers to the output bit sequence. In one example, the code length N of the second bit sequence is 2 to the power of n, that is, N=2 n .

[0029] The transmitting end may encode the first bit sequence as the input bit sequence according to the preset pre-ordered polarization sequence and the polarization permutation table to obtain the second bit sequence as the output bit sequence.

[0030] S120: Send the second bit sequence to the receiving end.

[0031] In one embodiment, encoding a first bit sequence according to a preset pre-ordered polarization sequence and a polarization permutation table to obtain a second bit sequence includes:

[0032] determining an information bit index set according to a pre-ordered polarization sequence, a number of input coded bits, and a code length of a second bit sequence;

[0033] Generate a first sequence to be encoded according to the information bit index set;

[0034] Performing rate adjustment on the first sequence to be encoded according to the polarization permutation table to generate a second sequence to be encoded;

[0035] The second sequence to be encoded is replaced according to the first bit sequence to obtain a corresponding third sequence to be encoded;

[0036] The third sequence to be encoded is encoded according to a preset polarization transformation matrix to obtain a second bit sequence.

[0037] In one embodiment, determining an information bit index set according to a pre-ordered polarization sequence, a number of input coded bits, and a code length of a second bit sequence includes:

[0038] Extracting a corresponding subsequence from the pre-ordered polarization sequence according to a code length of the second bit sequence to obtain a corresponding polarization sequence;

[0039] The K elements with the highest reliability in the polarization sequence constitute an information bit index set, and the other elements in the polarization sequence constitute a frozen bit index set.

[0040] Elements less than or equal to the code length of the second bit sequence are extracted from the pre-sorted polarization sequence to form a corresponding polarization sequence; then, the reliability of each element in the polarization sequence is determined, and K elements with the highest reliability form an information bit index set, and other elements in the polarization sequence form a frozen bit index set.

[0041] In one embodiment, for the pre-ordered polarization sequence, when the naturally ordered polarization subchannel indexes are divided into equal lengths according to a preset subblock length, the relative order of the reliability of the polarization subchannel indexes in any subblock is fixed. The preset subblock length is a fixed value, and the preset subblock length is a power of 2. For example, assuming that the preset subblock length is M, then M=2 m and m<n; the first sequence to be encoded can be divided according to the preset sub-block length to obtain N / M sub-blocks of equal length. In one example, the relative order of the reliability of the polarization sub-channel index in each sub-block is fixed, which can ensure that the node type at the same code rate in the second bit sequence is unique.

[0042] In one embodiment, for the polarization permutation table, each row of data is composed of three columns of data, which are respectively the target bit number, the sub-block index where the frozen bits requiring rate adjustment are located, and the sub-block index where the information bits requiring rate adjustment are located.

[0043] In one embodiment, for the polarization permutation table, each row of data represents a rate adjustment operation.

[0044] In one embodiment, for the polarization permutation table, the rate adjustment range to be executed is determined by the row index of the maximum target bit number that is less than or equal to the input coded bit number and a preset range parameter. The preset range parameter may be a fixed value, and the range of the rate adjustment operation to be executed in the polarization permutation table is: the row index of the maximum target bit number minus the preset range parameter, plus one as the starting row; the row of the maximum target bit number is the ending row.

[0045] In one embodiment, for the first sequence to be encoded, the elements indexed by the information bit index set and the frozen bit index set are initialized to different fixed values, respectively. For example, the elements in the information bit index set can be initialized to 1, while the elements in the frozen bit index set can be initialized to 0.

[0046] In one embodiment, for rate adjustment between sub-blocks in the first sequence to be encoded, an interleaver interleaves two sub-blocks and then exchanges the least reliable information bits and the most reliable frozen bits.

[0047] In one embodiment, for the second sequence to be encoded after the rate adjustment is completed, the initialization values ​​of all information bits in the second sequence to be encoded are replaced by the first bit sequence. For the second sequence to be encoded obtained after the rate adjustment operation is completed, the elements in which all information bits in the second sequence to be encoded are replaced by the first bit sequence.

[0048] In one embodiment, for the sub-blocks whose rate is adjusted through interleaving, the sub-blocks obtained through deinterleaving are used to replace the original sub-blocks in the first sequence to be encoded.

[0049] In one embodiment, Figure 2 is a flowchart of a decoding method provided by an embodiment of the present application. This embodiment is applied to the case of fast polar code decoding. This embodiment can be executed by a receiving end. The receiving end can also be understood as a decoding end, which can include a base station side or a terminal side. Figure 2 As shown, this embodiment includes: S210-S220.

[0050] S210: Receive a second bit sequence sent by a transmitting end.

[0051] The code length of the second bit sequence is N.

[0052] S220: Decode the second bit sequence to obtain a codeword estimation value.

[0053] After receiving the second bit sequence sent by the transmitter, the receiver decodes the second bit sequence to obtain a codeword estimate. Since the transmitter encodes the second bit sequence, the number of nodes to be processed in the fast decoding process is effectively reduced, thereby improving the decoding parallelism.

[0054] Embodiment 1

[0055] In one embodiment, a fast polar code encoding method is described by taking a transmitting end as a first communication node and a receiving end as a second communication node as an example. Exemplarily, a fast polar code encoding method includes:

[0056] The first communication node sends the encoded second bit sequence to the second communication node.

[0057] In an embodiment, the first communication node encodes a first bit sequence having an input coding bit number of K according to a preset pre-ordered polarization sequence and a polarization permutation table to obtain a second bit sequence.

[0058] Among them, the pre-ordered polarization sequence is used to indicate that the maximum code length is N maxThe polarization permutation table is used to indicate the sub-block indexes that need to be rate adjusted when the number of coded bits increases to K.

[0059] Assume that the first bit sequence is the input bit sequence c0,c1,c2,c3,...,c K-1 , the second bit sequence is the output bit sequence d = [d0 d1 d2 ... d N-1 The first communication node receives the input bit sequence c0, c1, c2, c3, ..., c K-1 The following steps are performed to obtain the encoded output bit sequence d0, d1, d2, ..., d N-1 :

[0060] Step 1: determine an information bit index set according to a pre-ordered polarization sequence, a code length N of a second bit sequence, and a number K of input coded bits of a first bit sequence.

[0061] Specifically, the polarization sequence corresponding to the code length N is is the pre-ordered polarization sequence A subset of The information bit index set is composed of all elements less than N. By polarization sequence The K elements with the highest reliability in the frozen bit index set Made up of the remaining elements.

[0062] Step 2: Index the set based on the information bit Generate the first sequence to be encoded v = [v0 v1 v2 ... v N-1 ].

[0063] Specifically, the sequence v = [v0 v1 v2 ... v N-1 ] all indexes belong to the information bit index set The elements of are assigned a fixed value, and the remaining elements are assigned another fixed value.

[0064] Step 3: The first sequence to be encoded v = [v0 v1 v2 ... v N-1 ] to adjust the rate and obtain the second sequence to be encoded.

[0065] Specifically, the sequence v=[v0 v1 v2 ... v N-1 ] is divided into N / M equal-length sub-blocks, where M = 2 mAnd m<n. According to the polarization permutation table, the sub-blocks that cannot be quickly decoded are converted into sub-blocks that can be quickly decoded, and the second sequence to be encoded v′=[v′0v′1v′2...v′ N-1 ].

[0066] Step 4: According to the first bit sequence, the second sequence to be encoded is v′=[v′0v′1v′2...v′ N-1 ] to generate the third sequence to be encoded u=[u0 u1 u2 ... u N-1 ].

[0067] Specifically, the sequence v′=[v′0v′1v′2...v′ N -1] are replaced by the input bit sequence c = [c0 c1 c2 ... c K-1 ], and obtain the sequence u=[u0 u1 u2 ... u N-1 ].

[0068] Step 5: transform the third sequence to be encoded u=[u0 u1 u2 ... u N-1 ] to perform polarization transformation and obtain the encoded output bit sequence d = [d0 d1 d2 ... d N-1 ].

[0069] Specifically, the output bit sequence d = [d0 d1 d2 ... d N-1 ] through d = uG N Get, where G N is the polarization transformation matrix.

[0070] The second communication node decodes the channel reception value to obtain a codeword estimation value.

[0071] Specifically, in this embodiment, the polar code with a code length of N is represented as a full binary tree with a depth of n, and the second communication node performs depth-first node traversal decoding.

[0072] In this embodiment, the second communication node performs fast decoding on different types of nodes (referring to each node in the full binary tree):

[0073] Specifically, if all leaf nodes of the current node correspond to information bits, the log-likelihood ratio information α received from the parent node is directly v Make a hard decision to obtain the codeword of the current node.

[0074] If all leaf nodes of the current node correspond to frozen bits, then the codeword estimate β of the current node is v = 0. Obtain codeword β vAfter that, the codeword β is fed back to the parent node v .

[0075] If only the leaf node with the largest index in the current node corresponds to the information bit, then the node is a REP node, and the messages received by the node from the parent node are summed to obtain the decoding result.

[0076] If only the leaf node with the smallest index in the current node corresponds to the frozen bit, the node is an SPC node. The decoder responds to the message α received from the parent node. v Perform a hard decision to determine whether the hard decision result satisfies the parity check. If the parity check is satisfied, the hard decision result is fed back to the parent node; otherwise, the hard decision result after flipping the most unreliable position is fed back to the parent node.

[0077] If only the two leaf nodes with the smallest index in the current node correspond to the frozen bit, the node is an SPC-2 node. The message α will be received from the parent node v The messages are divided into two groups according to the parity of the index, and the two groups of messages are respectively used as the input of the SPC node for decoding.

[0078] If only the two leaf nodes with the largest index in the current node correspond to information bits, then the node is a REP-2 node. The message α will be received from the parent node v The messages are divided into two groups according to the parity of the index, and the decoding result can be obtained by summing the two groups of messages respectively.

[0079] If only the three leaf nodes with the smallest index in the current node correspond to frozen bits, the node is an RPC node. The decoder first directly v Make a hard decision to obtain β v , according to the result of modulo 4 operation on the index, β v Divide into 4 groups, calculate the checksum of each group respectively, and decode the 4 checksums as a virtual repetition code with a rate of 1 / 4. Determine the group that does not meet the check relationship based on the decoding result of the virtual repetition code, and flip the hard decision result of the most unreliable position.

[0080] If only the three leaf nodes with the largest index in the current node correspond to information bits, the node is a PCR node. The decoder divides the results of the modulo 4 operation on the index into four groups, sums each group of messages to obtain four enhanced signals, and uses the enhanced signals as the input of an SPC node for decoding.

[0081] If the number of leaf nodes of the current node is N v=16 and only the 12th, 14th, 15th and 16th leaf nodes correspond to information bits, then the node is a Rate0-REP-SPC (RORS) node. The decoder divides the index into 8 groups according to the result of the modulo 8 operation, and sums each group of messages to obtain 8 enhanced signals, which are decoded as the input of an RPC node. If the decoding result of the RPC node does not satisfy the check relationship of the node, the decoding result of the RPC node is expanded by bit flipping, and the result that satisfies the check relationship is selected as the decoder output.

[0082] If the index is the largest N v / 2-3 leaf nodes and Nth v / 2 leaf nodes correspond to information bits, and this node is a REP-RPC node. The decoder first directly decodes α v Make a hard decision to obtain β v , for β v The first N v / 2 elements and N v / 2 elements are added modulo 2 and then summed. If the sum is less than N v / 4, then for β v The first N v / 2 elements and N v / 2 elements are summed to get N v / 2 enhanced signals, otherwise obtained by subtraction. Finally, N v / 2 enhanced signals are decoded as input of an RPC node.

[0083] If the index is the largest N v / 2-2 leaf nodes and the Nth v / 2 leaf nodes correspond to information bits, and this node is a REP-SPC2 node. The decoding process of this node is the same as that of the REP-RPC node, except that N v / 2 enhanced signals are decoded as the input of an SPC2 node.

[0084] If the index is the largest N v / 2-1 leaf node and Nth v / 2 leaf nodes correspond to information bits, and this node is a REP-SPC node. The decoding process of this node is the same as that of the REP-RPC node, except that N v / 2 enhanced signals are decoded as the input of an SPC node.

[0085] If N v = 16 and only the 1st, 2nd, 3rd, 4th, 5th and 9th leaf nodes correspond to frozen bits, and this node is a PCR-SPC node. The decoder first directly decodes αv Make a hard decision to obtain β v , according to the result of modulo 4 operation on the index, β v Divide into 4 groups, and the checksum of each group constitutes a virtual repetition code with a rate of 1 / 4, which is known to be an all-0 code. At the same time, divide the index by 4 and then round it down to the integer value. v Divide into 4 groups, and decode the checksum of each group as another virtual repetition code with a rate of 1 / 4. Determine the number of groups that do not meet the check relationship in the two virtual code words based on the decoding result of the virtual repetition code, and perform bit flipping on the groups that do not meet the check relationship in the virtual code words with a larger number, so that they meet the check relationship of the two virtual repetition codes at the same time.

[0086] If N v =16 and only the 1st, 2nd, 3rd, 5th and 9th leaf nodes correspond to frozen bits, and this node is a REP-SPC-SPC (RSS) node. The decoding process of this node is the same as that of PCR-SPC, except that the first virtual repetition code is unknown and needs to be decoded.

[0087] If N v =16 and only the 1st, 2nd, 3rd and 5th leaf nodes correspond to frozen bits, and the node is a REP-SPC-Rate1 (RSR1) node. The decoder first decodes the node as an RPC node. If the decoding result of the RPC node does not satisfy the check relationship of the node, the decoding result of the RPC node is expanded by bit flipping, and the result that satisfies the check relationship is selected as the decoder output.

[0088] If the current node is a non-leaf node and is a node that cannot be quickly decoded, the message sent to the left child node is calculated and the feedback message from the left child node is waited. After receiving the message returned by the left child node, the message sent to the right child node is calculated and the feedback message from the right child node is waited. After receiving the message from the right child node, the decoding result of the current node is calculated and fed back to the parent node.

[0089] Specifically, for nodes that cannot be quickly decoded, first calculate the message sent to the left child node

[0090]

[0091] The function f(x,y) is defined as: f(x,y) = 2atanh(tanh(x / 2)tanh(y / 2)), then Send to the left child node v l Then the local decoder v waits until the left child node v l Receive codeword Then calculate

[0092]

[0093] Then Send to the right child node v r Then the local decoder v waits until the left child node v r Receive codeword Finally, calculate β v :

[0094]

[0095] Then β v Feedback to parent node p v These local decoders will not be activated again in the subsequent decoding process, so the local decoding operation in is terminated here.

[0096] When the root node obtains the codewords fed back by the left and right child nodes and After that, the decoding result is:

[0097]

[0098] Table 1 Comparison of the number of nodes

[0099] R 1 / 8 2 / 8 3 / 8 4 / 8 5 / 8 6 / 8 7 / 8 Original number of nodes 36 52 61 65 59 56 37 Number of nodes 23 30 35 38 38 34 23

[0100] As shown in Table 1, a comparison of the number of nodes at different rates for 5G NR polar codes with a code length of 1024 is given. Compared with the existing Fast-SC algorithm, the fast polar code encoding and decoding method proposed in this application effectively reduces the number of nodes that need to be traversed during the decoding process.

[0101] Figure 3 : is a schematic diagram of the performance comparison of a polar code provided in an embodiment of the present application in different coding schemes. Figure 3 As shown in the figure, the performance comparison of (1024,768) polar code under different encoding methods is given. It can be seen that compared with the original SC decoding algorithm of 5G NR polar code, the fast polar code encoding algorithm in this application effectively reduces the number of decoding nodes while only causing a performance loss of 0.1dB. Figure 4 : is a schematic diagram of the performance comparison of another polar code provided in an embodiment of the present application in different coding schemes. Figure 4 As shown in the figure, the performance comparison of (1024, 832) polar code under different coding methods is given. It can be seen that compared with the SC decoding performance of the original 5G NR polar code of the polar code, the fast coding algorithm in this application only causes a performance loss of 0.1dB while effectively reducing the number of decoding nodes.

[0102] Embodiment 2

[0103] This embodiment further illustrates the characteristics of the pre-ordered polarization sequence based on the above embodiment 1.

[0104] The pre-ordered polarization sequence in this embodiment has the following characteristics:

[0105] (1) In the pre-sorted polarization sequence In , the sequences are arranged in ascending order of reliability, i.e. in, Represents the polarization subchannel index reliability.

[0106] (2) In the pre-sorted polarization sequence When the naturally ordered polariton channel index When the sub-block length M is divided into equal lengths, the reliability of the polarization sub-channel index in any segment The relative ordering is fixed.

[0107] For example, as shown in Table 2, N max = 1024, that is, 1024 polarization sub-channels. When the naturally ordered polarization sub-channel index When equal-length segmentation is performed according to M=16, the polarization subchannel indexes in the i-th subblock are {i×M, i×M+1, …, i×M+15}. After modulo operation on the subblock length M, the local index set {0, 1, 2, …, 15} in the subblock is obtained. The reliability ranking satisfies:

[0108] W(0)<W(1)<W(2)<W(4)<W(8)<W(3)<W(5)<W(6)

[0109] <W(9)<W(10)<W(12)<W(7)<W(11)<W(13)<W(14)<W(15)

[0110] Table 2 Pre-sorted polarization sequence and its corresponding reliability

[0111]

[0112]

[0113]

[0114] Embodiment 3: Based on Embodiment 1 and Embodiment 2, this embodiment performs a first encoding sequence v=[v0v1 v2 ... v N-1 ] is further explained.

[0115] Specifically, a possible assignment method is: sequence v = [v0 v1 v2 ... v N-1 ] all indexes belong to the information bit index set The value of 1 is assigned to the elements of , and the value of 0 is assigned to the remaining elements.

[0116] For example, let N = 8, K = 4, Then the sequence v = [0 0 0 1 0 1 1 1].

[0117] Embodiment 4: Based on Embodiments 1 to 3, this embodiment further illustrates the polarization permutation table.

[0118] The polarization permutation table T in this embodiment n It has the following characteristics:

[0119] (1) In the polarization permutation table T n Including K t , e I and e F Three columns of data;

[0120] (2) In the polarization permutation table T n In, K t Indicates the target number of bits, e I and e F It represents the sub-block index after the sequence v is divided into equal lengths according to the sub-block length M, that is, e F is the sub-block index where the frozen bit that needs rate adjustment is located, e I is the sub-block index where the information bit that needs rate adjustment is located;

[0121] (3) In the polarization permutation table T n In the example, the exchange index is e. I and e F The information bits and frozen bits in the sub-blocks can eliminate specific types of sub-codes that cannot be decoded quickly.

[0122] The polarization permutation table when N=1024 is shown in Table 3. The range of the number of input coding bits K compatible with the table is 128≤K≤910. The table can eliminate the subcodes with a length of 16 and rates of 5 / 16 and 9 / 16 in the polar code.

[0123] Table 3: Polarization permutation table P for N = 1024 10

[0124]

[0125]

[0126] Embodiment 5

[0127] This embodiment provides another example of a polarization permutation table based on Embodiments 1 to 4, as shown in Table 4. The difference between this embodiment and Embodiment 4 is that:

[0128] (1) In the polarization permutation table, the corresponding code length N=512;

[0129] (2) In the polarization permutation table, the applicable range of the number of input coding bits K is 64≤K≤455.

[0130] Table 4: Polarization permutation table P9 for N=512

[0131]

[0132] Embodiment 6

[0133] This embodiment provides another example of a polarization permutation table based on Embodiments 1 to 5, as shown in Table 5. The difference between this embodiment and Embodiments 4 to 5 is that:

[0134] (1) In the polarization permutation table, the corresponding code length N=256;

[0135] (2) In the polarization permutation table, the applicable range of the number of input coding bits K is 32≤K≤228.

[0136] Table 5: Polarization permutation table P8 for N=256

[0137]

[0138] Embodiment 7

[0139] This embodiment provides another example of a polarization permutation table based on Embodiments 1 to 6, as shown in Table 6. The difference between this embodiment and Embodiments 4 to 6 is that:

[0140] (1) In the polarization permutation table, the corresponding code length N=128;

[0141] (2) In the polarization permutation table, the applicable range of the number of input coding bits K is 16≤K≤114.

[0142] Table 6: Polarization permutation table P7 for N=128

[0143]

[0144]

[0145] Embodiment 8

[0146] This embodiment provides another example of a polarization permutation table based on Embodiments 1 to 7, as shown in Table 7. The difference between this embodiment and Embodiments 4 to 7 is that:

[0147] (1) In the polarization permutation table, the corresponding code length N=64;

[0148] (2) In the polarization permutation table, the applicable range of the number of input coding bits K is 8≤K≤57.

[0149] Table 7: Polarization permutation table P6 for N=64

[0150]

[0151] Embodiment 9

[0152] This embodiment further illustrates the process of sub-block rate adjustment based on Embodiments 1 to 8.

[0153] A possible process of adjusting the sub-block rate in this embodiment is as follows:

[0154] Determine the polarization permutation table T n All rate adjustment operations that need to be performed in the polarization permutation table T n Each row represents a rate adjustment operation. Specifically, let the polarization permutation table T n The largest K that is less than or equal to K t The index of the row is D t , then it is necessary to execute the polarization permutation table T n Middle D t -D+1 row to D t The preset parameter D is a positive integer. For example, when the code length N=1024, the parameter D can be preset to 11.

[0155] Determine the polarization permutation table T n Whether the rate adjustment indicated by the current row in needs to be performed.

[0156] Specifically, the sequence v = [v0 v1 v2 ... v N-1 ] F The sub-block is e I The sub-block is If the node type corresponding to the sub-block can be decoded quickly, the rate adjustment of the current row does not need to be performed, otherwise the rate adjustment operation needs to be performed. When the sub-block length M=16, a possible implementation method in this embodiment is to determine the sub-block v F The rate is 5 / 16 or 9 / 16. The sequence v = [v0 v1 v2 ... v N-1] is generated as shown in Example 3, then for the sub-block v F and v I The sum can be obtained by the number of information bits r of the sub-block F and r I If the sub-block v F The number of information bits r F If it is 5 or 9, the rate adjustment operation of the current row needs to be performed.

[0157] Adjust sub-block v F and v I rate.

[0158] Specifically, sub-block v F The most reliable frozen bits in the sub-block v are converted into information bits. I The least reliable information bit is converted into a frozen bit. When the sub-block length M = 16, a possible implementation is as follows:

[0159] 1) Pair block v F and v I They are interleaved respectively to sort them according to their reliability. The interleaved sub-blocks are recorded as and The interlaced pattern is shown in Table 8:

[0160] Table 8: Interlacing pattern Π(m)

[0161]

[0162] 2) If r I =10 or r I =6, then swap sub-blocks The index belongs to the set {Mr F -1,Mr F -2} elements and sub-blocks The index in belongs to the set {Mr I ,Mr I +1}; otherwise, swap the sub-blocks The index is Mr F -1 elements and sub-blocks The index is Mr I Elements of

[0163] 3) Pair Blocks and Deinterleave, and the deinterleaved sub-block is recorded as and

[0164] 4) Set the sequence v = [v0 v1 v2 ... v N-1 ] of the sub-block v F and vI Replace with v′ F and v′ I .

[0165] The above rate adjustment operation is performed repeatedly until the polarization permutation table T n Middle D t -D+1 row to D t All rate adjustment operations in the row range are traversed once.

[0166] Embodiment 10

[0167] This embodiment provides another example of adjusting the sub-block rate based on the ninth embodiment. A major difference between this embodiment and the ninth embodiment is that:

[0168] When the sub-block length is M, another possible implementation is as follows:

[0169] Get the frozen bit index set With sub-block v F The intersection of the index sets of the elements in , that is, v F The frozen bit position index in According to the reliability of the index Pair Collection The indexes in the rank order are sorted, and the indexes with the highest and second highest reliability are recorded as d F and d′ F ;

[0170] Get the information bit index set With sub-block v I The intersection of the index sets of the elements in , that is, v I The information bit position index in According to the reliability of the index Pair Collection The indexes in the rank order are sorted, and the indexes with the lowest and second lowest reliability are recorded as d I and d′ I ;

[0171] Swap sequence v = [v0 v1 v2 ... v N-1 ] and

[0172] If r I =10 or r I = 6, then the exchange sequence v = [v0 v1 v2 ... v N-1 ] and Otherwise, swap sequence v = [v0 v1 v2 ... v N-1 ] and

[0173] In one embodiment, Figure 5 is a structural block diagram of a coding device provided in an embodiment of the present application. This embodiment is applied to the transmitting end. Figure 5 As shown, the encoding device in this embodiment includes: an encoder 510 and a transmitter 520.

[0174] The encoder 510 is configured to encode the first bit sequence according to a preset pre-ordered polarization sequence and a polarization permutation table to obtain a second bit sequence.

[0175] The first bit sequence is a sequence with K input coding bits; the pre-ordered polarization sequence is used to indicate that the maximum code length is N. max The polarization permutation table is used to indicate the sub-block indexes that need to be rate adjusted when the number of input coded bits is K; the code length of the second bit sequence is N;

[0176] The transmitter 520 is configured to send the second bit sequence to the receiving end.

[0177] In one embodiment, the encoder 510 includes:

[0178] A first determining unit is configured to determine an information bit index set according to a pre-ordered polarization sequence, a number of input coded bits, and a code length of a second bit sequence;

[0179] A first generating unit, configured to generate a first sequence to be encoded according to an information bit index set;

[0180] A second generating unit is configured to perform rate adjustment on the first sequence to be encoded according to the polarization permutation table to generate a second sequence to be encoded;

[0181] A third generating unit is configured to replace the second sequence to be encoded according to the first bit sequence to obtain a corresponding third sequence to be encoded;

[0182] The encoding unit is configured to encode the third sequence to be encoded according to a preset polarization transformation matrix to obtain a second bit sequence.

[0183] In one embodiment, the first determining unit includes:

[0184] an extraction subunit, configured to extract a corresponding subsequence from the pre-ordered polarization sequence according to a code length of the second bit sequence to obtain a corresponding polarization sequence;

[0185] The division subunit is configured to form an information bit index set with K elements with the highest reliability in the polarization sequence, and to form a frozen bit index set with other elements in the polarization sequence.

[0186] In one embodiment, for the pre-ordered polarization sequence, when the naturally ordered polarization subchannel indexes are divided into equal lengths according to a preset sub-block length, the relative order of the reliability of the polarization subchannel indexes in any sub-block is fixed.

[0187] In one embodiment, for the polarization permutation table, each row of data is composed of three columns of data, which are respectively the target bit number, the sub-block index where the frozen bits requiring rate adjustment are located, and the sub-block index where the information bits requiring rate adjustment are located.

[0188] In one embodiment, for the polarization permutation table, each row of data represents a rate adjustment operation.

[0189] In one embodiment, for the polarization permutation table, the rate adjustment range to be executed is determined by the row index where the maximum target number of bits is located and a preset range parameter; wherein the maximum target number of bits is less than or equal to the input coded bit number.

[0190] In one embodiment, for the first sequence to be encoded, the elements whose indices belong to the information bit index set and the frozen bit index set are respectively initialized to different fixed values.

[0191] In one embodiment, for rate adjustment between sub-blocks in the first sequence to be encoded, an interleaver interleaves two sub-blocks and then exchanges the least reliable information bits and the most reliable frozen bits.

[0192] In one embodiment, for the second sequence to be encoded after rate adjustment, the initialization values ​​of all information bits in the second sequence to be encoded are replaced by the first bit sequence.

[0193] In one embodiment, for the sub-blocks whose rate is adjusted through interleaving, the sub-blocks obtained through deinterleaving are used to replace the original sub-blocks in the first sequence to be encoded.

[0194] The encoding device provided in this embodiment is configured to implement Figure 1 The encoding method applied to the transmitting end in the illustrated embodiment and the encoding device provided in this embodiment are similar in implementation principle and technical effect, and will not be described in detail here.

[0195] In one embodiment, Figure 6 is a structural block diagram of a decoding device provided in an embodiment of the present application. This embodiment is applied to a receiving end. Figure 6 As shown, the decoding device in this embodiment includes: a receiver 610 and a decoder 620.

[0196] The receiver 610 is configured to receive a second bit sequence sent by the transmitter; wherein the code length of the second bit sequence is N;

[0197] The decoder 620 is configured to decode the second bit sequence to obtain a codeword estimation value.

[0198] The decoding device provided in this embodiment is configured to implement Figure 2 The decoding method applied to the receiving end in the illustrated embodiment is similar to the implementation principle and technical effect of the decoding device provided in this embodiment, which will not be described in detail here.

[0199] In one embodiment, Figure 7 Schematic diagram of the structure of a communication device provided in an embodiment of the present application. Figure 7 As shown, the device provided by the present application includes: a processor 710, a memory 720 and a communication module 730. The number of processors 710 in the device can be one or more. Figure 7 In the example, a processor 710 is used. The number of memories 720 in the device may be one or more. Figure 7 A memory 720 is taken as an example. The processor 710, the memory 720 and the communication module 730 of the device can be connected via a bus or other means. Figure 7 In the embodiment, the bus connection is taken as an example. In this embodiment, the device may be a transmitting end.

[0200] The memory 720, as a computer-readable storage medium, may be configured to store software programs, computer executable programs, and modules, such as program instructions / modules corresponding to the device of any embodiment of the present application (e.g., the encoder 510 and the transmitter 520 in the encoding device). The memory 720 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created according to the use of the device, etc. In addition, the memory 720 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other non-volatile solid-state storage device. In some instances, the memory 720 may further include a memory remotely arranged relative to the processor 710, and these remote memories may be connected to the device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0201] In the case where the communication device is a transmitting end, the above-provided device can be configured to execute the encoding method applied to the transmitting end provided in any of the above-mentioned embodiments, and have corresponding functions and effects.

[0202] In the case where the communication device is a receiving end, the above-provided device can be configured to execute the decoding method applied to the receiving end provided in any of the above-mentioned embodiments, and have corresponding functions and effects.

[0203] The embodiment of the present application also provides a storage medium containing computer executable instructions. When the computer executable instructions are executed by a computer processor, they are used to execute a coding method applied to a transmitting end. The method includes: encoding a first bit sequence according to a preset pre-ordered polarization sequence and a polarization permutation table to obtain a second bit sequence; wherein the first bit sequence is a sequence with an input coding bit number of K; the pre-ordered polarization sequence is used to indicate that the maximum code length is N max The method comprises the following steps: a polarization permutation table is used to indicate a sub-block index for which rate adjustment is required when the number of input coding bits is K; the code length of the second bit sequence is N; and the second bit sequence is sent to a receiving end.

[0204] An embodiment of the present application also provides a storage medium containing computer executable instructions. When the computer executable instructions are executed by a computer processor, they are used to execute a decoding method applied to a receiving end. The method includes: receiving a second bit sequence sent by a sending end; wherein the code length of the second bit sequence is N; decoding the second bit sequence to obtain a codeword estimate.

[0205] It will be appreciated by those skilled in the art that the term user equipment encompasses any suitable type of wireless user equipment, such as a mobile phone, a portable data processing device, a portable web browser or a car-mounted mobile station.

[0206] In general, various embodiments of the present application can be implemented in hardware or dedicated circuits, software, logic or any combination thereof. For example, some aspects can be implemented in hardware, while other aspects can be implemented in firmware or software that can be executed by a controller, microprocessor or other computing device, although the present application is not limited thereto.

[0207] Embodiments of the present application may be implemented by executing computer program instructions by a data processor of a mobile device, for example in a processor entity, or by hardware, or by a combination of software and hardware. The computer program instructions may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages.

[0208] The block diagram of any logic flow in the drawings of the present application may represent program steps, or may represent interconnected logic circuits, modules and functions, or may represent a combination of program steps and logic circuits, modules and functions. A computer program may be stored on a memory. The memory may have any type suitable for the local technical environment and may be implemented using any suitable data storage technology, such as but not limited to read-only memory (ROM), random access memory (RAM), optical memory devices and systems (digital versatile discs (DVD) or compact disks (CD)), etc. Computer-readable media may include non-transient storage media. A data processor may be any type suitable for the local technical environment, such as but not limited to a general-purpose computer, a special-purpose computer, a microprocessor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FGPAs) and a processor based on a multi-core processor architecture.

[0209] The above are only preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A coding method, characterized in that: Applied to the sending end, including: The first bit sequence is encoded according to a preset pre-ordered polarization sequence and a polarization permutation table to obtain a second bit sequence; wherein the first bit sequence is a sequence with an input coding bit number of K; the pre-ordered polarization sequence is used to indicate that the maximum code length is N max The polarization permutation table is used to indicate the sub-block indexes that need to be rate adjusted when the number of input coded bits is K; the code length of the second bit sequence is N; The second bit sequence is sent to the receiving end.

2. The method according to claim 1, characterized in that The step of encoding the first bit sequence according to the preset pre-ordered polarization sequence and the polarization permutation table to obtain the second bit sequence includes: determining an information bit index set according to the pre-ordered polarization sequence, the number of input coded bits, and a code length of the second bit sequence; Generate a first sequence to be encoded according to the information bit index set; Performing rate adjustment on the first sequence to be encoded according to the polarization permutation table to generate a second sequence to be encoded; The second sequence to be encoded is replaced according to the first bit sequence to obtain a corresponding third sequence to be encoded; The third sequence to be encoded is encoded according to a preset polarization transformation matrix to obtain a second bit sequence.

3. The method according to claim 2, characterized in that The determining the information bit index set according to the pre-ordered polarization sequence, the input coded bit number and the code length of the second bit sequence includes: extracting a corresponding subsequence from the pre-ordered polarization sequence according to a code length of the second bit sequence to obtain a corresponding polarization sequence; The K elements with the highest reliability in the polarization sequence form an information bit index set, and the other elements in the polarization sequence form a frozen bit index set.

4. The method according to any one of claims 1 to 3, characterized in that: For the pre-ordered polarization sequence, when the naturally ordered polarization subchannel indexes are divided into equal lengths according to a preset sub-block length, the relative order of the reliability of the polarization subchannel indexes in any sub-block is fixed.

5. The method according to any one of claims 1 to 3, characterized in that: For the polarization permutation table, each row of data is composed of three columns of data, which are the target bit number, the sub-block index where the frozen bits that need to be rate adjusted are located, and the sub-block index where the information bits that need to be rate adjusted are located.

6. The method according to any one of claims 1 to 3, characterized in that: For the polarization permutation table, each row of data represents a rate adjustment operation.

7. The method according to any one of claims 1 to 3, characterized in that: For the polarization permutation table, the rate adjustment range to be executed is determined by the row index where the maximum target number of bits is located and a preset range parameter; wherein the maximum target number of bits is less than or equal to the input coding bit number.

8. The method according to claim 3, characterized in that For the first sequence to be encoded, the elements indexed by the information bit index set and the elements indexed by the frozen bit index set are respectively initialized to different fixed values.

9. The method according to claim 2, characterized in that: For rate adjustment between sub-blocks in the first sequence to be encoded, the interleaver interleaves two sub-blocks and then exchanges the least reliable information bits and the most reliable frozen bits.

10. The method according to claim 2, characterized in that For the second sequence to be encoded after rate adjustment, the initialization values ​​of all information bits in the second sequence to be encoded are replaced by the first bit sequence.

11. The method according to claim 9, characterized in that For the sub-blocks whose rate is adjusted through interleaving, the sub-blocks obtained through deinterleaving are used to replace the original sub-blocks in the first sequence to be encoded.

12. A decoding method, characterized in that: Applied to the receiving end, including: Receive a second bit sequence sent by a transmitting end; wherein the code length of the second bit sequence is N; The second bit sequence is decoded to obtain a codeword estimation value.

13. A communication device, characterized in that: include: memory, and one or more processors; The memory is configured to store one or more programs; When the one or more programs are executed by the one or more processors, the one or more processors implement the method as described in any one of claims 1 to 11 or 12 above.

14. A storage medium, characterized in that: The storage medium stores a computer program, and when the computer program is executed by a processor, the method according to any one of claims 1 to 11 or 12 is implemented.

Images