Chip testing method and device for asynchronous half-duplex communication protocol, and testing machine

Abstract

The invention relates to the technical field of chip testing, and discloses a chip testing method for an asynchronous half-duplex communication protocol, and the method comprises the steps: transmitting a testing instruction and a standard duration signal to a chip under the condition that the chip is powered on, so as to calculate the deviation proportions of internal clock signals and external clock signals of a plurality of gears; wherein the internal clock signals of different gears are in one-to-one correspondence with the deviation proportions; sampling the standard duration signal by using an internal clock to obtain deviation data for dynamic calibration; comparing the signal sampling results of the plurality of external input protocol frames with an expected deviation result to obtain a plurality of groups of calculation deviation values, and calculating an average deviation value based on the data; wherein the plurality of deviation value results are single protocol frame deviation values obtained by each comparison; and calculating a correction value of the clock skew according to the skew proportion, the average skew value and the internal count value of the protocol frame signal so as to calibrate the clock skew. The method can calibrate the clock skew in the chip test.

Description

Technical Field

[0001] The present application relates to the field of chip testing technology, for example, to a chip testing method and device, and a testing machine for an asynchronous half-duplex communication protocol. Background Art

[0002] Digital SoC (System on Chip) tape-out testing is a whole process from design specification definition to final product verification, covering key steps such as architecture design, hardware design, software design, integration testing, physical design, tape-out and packaging, and system verification and optimization. In this process, engineers need to conduct detailed simulation tests, select appropriate functional modules, write software programs, conduct system-level tests, optimize circuit design, and finally transform the design into actual semiconductor chips.

[0003] In order to realize SoC simulation test, the related technology discloses a method of synchronously testing a chip using an external clock input, including: generating a pattern that can be used by the test machine for test items at different clock frequencies, and the test machine checks the corresponding chip test items according to the pattern. The machine inputs the synchronous clock and communication interaction signal into the test chip, divides the communication process signal into test points with fixed intervals through the external clock, and receives the chip feedback signal from the test machine, and compares the test point and pattern to determine the test result.

[0004] In the process of implementing the embodiments of the present disclosure, it is found that there are at least the following problems in the related art:

[0005] During the transmission process of the asynchronous half-duplex communication protocol, the protocol itself does not have a synchronous clock signal. The chip needs to run based on the internal clock to complete the communication processing. When the internal clock signal of the chip is frequency-converted or the temperature fluctuates, the time reference may change, resulting in clock deviation and making it impossible to test the asynchronous half-duplex communication protocol of the chip. In addition, the clock deviation may cause the preset pattern to be unsuitable for large-scale test chips. In order to reduce the impact of clock deviation on the test, engineers need to adjust the pattern one by one.

[0006] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present application, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0007] In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. The summary is not an extensive review, nor is it intended to identify key / critical components or delineate the scope of protection of these embodiments, but rather serves as a prelude to the detailed description that follows.

[0008] The embodiments of the present disclosure provide a chip testing method and device and a testing machine for an asynchronous half-duplex communication protocol, which can calibrate clock deviation when performing an asynchronous half-duplex communication protocol test on a chip.

[0009] In some embodiments, the chip testing method for an asynchronous half-duplex communication protocol includes: when the chip is powered on, sending a test instruction and a standard time signal to the chip to respectively calculate the deviation ratio between the internal clock signal and the external clock signal of multiple gears; wherein the internal clock signals of the multiple gears correspond one-to-one to the multiple deviation ratios; using the internal clock to sample the standard time signal to obtain deviation data for dynamic calibration; comparing the sampling results of multiple groups of external input protocol frame signals with the expected deviation results to obtain multiple deviation values, and iterating the deviation values ​​to calculate the average deviation value; wherein the multiple deviation values ​​are single protocol frame deviation values ​​obtained for each comparison; according to the deviation ratio, the average deviation value and the internal count value of the protocol frame signal, calculating the correction value of the clock deviation to calibrate the clock deviation.

[0010] Optionally, calculating the average deviation value according to the deviation value includes: calculating the total number of deviations according to multiple deviation values ​​in sequence; and calculating the average deviation value when the total number of deviations is greater than an upper limit of the number of times.

[0011] Optionally, the total number of deviations is calculated in sequence based on multiple deviation values, and the deviation data includes a maximum allowable range and a reasonable threshold range, including: when the current deviation value exceeds the allowable range, determining whether the current deviation value exceeds the reasonable threshold range; when the current deviation value exceeds the reasonable threshold range, determining the direction in which the current deviation value exceeds the limit; and calculating the total number of deviations based on the direction in which the deviation value exceeds the limit.

[0012] Optionally, the total number of deviations is calculated according to the direction of the excess limit, including: when the current deviation value is a positive deviation, the total number of deviations is increased by 1; when the current deviation value is a negative deviation, the total number of deviations is decreased by 1.

[0013] Optionally, the chip testing method for the asynchronous half-duplex communication protocol further includes: adjusting the maximum limit of the deviation value when the current deviation value does not exceed the allowable range.

[0014] Optionally, the chip testing method for the asynchronous half-duplex communication protocol further includes: when the total number of deviations is greater than an upper limit of the number of times, adjusting a reasonable threshold range of the deviation value.

[0015] Optionally, according to the deviation ratio, the average deviation value and the internal count value of the protocol frame signal, a correction value of the clock deviation is calculated to calibrate the clock deviation, including calculating the correction value according to the following formula:

[0016] Ut =K gp ×(e t +D td )

[0017] Among them, U t is the correction value of the clock deviation, K gp is the deviation ratio, e t is the internal count value of the protocol frame signal, D td is the average deviation value.

[0018] Optionally, calculating the deviation ratio between the internal clock signal and the external clock signal includes: dividing the internal clock signal to obtain a divided clock signal; counting the duration of the standard duration signal according to the divided clock signal and the external clock signal respectively; and obtaining the deviation ratio based on the counting result.

[0019] In some embodiments, the chip testing device for the asynchronous half-duplex communication protocol includes: a processor and a memory storing program instructions, characterized in that the processor is configured to execute the chip testing method for the asynchronous half-duplex communication protocol as described above when running the program instructions.

[0020] In some embodiments, the test machine includes: a test machine body; and the chip testing device for the asynchronous half-duplex communication protocol as described above, installed in the test machine body.

[0021] The chip testing method and device and testing machine for asynchronous half-duplex communication protocol provided by the embodiments of the present disclosure can achieve the following technical effects:

[0022] In the disclosed embodiment, the deviation ratio is calculated for internal calibration of the counting result, and multiple external input protocol frame signals are sampled to calculate the average deviation value. Finally, the correction value of the clock deviation is calculated according to the deviation ratio, the average deviation value and the internal count value of the protocol frame signal. The calibration of the clock deviation is achieved through the correction value, which solves the problem of mismatch between the communication timing and the test machine caused by the clock deviation in the asynchronous half-duplex communication protocol, and realizes the feasibility of large-scale testing of the asynchronous half-duplex communication protocol of the chip. At the same time, it avoids the problem of manual debugging due to clock deviation during the test process, reduces the manual debugging time, and greatly improves the test efficiency.

[0023] The above general description and the following description are exemplary and explanatory only and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] One or more embodiments are exemplarily described by corresponding drawings, which do not limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements, and the drawings do not constitute a scale limitation, and wherein:

[0025] Figure 1 It is a schematic diagram of an implementation environment of a chip testing method for an asynchronous half-duplex communication protocol provided by an embodiment of the present disclosure;

[0026] Figure 2 is a schematic diagram of a chip testing method for an asynchronous half-duplex communication protocol provided by an embodiment of the present disclosure;

[0027] Figure 3 is a schematic diagram of another chip testing method for an asynchronous half-duplex communication protocol provided by an embodiment of the present disclosure;

[0028] Figure 4 is a schematic diagram of another chip testing method for an asynchronous half-duplex communication protocol provided by an embodiment of the present disclosure;

[0029] Figure 5 is a schematic diagram of calculating an average deviation value according to an embodiment of the present disclosure;

[0030] Figure 6 It is a schematic diagram of a chip testing device for an asynchronous half-duplex communication protocol provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0031] In order to be able to understand the features and technical contents of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display.

[0032] The terms "first", "second", etc. in the technical solutions described in the embodiments of the present disclosure are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged where appropriate, so as to describe the embodiments of the present disclosure described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0033] Unless otherwise stated, the term "plurality" means two or more.

[0034] In the embodiment of the present disclosure, the character " / " indicates that the preceding and following objects are in an "or" relationship. For example, A / B indicates: A or B.

[0035] The term "and / or" is a description of the association relationship between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or, A and B.

[0036] The term "correspondence" may refer to an association relationship or a binding relationship. The correspondence between A and B means that there is an association relationship or a binding relationship between A and B.

[0037] At present, system-level chip testing requires testing the asynchronous half-duplex communication protocol in the CP (Chip-Probing) stage and the FT (Functional Test) stage. Compared with the related technology that uses an external clock source to assist in testing, the embodiment of the present disclosure calibrates the chip output signal through dynamic calibration for standard clock deviation and clock temperature drift deviation.

[0038] Figure 1 FIG. 1 is a schematic diagram of an implementation environment of a chip testing method for an asynchronous half-duplex communication protocol provided by an embodiment of the present disclosure. Figure 1 As shown, the implementation environment may include a test machine 100 and a test chip 200 , wherein the test chip includes a clock comparison module 201 , a dynamic calibration module 202 and a communication module 203 .

[0039] Among them, the test machine 100 can send preset instructions to enable the test chip 200 to execute the clock calibration test process item. The test machine 100 sends a test instruction, the test chip 200 identifies the test finger and enters the corresponding test process, and the clock comparison module 201 counts the duration of the standard duration signal sent by the test machine 100 according to the internal and external clock signals, obtains the difference between the internal clock signal and the external clock signal, and calculates the deviation ratio between the internal clock signal and the external clock signal. The dynamic calibration module 202 can calculate the average deviation value according to the sampling result of the protocol frame signal and the expected deviation result. The communication module 203 inputs the internal count value of the protocol frame signal into the dynamic calibration module 202, so that the dynamic calibration module 202 calculates the correction value of the clock deviation according to the deviation ratio, the average deviation value and the internal count value of the protocol frame signal to calibrate the clock deviation.

[0040] Combination Figure 2 As shown, the embodiment of the present disclosure provides a chip testing method for an asynchronous half-duplex communication protocol, comprising:

[0041] S201, when the chip is powered on, the test machine sends a test instruction and a standard time length signal to the chip, so that the test chip can calculate the deviation ratios of the internal clock signals and the external clock signals of the multiple gears respectively; wherein the internal clock signals of the multiple gears correspond to the multiple deviation ratios one by one.

[0042] S202, the test chip samples the standard time length signal using the internal clock to obtain deviation data for dynamic calibration.

[0043] S203, the test machine controls the output of multiple groups of protocol frame signal stimuli through instructions, and the test chip receives the instructions and compares the sampling results of the external stimuli with the expected deviation results to obtain multiple deviation values, and iterates the deviation values ​​to calculate the average deviation value; wherein, the multiple deviation values ​​are single protocol frame deviation values ​​obtained in each comparison.

[0044] S204, the test chip calculates a correction value of the clock deviation according to the deviation ratio, the average deviation value and the internal count value of the protocol frame signal to calibrate the clock deviation.

[0045] The chip testing method for the asynchronous half-duplex communication protocol provided by the embodiment of the present disclosure is adopted to calculate the deviation ratio for internal calibration counting results, sample multiple external input protocol frame signals to calculate the average deviation value, and finally calculate the correction value of the clock deviation according to the deviation ratio, the average deviation value and the internal count value of the protocol frame signal. The calibration of the clock deviation is realized by the correction value, which solves the problem of mismatch between the communication timing and the test machine caused by the clock deviation in the asynchronous half-duplex communication protocol, and realizes the feasibility of large-scale testing of the asynchronous half-duplex communication protocol of the chip. At the same time, it avoids the problem of manual debugging due to clock deviation during the test process, reduces the manual debugging time, and greatly improves the test efficiency.

[0046] Optionally, calculating the average deviation value based on multiple deviation values ​​includes: calculating the total deviation value based on the multiple deviation values ​​in sequence; when the total deviation value is greater than the upper limit of the number of times, calculating the average deviation value based on the current deviation value and the previous deviation value.

[0047] Combination Figure 3 As shown, the embodiment of the present disclosure provides another chip testing method for an asynchronous half-duplex communication protocol, comprising:

[0048] S301, when the chip is powered on, the test machine sends a test instruction and a standard time length signal to the chip, and the test chip calculates the deviation ratios between the internal clock signal and the external clock signal of multiple gears respectively; wherein the internal clock signals of multiple gears correspond to the multiple deviation ratios one by one.

[0049] S302, the test chip samples the standard time length signal using the internal clock to obtain deviation data for dynamic calibration.

[0050] S303, the test machine controls the output of multiple groups of protocol frame signal stimuli through instructions, and the test chip receives and compares the sampling results of the external stimuli with the expected deviation results to obtain multiple deviation values.

[0051] S304, the test chip iteratively calculates the total deviation according to the multiple deviation values ​​in sequence.

[0052] S305, when the total number of deviations of the test chip is greater than the upper limit of the number of deviations, calculate the average deviation value.

[0053] S306, the test chip calculates a correction value of the clock deviation according to the deviation ratio, the average deviation value and the internal count value of the protocol frame signal to calibrate the clock deviation.

[0054] In the disclosed embodiment, the average deviation value (Deviation_ave) is the average value of the accumulated deviation values ​​within the range of a dynamic threshold value that is adjusted once. The process of iteratively calculating the average deviation value according to multiple deviation values ​​includes calculating the total number of deviations according to the multiple deviation values ​​in turn, and calculating the average deviation value when the total number of deviations exceeds a preset upper limit of times. By accumulating multiple deviation values ​​and calculating the average value of the deviation values ​​after reaching a certain number, a more stable and reliable deviation indicator can be obtained. In this way, by setting an upper limit on the number of times, the influence of individual extreme deviation values ​​on the average deviation value can be avoided, thereby ensuring the stability and reliability of the test results. In addition, it can also help testers better understand the distribution of deviation data, and provide strong data support for further analysis and calibration.

[0055] Optionally, the total number of deviations is calculated in sequence based on multiple deviation values, and the deviation data includes a maximum allowable range and a reasonable threshold range, including: when the current deviation value exceeds the allowable range, determining whether the current deviation value exceeds the reasonable threshold range; when the current deviation value exceeds the reasonable threshold range, determining the direction in which the current deviation value exceeds the limit; and calculating the total number of deviations based on the direction in which the deviation value exceeds the limit.

[0056] In the disclosed embodiment, it includes a maximum limit and a reasonable threshold range. The maximum limit (Max_range) refers to the boundary range within which the dynamic threshold can be adjusted, that is, the maximum upper limit (Upper_threshold) and the minimum lower limit (Lower_threshold) of the dynamic threshold. The reasonable threshold range (Range_reasonable) is a fixed value, and the upper and lower limits change dynamically with the calculation process.

[0057] The test machine sends a standard duration signal, and uses the internal clock to sample the signal at the maximum operating temperature, minimum operating temperature, and normal temperature, and obtains the deviation range of the same signal count value under the three-temperature test as the deviation limit of the dynamic calibration process. Among them, the upper limit of the dynamic threshold is measured at the maximum operating temperature limit of the chip, and the lower limit of the dynamic threshold is measured at the minimum operating temperature limit of the chip. The result measured at normal temperature is used as the expected deviation result.

[0058] In the embodiment of the present disclosure, the total number of deviations is calculated based on whether the current deviation value exceeds a threshold value, and each deviation value is compared with a preset maximum limit and a reasonable threshold range to determine whether the deviation value needs to be included in the calculation of the total number of deviations.

[0059] By setting the maximum limit and reasonable threshold range, the deviation data collection process can be controlled more accurately to avoid the impact of extreme deviation values ​​on the overall test results. At the same time, a flexible deviation data processing mechanism is also provided, which can dynamically adjust the maximum limit and reasonable threshold range according to changes in test conditions and environment, thereby improving the adaptability and accuracy of the test.

[0060] Optionally, the total number of deviations is calculated according to the direction of the excess limit, including: when the current deviation value is a positive deviation, the total number of deviations is increased by 1; when the current deviation value is a negative deviation, the total number of deviations is decreased by 1.

[0061] The disclosed embodiment provides a method for calculating the total deviation according to the positive and negative directions of the deviation value. Specifically, when the current deviation value is a positive deviation, the total deviation increases; when the current deviation value is a negative deviation, the total deviation decreases. The directionality of each deviation value is judged, and the total deviation is adjusted accordingly according to the judgment result.

[0062] In this way, the test process can more accurately reflect the actual impact of clock deviation, thereby more effectively identifying and correcting clock deviation, thereby improving the accuracy of the test and the synchronization of the communication protocol.

[0063] Optionally, the chip testing method for the asynchronous half-duplex communication protocol further includes: adjusting the maximum limit of the deviation value when the current deviation value does not exceed the allowable range.

[0064] In the embodiment of the present disclosure, when the current deviation value does not exceed the allowable range, the maximum deviation value is dynamically adjusted to adapt to different test conditions and environmental changes.

[0065] By dynamically adjusting the maximum limit of the deviation value, the flexibility and adaptability of the test method can be improved. When the test conditions or environment change, the maximum limit can be adjusted to ensure the accuracy and reliability of the test results. In addition, it can also help testers better understand the changing trend of the deviation value, providing strong data support for further analysis and calibration.

[0066] Optionally, the chip testing method for the asynchronous half-duplex communication protocol further includes: when the total number of deviations is greater than an upper limit of the number of times, adjusting a reasonable threshold range of the deviation value.

[0067] In the embodiment of the present disclosure, when the total number of deviations is greater than the upper limit of the number of times, the reasonable threshold range of the deviation value is dynamically adjusted to ensure the stability and reliability of the test results.

[0068] By adjusting the reasonable threshold range when the total number of deviations exceeds the preset upper limit, unstable test results caused by a large number of deviation values ​​can be avoided. At the same time, it can also help testers better control the distribution of deviation data and ensure the accuracy of the test process and the synchronization of the communication protocol.

[0069] In practical applications, combined with Figure 5 The schematic diagram of calculating the average deviation value shown in the figure tests the dynamic adjustment module of the chip, and pre-configures the registers for setting the dynamic threshold deviation range and the total number of threshold deviations. The configuration values ​​can be gradually adjusted during the subsequent test process. The purpose of pre-setting the dynamic threshold deviation range is to eliminate the error caused by input / output delay or synchronization signal, so it should not be set too large.

[0070] After the configuration is completed, the whole group of protocol frame signals received during external input are sampled, and the communication module outputs the results according to the protocol provisions, including the number of frames and the count of the duration of received data. The dynamic calibration module calculates the average count of the unit protocol frame, and then records the deviation value of the unit duration of two adjacent whole groups of protocol frames. When the current deviation value does not exceed the allowable range, the average deviation value is calculated based on multiple deviation values, and the reasonable threshold range is adjusted. When the current deviation value exceeds the allowable range, it is determined whether the current deviation value exceeds the reasonable threshold range. When the current deviation value exceeds the reasonable threshold range, the direction of the current deviation value exceeding the limit is determined. When the current deviation value does not exceed the reasonable threshold range, the average deviation value is calculated based on multiple deviation values, and the reasonable threshold range is adjusted. When the current deviation value is a positive deviation, the total deviation value increases by 1. When the current deviation value is a negative deviation, the total deviation value decreases by 1. When the total deviation value is greater than the upper limit of the number of times, the average deviation value is calculated based on multiple deviation values, and the reasonable threshold range of the deviation value is adjusted. The dynamic adjustment module outputs the average deviation value result. When the total deviation value is less than or equal to the upper limit of the number of times, the deviation value does not need to be included in the calculation of the total deviation value.

[0071] The allowed range refers to the boundary range within which the dynamic value can be adjusted. The maximum limit of the allowed range (Max_range) includes the maximum upper limit (Upper_threshold) and the minimum lower limit (Lower_threshold) of the dynamic value. The maximum acceptable deviation range is defined. Deviation values ​​exceeding this range are considered unacceptable and require special processing.

[0072] The reasonable threshold range is a fixed value, whose upper and lower limits change dynamically with the calculation process, and is used to describe the expected deviation range under normal operating conditions. The reasonable threshold range is used to identify those deviation values ​​that may still require attention or adjustment although they are within the maximum limit of the allowable range. In short, the maximum limit of the allowable range is used to define the maximum acceptable deviation range, while the reasonable threshold range is further refined within the maximum limit of the allowable range to define a more reasonable and expected deviation range.

[0073] Optionally, according to the deviation ratio, the average deviation value and the internal count value of the protocol frame signal, a correction value of the clock deviation is calculated to calibrate the clock deviation, including calculating the correction value according to the following formula:

[0074] U t =K gp ×(e t +D td )

[0075] Among them, U t is the correction value of the clock deviation, K gp is the deviation ratio, e t is the internal count value of the protocol frame signal, D td is the average deviation value.

[0076] In the disclosed embodiment, a specific formula is used to calculate the correction value of the clock deviation according to the deviation ratio, the average deviation value and the internal count value of the protocol frame signal. The deviation ratio, the average deviation value and the internal count value can be comprehensively considered to calculate an accurate correction value.

[0077] By applying the formula, the correction amount required for the clock deviation can be accurately calculated, thereby achieving accurate calibration of the chip clock, improving the synchronization and overall performance of the communication protocol, and ensuring the accuracy and reliability of data transmission during asynchronous half-duplex communication.

[0078] Furthermore, the communication module of the test chip can choose whether to adopt the correction value.

[0079] Optionally, calculating the deviation ratio between the internal clock signal and the external clock signal includes: dividing the internal clock signal to obtain a divided clock signal; counting the duration of the standard duration signal according to the divided clock signal and the external clock signal respectively; and obtaining the deviation ratio based on the counting result.

[0080] Combination Figure 4 As shown, the embodiment of the present disclosure provides another chip testing method for an asynchronous half-duplex communication protocol, comprising:

[0081] S401, when the chip is powered on, the test machine sends a test instruction and a standard time length signal, and the test chip performs frequency division processing on the internal clock signal to obtain a divided clock signal.

[0082] S402, the test chip counts the duration of the standard duration signal according to the frequency division signal and the external clock signal respectively.

[0083] S403, the test chip iteratively calculates and obtains the deviation ratio according to the counting result.

[0084] S404, the test chip samples the standard time length signal using the internal clock to obtain deviation data for dynamic calibration.

[0085] S405, the test machine controls the output of multiple groups of protocol frame signal stimuli through instructions, and the test chip receives the instructions and compares the sampling results of the external stimuli with the expected deviation results to obtain multiple deviation values, and iterates the deviation values ​​to calculate the average deviation value; among which, the multiple deviation values ​​are single protocol frame deviation values ​​obtained in each comparison.

[0086] S406, the test chip calculates a correction value of the clock deviation according to the deviation ratio, the average deviation value and the internal count value of the protocol frame signal to calibrate the clock deviation.

[0087] In the embodiment of the present disclosure, when the chip is powered on, the deviation ratio is calculated by frequency-dividing the internal clock signal and counting the duration of the standard duration signal. The internal clock signal is frequency-divided to obtain a frequency-divided signal synchronized with the external clock signal, and then the duration of the standard duration signal is counted according to the frequency-divided clock signal and the external clock signal, and finally the deviation ratio is calculated according to the counting result.

[0088] Clock frequency division and counting can accurately measure and calculate clock deviation, providing accurate basic data for subsequent dynamic calibration and optimization of communication protocols. It can also help testers better understand the nature and impact of clock deviation, providing strong data support for further analysis and calibration.

[0089] For example, in actual applications, the internal clock signal is used after corresponding frequency division and then transmitted to the clock comparison module as a divided signal of approximately 1Mhz. At the same time, the 1Mhz standard clock signal emitted by the test machine is used as an external clock signal to access the external clock interface of the chip multiplexing. The external input clock is synchronized with the internal clock signal and then transmitted to the clock comparison module.

[0090] Furthermore, the test chip actively sends a standard duration signal of the same duration, uses an undivided clock to count and brings in a calibration value corresponding to the division ratio, and the test machine can determine the accuracy of the deviation ratio by measuring.

[0091] Combination Figure 6 As shown, the embodiment of the present disclosure provides a chip testing device 60 for an asynchronous half-duplex communication protocol, including a processor 600 and a memory 601. Optionally, the device 60 may also include a communication interface 602 and a bus 603. The processor 600, the communication interface 602, and the memory 601 may communicate with each other through the bus 603. The communication interface 602 may be used for information transmission. The processor 600 may call the logic instructions in the memory 601 to execute the chip testing method for the asynchronous half-duplex communication protocol of the above embodiment.

[0092] In addition, the logic instructions in the memory 601 described above can be implemented in the form of software functional units and can be stored in a computer-readable storage medium when sold or used as an independent product.

[0093] The memory 601 is a computer-readable storage medium that can be used to store software programs and computer executable programs, such as program instructions / modules corresponding to the method in the embodiment of the present disclosure. The processor 600 executes the functional application and data processing by running the program instructions / modules stored in the memory 601, that is, the chip testing method for the asynchronous half-duplex communication protocol in the above embodiment is implemented.

[0094] The memory 601 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and an application required for at least one function; the data storage area may store data created according to the use of the terminal device, etc. In addition, the memory 601 may include a high-speed random access memory and may also include a non-volatile memory.

[0095] The disclosed embodiment provides a test machine, including: a test machine body, and the above-mentioned chip test device 60 for the asynchronous half-duplex communication protocol. The chip test device 60 for the asynchronous half-duplex communication protocol is used in the test machine body. The usage relationship described here is not limited to the placement inside the test machine body, but also includes the connection method with other components of the test machine, including but not limited to physical connection, electrical connection or signal transmission connection, etc. Those skilled in the art can understand that the chip test device 60 for the asynchronous half-duplex communication protocol can be adapted to a feasible test machine body, thereby realizing other feasible embodiments.

[0096] The technical solution of the embodiment of the present disclosure can be embodied in the form of a software product, which is stored in a storage medium and includes one or more instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in the embodiment of the present disclosure. The aforementioned storage medium may be a non-transient storage medium, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a disk or an optical disk, and other media that can store program codes.

[0097] The above description and the accompanying drawings fully illustrate the embodiments of the present disclosure so that those skilled in the art can practice them. Other embodiments may include structural, logical, electrical, process and other changes. The embodiments represent only possible changes. Unless explicitly required, separate components and functions are optional, and the order of operation may vary. The parts and features of some embodiments may be included in or replace the parts and features of other embodiments. Moreover, the words used in this application are only used to describe the embodiments and are not used to limit the claims. As used in the description of the embodiments and the claims, unless the context clearly indicates, the singular forms of "a", "an" and "the" are intended to include plural forms as well. Similarly, the term "and / or" as used in this application refers to any and all possible combinations of listings containing one or more associated ones. In addition, when used in the present application, the term "comprise" and its variants "comprises" and / or comprising refer to the presence of stated features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the presence of other identical elements in the process, method or device comprising the elements. In this article, each embodiment may focus on the differences from other embodiments, and the same and similar parts between the various embodiments may refer to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method part disclosed in the embodiments, then the relevant parts can refer to the description of the method part.

[0098] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software may depend on the specific application and design constraints of the technical solution. The technicians may use different methods for each specific application to implement the described functions, but such implementations should not be considered to exceed the scope of the embodiments of the present disclosure. The technicians may clearly understand that, for the convenience and simplicity of description, the specific working processes of the systems, devices and units described above may refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here.

[0099] In the embodiments disclosed herein, the disclosed methods and products (including but not limited to devices, equipment, etc.) can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units can be only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between each other shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms. The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to implement this embodiment. In addition, each functional unit in the embodiment of the present disclosure may be integrated in a processing unit, or each unit may exist physically alone, or two or more units may be integrated in one unit.

[0100] The flowchart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to the embodiment of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of the code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. In some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, which can depend on the functions involved. In the description corresponding to the flowchart and the block diagram in the accompanying drawings, the operations or steps corresponding to different boxes can also occur in a different order from the order disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, which can depend on the functions involved. Each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified functions or actions, or may be implemented by a combination of dedicated hardware and computer instructions.

Claims

1. A chip testing method for an asynchronous half-duplex communication protocol, characterized in that: include: When the chip is powered on, a test instruction and a standard time length signal are sent to the chip to respectively calculate the deviation ratios of the internal clock signal and the external clock signal of the multiple gears; wherein the internal clock signals of the multiple gears correspond to the multiple deviation ratios one by one; The standard time length signal is sampled using an internal clock to obtain deviation data for dynamic calibration; Compare the sampling results of multiple groups of external input protocol frame signals with the expected deviation results to obtain multiple deviation values, and iterate the deviation values ​​to calculate the average deviation value; wherein the multiple deviation values ​​are single protocol frame deviation values ​​obtained in each comparison; According to the deviation ratio, the average deviation value and the internal count value of the protocol frame signal, a correction value of the clock deviation is calculated for calibrating the clock deviation.

2. The chip testing method according to claim 1, characterized in that: Calculate the average deviation value based on the deviation values, including: Calculating the total number of deviations in turn based on the multiple deviation values; When the total number of deviations is greater than the upper limit, the average deviation value is calculated.

3. The chip testing method according to claim 2, characterized in that: Deviation data includes the maximum allowable range and the reasonable threshold range. The total number of deviations is calculated based on multiple deviation values, including: When the current deviation value exceeds the allowable range, determine whether the current deviation value exceeds the reasonable threshold range; When the current deviation value exceeds a reasonable threshold range, determine the direction in which the current deviation value exceeds the limit; The total number of deviations is calculated based on the direction of the excess.

4. The chip testing method according to claim 3, characterized in that: The total number of deviations is calculated based on the direction of the excess, including: When the current deviation value is a positive deviation, the total deviation value increases by 1; In the case where the current deviation value is a negative deviation, the total number of deviations is reduced by 1.

5. The chip testing method according to claim 3, characterized in that: Also includes: When the current deviation value does not exceed the allowable range, adjust the maximum limit of the deviation value.

6. The chip testing method according to claim 3, characterized in that: Also includes: When the total number of deviations is greater than the upper limit, adjust the reasonable threshold range of the deviation value.

7. The chip testing method according to any one of claims 1 to 6, characterized in that: According to the deviation ratio, the average deviation value and the internal count value of the protocol frame signal, a correction value of the clock deviation is calculated to calibrate the clock deviation, including calculating the correction value according to the following formula: U t =K gp ×(e t +D td ) Among them, U t is the correction value of the clock deviation, K gp is the deviation ratio, e t is the internal count value of the protocol frame signal, D td is the average deviation value.

8. The chip testing method according to any one of claims 1 to 6, characterized in that: Calculate the deviation ratio between the internal clock signal and the external clock signal, including: Perform frequency division processing on the internal clock signal to obtain a frequency division signal; Counting the duration of the standard duration signal according to the frequency division signal and the external clock signal respectively; The deviation ratio is calculated based on the counting results.

9. A chip testing device for an asynchronous half-duplex communication protocol, comprising a processor and a memory storing program instructions, characterized in that: The processor is configured to run the program instructions to execute the chip testing method for the asynchronous half-duplex communication protocol according to any one of claims 1 to 8.

10. A testing machine, characterized in that: include: Test machine body; The chip testing device for the asynchronous half-duplex communication protocol as claimed in claim 9 is installed on the test machine body.

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